Etch profile control of gate contact openings

Abstract

The present disclosure relates to etch profile control of gate contact openings. A method includes forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etch process to form a gate contact opening that extends through the ILD layer and terminates before reaching the etch resistant layer; performing a second etch process to deepen the gate contact opening, wherein the second etch process etches the etch resistant layer at a slower etch rate than the etch rate of etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more particularly to the control of the etch profile of gate contact openings. Background Technology

[0002] Technological advancements in IC materials and design have resulted in several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (the number of interconnect devices per chip area) has typically increased, while geometry (the smallest component (or line) that can be produced using manufacturing processes) has decreased. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. Summary of the Invention

[0003] One aspect of this disclosure provides a method of forming a semiconductor device, comprising: forming a gate structure on a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap on the etched-back gate structure; depositing an etch resist layer on the gate dielectric cap; depositing a contact etch stop layer on the etch resist layer and depositing an interlayer dielectric (ILD) layer on the contact etch stop layer; performing a first etch process to form a gate contact opening extending through the ILD layer and terminating before reaching the etch resist layer; performing a second etch process to deepen the gate contact opening, wherein the second etch process etches the etch resist layer at an etch rate slower than that used to etch the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

[0004] Another aspect of this disclosure provides a method of forming a semiconductor device, comprising: forming a first gate dielectric cap over a first gate structure and forming a second gate dielectric cap over a second gate structure; depositing an etch resist layer over the first gate dielectric cap and the second gate dielectric cap; depositing a contact etch stop layer over the etch resist layer and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a first gate contact opening and a second gate contact opening extending through the ILD layer, wherein the width of the first gate contact opening is smaller than the width of the second gate contact opening; performing a second etching process to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein after the second etching process etches through the etch resist layer, the sidewall profile of the first gate contact opening becomes more perpendicular than before etching the etch resist layer; and after performing the second etching process, forming a first gate contact in the first gate contact opening and forming a second gate contact in the second gate contact opening.

[0005] Another aspect of this disclosure provides a semiconductor device comprising: a plurality of source / drain epitaxial structures located on a substrate; a plurality of source / drain contacts, each located on the plurality of source / drain epitaxial structures; a gate structure laterally located between the plurality of source / drain contacts; a gate dielectric cap located on the gate structure with its bottom surface lower than the top surface of the plurality of source / drain contacts; an oxide-based etch resist layer located on the gate dielectric cap; a nitride-based etch stop layer located on the oxide-based etch resist layer; an interlayer dielectric (ILD) layer located on the nitride-based etch stop layer; and gate contacts extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch resist layer, and the gate dielectric cap to be electrically connected to the gate structure. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1 to 20B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown.

[0008] Figures 21 to 39B Perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure are shown. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of description, this document uses spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. As used herein, “approximately,” “about,” “close to,” or “substantially” should generally mean within twenty percent, or ten percent, or five percent of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “close to,” or “substantially” can be inferred unless explicitly stated otherwise.

[0011] This disclosure generally relates to integrated circuit structures and methods of forming them, and more specifically, to the fabrication of transistors (e.g., FinFETs, Gate All-Around (GAA) transistors), and gate contacts above the gate structures of transistors. It should also be noted that embodiments are presented in the form of multi-gate transistors. Multi-gate transistors include transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices can include p-type or n-type metal-oxide-semiconductor devices. Specific examples are presented here and referred to as FinFETs due to their fin-like structures. FinFETs have gate structures formed on three sides of a channel region (e.g., around the upper portion of the channel region in a semiconductor fin). Embodiments of a class of multi-gate transistors referred to as GAA devices are also presented herein. GAA devices include any device whose gate structure or a portion thereof is formed on all four sides of a channel region (e.g., around a portion of the channel region). Devices presented herein also include embodiments in which the channel region is arranged in one or more nanosheet channels, one or more nanowire channels, and / or other suitable channel configurations.

[0012] After the front-end-of-line (FEOL) process for manufacturing transistors is completed, gate contacts are formed on the gate structure of the transistor. The formation of gate contacts typically includes, for example, but not limited to: depositing an interlayer dielectric (ILD) layer on a gate dielectric cap covering a high-k / metal gate (HKMG) structure; forming gate contact openings extending through the ILD layer and the gate dielectric cap using one or more etching processes; and then depositing one or more metal layers in the gate contact openings to serve as gate contacts.

[0013] In some embodiments, prior to forming the ILD layer, an additional etch stop layer (also known as an intermediate contact etch stop layer (MCESL)) is formed blanket-formed over the gate dielectric cap. The MCESL has a different etch selectivity than the ILD layer, thus slowing down the etch process that etches through the ILD layer. After performing a contact etch process to form the gate contact opening extending through the ILD layer, another etch process (sometimes called liner removal (LRM) etch, since the MCESL and gate dielectric cap can be combined as a liner over the top surface of the gate structure) is performed to break through the MCESL and gate dielectric cap.

[0014] Contact etching processes can create gate contact openings of varying sizes depending on circuit function and / or design rules. Alternatively, size variations in gate contact openings may unintentionally occur due to inaccuracies in the contact etching process. Size variations formed during contact etching can cause wider gate contact openings to extend deeper into the MCESL than narrower gate contact openings. This difference in opening depth is known as the depth loading problem. Due to this depth loading problem, wider gate contact openings may sometimes penetrate the MCESL, or even the gate dielectric cap, before the LRM etching process is performed. Therefore, the LRM etching process may further deepen the wider gate contact openings into, for example, the gate spacer next to the gate structure, creating a serrated recess in the gate spacer, which in turn increases the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact). Furthermore, due to this depth loading, narrower gate contact openings may sometimes have a more tapered profile than wider gate contact openings, which in turn reduces the gate contact area and thus increases contact resistance.

[0015] Therefore, in various embodiments, this disclosure provides an additional oxide layer on the gate dielectric cap. This oxide layer has a different material composition than the gate dielectric cap and / or MCESL, and thus has a different etch selectivity. Therefore, this oxide layer allows the LRM etching process to be slowed down when the gate contact opening reaches the oxide layer. Slowing down the LRM etching prevents serrated patterns in wider openings, which in turn reduces the risk of leakage current. Furthermore, slowing down the LRM etching allows the formation of contact openings with a more vertical profile, which in turn increases the gate contact area and thus reduces the contact resistance.

[0016] Figures 1 to 20BPerspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type FinFETs) and n-type transistors (e.g., n-type FinFETs). In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. It should be understood that additional embodiments of the method may be available. Figure 1-20B Additional operations are provided before, during, and after the processes shown, and some of these operations can be replaced or eliminated. The order of these operations / processes can be interchangeable.

[0017] Figure 1 A perspective view of the initial structure is shown. This initial structure includes a substrate 12. The substrate 12 may be a semiconductor substrate (also referred to as a wafer in some embodiments), which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. According to some embodiments of this disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon-germanium (SiGe) layer or germanium layer (without silicon) on the bulk silicon substrate. The substrate 12 may be doped with p-type or n-type impurities. Isolation regions 14, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 12. The portion of the substrate 12 located between adjacent STI regions 14 is referred to as a semiconductor strip 102.

[0018] STI region 14 may include a liner oxide (not shown). The liner oxide may be formed from a thermal oxide formed by thermal oxidation of a surface layer of substrate 12. The liner oxide may also be a deposited silicon oxide layer formed using methods such as atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). STI region 14 may also include a dielectric material situated on the liner oxide, and this dielectric material may be formed using flowable chemical vapor deposition (FCVD) or spin coating, etc.

[0019] refer to Figure 2 The STI region 14 is recessed such that the top portion of the semiconductor strip 102 protrudes above the top surface of the adjacent STI region 14 to form a protruding fin 104. This etching can be performed using a dry etching process, wherein NH3 and NF3 are used as etching gases. A plasma may be generated during this etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of the STI region 14 is performed using a wet etching process. For example, the etching chemicals may include diluted HF.

[0020] In the exemplary embodiments described above, the fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, spacing smaller than that achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0021] The material of the protruding fin 104 can also be replaced with a material different from that of the substrate 12. For example, if the protruding fin 104 is used in an n-type transistor, it can be formed of Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs). On the other hand, if the protruding fin 104 is used in a p-type transistor, it can be formed of Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb).

[0022] refer to Figure 3A and Figure 3B A dummy gate structure 106 is formed on the top surface and sidewalls of the protruding fin 104. Figure 3B It shows the contents Figure 3A A cross-sectional view obtained from the vertical plane of line BB in the diagram. The formation of the dummy gate structure 106 includes the sequential deposition of a gate dielectric layer and a dummy gate electrode layer across fin 104, followed by patterning of the gate dielectric layer and the dummy gate electrode layer. As a result of this patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 located above the gate dielectric layer 108. The gate dielectric layer 108 can be any acceptable dielectric layer (e.g., silicon oxide, silicon nitride, etc., or combinations thereof) and can be formed using any acceptable process (e.g., thermal oxidation, spin coating, CVD, etc.). The dummy gate electrode 110 can be any acceptable electrode layer, including, for example, polysilicon, metal, etc., or combinations thereof. The gate electrode layer can be deposited using any acceptable deposition process, such as CVD, plasma-enhanced CVD (PECVD), etc. Each dummy gate structure 106 spans one or more protruding fins 104. The dummy gate structure 106 may have a length direction perpendicular to the length direction of the corresponding protruding fin 104.

[0023] A mask pattern can be formed on the dummy gate electrode layer to assist in patterning. In some embodiments, the hard mask pattern includes a bottom mask 112 on top of the blanket polysilicon layer and a top mask 114 on top of the bottom mask 112. The hard mask pattern is made of one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. In some embodiments, the bottom mask 112 comprises silicon nitride, and the top mask 114 comprises silicon oxide. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode 110, and the blanket gate dielectric layer is patterned into the gate dielectric layer 108.

[0024] Next, as Figure 4 As shown, a gate spacer 116 is formed on the sidewall of the dummy gate structure 106. In some embodiments of the gate spacer formation step, a spacer material layer is deposited on the substrate 12. The spacer material layer may be a conformal layer that is subsequently etched back to form the gate spacer 116. In some embodiments, the spacer material layer comprises multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed on the first spacer layer 118. The first spacer layer 118 and the second spacer layer 120 are each made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. By way of example and not limitation, the first spacer layer 118 and the second spacer layer 120 may be formed by sequentially depositing two different dielectric materials on the dummy gate structure 106 using a process such as a CVD process, a subatmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable processes. An anisotropic etching process is then performed on the deposited spacer layers 118 and 120 to expose portions of fin 104 not covered by dummy gate structure 106 (e.g., in the source / drain regions of fin 104). The portion of spacer layers 118 and 120 directly above the dummy gate structure 106 can be completely removed by this anisotropic etching process. The portions of spacer layers 118 and 120 on the sidewalls of the dummy gate structure 106 can be retained to form a gate sidewall spacer, which is referred to as gate spacer 116 for simplicity. In some embodiments, the first spacer layer 118 is formed of silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed of silicon nitride, which has higher etch resistance than silicon oxide for subsequent etching processes (e.g., etching the source / drain recesses in fin 104). In some embodiments, gate spacer 116 can be used to offset subsequently formed doped regions (e.g., source / drain regions). The gate spacer 116 can be further used to design or modify the source / drain region profile.

[0025] exist Figure 5 In this process, after the gate spacer 116 is formed, a source / drain structure 122 is formed on the source / drain region of the fin 104 that is not covered by the dummy gate structure 106 and the gate spacer 116. In some embodiments, the formation of the source / drain structure 122 includes recessing the source / drain region of the fin 104 and then epitaxially growing semiconductor material in the recessed source / drain region of the fin 104.

[0026] A suitable selective etching process can be used to recess the source / drain regions of the fin 104. This suitable selective etching process etches the semiconductor fin 104 but hardly etches the gate spacer 116 and the top mask 114 of the dummy gate structure 106. For example, recessing the semiconductor fin 104 can be performed by dry chemical etching using a plasma source and an etchant gas. The plasma source can be inductively coupled plasma (ICR) etching, transformer coupled plasma (TCP) etching, electron cyclotron resonance (ECR) etching, reactive ion etching (RIE), etc., and the etchant gas can be fluorine, chlorine, bromine, or combinations thereof, which etches the semiconductor fin 104 at a faster etch rate than etching the gate spacer 116 and the top mask 114 of the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by wet chemical etching (e.g., ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof), which etches the semiconductor fin 104 at a faster etch rate than etching the top mask 114 of the gate spacer 116 and the dummy gate structure 106. In some other embodiments, recessing the semiconductor fin 104 can be performed by a combination of dry chemical etching and wet chemical etching.

[0027] Once a recess is formed in the source / drain region of fin 104, a source / drain epitaxial structure 122 is formed in the source / drain recess in fin 104 using one or more epitaxial processes that provide one or more epitaxial materials on semiconductor fin 104. During the epitaxial growth process, gate spacer 116 confines the one or more epitaxial materials in the source / drain region of fin 104. In some embodiments, the lattice constant of epitaxial structure 122 is different from the lattice constant of semiconductor fin 104, such that strain or stress can be applied to the channel region in fin 104 and between epitaxial structures 122 through epitaxial structures 122 to improve carrier mobility and enhance device performance of semiconductor device. Epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. Epitaxial processes can use gaseous and / or liquid precursors that interact with the components of semiconductor fin 104.

[0028] In some embodiments, the source / drain epitaxial structure 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structure 122 may be in-situ doped during the epitaxial process by introducing dopants, including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations of the foregoing. If the source / drain epitaxial structure 122 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 122. In some exemplary embodiments, the source / drain epitaxial structure 122 in an n-type transistor includes SiP, while the source / drain epitaxial structure 122 in a p-type transistor includes GeSnB and / or SiGeSnB. In embodiments with different device types, a mask (e.g., photoresist) can be formed over the n-type device region while exposing the p-type device region, and a p-type epitaxial structure can be formed on the exposed fin 104 in the p-type device region. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type device region while exposing the n-type device region, and an n-type epitaxial structure can be formed on the exposed fin 104 in the n-type device region. The mask can then be removed.

[0029] Once the source / drain epitaxial structure 122 is formed, an annealing process can be performed to activate the p-type or n-type dopant in the source / drain epitaxial structure 122. This annealing process can be, for example, rapid thermal annealing (RTA), laser annealing, millisecond thermal annealing (MSA), etc.

[0030] Next, in Figure 6In this process, an interlayer dielectric (ILD) layer 126 is formed on substrate 12. In some embodiments, a contact etch stop layer (CESL) may be formed prior to the formation of the ILD layer 126. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having a different etch selectivity than the ILD layer 126. The CESL may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as oxides forming tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), etc.), and / or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer 126 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 126 is formed, the wafer may undergo a high thermal budget process to anneal the ILD layer 126.

[0031] In some examples, after the formation of the ILD layer 126, a planarization process can be performed to remove excess material from the ILD layer 126. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 126 (and the CESL layer, if present) above the dummy gate structure 106. In some embodiments, the CMP process also removes hard mask layers 112, 114 (e.g., Figure 5 (as shown) and exposes the dummy gate electrode 110.

[0032] Next, as Figure 7 As shown, the remaining dummy gate structure 106 is removed, thereby forming a gate trench GT1 between the respective gate spacers 116. The dummy gate structure 106 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the material in the dummy gate structure 106 at a faster etch rate than etching other materials (e.g., gate spacers 116 and / or ILD layer 126).

[0033] After that, as Figure 8As shown, alternative gate structures 130 are formed in the gate trench GT1. Gate structures 130 can be the final gate of a FinFET. Each final gate structure can be a high-k / metal gate (HKMG) stack, however other compositions are also possible. In some embodiments, each gate structure 130 forms a gate associated with three sides of the channel region provided by the fin 104. In other words, each gate structure 130 surrounds the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a work function metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 formed over the work function metal layer 134 and filling the remaining portion of the gate trench GT1. The gate dielectric layer 132 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, high-k gate dielectrics include dielectric materials having a high dielectric constant (e.g., greater than the dielectric constant of thermally oxidized silicon (about 3.9)). The work function metal layer 134 and / or fill metal 136 used in the high-k / metal gate structure 130 may include metals, metal alloys, or metal silicides. The formation of the high-k / metal gate structure 130 may include various deposition processes for forming various gate materials, one or more inner liner layers, and one or more CMP processes for removing excess gate material.

[0034] In some embodiments, the interface layer of the gate dielectric layer 132 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 132 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitride (SiON), and combinations thereof.

[0035] The work function metal layer 134 may include a work function metal for providing a suitable work function for the high-k / metal gate structure 130. For an n-type FinFET, the work function metal layer 134 may include one or more n-type work function metals (N-metals). The n-type work function metals may, exemplarily, include, but are not limited to, the following: titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 134 may include one or more p-type work function metals (P-metals). p-type work function metals may include, but are not limited to, the following: titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0036] In some embodiments, the filler metal 136 may include, but is not limited to, the following: tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0037] Then refer to Figure 9 An etch-back process is performed to etch back the gate structure 130 and the gate spacer 116, thereby forming a recess R1 on the etched-back gate structure 130 and the etched-back gate spacer 116. In some embodiments, since the material replacing the gate structure 130 has a different etch selectivity than the gate spacer 116, a first selective etch-back process can be initially performed to etch back the gate structure 130, thereby reducing the replacement gate structure 130 to be lower than the gate spacer 116. Then, a second selective etch-back process is performed to reduce the gate spacer 116. As a result, the top surface of the replacement gate structure 130 can be at a different level than the top surface of the gate spacer 116. For example, in... Figure 9 In the illustrated embodiment, the top surface of the replacement gate structure 130 is lower than the top surface of the gate spacer 116. However, in some other embodiments, the top surface of the replacement gate structure 130 may be flush with or higher than the top surface of the gate spacer 116.

[0038] Subsequently, a gate metal cap 138 is optionally formed on top of the replacement gate structure 130 using a suitable process such as CVD or ALD. In some embodiments, the metal cap 138 is formed on the replacement gate structure 130 in a bottom-up manner. For example, the metal cap 138 is selectively grown on a metal surface (e.g., work function metal layer 134 and filler metal 136), so that the sidewalls of the gate spacer 116 are substantially without the metal cap 138. By way of example and not limitation, the metal cap 138 may be a substantially fluorine-free tungsten (FFW) film, wherein in embodiments where the FFW is formed using a chlorine-containing precursor, the amount of fluorine impurities is less than 5 atomic percent and the amount of chlorine impurities is greater than 3 atomic percent. For example, one or more non-fluorine-based tungsten precursors (e.g., but not limited to, tungsten pentachloride (WCl5), tungsten hexachloride (WCl6)) may be used to form the FFW film or a film including the FFW by ALD or CVD. In some embodiments, portions of the metal cap 138 may extend over the gate dielectric layer 132, such that the metal cap 138 may also cover the exposed surface of the gate dielectric layer 132. Since the metal cap 138 is formed in a bottom-up manner, its formation can be simplified, for example, by reducing repeated etch-back processes used to remove unwanted metallic material resulting from conformal growth.

[0039] In some embodiments where the metal cap 138 is formed using a bottom-up approach, the growth of the metal cap 138 on the metal surface (i.e., the metal in the gate structure 130) has a different nucleation delay compared to the dielectric surface (i.e., the dielectric in the gate spacer 116 and / or the ILD layer 126). The nucleation delay on the metal surface is shorter than that on the dielectric surface. Therefore, the difference in nucleation delay allows for selective growth on the metal surface. This disclosure utilizes such selectivity in various embodiments to allow metal growth from the gate structure 130 while suppressing metal growth from the gate spacer 116 and / or the ILD layer 126. As a result, the deposition rate of the metal cap 138 on the gate structure 130 is faster than that on the gate spacer 116 and the ILD layer 126. In some embodiments, the top surface of the resulting metal cap 138 is lower than the top surface of the etched-back gate spacer 116. However, in some other embodiments, the top surface of the metal cap 138 may be flush with or above the top surface of the etched-back gate spacer 116.

[0040] Next, as Figure 10As shown, a dielectric capping layer 140 is deposited on substrate 12 until the recess R1 is overfilled. The dielectric capping layer 140 includes SiN, SiC, SiCN, SiON, SiCON, combinations thereof, etc., and is formed by a suitable deposition technique, such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), or combinations thereof. Then, a CMP process is performed to remove the capping layer located outside the recess R1, thereby leaving the portion of the dielectric capping layer 140 located in the recess R1 to serve as the gate dielectric capping layer 142. Figure 11 The resulting structure is shown.

[0041] refer to Figure 12 A source / drain contact 144 is formed, extending through the ILD layer 126. By way of example and not limitation, the formation of the source / drain contact 144 includes: performing one or more etching processes to form contact openings extending through the ILD layer 126 (and CESL, if present) to expose the source / drain epitaxial structure 122; depositing one or more metal materials to overfill the contact openings; and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 126 at a faster etch rate than etching the gate dielectric cap 142 and the gate spacer 116. As a result, this selective etching is performed using the gate dielectric cap 142 and the gate spacer 116 as an etch mask, such that the contact openings are formed to be self-aligned with the source / drain epitaxial structure 122 (and therefore the source / drain contact 144 is formed to be self-aligned with the source / drain epitaxial structure 122) without using additional photolithography processes. In this case, the source / drain contact 144 can be referred to as a self-aligned contact (SAC), and the gate dielectric cap 142 that allows the formation of the self-aligned contact 144 can be referred to as the SAC cap 142. As a result of the formation of the self-aligned contact, each of the SAC caps 142 has opposing sidewalls that respectively contact the source / drain contact 144.

[0042] exist Figure 13In this process, an etch resist layer 145 is formed over the gate dielectric cap 142 and the source / drain contacts 144. The etch resist layer 145 can be formed using an ALD process, a PECVD process, and / or other suitable deposition processes. In some embodiments, the etch resist layer 145 is made of a material different from the material of the gate dielectric cap 142 and the subsequently formed MCESL. For example, the gate dielectric cap 142 and the subsequently formed MCESL are made of the same material (e.g., silicon nitride), with no etch selectivity between them, and the etch resist layer 145 is made of an oxide-based material or other suitable dielectric material different from silicon nitride. Oxide-based materials include, but are not limited to, silicon oxide (SiO2). x The resist layer 145 may be a TEOS (tetraethoxysilane; tetraethyl orthosilicate; tetraethoxysilicate; tetraethoxysilicide) oxide, silicon-rich silicon oxide, or another suitable oxide-based dielectric material. Silicon-rich silicon oxide is silicon oxide comprising more than 50% silicon. Due to the material differences, the resist layer 145 has a different etch selectivity than the subsequently formed MCESL and gate dielectric cap 142. As a result, the resist layer 145 can have a slower etch rate in the subsequent LRM etch process than both the gate dielectric cap 142 and the MCESL, which allows for a slower LRM etch process, as will be discussed in more detail below.

[0043] In some embodiments, the etch resist layer 145 has a thickness T1. In some embodiments, for the 3nm technology node, the thickness T1 ranges from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of thickness T1 to the maximum thickness T2 of the gate dielectric cap 142 ranges from about 3:100 to about 60:100. If the thickness is too small than T1 / T2, the etch resist layer 145 may be too thin to slow down the subsequent LRM etching process. If the thickness is too large than T1 / T2, the etch resist layer 145 may be too thick to be penetrated within the expected etching duration. For other technology nodes, such as the 20nm, 16nm, 10nm, 7nm, and / or 5nm nodes, the thickness T1 of the etch resist layer 145 may range from about 1nm to about 20nm.

[0044] exist Figure 14 Once an etch resist layer 145 has been formed over the gate dielectric cap 142, an intermediate contact etch stop layer (MCESL) 146 is formed over the etch resist layer 145. The MCESL 146 can be formed using a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or has a junction with the subsequently formed ILD layer (e.g., Figure 15Other suitable materials with different etch selectivity (as shown). In some embodiments, both the gate dielectric cap 142 and MCESL 146 are nitride-based materials (e.g., silicon nitride), so the etch resist layer 145 (e.g., an oxide-based layer) has different etch selectivity than both the gate dielectric cap 142 and MCESL 146. In some embodiments, the thickness T3 of MCESL 146 is greater than the thickness T1 of the etch resist layer 145. For example, the thickness T3 of MCESL 146 is in the range of about 3 nm to about 20 nm.

[0045] refer to Figure 15 Another ILD layer 148 is formed on top of the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials (e.g., silicon nitride) having a different etch selectivity than the MCESL 146. In some embodiments, the ILD layer 148 is made of silicon oxide (SiO2). x The ILD layer 148 is formed by a PECVD process or other suitable deposition techniques. In some embodiments, the thickness T4 of the ILD layer 148 is greater than the thickness T3 of the MCESL 146 and the thickness T1 of the etch-resistant layer 145. In some other embodiments, the thickness T4 of the ILD layer 148 is greater than the total thickness of the MCESL 146 and the etch-resistant layer 145. For example, the thickness T4 of the ILD layer 148 is in the range of about 3 nm to about 100 nm.

[0046] refer to Figure 16 The ILD layer 148 is patterned using a first etching process (also known as a contact etching process) ET1 to form gate contact openings O21 and O22 extending through the ILD layer 148. In some embodiments, the contact etching process ET1 is an anisotropic etching process, such as plasma etching. Taking plasma etching as an example, the ILD layer 148 is patterned using a first etching process (also known as a contact etching process) ET1 to form gate contact openings O21 and O22 extending through the ILD layer 148. Figure 15The semiconductor substrate 12 of the illustrated structure is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gaseous mixture of fluorine-containing gas (e.g., C4F8, C5F8, C4F6, CHF3, or similar substances), an inert gas (e.g., argon or helium), and optionally a weak oxidant (e.g., O2 or CO, or similar substances) for a duration sufficient to etch through the ILD layer 148 and recess the exposed portion of the MCESL 146 at the bottom of the gate contact openings O21 and O22. The plasma generated in a gaseous mixture including C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148 and recess the exposed portion of the MCESL 146 at the bottom of the gate contact openings O21 and O22. The pressure of the plasma etching environment is between about 10 mTorr and about 100 mTorr, and the plasma is generated by RF power between about 50 watts and 1000 watts.

[0047] In some embodiments, the aforementioned etchant and etching conditions for the contact etching process ET1 are selected in such a way that MCESL 146 (e.g., SiN) exhibits better performance than ILD layer 148 (e.g., SiO2). x A slower etch rate. This allows MCESL 146 to act as a detectable etch endpoint, which in turn prevents over-etching and therefore prevents punch-through or penetration through MCESL 146. In other words, the contact etch process ET1 is tuned to etch silicon oxide at a faster etch rate than etching silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated from a hydrogen (H2) gaseous mixture. Therefore, according to some embodiments of this disclosure, the contact etch process ET1 is performed using a hydrogen-free gaseous mixture. In other words, the plasma in the contact etch process ET1 is generated in a hydrogen-free (H2) gaseous mixture. This keeps the silicon nitride etch rate low in the contact etch process ET1, which in turn allows the silicon oxide (i.e., the ILD material) to be etched at a faster etch rate than etching silicon nitride (i.e., MCESL and gate dielectric cap material).

[0048] In some embodiments, a photolithography process is performed prior to the contact etching process ET1 to define a desired top-view pattern of gate contact openings O21 and O22. For example, this photolithography process may include: etching the ILD layer 148 (e.g., ...) Figure 15 A photoresist layer is spin-coated onto the photoresist layer (as shown), a post-exposure baking process is performed, and the photoresist layer is developed to form a patterned mask with a top-view pattern of gate contact openings O21 and O22. In some embodiments, the patterning of the photoresist to form the patterned mask can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography.

[0049] exist Figure 16 In some embodiments shown, a gate contact opening O21 having a first lateral dimension (e.g., a first maximum width W21) and a gate contact opening O22 having a second lateral dimension (e.g., a second maximum width W22) are simultaneously formed in the contact etching process ET1. The second maximum width W22 may be greater than the first maximum width W21. The width difference between the gate contact openings O21 and O22 may be intentionally formed according to circuit function and / or design rules. Alternatively, the width difference between the gate contact openings O21 and O22 may be unintentionally formed due to inaccuracies in the contact etching process ET1. For example, one or more of the gate contact openings O21 and O22 may be defined by other features (e.g., a patterned mask formed on the ILD layer 148) and have different dimensions from the original design when the formed gate contact openings O21 and O22 are misaligned relative to the original design. Although the accompanying drawings throughout the specification show an integrated circuit structure 100 including only the narrower gate contact opening O21 and the wider gate contact opening O22, this is merely an example. Depending on the application, the integrated circuit structure 100 can accommodate any number of gate contacts of different sizes.

[0050] It has been observed that the width difference between gate contact openings O21 and O22 affects the result of contact etching process ET1, causing the wider gate contact opening O22 to be deeper than the narrower gate contact opening O21. More specifically, once contact etching process ET1 is complete, the narrower gate contact opening O21 has a depth D21, and the wider gate contact opening O22 has a depth D22 greater than D21. This difference in depth between gate contact openings O21 and O22 is referred to as depth loading caused by the width difference of the gate contact openings.

[0051] Figure 17 A cross-sectional view of the initial stage of a second etching process (also known as an LRM etching process) ET2 according to some embodiments of the present disclosure is shown. Figure 18 A cross-sectional view of the next stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown, as well as Figure 19A A cross-sectional view of the final stage of the LRM etching process ET2 according to some embodiments of the present disclosure is shown. The etching duration of the LRM etching process ET2 is controlled to penetrate (or pass through) the MCESL 146, the resist layer 145, and the gate dielectric cap 142, thereby deepening or extending the gate contact openings O21 and O22 downwards to the gate dielectric cap 138 above the gate structure 130. As a result of the LRM etching process ET2, the gate dielectric cap 138 is exposed at the bottom of the deepened gate contact openings O21 and O22.

[0052] In some embodiments, the LRM etching process ET2 is an anisotropic etching process using different etchants and / or etching conditions than the contact etching process ET1, such as plasma etching (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc.). The etchant and / or etching conditions of the LRM etching process ET2 are selected such that the resist layer 145 (e.g., an oxide-based material) exhibits a slower etching rate than the MCESL 146 and the gate dielectric cap 142 (e.g., a nitride-based material). In other words, in the LRM etching process ET2, the resist layer 145 has higher etch resistance than the MCESL 146 and the gate dielectric cap 142. In this way, the resist layer 145 can slow down the LRM etching process ET2, which in turn slows down the vertical etching rate and thus slows down the depth increase in the gate contact openings O21 and O22 as they reach the resist layer 145. Therefore, the depth difference between the narrower gate contact opening O21 and the wider gate contact opening O22 can be reduced by the resist layer 145. This reduced depth loading thus prevents the formation of a serrated pattern in the wider gate contact opening O22, which in turn reduces the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact). Furthermore, since the resist layer 145 slows down the vertical etch rate of the lower portion of the gate contact openings O21 and O22 but not their lateral etch rate as the gate contact openings O21 and O22 reach the resist layer 145, the LRM etching process ET2 can laterally extend the lower portion of the gate contact openings O21 and O22 during etching the resist layer 145, allowing the bottom width of the gate contact openings O21 and O22 to increase, and the sidewall profiles of the gate contact openings O21 and O22 to become more vertical or steeper than before penetrating the resist layer 145, such as... Figures 17-18 As shown.

[0053] Taking plasma etching as an example of the LRM etching process ET2, it will have Figure 16 The semiconductor substrate 12 with the structure shown is loaded into a plasma tool and exposed to fluorine-containing gases (e.g., CHF3, CF4, C2F2, C4F6, C6) by RF or microwave power. x H y F zA plasma environment is generated in a gaseous mixture of one or more of the following: (x, y, z = 0-9 or similar substances), hydrogen-containing gas (e.g., H2), nitrogen-containing gas (e.g., N2), oxygen-containing gas (e.g., O2), and inert gas (e.g., argon or helium) for a duration sufficient to etch through the resist layer 145 and the underlying gate dielectric cap 142. The pressure of the plasma etching environment is between about 10 mTorr and about 100 mTorr, and the plasma is generated by an RF power between about 50 watts and 1000 watts.

[0054] The plasma generated by the hydrogen-containing gas mixture can etch silicon nitride at a faster etch rate than etching oxide-based materials (e.g., silicon oxide). Therefore, the LRM etching process ET2 using the hydrogen-containing gas mixture etches the oxide-based resist layer 145 at a slower etch rate than the MCESL 146 etching based on nitrides. In this way, the resist layer 145 can slow down the LRM etching process ET2. In some embodiments, the LRM etching ET2 uses a gas mixture of CHF3 and H2, wherein the flow rate ratio of CHF3 to H2 is from about 1:1 to about 1:100. In some embodiments, the LRM etching ET2 uses a gas mixture of CF4 and H2, wherein the flow rate ratio of CF4 to H2 is from about 1:1 to about 1:100. Excessively high H2 gas flow rates can result in excessively fast etch rates when etching through the gate dielectric cap 142, which in turn can lead to non-negligible serrated recesses in the wider gate contact opening O22. Insufficient H2 gas flow rate may result in inadequate etch selectivity between the resist layer 145 and the MCESL 146. In some embodiments, the ratio of the etch rate of the resist layer 145 to the etch rate of the MCESL 146 and / or the gate dielectric cap 142 is in the range of about 5 to about 10.

[0055] In the initial stage of the LRM etching process ET2, such as Figure 17 As shown, the plasma etchant etches the MCESL 146 at a first vertical etch rate A1. In the next stage of the LRM etching process ET2, once the gate contact openings O21 and O22 penetrate the MCESL 146, the resist layer 145 is exposed, and then the plasma etchant etches the resist layer 145 at a second vertical etch rate A2, which is slower than the first vertical etch rate A1, as shown. Figure 18As shown. As a result, the depth difference between the narrower gate contact opening O21 and the wider gate contact opening O22 can be reduced by the etch resist layer 145. Furthermore, the LRM etching process ET2 can laterally expand the lower portions of the gate contact openings O21 and O22 during etching the etch resist layer 145, resulting in gate contact openings O21 and O22 having increased bottom width and more vertical sidewall profiles, such as... Figure 18 As shown. This is a result of the LRM etching process ET2, as... Figure 19A As shown, the gate contact openings O21 and O22 have substantially vertical sidewalls and no tiger-tooth-shaped recesses.

[0056] In some embodiments, the sidewalls of the gate contact openings O21 and O22 extend linearly and vertically through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, the entire thickness of the etch-resistant layer 145, and the entire thickness of the dielectric cap 142, without any change in slope. Figure 19B In some other embodiments shown, since the LRM etching process ET2 can etch the gate dielectric cap 142 at a faster vertical etch rate than etching the resist layer 145, especially when the gate dielectric cap 142 is formed of the same material as MCESL 146 (e.g., silicon nitride), the lower sidewalls of the gate contact openings O21 and O22 can be tapered. In this case, the sidewalls of the gate contact openings O21 and O22 can be more vertical (or steeper) in the upper part of the gate contact openings O21 and O22 than in the lower part, and the slope change of the sidewalls of the gate contact openings O21 and O22 occurs at the interface between the resist layer 145 and the gate dielectric cap 142.

[0057] In such Figure 19AIn some embodiments shown, the wider gate contact opening O22 may extend into the adjacent gate spacer 116, thereby creating a notched corner C22 in the gate spacer 116. This notched corner C22 may be unintentionally formed due to inaccuracies in the contact etching process ET1 and / or the LRM etching process ET2. However, even in this case, the gate spacer 116 will not be unintentionally over-etched to form a serrated recess because the increase in depth in the wider gate contact opening O22 is slowed during the penetration through the resist layer 145, as previously described. Given that the wider gate contact opening O22 does not have a serrated recess or has a negligible serrated recess, the risk of leakage current (e.g., leakage current between the source / drain contacts and the gate contact subsequently formed in the gate contact opening O22) can be reduced. In some embodiments where the gate spacer 116 is a double-layer structure, the notched gate spacer 116 has a stepped top surface structure, wherein the lower step of the stepped top surface structure is the top surface of the first spacer layer 118 recessed by the LRM etching process ET2, and the upper step of the stepped top surface structure is the top surface of the second spacer layer 120 not recessed by the LRM etching process ET2.

[0058] In some embodiments, the contact etching process ET1 and LRM etching process ET2 described above are performed in situ (e.g., using the same plasma etching tool without disrupting the vacuum). In some embodiments, the contact etching process ET1 and LRM etching process ET2 are combined into an in-situ etching process comprising four stages: etching through ILD layer 148 (e.g., silicon oxide), etching through MCESL 146 (e.g., silicon nitride), etching through resist layer 145 (e.g., silicon oxide), and etching through SAC cap 142 (e.g., silicon nitride). In some embodiments, the contact etching process ET1 and LRM etching process ET2 described above are performed out of situ. Contact etching process ET1 comprises two stages: 1) etching through ILD layer 148 (e.g., silicon oxide) and 2) etching through MCESL 146 (e.g., silicon nitride). LRM etching process ET2 comprises two stages: 1) etching through resist layer 145 (e.g., silicon oxide) and 2) etching through SAC cap 142 (e.g., silicon nitride). According to various embodiments of this disclosure, the gas ratios and / or power of these stages may be the same or different. In some embodiments, since the thickness of the etch-resistant layer 145 is no greater than about 50 angstroms, it can be naturally penetrated without concern about etch stopping (i.e., there is no concern that the etch process may be stopped by the etch-resistant layer 145).

[0059] refer to Figure 20AGate contacts 151 and 152 are then formed in gate contact openings O21 and O22 to be electrically connected to the HKMG structure 130 via a gate metal cap 138. By way of example and not limitation, gate contacts 151 and 152 are formed by depositing one or more metal materials to overfill gate contact openings O21 and O22, followed by a CMP process to remove excess metal(s) material outside gate contact openings O21 and O22. As a result of the CMP process, gate contacts 151 and 152 have a top surface substantially coplanar with the ILD layer 148. Gate contacts 151 and 152 may include metal materials such as copper, aluminum, tungsten, or combinations thereof, and may be formed using PVD, CVD, or ALD, etc. In some embodiments, gate contacts 151 and 152 may further include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148, MCESL 146, etch resist layer 145, and / or gate dielectric cap 142 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, or tantalum nitride, and may be formed using PVD, CVD, or ALD, etc.

[0060] In some embodiments, gate contacts 151 and 152 inherit the geometry of gate contact openings O21 and O22, which have vertical sidewall profiles and no serrated profiles. Therefore, gate contacts 151 and 152 also have vertical sidewall profiles and no serrated profiles. More specifically, the sidewalls of gate contacts 151 and 152 extend linearly and vertically through the entire thickness of the ILD layer 148, the entire thickness of the MCESL 146, the entire thickness of the etch resist layer 145, and the entire thickness of the dielectric cap 142, without any change in slope. Figure 20B In some other embodiments shown, since the LRM etching process ET2 can etch the gate dielectric cap 142 at a faster vertical etch rate than the etching resist layer 145, especially when the gate dielectric cap 142 is formed of the same material as MCESL 146 (e.g., silicon nitride), the lower sidewalls of the gate contacts 151 and 152 can be tapered. In this case, the sidewalls of the gate contacts 151 and 152 can be more vertical (or steeper) in the upper part of the gate contacts 151 and 152 than in the lower part, and the slope change of the sidewalls of the gate contacts 151 and 152 can occur at the interface between the etch resist layer 145 and the gate dielectric cap 142.

[0061] Figures 21 to 39BPerspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure are shown. According to some exemplary embodiments, the formed transistors may include p-type transistors (e.g., p-type GAA FETs) and n-type transistors (e.g., n-type FAA FETs). In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional embodiments of the method may be available. Figures 21 to 39B Additional operations are provided before, during, and after the processes shown, and some of these operations can be replaced or eliminated. The order of these operations / processes can be interchangeable.

[0062] Figure 21 , Figure 22 , Figure 23 , Figure 24A , Figure 25A , Figure 26A and Figure 27A These are perspective views of some embodiments of an integrated circuit structure 200 during an intermediate stage of manufacturing. Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figures 28-30 , Figure 31A and Figure 32-39B These are some embodiments of the integrated circuit structure 200 during intermediate stages of manufacturing, along the first tangent (e.g., Figure 24A A cross-sectional view of the tangent XX in the channel, the first tangent being along the length of the channel and perpendicular to the top surface of the substrate. Figure 31B This refers to some embodiments of the integrated circuit structure 200 during intermediate stages of manufacturing, along the second tangent (e.g., Figure 24A A cross-sectional view of the second tangent (YY) in the gate region, which is perpendicular to the length direction of the channel.

[0063] refer to Figure 21An epitaxial stack 220 is formed on substrate 210. In some embodiments, substrate 210 may include silicon (Si). Alternatively, substrate 210 may include germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof), or other suitable semiconductor materials. In some embodiments, substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, substrate 210 may include a buried dielectric layer such as a buried oxide (BOX) layer, which is formed, for example, by a technique called oxygen implantation separation (SIMOX), wafer bonding, SEG, or other suitable methods.

[0064] The epitaxial stack 220 includes epitaxial layers 222 having a first composition, with epitaxial layers 224 having a second composition interposed in these epitaxial layers 222. The first and second compositions may be different. In some embodiments, the epitaxial layer 222 is SiGe, and the epitaxial layer 224 is silicon (Si). However, other embodiments are possible, including those providing first and second compositions with different oxidation rates and / or etch selectivity. In some embodiments, the epitaxial layer 222 comprises SiGe, and in the case where the epitaxial layer 224 comprises Si, the Si oxidation rate of the epitaxial layer 224 is less than the SiGe oxidation rate of the epitaxial layer 222.

[0065] Epitaxial layer 224, or portions thereof, can form one or more nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term encompasses both elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The use of epitaxial layer 224 to define one or more channels of a device is further discussed below.

[0066] Note that the three layers of epitaxial layer 222 and the three layers of epitaxial layer 224 are as follows: Figure 21 The alternating arrangement shown is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 220; the number of layers depends on the desired number of channel regions of the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10.

[0067] As described in more detail below, epitaxial layer 224 can be used as one or more channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 222 can eventually be removed and is used to define the vertical distance between adjacent channel regions(s) of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Therefore, epitaxial layer 222 can also be referred to as a sacrificial layer, and epitaxial layer 224 can also be referred to as a channel layer.

[0068] For example, the epitaxial growth of the layers of epitaxial stack 220 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer (e.g., epitaxial layer 224) comprises the same material as the substrate 210. In some embodiments, the epitaxially grown layers 222 and 224 comprise materials different from the substrate 210. As described above, in at least some examples, epitaxial layer 222 comprises an epitaxially grown silicon-germanium (SiGe) layer, and epitaxial layer 224 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either epitaxial layer 222 or 224 may comprise other materials, such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed, the materials of epitaxial layers 222 and 224 can be selected based on providing different oxidation and / or etch selectivity characteristics. In some embodiments, epitaxial layers 222 and 224 are substantially doped (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 18 cm -3 (the concentration of non-intrinsic dopants), where, for example, no intentional doping is performed during the epitaxial growth process.

[0069] refer to Figure 22A plurality of semiconductor fins 230 extending from the substrate 210 are formed. In various embodiments, each fin 230 includes a substrate portion 212 formed from the substrate 210, and portions of each epitaxial layer of the epitaxial stack including epitaxial layers 222 and 224. The fins 230 can be fabricated using suitable processes including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns, for example, with spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 230 can then be patterned using the remaining spacers or mandrels by etching the initial epitaxial stack 220. This etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0070] exist Figure 21 and Figure 22 In the illustrated embodiment, a hard mask (HM) layer 910 is formed on the epitaxial stack 220 prior to patterning the fin 230. In some embodiments, the HM layer includes an oxide layer 912 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 914 (e.g., a pad nitride layer that may include Si3N4) formed on the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914, and may also act as an etch stop layer for etching the nitride layer 914. In some examples, the HM oxide layer 912 includes thermally grown oxides, oxides deposited by chemical vapor deposition (CVD), and / or oxides deposited by atomic layer deposition (ALD). In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0071] The fins 230 can then be fabricated using appropriate processes including photolithography and etching. The photolithography process may include: forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a patterned mask comprising the photoresist. In some embodiments, patterning the photoresist to form patterned mask elements can be performed using electron beam lithography or extreme ultraviolet (EUV) lithography utilizing light in the EUV region (having wavelengths of, for example, about 1-200 nm). The patterned mask can then be used to protect certain areas of the substrate 210 and the layers formed on those areas, while the etching process forms trenches 202 in the unprotected areas, which penetrate the HM layer 910, through the epitaxial stack 220, and into the substrate 210, thereby leaving a plurality of extended fins 230. The trench 202 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of methods for forming fins on a substrate can also be used, including, for example, defining fin regions (e.g., through a mask or isolation region) and epitaxially growing an epitaxial stack 220 in the form of fins 230.

[0072] Next, as Figure 23 As shown, an STI region 240 is formed between the insertion fins 230. The material and process details of the STI region 240 are similar to those of the previously discussed STI region 14, and therefore will not be repeated for the sake of brevity.

[0073] refer to Figure 24A and Figure 24B A dummy gate structure 250 is formed on the substrate 210 and is at least partially disposed on the fin 230. The portion of the fin 230 located below the dummy gate structure 250 may be referred to as a channel region. The dummy gate structure 250 may also define a source / drain (S / D) region of the fin 230, for example, a region of the fin 230 adjacent to the channel region and located on the opposite side of the channel region.

[0074] The dummy gate formation step first forms a dummy gate dielectric layer 252 over the fin 230. Subsequently, a dummy gate electrode layer 254 and a hard mask are formed over the dummy gate dielectric layer 252. The hard mask may include multiple layers 256 and 258 (e.g., oxide layer 256 and nitride layer 258). The hard mask is then patterned, and subsequently, the dummy gate electrode layer 254 is patterned using the patterned hard mask as an etch mask. In some embodiments, after the dummy gate electrode layer 254 is patterned, the dummy gate dielectric layer 252 is removed from the S / D region of the fin 230. The etching process may include wet etching, dry etching, and / or combinations thereof. The etching process is selected to selectively etch the dummy gate dielectric layer 252 while substantially not etching the fin 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the previously discussed dummy gate dielectric layer 108 and dummy gate electrode layer 110, so they will not be repeated for the sake of brevity.

[0075] After the dummy gate structure 250 is formed, gate spacers 260 are formed on the sidewalls of the dummy gate structure 250. For example, a spacer material layer is deposited on the substrate 210. The spacer material layer may be a conformal layer, which is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, the spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structure 250. The spacer material layer 260 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the spacer material layer 260 includes multiple layers, such as a first spacer layer 262 and a second spacer layer 264 formed on the first spacer layer 262 (in Figure 24B (As shown in the diagram). For example, spacer material layer 260 can be formed by depositing a dielectric material on gate structure 250 using a suitable deposition process. An anisotropic etching process is then performed on the deposited spacer material layer 260 to expose portions of fin 230 not covered by dummy gate structure 250 (e.g., in the source / drain regions of fin 230). The portion of the spacer material layer directly above the dummy gate structure 250 can be completely removed by this anisotropic etching process. The portions of the spacer material layer on the sidewalls of the dummy gate structure 250 can be retained, forming gate sidewall spacers, which are referred to as gate spacers 260 for simplicity. It should be noted that although gate spacers 260 are... Figure 24B The cross-sectional view shows a multi-layered structure, but for simplicity, they are... Figure 24A It is shown as a single-layer structure in the perspective view.

[0076] Next, as Figure 25A and Figure 25B As shown, a recess R6 is formed in the semiconductor fin 230 and between the corresponding dummy gate structures 250 by etching the lateral extension of the semiconductor fin 230 beyond the exposed portion of the gate spacer 260 (e.g., in the source / drain region of the fin 230) using, for example, an anisotropic etching process. This anisotropic etching process uses the dummy gate structures 250 and the gate spacer 260 as etching masks. After this anisotropic etching, the end faces of the sacrificial layer 222 and the channel layer 224 are aligned with the corresponding outermost walls of the gate spacer 260 due to the anisotropic etching. In some embodiments, this anisotropic etching can be performed by dry chemical etching utilizing a plasma source and reactive gases. The plasma source can be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactant gas can be, for example, a fluorine-based gas (e.g., SF6, CH2F2, CH3F, CHF3, etc.), a chlorine-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or a combination of the foregoing.

[0077] Next, in Figure 26A and Figure 26B In this process, the sacrificial layer 222 is recessed laterally or horizontally using a suitable etching technique to form lateral recesses R7, each of which is vertically located between the respective channel layers 224. This step can be performed using a selective etching process. By way of example and not limitation, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective etching of the sacrificial layer 222. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture), which etches SiGe at a faster etch rate than etching Si. In some embodiments, selective etching includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 is not significantly etched by the process of laterally recessed sacrificial layer 222. As a result, the channel layer 224 extends laterally beyond the opposite end face of sacrificial layer 222.

[0078] exist Figure 27A and Figure 27B In the middle, an internal spacer material layer 270 is formed to fill the spacer material layer 270 formed by the reference above. Figure 26Aand Figure 26B The recess R7 left by the lateral etching of the sacrificial layer 222 is discussed. The internal spacer material layer 270 can be a low-k dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and the internal spacer material layer 270 can be formed by a suitable deposition method such as ALD. After the deposition of the internal spacer material layer 270, an anisotropic etching process can be performed to trim the deposited internal spacer material 270 so that only a portion of the deposited internal spacer material 270 filling the recess R7 left by the lateral etching of the sacrificial layer 222 is retained. After the trimming process, for simplicity, the remaining portion of the deposited internal spacer material is referred to as the internal spacer 270. The internal spacer 270 is used to isolate the metal gate from the source / drain epitaxial structure formed in subsequent processing. Figure 27A and Figure 27B In the example, the outermost wall of the inner spacer 270 is substantially aligned with the sidewall of the channel layer 224.

[0079] exist Figure 28 In this process, a source / drain epitaxial structure 280 is formed on the source / drain region S / D of the semiconductor fin 230. The source / drain epitaxial structure 280 can be formed by performing an epitaxial growth process that provides epitaxial material on the fin 230. During this epitaxial growth process, the gate sidewall spacer 260 and the internal spacer 270 confine the source / drain epitaxial structure 280 to the source / drain region S / D. The material and process details of the source / drain epitaxial structure 280 of the GAA FET are similar to those of the previously discussed FinFET source / drain epitaxial structure 122, and therefore will not be repeated for the sake of brevity.

[0080] exist Figure 29 In this configuration, an interlayer dielectric (ILD) layer 310 is formed on the substrate 210. In some embodiments, a contact etch stop layer (CESL) may be optionally formed prior to the formation of the ILD layer 310. In some examples, a planarization process may be performed after depositing the ILD layer 310 to remove excess material from the ILD layer 310. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes the portion of the ILD layer 310 (and the CESL layer, if present) above the dummy gate structure 250 and planarizes the top surface of the integrated circuit structure 200. In some embodiments, the CMP process also removes hard mask layers 256, 258 (e.g., Figure 28 (as shown) and exposes the dummy gate electrode layer 254.

[0081] Subsequently, the dummy gate structure 250 is removed first, and then the sacrificial layer 222 is removed. Figure 30The resulting structure is illustrated. In some embodiments, the dummy gate structure 250 is removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the dummy gate structure 250 at a faster etch rate than etching other materials (e.g., gate sidewall spacers 260 and / or ILD layer 310), thereby forming a gate trench GT2 between the respective gate sidewall spacers 260, and exposing the sacrificial layer 222 in the gate trench GT2. Subsequently, the sacrificial layer 222 in the gate trench GT2 is removed using another selective etching process that etches the sacrificial layer 222 at a faster etch rate than etching the channel layer 224, thereby forming an opening O6 between adjacent channel layers 224. In this way, the channel layer 224 becomes a nanosheet suspended above the substrate 210 and located between the source / drain epitaxial structures 280. This step is also referred to as a channel release process. In this intermediate processing step, the openings O6 between the nanosheets 224 can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the nanosheets 224 can be interchangeably referred to as nanowires, nanoplates, and nanorings depending on their geometry. For example, in some other embodiments, the channel layer 224 can be trimmed into a substantially circular shape (i.e., cylindrical) due to a selective etching process used to completely remove the sacrificial layer 222. In this case, the resulting channel layer 224 can be referred to as nanowires.

[0082] In some embodiments, the sacrificial layer 222 is removed using a selective wet etching process. In some embodiments, the sacrificial layer 222 is SiGe and the channel layer 224 is silicon, thereby allowing selective removal of the sacrificial layer 222. In some embodiments, the selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by O3 cleaning, then SiGeO x Removed by an etchant such as NH4OH, which selectively etches SiGeO at a faster etch rate than Si. x Furthermore, because the oxidation rate of Si is much lower than that of SiGe (sometimes as low as 1 / 30th), the channel layer 224 may not be significantly etched by the channel release process. It can be noted that the channel release step and the preceding lateral recess sacrificial layer step (such as...) Figure 26A and Figure 26BBoth steps (as shown) use a selective etching process to etch SiGe at a faster etch rate than etching Si, so in some embodiments, the two steps can use the same etchant chemicals. In this case, the etch time / duration of the channel release step is longer than the etch time / duration of the previous lateral recess sacrificial layer step in order to completely remove the sacrificial SiGe layer.

[0083] exist Figure 31A and Figure 31B In this configuration, replacement gate structures 320 are respectively formed in the gate trench GT2 to surround each nanosheet 224 suspended in the gate trench GT2. The gate structure 320 can be the final gate of a GAA FET. The final gate structure can be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each gate structure 320 forms a gate associated with a multi-channel provided by a plurality of nanosheets 224. For example, the high-k / metal gate structure 320 is formed in an opening O6 provided by releasing the nanosheets 224 (e.g., ...). Figure 30 (As shown). In various embodiments, the high-k / metal gate structure 320 includes: a gate dielectric layer 322 formed around the nanosheet 224, a work function metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the work function metal layer 324 and filling the remaining portion of the gate trench GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer located above the interface layer. As used and described herein, the high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant (~3.9) of thermally heated silicon oxide). The work function metal layer 324 and / or the fill metal layer 326 used within the high-k / metal gate structure 320 may include a metal, a metal alloy, or a metal silicide. The formation of the high-k / metal gate structure 320 may include deposition for forming various gate materials, one or more liner layers, and one or more CMP processes for removing excess gate material. As shown in the figure taken along the longitudinal axis of the high-k / metal gate structure 320 Figure 31B As shown in the cross-sectional view, the high-k / metal gate structure 320 surrounds each nanosheet 224 and is therefore referred to as the gate of the GAA FET. The material and process details of the gate structure 320 of the GAA FET are similar to those of the gate structure 130 of the FinFET, and therefore will not be repeated for the sake of brevity.

[0084] exist Figure 32In this process, an etch-back process is performed to replace the gate structure 320 and the gate spacer 260, thereby forming a recess on the etch-back gate structure 320 and the etch-back gate spacer 260. In some embodiments, because the material replacing the gate structure 320 has a different etch selectivity than the gate spacer 260, the top surface of the replacing gate structure 320 can be at a different level than the top surface of the gate spacer 260. For example, in... Figure 32 In the illustrated embodiment, the top surface of the replacement gate structure 320 is lower than the top surface of the gate spacer 260. However, in some other embodiments, the top surface of the replacement gate structure 320 may be flush with or higher than the top surface of the gate spacer 260.

[0085] Then, a gate metal cap 330 is optionally formed on top of the etched-back replacement gate structure 320 using a suitable process such as CVD or ALD. By way of example and not limitation, the metal cap 330 may be a substantially fluorine-free tungsten (FFW) film with less than 5 atomic percent fluorine impurities and more than 3 atomic percent chlorine impurities. Process details regarding the formation of the FFW have been previously discussed with respect to the gate metal cap 138, and will therefore be repeated for the sake of brevity.

[0086] exist Figure 33 In this configuration, a gate dielectric cap 340 is formed over the gate metal cap 330 and the gate spacer 260. Because the top surface of the gate metal cap 330 is lower than the top surface of the gate spacer 260, each gate dielectric cap 340 has a stepped bottom surface, with the lower step contacting the top surface of the gate metal cap 330 and the upper step contacting the top surface of the gate spacer 260. The material and process details for the dielectric caps are similar to those for the previously discussed gate dielectric cap 142, and therefore will not be repeated for simplicity.

[0087] exist Figure 34In this process, source / drain contacts 350 extending through the ILD layer 310 are formed. By way of example and not limitation, the formation of the source / drain contacts 350 includes: performing one or more etching processes to form contact openings extending through the ILD layer 310 to expose the source / drain epitaxial structure 280, depositing one or more metal materials to overfill the contact openings, and then performing a CMP process to remove excess metal material located outside the contact openings. In some embodiments, the one or more etching processes are selective etching, which etches the ILD layer 310 at a faster etch rate than etching the gate dielectric cap 340 and the gate spacer 260. As a result, this selective etching is performed using the gate dielectric cap 340 and the gate spacer 260 as etch masks, such that the contact openings, and therefore the source / drain contacts 350, are formed to be self-aligned with the source / drain epitaxial structure 280 without the use of additional photolithography processes. In this case, the source / drain contact 350 may be referred to as a self-aligned contact (SAC), and the gate dielectric cap 340 that allows the formation of the self-aligned contact 350 may be referred to as the SAC cap 340.

[0088] exist Figure 35 In this process, an etch resist layer 352 is formed over the gate dielectric cap 340 and the source / drain contacts 350 using an ALD process, a PECVD process, and / or other suitable deposition processes. In some embodiments, the etch resist layer 352 is made of a different material than that of the gate dielectric cap 340 and the subsequently formed MCESL. For example, when the gate dielectric cap 340 and the subsequently formed MCESL are made of the same material (e.g., silicon nitride), the etch resist layer 352 is made of an oxide-based material, such as silicon oxide, TEOS oxide, silicon-rich silicon oxide, or other suitable oxide-based dielectric materials. Due to the material difference, the etch resist layer 352 has a different etch selectivity than the subsequently formed MCESL and the gate dielectric cap 340. As a result, the etch resist layer 352 can have a slower etch rate in the subsequent LRM etch process than both the gate dielectric cap 340 and the MCESL, which allows for a slower LRM etch process, as will be discussed in more detail below.

[0089] In some embodiments, the resist layer 352 has a thickness T5. In some embodiments, for the 3nm technology node, the thickness T5 ranges from about 1 angstrom to about 50 angstroms. In some other embodiments, the ratio of thickness T5 to the maximum thickness T6 of the gate dielectric cap 340 ranges from about 3:100 to about 60:100. If the thickness is too small than T5 / T6, the resist layer 352 may be too thin to slow down the subsequent LRM etching process. If the thickness is too large than T5 / T6, the resist layer 352 may be too thick to be penetrated within the expected duration. For other technology nodes, such as the 20nm, 16nm, 10nm, 7nm, and / or 5nm nodes, the thickness T5 of the resist layer 352 can range from about 1nm to about 20nm.

[0090] exist Figure 36 In this process, after an etch resist layer 352 has been formed on the gate dielectric cap 340, an MCESL 360 is subsequently deposited on the etch resist layer 352. Then, another ILD layer 370 is deposited on the MCESL 360. In some embodiments, both the gate dielectric cap 340 and the MCESL 360 are nitride-based materials (e.g., silicon nitride), and both the etch resist layer 352 and the ILD layer 370 are oxide-based materials (e.g., silicon oxide), thus the ILD layer 370 and the etch resist layer 352 have different etch selectivity than both the gate dielectric cap 340 and the MCESL 360. In some embodiments, the thickness T7 of the MCESL 360 is greater than the thickness T5 of the etch resist layer 352. For example, the thickness T7 of the MCESL 360 is in the range of about 3 nm to about 20 nm. In some embodiments, the thickness T8 of the ILD layer 370 is greater than the thickness T7 of the MCESL 360 and the thickness T5 of the etch resist layer 352. In some other embodiments, the thickness T8 of the ILD layer 370 is greater than the combined thickness of the MCESL 360 and the etch-resistant layer 352. For example, the thickness T8 of the ILD layer 370 is in the range of about 3 nm to about 100 nm.

[0091] exist Figure 37 In this process, the ILD layer 370 is patterned using a first etching process (also known as a contact etching process) ET3 to form gate contact openings O41 and O42 extending through the ILD layer 370. In some embodiments, the contact etching process ET3 is an anisotropic etching process, such as plasma etching. The process details of the contact etching process ET3 are similar to those of the previously discussed contact etching process ET1, and therefore will not be repeated for the sake of brevity.

[0092] exist Figure 37In some embodiments shown, a gate contact opening O41 having a first lateral dimension (e.g., a first maximum width W41) and a gate contact opening O42 having a second lateral dimension (e.g., a second maximum width W42) are simultaneously formed in the contact etching process ET3. The second maximum width W42 may be greater than the first maximum width W41. The width difference between the gate contact openings O41 and O42 may be intentionally formed according to circuit function and / or design rules. Alternatively, the width difference between the gate contact openings O41 and O42 may be unintentionally formed due to inaccuracies in the contact etching process ET3, as previously discussed with respect to gate contact openings O21 and O22. This difference in the width of the gate contact openings O41 and O42 results in the wider gate contact opening O42 being deeper than the narrower gate contact opening O41.

[0093] exist Figure 38A In this process, LRM etching process ET4 is performed to penetrate MCESL 360, resist layer 352, and gate dielectric cap 340, thereby deepening the gate contact openings O41 and O42 downwards to the gate metal cap 330 above the gate structure 320. As a result of LRM etching process ET4, the gate metal cap 330 is exposed at the bottom of the deepened gate contact openings O41 and O42. The etchant and / or etching conditions of LRM etching process ET4 are selected in such a way that resist layer 352 exhibits a slower etching rate than MCESL 360 and gate dielectric cap 340. Process details of LRM etching process ET4 have been previously discussed with respect to LRM etching process ET2, and therefore will not be repeated for the sake of brevity.

[0094] Due to the etch selectivity between the resist layer 352 and the MCESL 360, the resist layer 352 can slow down the LRM etching process ET4 when the MCESL 360 is punched through. This, in turn, slows down the vertical etch rate and depth increase in the gate contact openings O41 and O42 as they reach the resist layer 352. Therefore, the depth difference between the narrower gate contact opening O41 and the wider gate contact opening O42 can be reduced by the resist layer 352. This reduced depth loading thus prevents the formation of a serrated pattern in the wider gate contact opening O42, which in turn reduces the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact). Furthermore, since the etch resist layer 352 slows down the vertical etch rate but not the lateral etch rate when the gate contact openings O41 and O42 reach the etch resist layer 352, the LRM etching process ET4 can laterally expand the lower part of the gate contact openings O41 and O42 during the etching of the etch resist layer 352, thereby increasing the bottom width of the gate contact openings O41 and O42, and making the gate contact openings O41 and O42 more vertical than before the etch resist layer 352 was penetrated.

[0095] In some embodiments, the sidewalls of the gate contact openings O41 and O42 extend linearly and vertically through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, the entire thickness of the etch resist layer 352, and the entire thickness of the gate dielectric cap 340, without any change in slope. Figure 38B In some other embodiments shown, since the LRM etching process ET4 can etch the gate dielectric cap 340 at a faster vertical etch rate than etching the etch resist layer 352, especially when the gate dielectric cap 340 is formed of the same material as MCESL 360 (e.g., silicon nitride), the lower sidewalls of the gate contact openings O41 and O42 can be tapered. In this case, the sidewalls of the gate contact openings O41 and O42 can be more vertical (or steeper) in the upper part of the gate contact openings O41 and O42 than in the lower part, and the slope change of the sidewalls of the gate contact openings O41 and O42 can occur at the interface between the etch resist layer 352 and the gate dielectric cap 340.

[0096] In such Figure 38AIn some embodiments shown, the wider gate contact opening O42 may extend into the adjacent gate spacer 260, thereby creating a notched corner C42 in the gate spacer 260. This notched corner C42 may be unintentionally formed due to inaccuracies in the contact etching process ET3 and / or the LRM etching process ET4. However, even in this case, the gate spacer 260 will not be unintentionally over-etched to form a serrated recess because the increase in depth in the wider gate contact opening O42 is slowed down during the penetration through the resist layer 352, as previously described. Given that the wider gate contact opening O42 does not have a serrated recess or has a negligible serrated recess, the risk of leakage current (e.g., leakage current between the source / drain contacts and the gate contact subsequently formed in the gate contact opening O42) can be reduced. In some embodiments where the gate spacer 260 is a dual-layer structure, the notched gate spacer 260 has a stepped top surface structure, wherein the lower step of the stepped top surface structure is the top surface of the first spacer layer 262 recessed by the LRM etching process ET4, and the upper step of the stepped top surface structure is the top surface of the second spacer layer 264 not recessed by the LRM etching process ET4.

[0097] exist Figure 39A In the process, narrower gate contacts 381 and wider gate contacts 382 are formed in the narrower gate contact opening O41 and wider gate contact opening O42, respectively, to be electrically connected to the HKMG structure 320 via the gate metal cap 330. The material and process details of gate contacts 381 and 382 are similar to those of gate contacts 151 and 152 discussed earlier, and therefore will not be repeated for the sake of brevity.

[0098] In some embodiments, gate contacts 381 and 382 inherit the geometry of gate contact openings O41 and O42, which have vertical sidewall profiles and no serrated profiles. Therefore, gate contacts 381 and 382 also have vertical sidewall profiles and no serrated profiles. More specifically, the sidewalls of gate contacts 381 and 382 extend linearly and vertically through the entire thickness of the ILD layer 370, the entire thickness of the MCESL 360, the entire thickness of the etch resist layer 352, and the entire thickness of the gate dielectric cap 340, without any change in slope. Figure 39BIn some other embodiments shown, since the LRM etching process ET4 can etch the gate dielectric cap 340 at a faster vertical etch rate than etching the resist layer 352, especially when the gate dielectric cap 340 is formed of the same material as MCESL 360 (e.g., silicon nitride), the lower sidewalls of the gate contacts 381 and 382 can be tapered. In this case, the sidewalls of the gate contacts 381 and 382 can be more vertical (or steeper) in the upper part of the gate contacts 381 and 382 than in the lower part, and the slope change of the sidewalls of the gate contacts 381 and 382 can occur at the interface between the resist layer 352 and the gate dielectric cap 340.

[0099] Based on the above discussion, it can be seen that this disclosure provides advantages in various embodiments. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no particular advantage is necessary for all embodiments. One advantage is that the depth loading problem of the gate contact opening can be mitigated. Another advantage is that the gate contact opening can have a more vertical sidewall profile. Another advantage is that the gate contact resistance can be reduced because the bottom surface area of ​​a gate contact with a vertical sidewall profile can be increased compared to a tapered gate contact. Another advantage is that the risk of leakage current (e.g., leakage current from the gate contact to the source / drain contact) can be reduced.

[0100] In some embodiments, a method includes: forming a gate structure on a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap on the etched-back gate structure; depositing an etch resist layer on the gate dielectric cap; depositing a contact etch stop layer on the etch resist layer and depositing an interlayer dielectric (ILD) layer on the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating before reaching the etch resist layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch resist layer at an etch rate slower than that used to etch the contact etch stop layer; and forming a gate contact in the deepened gate contact opening. In some embodiments, the second etching process etches the gate dielectric cap at an etch rate faster than that used to etch the etch resist layer. In some embodiments, the gate dielectric cap is formed of the same material as the contact etch stop layer. In some embodiments, the gate dielectric cap and the contact etch stop layer are nitride-based. In some embodiments, the etch resist layer is oxide-based. In some embodiments, the thickness of the etch resist layer is less than the thickness of the contact etch stop layer. In some embodiments, the thickness of the etch resist layer is less than the maximum thickness of the gate dielectric cap. In some embodiments, the thickness of the etch-resistant layer ranges from about 1 angstrom to about 50 angstroms. In some embodiments, the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gaseous mixture. In some embodiments, the second etching process is a plasma etching process that uses plasma generated from a hydrogen-containing gaseous mixture. In some embodiments, the hydrogen-containing gaseous mixture is a mixture of a fluorine-containing gas and hydrogen. In some embodiments, the fluorine-containing gas is CHF3 gas, CF4 gas, or C. x H y F z A gas, or a combination thereof, wherein x, y, and z are greater than zero.

[0101] In some embodiments, a method includes: forming a first gate dielectric cap over a first gate structure and forming a second gate dielectric cap over a second gate structure; depositing an etch resist layer over the first and second gate dielectric caps; depositing a contact etch stop layer over the etch resist layer and depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a first gate contact opening and a second gate contact opening extending through the ILD layer, wherein the width of the first gate contact opening is smaller than the width of the second gate contact opening; performing a second etching process to extend the first and second gate contact openings toward the first and second gate structures, wherein after the second etching process etches through the etch resist layer, the sidewall profile of the first gate contact opening becomes more perpendicular than before etching the etch resist layer; and after performing the second etching process, forming a first gate contact in the first gate contact opening and a second gate contact in the second gate contact opening. In some embodiments, the first etching process causes the depth of the first gate contact opening to be smaller than the depth of the second gate contact opening. In some embodiments, after the second etching process etches through the resist layer, the depth difference between the first gate contact opening and the second gate contact opening becomes smaller than before the second etching process was performed. In some embodiments, the second etching process uses a gas mixture with hydrogen, and the first etching process does not contain hydrogen.

[0102] In some embodiments, a device includes: a plurality of source / drain epitaxial structures on a substrate; a plurality of source / drain contacts, each on the plurality of source / drain epitaxial structures; a gate structure laterally located between the plurality of source / drain contacts; a gate dielectric cap on the gate structure with its bottom surface lower than the top surface of the source / drain contacts; an oxide-based etch resist layer on the gate dielectric cap; a nitride-based etch stop layer on the oxide-based etch resist layer; an interlayer dielectric (ILD) layer on the nitride-based etch stop layer; and gate contacts extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch resist layer, and the gate dielectric cap for electrical connection to the gate structure. In some embodiments, the oxide-based etch resist layer is thinner than the nitride-based etch stop layer. In some embodiments, the oxide-based etch resist layer is thinner than the gate dielectric cap.

[0103] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0104] Example 1. A method of forming a semiconductor device, comprising:

[0105] A gate structure is formed on a semiconductor substrate;

[0106] Etching back the gate structure;

[0107] A gate dielectric cap is formed on the gate structure after being etched back;

[0108] An etch-resistant layer is deposited on the gate dielectric cap;

[0109] A contact etch stop layer is deposited on the etch-resistant layer, and an interlayer dielectric (ILD) layer is deposited on the contact etch stop layer.

[0110] A first etching process is performed to form a gate contact opening that extends through the ILD layer and terminates before reaching the etch-resistant layer;

[0111] A second etching process is performed to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than that used to etch the contact etch stop layer; and

[0112] A gate contact is formed in the deepened gate contact opening.

[0113] Example 2. The method according to Example 1, wherein the second etching process etches the gate dielectric cap at an etching rate faster than etching the etch-resistant layer.

[0114] Example 3. The method according to Example 1, wherein the gate dielectric cap is formed of the same material as the contact etch stop layer.

[0115] Example 4. The method according to Example 1, wherein the gate dielectric cap and the contact etch stop layer are nitride-based.

[0116] Example 5. The method according to Example 1, wherein the etch-resistant layer is oxide-based.

[0117] Example 6. The method according to Example 1, wherein the thickness of the etch-resistant layer is less than the thickness of the contact etch-stop layer.

[0118] Example 7. The method according to Example 1, wherein the thickness of the etch-resistant layer is less than the maximum thickness of the gate dielectric cap.

[0119] Example 8. The method according to Example 1, wherein the thickness of the etch-resistant layer is in the range of about 1 angstrom to about 50 angstroms.

[0120] Example 9. The method according to Example 1, wherein the etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD).

[0121] Example 10. The method according to Example 1, wherein the first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gaseous mixture.

[0122] Example 11. According to the method of Example 1, wherein the second etching process is a plasma etching process that uses plasma generated from a hydrogen-containing gaseous mixture.

[0123] Example 12. The method according to Example 11, wherein the hydrogen-containing gaseous mixture is a mixture of fluorine-containing gas and hydrogen.

[0124] Example 13. The method according to Example 12, wherein the fluorine-containing gas is CHF3 gas, CF4 gas, or C x H y F z Gases, or combinations thereof, wherein x, y, and z are greater than zero.

[0125] Example 14. A method of forming a semiconductor device, comprising:

[0126] A first gate dielectric cap is formed on the first gate structure, and a second gate dielectric cap is formed on the second gate structure.

[0127] An etch-resistant layer is deposited on the first gate dielectric cap and the second gate dielectric cap;

[0128] A contact etch stop layer is deposited on the etch-resistant layer, and an interlayer dielectric (ILD) layer is deposited on the contact etch stop layer.

[0129] A first etching process is performed to form a first gate contact opening and a second gate contact opening extending through the ILD layer, wherein the width of the first gate contact opening is smaller than the width of the second gate contact opening;

[0130] A second etching process is performed to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, wherein, after the second etching process etches through the etch resist layer, the sidewall profile of the first gate contact opening becomes more perpendicular than before etching the etch resist layer; and

[0131] After performing the second etching process, a first gate contact is formed in the first gate contact opening, and a second gate contact is formed in the second gate contact opening.

[0132] Example 15. The method according to Example 14, wherein the first etching process causes the depth of the first gate contact opening to be less than the depth of the second gate contact opening.

[0133] Example 16. The method according to Example 14, wherein, after the second etching process etches through the resist layer, the depth difference between the first gate contact opening and the second gate contact opening becomes smaller than before the second etching process is performed.

[0134] Example 17. The method according to Example 14, wherein the second etching process uses a gas mixture with hydrogen, and the first etching process does not contain the hydrogen.

[0135] Example 18. A semiconductor device comprising:

[0136] Multiple source / drain epitaxial structures are located on the substrate;

[0137] Multiple source / drain contacts are each located on the multiple source / drain epitaxial structures;

[0138] A gate structure is laterally located between the plurality of source / drain contacts;

[0139] A gate dielectric cap is located above the gate structure and its bottom surface is lower than the top surface of the plurality of source / drain contacts;

[0140] An oxide-based etch-resistant layer is located on top of the gate dielectric cap;

[0141] A nitride-based etch stop layer is located above the oxide-based etch resist layer;

[0142] An interlayer dielectric (ILD) layer is located above the nitride-based etch stop layer; and

[0143] A gate contact extends through the ILD layer, the nitride-based etch stop layer, the oxy-based etch resist layer, and the gate dielectric cap to be electrically connected to the gate structure.

[0144] Example 19. The device according to Example 18, wherein the oxygen-based etch-resistant layer is thinner than the nitride-based etch-stop layer.

[0145] Example 20. The device according to Example 18, wherein the oxy-oxide etch-resistant layer is thinner than the gate dielectric cap.

Claims

1. A method for forming a semiconductor device, comprising: A gate structure is formed on a semiconductor substrate; Etching back the gate structure; A gate dielectric cap is formed on the gate structure after back etching; An etch-resistant layer is deposited on the gate dielectric cap; A contact etch stop layer is deposited on the etch-resistant layer, and an interlayer dielectric (ILD) layer is deposited on the contact etch stop layer; A first etching process is performed to form a gate contact opening that extends through the ILD layer and terminates before reaching the etch-resistant layer; A second etching process is performed to deepen the gate contact opening and extend it through the etch resist layer and the gate dielectric cap, wherein the second etching process etches the etch resist layer at a slower etching rate than etching the contact etch stop layer and the gate dielectric cap; as well as A gate contact is formed in the deepened gate contact opening.

2. The method according to claim 1, wherein, The gate dielectric cap is formed of the same material as the contact etch stop layer.

3. The method according to claim 1, wherein, The gate dielectric cap and the contact etch stop layer are nitride-based.

4. The method according to claim 1, wherein, The etch-resistant layer is oxide-based.

5. The method according to claim 1, wherein, The thickness of the anti-etching layer is less than the thickness of the contact etch stop layer.

6. The method according to claim 1, wherein, The thickness of the etch-resistant layer is less than the maximum thickness of the gate dielectric cap.

7. The method according to claim 1, wherein, The thickness of the etch-resistant layer is in the range of 1 angstrom to 50 angstroms.

8. The method according to claim 1, wherein, The etch-resistant layer is deposited using atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD).

9. The method according to claim 1, wherein, The first etching process is a plasma etching process that uses plasma generated from a hydrogen-free gaseous mixture.

10. The method according to claim 1, wherein, The second etching process is a plasma etching process that uses plasma generated from a hydrogen-containing gaseous mixture.

11. The method according to claim 10, wherein, The hydrogen-containing gaseous mixture is a mixture of fluorine-containing gas and hydrogen.

12. The method according to claim 11, wherein, The fluorine-containing gas is C. x H y F z A gas, wherein x, y, and z are greater than zero.

13. The method according to claim 11, wherein, The fluorine-containing gas is CHF3 gas, CF4 gas, or a combination thereof.

14. A method of forming a semiconductor device, comprising: A first gate dielectric cap is formed on the first gate structure, and a second gate dielectric cap is formed on the second gate structure. An etch-resistant layer is deposited on the first gate dielectric cap and the second gate dielectric cap; A contact etch stop layer is deposited on the etch-resistant layer, and an interlayer dielectric (ILD) layer is deposited on the contact etch stop layer; A first etching process is performed to form a first gate contact opening and a second gate contact opening extending through the ILD layer, wherein the width of the first gate contact opening is smaller than the width of the second gate contact opening; A second etching process is performed to extend the first gate contact opening and the second gate contact opening toward the first gate structure and the second gate structure, the second etching process etching the etch resist layer at a slower etch rate than etching the contact etch stop layer, the first gate dielectric cap, and the second gate dielectric cap, wherein after the second etching process etches through the etch resist layer, the sidewall profile of the first gate contact opening becomes more perpendicular than before etching the etch resist layer; and After performing the second etching process, a first gate contact is formed in the first gate contact opening, and a second gate contact is formed in the second gate contact opening.

15. The method according to claim 14, wherein, The first etching process makes the depth of the first gate contact opening smaller than the depth of the second gate contact opening.

16. The method of claim 14, wherein, After the second etching process etches through the resist layer, the depth difference between the first gate contact opening and the second gate contact opening becomes smaller than before the second etching process was performed.

17. The method of claim 14, wherein, The second etching process uses a gas mixture with hydrogen, while the first etching process does not contain the hydrogen.

18. A semiconductor device, comprising: Multiple source / drain epitaxial structures are located on the substrate; Multiple source / drain contacts are each located on the multiple source / drain epitaxial structures; A gate structure is laterally located between the plurality of source / drain contacts; A gate dielectric cap is located above the gate structure and its bottom surface is lower than the top surface of the plurality of source / drain contacts; An oxide-based etch-resistant layer is located above the gate dielectric cap and the plurality of source / drain contacts, wherein the bottom surface of the oxide-based etch-resistant layer contacts the top surface of the plurality of source / drain contacts. A nitride-based etch stop layer is located above the oxide-based etch resist layer; An interlayer dielectric (ILD) layer is located above the nitride-based etch stop layer; and A gate contact extends through the ILD layer, the nitride-based etch stop layer, the oxide-based etch resist layer, and the gate dielectric cap to be electrically connected to the gate structure, wherein the bottom surface of the gate contact is entirely lower than the top surfaces of the gate dielectric cap and the plurality of source / drain contacts. The oxide-based etch-resistant layer has a slower etch rate than the nitride-based etch-stop layer and the gate dielectric cap.

19. The device according to claim 18, wherein, The oxide-based etch-resistant layer is thinner than the nitride-based etch-stop layer.

20. The device according to claim 18, wherein, The oxide-based etch-resistant layer is thinner than the gate dielectric cap.

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