Semiconductor device

Abstract

The present application provides a semiconductor device, in the case of integrating an output stage element and a detection element for detecting a main current flowing through the output stage element into the same semiconductor chip, the chip area can be reduced. The output stage element and the detection element have: a channel formation region provided at an upper portion of a drift region; a main electrode region provided at an upper portion of the channel formation region; and a gate electrode buried through a gate insulating film into a first trench which is in contact with the main electrode region, the channel formation region, and the drift region, wherein, in a planar pattern, a plurality of first trenches common to the output stage element and the detection element extend, a plurality of second trenches which are orthogonal to the first trenches and extend parallel to each other sandwich the detection element, thereby separating the channel formation region of the output stage element from the channel formation region of the detection element.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a power semiconductor integrated circuit (power IC). Background Technology

[0002] Power semiconductor devices such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) sometimes include sensing elements. These sensing elements detect the main current of the main device, and their structure is largely the same as that of the main device. Furthermore, for the purposes of high reliability, miniaturization, and low cost, a power IC has been proposed that monolithically integrates (co-loads) the vertical MOS transistor (hereinafter referred to as the "output stage device") and the control circuitry used to control the output stage device onto the same semiconductor chip. For example, automotive power ICs known as intelligent power switches (IPS) can be cited.

[0003] The power IC, which includes output stage components, also integrates a vertical transistor (hereinafter referred to as a "detection element") as a sensing element. This sensing element is used to detect the main current flowing through the output stage components, which are the main components. By processing the detection results of the detection element by the control circuit, various functions of the power IC, such as protection and status detection, are realized (see Patent Documents 1 and 2).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 5481030

[0007] Patent Document 2: Japanese Patent No. 5772842 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] The sensing element has the same structure as the output stage element, but the active area (unit area) is different. A current proportional to the main current flowing through the output stage element is passed to the sensing element. The main current flowing through the output stage element is calculated based on the proportionality coefficient (sensing ratio) and information such as the potential or current obtained from the sensing element. Typically, control is performed by applying the same potential to the gates of both the output stage element and the sensing element to make the sensing ratio approximately equal to the active area ratio.

[0010] Generally, the sensing element and the output stage element are configured separately. In this case, the gate of the sensing element and the gate of the output stage element are connected by metal wiring. However, to improve the area efficiency of the chip, it is preferable to bury the sensing element inside the output stage element, making full use of the fact that the sensing element and the output stage element have the same structure to maximize component sharing. For example, sharing the gate of the sensing element and the output stage element can reduce the metal wiring area.

[0011] In the case where the detection element is buried inside the output stage element, a structure is needed between the detection element and the output stage element to separate the channel formation area of ​​the detection element from the channel formation area of ​​the output stage element, as well as a terminal structure to ensure withstand voltage. Therefore, the chip area reduction effect is small.

[0012] In view of the above problems, the object of the present invention is to provide a semiconductor device that can reduce the chip area when integrating the output stage components and the detection element for detecting the main current flowing through the output stage components into the same semiconductor chip.

[0013] Solution for solving the problem

[0014] One aspect of the present invention relates to a semiconductor device having an output stage element and a detection element for detecting the current of the output stage element. The output stage element and the detection element each include: (a) a drift region of a first conductivity type; (b) a channel forming region of a second conductivity type disposed above the drift region; (c) a main electrode region of the first conductivity type disposed above the channel forming region; and (d) a gate electrode that is buried in a first trench connected to the main electrode region, the channel forming region, and the drift region through a gate insulating film. In a planar pattern, multiple first trenches shared by the detection element and the output stage element extend parallel to each other, and multiple second trenches extending orthogonally to and parallel to the multiple first trenches sandwich the detection element in the middle, thereby separating the channel forming region of the output stage element from the channel forming region of the detection element.

[0015] The present invention also relates to a semiconductor device having an output stage element and a detection element for detecting the current of the output stage element. The output stage element and the detection element each include: (a) a drift region of a first conductivity type; (b) a channel forming region of a second conductivity type disposed above the drift region; (c) a main electrode region of the first conductivity type disposed above the channel forming region; and (d) a gate electrode embedded, separated by a gate insulating film, in a first trench connected to the main electrode region, the channel forming region, and the drift region. In a planar pattern, multiple first trenches shared by the detection element and the output stage element extend parallel to each other, and at least one second trench orthogonal to the multiple first trenches separates the channel forming region of the output stage element from the channel forming region of the detection element. The output stage element is disposed on only one side of the detection element along the long side of the first trench.

[0016] Another aspect of the present invention relates to a semiconductor device having an output stage element and a detection element for detecting the current of the output stage element. The output stage element and the detection element each include: (a) a drift region of a first conductivity type; (b) a channel forming region of a second conductivity type disposed above the drift region; (c) a main electrode region of the first conductivity type disposed above the channel forming region; and (d) a gate electrode embedded, through a gate insulating film, in a first trench connected to the main electrode region, the channel forming region, and the drift region. In a planar pattern, multiple detection elements and output stage elements share common features. The first trenches extend parallel to each other. On the planar pattern, at least one second trench extends orthogonally to the multiple first trenches, separating the channel forming region of the output stage element from the channel forming region of the detection element. The end of the channel forming region of the detection element, opposite to the side that is separated from the channel forming region of the output stage element by the second trench, is connected to the first electric field mitigation region of the second conductivity type with a depth greater than the depth of the first trench. In the long side direction of the first trench, the channel forming region of the output stage element is connected to the second electric field mitigation region of the second conductivity type, which is separated from the first electric field mitigation region and has a depth greater than the depth of the first trench.

[0017] The effects of the invention

[0018] According to the present invention, a semiconductor device is provided in which the chip area can be reduced by integrating the output stage components and the detection element for detecting the main current flowing through the output stage components into the same semiconductor chip. Attached Figure Description

[0019] Figure 1 This is a top view showing an example of a semiconductor device according to the first embodiment.

[0020] Figure 2 yes Figure 1Top view of area A.

[0021] Figure 3 From Figure 2 A cross-sectional view observed along the AA direction.

[0022] Figure 4 From Figure 2 A cross-sectional view observed along the BB direction.

[0023] Figure 5 From Figure 2 A cross-sectional view observed in the CC direction.

[0024] Figure 6 This is a top view of the semiconductor device involved in the first comparative example.

[0025] Figure 7 yes Figure 6 Top view of area A.

[0026] Figure 8 From Figure 7 A cross-sectional view observed along the AA direction.

[0027] Figure 9 From Figure 7 A cross-sectional view observed along the BB direction.

[0028] Figure 10 From Figure 7 A cross-sectional view observed in the CC direction.

[0029] Figure 11 This is a top view of the semiconductor device involved in the second comparative example.

[0030] Figure 12 yes Figure 11 Top view of area A.

[0031] Figure 13 From Figure 12 A cross-sectional view observed along the AA direction.

[0032] Figure 14 From Figure 12 A cross-sectional view observed along the BB direction.

[0033] Figure 15 This is a top view of the main parts of the semiconductor device according to the second embodiment.

[0034] Figure 16 From Figure 15 A cross-sectional view observed along the AA direction.

[0035] Figure 17 From Figure 15 A cross-sectional view observed along the BB direction.

[0036] Figure 18 From Figure 15 A cross-sectional view observed in the CC direction.

[0037] Figure 19 From Figure 15 A cross-sectional view observed in the DD direction.

[0038] Figure 20 From Figure 15 A cross-sectional view observed in the EE direction.

[0039] Figure 21 This is a cross-sectional view of the main part of the semiconductor device involved in the first variation of the second embodiment.

[0040] Figure 22 This is a cross-sectional view of other major parts of the semiconductor device involved in the first variation of the second embodiment.

[0041] Figure 23 This is a top view of a semiconductor device according to a second variation of the second embodiment.

[0042] Figure 24 This is a top view showing the semiconductor device involved in the third variation of the second embodiment.

[0043] Figure 25 This is a top view showing the semiconductor device involved in the fourth variation of the second embodiment.

[0044] Explanation of reference numerals in the attached figures

[0045] 1: High resistivity layer; 2a~2i: Channel formation region; 3a~3d, 4a~4n: Main electrode region; 5, 5a, 5b: Electric field mitigation region; 5ax, 5ay, 5bx, 5by, 5x, 5y, 10x: End points; 6a~6i, 6x, 6y: Trench; 7: Gate insulating film; 8a~8i, 8x, 8y: Gate electrode; 9, 9a, 9b: Gate wiring; 10: Field insulation 11: Low resistivity layer; 12a-12e: Connector; 21: Detection electrode; 21a, 21b, 22a-22c, 23a, 24a, 25a: Contact; 22, 23, 24: Main electrode (source wiring); 25: Upper layer wiring; 26: Insulating film; 101: Output circuit (output stage component); 102: Detection circuit (detection component); 103: Control circuit. Detailed Implementation

[0046] The first and second embodiments of the present invention will now be described with reference to the accompanying drawings. In the drawings referred to in the following description, the same or similar parts are labeled with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it is self-evident that the drawings also include parts with different dimensional relationships and ratios.

[0047] In the following description, "first main electrode region" and "second main electrode region" refer to the main electrode regions of a semiconductor device through which the main current flows in or out. For an insulated-gate bipolar transistor (IGBT), the "first main electrode region" refers to the semiconductor region that becomes either the emitter region or the collector region. For a field-effect transistor (FET) or a stationary inductor transistor (SIT), the "first main electrode region" refers to the semiconductor region that becomes either the source region or the drain region. For a stationary inductor thyristor (SI thyristor) or a gate turn-off thyristor (GTO), the "first main electrode region" refers to the semiconductor region that becomes either the anode region or the cathode region. For an IGBT, the "second main electrode region" refers to the region that becomes either the emitter region or the collector region, but not the first main electrode region. For a FET or a SIT, the "second main electrode region" refers to the semiconductor region that becomes either the source region or the drain region, but not the first main electrode region. For SI thyristors and GTOs, the "second main electrode region" refers to the region that is neither the anode nor the cathode region, but rather the region that is not part of the aforementioned first main electrode region. That is, if the "first main electrode region" is the source region, then the "second main electrode region" refers to the drain region. If the "first main electrode region" is the emitter region, then the "second main electrode region" refers to the collector region. If the "first main electrode region" is the anode region, then the "second main electrode region" refers to the cathode region.

[0048] Furthermore, the definitions of "upper surface," "lower surface," and other terms related to up / down, left / right, etc., in the following description are merely for ease of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° for observation, the up / down orientation is changed to left / right; if the object is rotated 180° for observation, the up / down orientation is reversed. This is self-evident.

[0049] Furthermore, the following description illustrates, illustratively, the case where the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types can also be chosen in reverse order, with the first conductivity type being p-type and the second conductivity type being n-type. Additionally, the "+" or "-" notation for "n" and "p" indicates a semiconductor region with a relatively high or relatively low impurity concentration (in other words, a relatively low or relatively high resistivity) compared to semiconductor regions without "+" or "-" notation. However, in the accompanying drawings, even semiconductor regions labeled with the same "n" do not necessarily have strictly identical impurity concentrations (resistivity).

[0050] (First Implementation)

[0051] like Figure 1 As shown, the semiconductor device according to the first embodiment is an integrated circuit comprising an output circuit (output stage element) 101, a detection circuit (detection element) 102, and a control circuit 103 monolithically integrated onto the same semiconductor chip. The semiconductor device according to the first embodiment is a so-called "embedded" semiconductor device in which the detection element 102 is embedded within the output stage element 101. Furthermore, the detection element 102 is located inside the output stage element 101 on the side closer to the control circuit 103, but the location of the detection element 102 within the output stage element 101 is not particularly limited.

[0052] The output stage element 101 is composed of semiconductor elements such as trench-gate vertical MOS transistors, which serve as the output stage. The detection element 102, for example, has the same structure as the output stage element 101, and is composed of semiconductor elements such as trench-gate vertical MOS transistors. The detection element 102 detects the main current flowing through the output stage element 101. That is, the active area of ​​the detection element 102 is set to a predetermined ratio (e.g., about 1 / 5000 to 1 / 1000) relative to the active area of ​​the output stage element 101, and the main current flowing through the output stage element 101 can be detected based on the active area ratio and the current value flowing through the detection element 102. The control circuit 103 controls the output stage element 101 based on the detection result of the detection element 102. The control circuit 103 is, for example, constructed by integrating semiconductor elements such as lateral MOS transistors.

[0053] Figure 2 Show Figure 1 A top view of region A near the right end of the detection element 102, enclosed by a dashed line. Furthermore, Figure 1 The left end of the detection element 102 shown in the figure is near the boundary of the output stage element 101. Figure 2 The same planar layout is symmetrical from left to right.

[0054] like Figure 2 As shown, along the planar pattern Figure 2 Linear gate electrodes 8a-8f, buried in trenches, are arranged in a manner that extends parallel to each other in the vertical direction. The leftmost gate electrodes 8a-8c of the gate electrodes 8a-8f are shared by the detection element 102 and the output stage element 101. The direction is orthogonal to the direction in which the gate electrodes 8a-8f extend ( Figure 2 Linear gate electrodes 8x and 8y, which are buried in trenches, are arranged in a manner that extends parallel to each other in the left-right direction. The gate electrodes 8x and 8y are arranged in such a way that the detection element 102 is sandwiched in the middle. The gate electrodes 8a to 8f, 8x, and 8y are buried in the trenches with a gate insulating film (not shown) in between.

[0055] Gate electrodes 8x and 8y extend to Figure 1 The left end of the detection element 102 shown in the image. That is, by means of the detection element 102 along... Figure 2 Gate electrodes 8x and 8y extending in the left and right directions, along Figure 2 The gate electrode 8c extending vertically and along the left end of the detection element 102 Figure 2 The gate electrode, extending vertically, surrounds the entire periphery of the detection element 102, thereby separating the detection element 102 from the output stage element 101. Figure 2 In the process, two gate electrodes 8x and 8y are provided, but multiple gate electrodes can also be provided at the respective positions of gate electrodes 8x and 8y in a manner that extends in parallel with each other.

[0056] The detection element 102 is defined as being composed of along Figure 2 The gate electrode 8c extending in the vertical direction and along the Figure 2 The region is surrounded by gate electrodes 8x and 8y extending in the left and right directions. The detection element 102 has channel formation regions 2a and 2b of the second conductivity type (p-type) and a first conductivity type (n-type) disposed above the channel formation regions 2a and 2b. + The first main electrode region (source region) 3a-3d of the type, and gate electrodes 8a, 8b, 8c are provided in such a way that they are connected to the first main electrode region 3a-3d via a gate insulating film (not shown).

[0057] on the other hand, Figure 1 The output stage element 101 shown is defined as the area surrounding the detection element 102. For example... Figure 2 As shown, the output stage element 101 has a second conductivity type (p-type) channel forming region 2c-2i and a first conductivity type (n-type) channel forming region disposed on the upper part of the channel forming region 2c-2i. +The first main electrode regions 4a to 4n (of type 101) and the gate electrodes 8a to 8f are provided in connection with the first main electrode regions 4a to 4n. The detection element 102 and the output stage element 101 share the gate electrodes 8a to 8c.

[0058] In the planar pattern, the upper side of the channel forming areas 2a, 2b of the detection element 102 passes through along... Figure 2 The gate electrode 8x, extending in the left-right direction, is separated from the channel formation regions 2f and 2g of the output stage element 101. The channel formation region 2b at the right end of the detection element 102 is separated by... Figure 2 The gate electrode 8c, extending vertically, is separated from the channel formation region 2c of the output stage element 101. The lower side of the channel formation regions 2a and 2b of the detection element 102 is separated by... Figure 2 The gate electrode 8y extends in the left and right directions to separate from the channel formation regions 2h and 2i of the output stage element 101.

[0059] Figure 3 Showing from along Figure 2 A cross-sectional view observed along the AA direction (left-right direction). For example... Figure 3 As shown, the semiconductor device according to the first embodiment includes a semiconductor substrate (1, 11) constituting a semiconductor chip. The semiconductor substrate (1, 11) includes components made of n + A low resistivity layer 11 is formed from a semiconductor substrate (Si wafer), and an n-type semiconductor material with a lower impurity concentration than the low resistivity layer 11 is epitaxially grown on the low resistivity layer 11. - The high resistivity layer 1 is an example of a semiconductor substrate (1, 11) using a semiconductor material such as silicon (Si) as the base material, but the base material is not limited to Si. Alternatively, the high resistivity layer 1 can be formed by ion implantation or thermal diffusion. - The lower surface of a type of semiconductor substrate (Si wafer) is formed with n + A low resistivity layer 11, consisting of a type of impurity addition layer, is used to form the semiconductor substrate (1, 11).

[0060] Figure 3 The output stage element 101 shown on the right has n - A portion of the high resistivity layer 1 serves as a drift region. Furthermore, the output stage element 101 includes an n-type element disposed on the lower surface of the drift region. + A portion of the low resistivity layer 11 serves as the second main electrode region (drain region). P-type channel forming regions 2c to 2e are provided on the drift region. An n-type channel forming region is provided above the channel forming regions 2c to 2e. + The first main electrode region (source region) 4a to 4e of the type. The first main electrode region 4a to 4e is connected to the main electrode (source electrode) 22 via contact portions 22a and 22b.

[0061] exist Figure 3 In the output stage element 101 shown on the right, trenches 6c to 6e are provided in such a way that they penetrate the channel forming regions 2c to 2e and reach the high resistivity layer 1. + The first main electrode region (source region) 4a-4e, the channel forming regions 2c, 2d, 2e, and the high resistivity layer 1 are connected to n. + The first main electrode region (source region) 4a-4e of the type is connected to the pn junction of the channel formation regions 2c, 2d, 2e, and the pn junction of the channel formation regions 2c, 2d, 2e to the high resistivity layer 1. The trench 6c is a trench that separates the detection element 102 from the output stage element 101, and is shared by the detection element 102 and the output stage element 101.

[0062] A gate insulating film 7 is provided on the inner surface of trenches 6a to 6e. For example, a silicon oxide film (SiO2 film) can be used as the gate insulating film 7, but in addition to SiO2 film, silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, and aluminum oxide (Al2O3) film can also be used. Alternatively, it can be a magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film. Furthermore, composite films formed by stacking multiple single-layer films selected from these single-layer films can also be used.

[0063] Inside the trenches 6c to 6e, gate electrodes 8c to 8e are buried through the gate insulating film 7. The gate insulating film 7 and the gate electrodes 8c to 8e constitute the trench gate structure (7, 8c), (7, 8d), and (7, 8e).

[0064] For the gate electrodes 8a to 8e, polysilicon with a high concentration of n-type impurities (doped polysilicon) can be used, but in addition to doped polysilicon (DOPOS), high-melting-point metals such as tungsten (W), molybdenum (Mo), and titanium (Ti), as well as silicides of high-melting-point metals and polysilicon, can also be used. The material for the gate electrodes 8a to 8e can also be a composite film of polysilicon and a silicide of a high-melting-point metal, i.e., a polysilicon-metal silicide.

[0065] on the other hand, Figure 3 The detection element 102 shown on the left has n - A portion of the high resistivity layer 1 serves as a drift region. Furthermore, the detection element 102 includes an n-type sensor disposed on the lower surface of the drift region. +A portion of the low resistivity layer 11 serves as the second main electrode region (drain region). P-type channel forming regions 2a and 2b are formed on the drift region. An n-type channel forming region is formed above the channel forming regions 2a and 2b. + The first main electrode region (source region) 3a to 3d is connected to the detection electrode (source electrode) 21 via contact portions 21a and 21b. The detection electrode 21 is separate from the main electrode 22 of the output stage element 101.

[0066] exist Figure 3 In the detection element 102 shown on the left, trenches 6a to 6c are provided in such a way that they penetrate the channel forming regions 2a to 2b and reach the high resistivity layer 1. Trenches 6a to 6c and n + The first main electrode region (source region) 3a-3d, the channel forming regions 2a and 2b, and the high resistivity layer 1 are connected and connected to n. + The first main electrode region (source region) 3a-3d of the type is connected to the pn junction of the channel forming regions 2a and 2b, and the pn junction of the channel forming regions 2a and 2b is connected to the high resistivity layer 1. A gate insulating film 7 is disposed on the inner surface of the trenches 6a-6c. Gate electrodes 8a-8c are buried inside the trenches 6a-6c through the gate insulating film 7. The gate insulating film 7 and the gate electrodes 8a-8c constitute the trench gate structure (7, 8a), (7, 8b), and (7, 8c).

[0067] An insulating film 26 is provided to cover the upper surfaces of the gate electrodes 8a to 8e, as well as the detection electrode 21 and the main electrode 22. The insulating film 26 can be, for example, a single-layer film or a stacked structure of insulating films made of silicon oxide film (SiO2 film), but it also depends on the arrangement position of the insulating film 26.

[0068] When the semiconductor device according to the first embodiment is operated, a predetermined voltage is applied to the gate electrodes 8a-8e. The gate electrodes 8a-8e electrostatically control the surface potential of the channel formation regions 2a-2e through the gate insulating film 7, thereby forming an inverted channel in the channel formation regions 2a-2e. Current flows through this inverted channel between the first main electrode regions (source regions) 3a-3d, 4a-4e and the second main electrode region (drain region) formed by a portion of the low resistivity layer 11 facing the first main electrode regions 3a-3d, 4a-4e.

[0069] Figure 4 Showing from along Figure 2 The cross-sectional view observed in the BB direction (vertical direction). Figure 4 The detection element 102 on the central side is Figure 4 The output stage components 101 on the left and right sides are sandwiched in the middle. Figure 4In the detection element 102 shown in the center side, in n - A p-type channel forming region 2a is provided on the high resistivity layer 1. The channel forming region 2a is separated from the channel forming regions 2f and 2h of the output stage element 101 by trenches 6x and 6y. An n-type channel forming region is provided on the upper part of the channel forming region 2a. + The first main electrode region 3a of the type.

[0070] The first main electrode region 3a is connected to the detection electrode 21 via contact portion 21a. The source potential of the detection element 102 needs to be led out to the control circuit 103 side separately from the main electrodes 23 and 24. Therefore, the detection electrode 21 is connected to the upper layer wiring 25, which is located above the detection electrode 21, via contact portion 25a. The source potential of the detection element 102 is output to the control circuit 103 side via the detection electrode 21 and the upper layer wiring 25. Figure 1 The control circuit 103 shown in the figure has a protective film to cover the upper wiring 25, but in Figure 4 The illustration is omitted.

[0071] On the other hand, Figure 4 In the left and right output stage components 101, in n - The upper portion of the high resistivity layer 1 is provided with p-type channel forming regions 2f and 2h. The upper portions of the channel forming regions 2f and 2h are respectively provided with n-type channel forming regions. + The first main electrode regions 4g and 4k are of type 24. The first main electrode region 4g is connected to the main electrode 23 via contact portion 23a. The first main electrode region 4k is connected to the main electrode 24 via contact portion 24a.

[0072] exist Figure 4 The right side shows the end region of the output stage element 101, in n - A p-type electric field mitigation region (well region) 5 is provided on the upper part of the high resistivity layer 1. The electric field mitigation region 5 is in contact with the channel formation region 2h, and the electric field mitigation region 5 is provided deeper than the channel formation region 2h. The impurity concentration of the electric field mitigation region 5 is set to be higher than that of the channel formation region 2h, but it can also be equal to or lower than that of the channel formation region 2h.

[0073] A field insulating film 10, composed of a local insulating film (LOCOS film) or similar material, is disposed on a portion of the electric field mitigation region 5. The field insulating film 10 connects the output stage element 101 to... Figure 1 The control circuit 103 shown is separate. A gate wiring 9 is disposed in the electric field mitigation region 5, separated by an insulating film 26. Figure 4In this configuration, the left end 9x of the gate wiring 9 is located to the right of the left side of the field-relaxed region 5. The right end 9y of the gate wiring 9 is located to the right of the right side of the field-relaxed region 5. The gate wiring 9 may, for example, be integrally formed of the same material as the gate electrodes 8a to 8e.

[0074] like Figure 2 As shown, on the planar pattern, the gate wiring 9 is along... Figure 2 It extends in the left-right direction and is disposed at the end of the long side of the gate electrodes 8a to 8f. Figure 2 In the diagram, the end 10x of the field insulating film 10, hidden under the gate wiring 9, is schematically shown with a double-dotted line. Additionally, the mutually parallel ends 5x and 5y of the electric field mitigation region 5 are schematically shown with single-dotted lines. The electric field mitigation region 5 is configured to cover the ends of the gate electrodes 8a to 8f.

[0075] exist Figure 2 In the planar pattern, the positions of the lower ends of the channel formation regions 2c-2e, 2h, and 2i are shown by thick dotted lines. The positions of the lower ends of the channel formation regions 2c-2e, 2h, and 2i are approximately consistent with the position of the end 9x of the gate wiring 9.

[0076] Figure 5 Showing from along Figure 2 A cross-sectional view observed along the CC direction in the vertical direction. (Widely covering) Figure 5 The output stage element 101 shown on the left, the detection element 102 shown in the center, and the output stage element 101 shown on the right are all located in n - A trench 6b is formed on the upper part of the high resistivity layer 1, extending in a left-right direction. A gate electrode 8b is buried in the trench 6b, separated by a gate insulating film 7. Figure 2 The right side of the output stage element 101 shown has a gate wiring 9 connected to the right end of the gate electrode 8b. The side and bottom surfaces of the right end of the trench 6b are covered by a p-type electric field mitigation region 5.

[0077] <First Comparative Example>

[0078] Next, the semiconductor device involved in the first comparative example will be described. The semiconductor device involved in the first comparative example and... Figure 1 The common feature of the semiconductor devices involved in the first embodiment shown is that: Figure 6 As shown, it includes an output circuit (output stage element) 101, a detection circuit (detection element) 102, and a control circuit 103 integrated into the same semiconductor chip. However, the semiconductor device involved in the first comparative example is different from... Figure 1The difference between the semiconductor device involved in the first embodiment shown is that it is a "separate type" semiconductor device in which the detection element 102 and the output stage element 101 are separated.

[0079] Figure 7 Show Figure 6 A top view of area A near the lower right end of the detection element 102, enclosed by a dashed line. Furthermore, Figure 6 The output stage element 101 shown has the same structure as the detection element 102, therefore Figure 6 The top view of area B near the lower right end of the output stage element 101, which is surrounded by dashed lines, is also consistent with... Figure 7 Same floor plan layout.

[0080] like Figure 7 As shown, near the lower right end of the detection element 102, along... Figure 7 Linear gate electrodes 8a to 8c are provided, extending parallel to each other in the vertical direction. Gate wiring 9 is provided at the ends of the gate electrodes 8a to 8c (shown as dashed lines).

[0081] Figure 8 Showing from along Figure 7 A cross-sectional view observed along the AA direction (left-right direction). In n - The high resistivity layer 1 has p-type channel forming regions 2a to 2c on its upper part. N-type channels are formed on the upper part of the channel forming regions 2a and 2b. + The first main electrode regions 3a to 3d are of type 2. The first main electrode regions 3a to 3d are connected to the detection electrode 21 via contact portions 21a and 21b. A protective film is provided to cover the detection electrode 21, but... Figure 8 The diagram is omitted. Trench 6a-6c is provided in such a way that it is connected to the first main electrode regions 3a-3d and the channel forming regions 2a-2c and reaches the high resistivity layer 1. Gate electrodes 8a-8c are buried in the trenches 6a-6c, separated by the gate insulating film 7. An insulating film 26 is provided to cover the upper surface of the gate electrodes 8a-8c and the gate wiring 9.

[0082] The rightmost groove 6c of the detection element 102 has its side and bottom surfaces covered by a p-type electric field mitigation region 5. A field insulating film 10 is disposed on the upper surface of the electric field mitigation region 5. Figure 7 In the diagram, the end 10x of the field insulating film 10, hidden under the gate wiring 9, is schematically shown with a double-dotted line. Additionally, the L-shaped, parallel planar patterns of the electric field mitigation region 5 are schematically shown with a single-dotted line. The electric field mitigation region 5 is configured to cover the right side of the trench 6c and the lower ends of the trenches 6a to 6c.

[0083] Figure 9Showing from along Figure 7 A cross-sectional view observed along the BB direction in the left and right directions. Figure 9 The image shows the vicinity of the ends of trenches 6a-6c. Gate wiring 9 is connected to the upper surface of the gate electrodes 8a-8c, which are buried in trenches 6a-6c through a gate insulating film 7. The sides and bottom surfaces near the ends of trenches 6a-6c are covered by p-type electric field mitigation regions 5.

[0084] Figure 10 Showing from along Figure 7 A cross-sectional view observed along the CC direction in the vertical direction. Trench 6b along... Figure 10 It extends in the left and right directions. The side and bottom surfaces of the right end of the trench 6b are covered by the p-type electric field mitigation region 5.

[0085] In the semiconductor device involved in the first comparative example, such as Figures 7-10 As shown, the detection element 102 includes the ends of trenches 6a to 6c. To prevent electric field concentration at the ends of trenches 6a to 6c, it is necessary to cover the electric field mitigation region 5 at the ends of trenches 6a to 6c. In contrast, according to the semiconductor device of the first embodiment, such as... Figures 2-5 As shown, gate electrodes 8x and 8y, orthogonal to gate electrodes 8a to 8f, are provided to separate the channel formation regions 2a and 2b of the detection element 102 from the channel formation regions 2c, 2f to 2i of the output stage element 101. Therefore, the detection element 102 is surrounded by the output stage element 101, and thus does not need the ends of gate electrodes 8a to 8c, thereby eliminating the need for an electric field mitigation region 5 as in the semiconductor device described in the first comparative example.

[0086] <Second Comparative Example>

[0087] Next, the semiconductor device involved in the second comparative example will be described. The semiconductor device involved in the second comparative example is... Figure 1 The common feature of the semiconductor devices involved in the first embodiment shown is that: Figure 11 As shown, the semiconductor device includes an output circuit (output stage element) 101, a detection circuit (detection element) 102, and a control circuit 103 integrated into the same semiconductor chip. It is an "embedded" semiconductor device in which the detection element 102 is embedded within the output stage element 101. However, the semiconductor device involved in the second comparative example is different from... Figure 1 The difference between the semiconductor device in the first embodiment shown is that the detection element 102 is located at the end of the output stage element 101, and the output stage element 101 is arranged on only one side of the detection element 102 along the long side of the trench.

[0088] Figure 12 Show Figure 11A top view of area A near the right end of the detection element 102, enclosed by a dashed line. (See attached image.) Figure 12 As shown, along the planar pattern Figure 12 Linear gate electrodes 8a to 8c of the detection element 102 are arranged in a manner that extends parallel to each other in the vertical direction. On the sides of the gate electrodes 8a to 8c, n are provided with a gate insulating film (not shown) as a barrier. + The first main electrode regions 3a to 3d of the type are provided. Linear gate electrodes 8d to 8i of the output stage element 101 are provided in a parallel manner. On the sides of the gate electrodes 8d to 8i, n are provided through a gate insulating film (not shown). + The first main electrode region of the type is 4a to 4j.

[0089] Figure 13 Showing from along Figure 12 A cross-sectional view observed along the AA direction in the left and right directions. Figure 13 In the detection element 102 shown on the left, n - The high resistivity layer 1 has p-type channel forming regions 2a to 2c on its upper part. N-type channels are formed on the upper part of the channel forming regions 2a and 2b. + The first main electrode regions 3a to 3d are connected to the detection electrode 21 via contact portions 21a and 21b. Trench 6a to 6c are provided in such a manner that they connect to the first main electrode regions 3a to 3d and the channel forming regions 2a and 2b, reaching the high resistivity layer 1. Gate electrodes 8a to 8c are buried in the trench 6a to 6c, separated by the gate insulating film 7. The side and bottom surfaces of the right end of the trench 6c are covered by a p-type electric field mitigation region 5a.

[0090] On the other hand, Figure 13 In the output stage element 101 shown on the right, in n - A p-type channel forming region 2g and 2h are provided on the upper part of the high resistivity layer 1. An n-type channel forming region is provided on the upper part of the channel forming region 2h. + The first main electrode regions 4i and 4j are connected to the main electrode 22 via contact portion 22a. Trench 6h and 6i are provided in a manner that penetrates the channel forming regions 2g and 2h and reaches the high resistivity layer 1. Gate electrodes 8h and 8i are buried in the trenches 6h and 6i, separated by the gate insulating film 7. The left side and bottom surface of the trench 6h are covered by a p-type electric field mitigation region 5b.

[0091] The electric field mitigation regions 5a and 5b are separated from each other. A field insulating film 10 is disposed in the high resistivity layer 1, sandwiched between the electric field mitigation regions 5a and 5b. An insulating film 26 is disposed on the gate electrodes 8a-8c, 8h, 8i, the electric field mitigation regions 5a and 5b, and the upper surface of the field insulating film 10. A protective film is disposed to cover the detection electrode 21 and the main electrode 22, but... Figure 13 The illustration is omitted.

[0092] exist Figure 12 In the diagram, the ends 5ax and 5ay of the p-type electric field mitigation region 5a are schematically shown with single-dotted lines. Similarly, the ends 5bx and 5by of the p-type electric field mitigation region 5b are schematically shown with single-dotted lines. Furthermore, the portion of the field insulating film 10 hidden beneath the gate wirings 9a and 9b is shown with double-dotted lines.

[0093] The p-type electric field mitigation region 5a has a planar pattern sandwiched between ends 5ax and 5ay, and is configured to surround the detection element 102. The p-type electric field mitigation region 5a covers both ends of the long sides of the grooves 6a to 6c included in the detection element 102. The p-type electric field mitigation region 5b has a planar pattern sandwiched between ends 5bx and 5by, and is configured to surround the output stage element 101. The p-type electric field mitigation region 5b covers the ends of the grooves 6d to 6i included in the output stage element 101. A field insulating film 10 is provided between the end 5ax of the electric field mitigation region 5a and the end 5by of the electric field mitigation region 5b. The field insulating film 10 separates the output stage element 101 from the detection element 102.

[0094] Figure 14 Showing from along Figure 12 A cross-sectional view observed along the BB direction in the vertical direction. Figure 14 In the output stage element 101 shown on the left, a trench 6e extends in the left-right direction. A gate electrode 8e is buried in the trench 6e, separated by a gate insulating film 7. The gate electrode 8e is connected to the gate wiring 9a. The side and bottom surfaces of the right end of the trench 6e are covered by a p-type electric field mitigation region 5a.

[0095] On the other hand, Figure 14 In the detection element 102 shown on the right, a trench 6b extends in the left-right direction. A gate electrode 8b is buried in the trench 6b, separated by a gate insulating film 7. The gate electrode 8b is connected to a gate wiring 9a. The side and bottom surfaces of the left end of the trench 6b are covered by a p-type electric field mitigation region 5b. A field insulating film 10 is disposed in the high resistivity layer 1, sandwiched between the electric field mitigation regions 5a and 5b. Gate wiring 9a is disposed on the field insulating film 10 to connect the gate electrodes 8b and 8e.

[0096] In the semiconductor device involved in the second comparative example, such as Figures 12-14 As shown, in order to separate the channel formation regions 2d and 2e of the output stage element 101 from the channel formation regions 2a and 2b of the detection element 102, the trench needs to be divided into trenches 6d to 6f of the output stage element 101 and trenches 6a to 6c of the detection element 102. Furthermore, in order to mitigate the electric field concentration at the long-side ends of the trenches 6d to 6f of the output stage element 101 and at the long-side ends of the trenches 6a to 6c of the detection element 102, electric field mitigation regions 5a and 5b are required.

[0097] In contrast, the semiconductor device according to the first embodiment, such as Figures 2-5 As shown, gate electrodes 8x and 8y, orthogonal to gate electrodes 8a to 8f, are provided to separate the channel formation regions 2a and 2b of the detection element 102 from the channel formation regions 2c, 2f to 2i of the output stage element 101. Therefore, the trenches 6a to 6f do not need to be separated in the output stage element 101 and the detection element 102, and the gate electrodes 8a to 8f can be shared. Therefore, the detection element 102 is surrounded by the output stage element 101, so it does not need to have the ends in the long side direction of the trenches 6a to 6c, and the electric field mitigation regions 5a and 5b as in the semiconductor device according to the second comparative example are not required.

[0098] (Second Implementation)

[0099] The outline layout of the semiconductor device involved in the second embodiment and Figure 11 The semiconductor device involved in the second comparative example shown is the same. The semiconductor device involved in the second embodiment is the same as... Figure 1 The common feature of the semiconductor devices involved in the first embodiment shown is that: Figure 11 As shown, the semiconductor integrated circuit includes an output stage element 101, a detection element 102, and a control circuit 103 integrated into the same semiconductor chip, and the detection element 102 is embedded inside the output stage element 101, making it a "buried type" semiconductor integrated circuit. However, the semiconductor device according to the second embodiment is different from... Figure 1 The difference between the semiconductor device according to the first embodiment shown is that the detection element 102 is located at the end of the output stage element 101, and the output stage element 101 is arranged on only one side of the detection element 102 along the long side direction of the trench.

[0100] Figure 15 Show Figure 11 A top view of area A near the right end of the detection element 102, enclosed by a dashed line. Furthermore, Figure 11 The area near the left end of the detection element 102 has a similar Figure 15 The plan layout is symmetrical from left to right.

[0101] like Figure 15 As shown, in the semiconductor device according to the second embodiment, along the planar pattern Figure 15 Linear gate electrodes 8a to 8f are provided, extending parallel to each other in the vertical direction. Furthermore, in a manner orthogonal to the gate electrodes 8a to 8f... Figure 15 A linear gate electrode 8x is provided extending in the left-right direction. Furthermore, in Figure 15 In the example shown, only one gate electrode 8x is provided. However, it is also possible to provide multiple gate electrodes at the location of gate electrode 8x, extending in parallel to each other. The gate electrodes 8a to 8f and 8x are buried in the trench through a gate insulating film (omitted from the illustration).

[0102] The right end of the detection element 102 is separated from the output stage element 101 by gate electrodes 8c and 8x. Gate electrode 8x extends from the right end of the detection element 102 to the left end of the detection element 102. The left end of the detection element 102 is separated from the output stage element 101 by gate electrode 8x and other gate electrodes extending parallel to gate electrode 8c, but these are not shown in the figure.

[0103] The detection element 102 has p-type channel forming regions 2a and 2b, and an n-type channel forming region 2a and 2b is grounded and disposed above the channel forming regions 2a and 2b. + The first main electrode regions 3a-3d are p-type, and gate electrodes 8a-8c are connected to the first main electrode regions 3a-3d via a gate insulating film (not shown). The output stage element 101 has p-type channel forming regions 2d-2h and an n-type channel forming region 2d-2h grounded above the channel forming regions 2d-2h. + The first main electrode regions 4a-4j and gate electrodes 8a-8f connected to the first main electrode regions 4a-4j via a gate insulating film (not shown) are included. The gate electrodes 8a-8c are shared by the detection element 102 and the output stage element 101.

[0104] exist Figure 15 In the planar pattern, the positions of the lower ends of the channel formation regions 2a, 2b, 2f to 2h are shown by thick dotted lines. The positions of the lower ends of the channel formation regions 2a, 2b, 2f to 2h are approximately consistent with the positions of the ends 9x of the gate wiring 9.

[0105] Figure 16 Showing from along Figure 15 A cross-sectional view observed along the AA direction in the left and right directions. Figure 16 In the output stage element 101 shown on the right, in n -A p-type channel forming region 2f to 2h is formed on a high resistivity layer 1. An n-type channel forming region is formed above the channel forming region 2f to 2h. + The first main electrode regions (source regions) 4e to 4j are connected to the main electrode 22 via contact portions 22a to 22c. Trench 6c to 6f are provided to penetrate the channel forming regions 2f to 2h and reach the high resistivity layer 1. The trenches 6c to 6f are connected to n... + The first main electrode region 4e-4j, the channel formation region 2f-2h, and the high resistivity layer 1 are connected and are connected to n. + The first main electrode regions 4e-4j of the type are connected to the pn junction of the channel formation regions 2f-2h, and the channel formation regions 2f-2h are connected to the pn junction of the high resistivity layer 1. In the trenches 6c-6f, the gate electrodes 8c-8f are buried in the trenches through the gate insulating film 7.

[0106] exist Figure 16 In the detection element 102 shown on the left, n - A p-type channel forming region 2a and 2b is formed on a high resistivity layer 1. An n-type channel forming region is formed above the channel forming regions 2a and 2b. + The first main electrode regions 3a to 3d are connected to the detection electrode 21 via contact portions 21a and 21b. Trench 6a to 6c are provided to penetrate the channel forming regions 2a and 2b and reach the high resistivity layer 1. The trench 6a to 6c and n... + The first main electrode region 3a-3d, the channel forming regions 2a and 2b, and the high resistivity layer 1 are connected and connected to n. + The first main electrode regions 3a-3d of the type are connected to the pn junctions of the channel forming regions 2a and 2b, and the pn junctions of the channel forming regions 2a and 2b are connected to the high resistivity layer 1. In the trenches 6a-6c, the gate electrodes 8a-8c are buried in the trenches through the gate insulating film 7.

[0107] Trench 6c is a trench that separates the output stage element 101 from the detection element 102, and is shared by both the output stage element 101 and the detection element 102. Similar to the semiconductor device according to the first embodiment, n is provided on the lower surface of the high resistivity layer 1. + A low resistivity layer of the type, but in Figure 16 The diagram is omitted. A portion of this low resistivity layer functions as the second main electrode region (drain region) of the output stage element 101 and the second main electrode region (drain region) of the detection element 102.

[0108] An insulating film 26 is provided on the upper surface of the gate electrodes 8a to 8f. A protective film is provided to cover the detection electrode 21 and the main electrode 22, but in Figure 16 The illustration is omitted.

[0109] Figure 17 Showing from along Figure 15 The cross-sectional view observed in the BB direction (left and right). Figure 17 The area near the ends of trenches 6a to 6f along their long sides is shown. To align (match) the positions of the detection element 102 and the ends of the output stage element 101, as follows... Figure 17 As shown on the left, the detection element 102 includes the ends of the trenches 6a to 6c along their long sides. The side surfaces and bottom surfaces near the ends of the trenches 6a and 6b along their long sides are covered by a p-type electric field mitigation region 5a. Figure 17 The output stage element 101 shown on the right includes the ends of trenches 6c to 6f in the long side direction. The side surfaces and bottom surfaces near the ends of trenches 6d to 6f in the long side direction are covered by a p-type electric field mitigation region 5b.

[0110] The electric field mitigation regions 5a and 5b are separated to prevent a short circuit between the rightmost channel forming region 2b of the detection element 102 and the leftmost channel forming region 2c of the output stage element 101. Here, electric field concentration may occur near the long side end of the trench 6c located between the electric field mitigation regions 5a and 5b, which is not covered by the electric field mitigation regions 5a and 5b, leading to a decrease in withstand voltage.

[0111] To address this, the distance D1 between the electric field mitigation regions 5a and 5b is set such that when a high voltage, different from normal operation, is applied between the drain and source of the output stage element 101 and the detection element 102, the depletion layer extending from the drift region formed by the high resistivity layer 1 and the pn junction of the electric field mitigation region 5a connects with the depletion layer extending from the drift region formed by the high resistivity layer 1 and the pn junction of the electric field mitigation region 5b. This mitigates the electric field at the end of the trench 6c along its long side, preventing a drop in withstand voltage. For example, when the withstand voltage is around 60V, it is preferable to set the distance D1 between the electric field mitigation regions 5a and 5b to approximately 1 μm or more and 3 μm or less.

[0112] Figure 18 Showing from along Figure 15 A cross-sectional view observed in the CC direction (vertical and horizontal). Figure 18 In the output stage element 101 shown on the left, in n - A p-type channel forming region 2d is formed on a high resistivity layer 1. An n-type channel forming region is formed on the upper part of the channel forming region 2d. + The first main electrode region 4a is connected to the main electrode 23 via a contact portion 23a.

[0113] On the other hand, Figure 18 In the detection element 102 shown on the right, in n -A p-type channel forming region 2a is provided on a high resistivity layer 1. An n-type channel forming region is provided above the channel forming region 2a. + The first main electrode region 3a is of type 23. The first main electrode region 3a is connected to the detection electrode 21 via a contact portion 21a. A protective film is provided covering the detection electrode 21 and the main electrode 23, but in... Figure 18 The illustration is omitted.

[0114] Since the detection electrode 21 is not completely surrounded by the main electrode 23 of the output stage element 101, the source potential of the detection element 102 can be led out to the control circuit 103 side by means of the detection electrode 21 which is on the same layer (first layer) as the main electrode 23. Therefore, compared with the semiconductor device according to the first embodiment, a multilayer wiring structure for leading out the source potential is not required.

[0115] The side and bottom surfaces of the right end of the channel forming region 2a are covered by a p-type electric field mitigation region 5a. A field insulating film 10 is disposed on the upper surface of the electric field mitigation region 5a. Gate wiring 9 is disposed on the upper surface of the electric field mitigation region 5a, separated by the insulating film 26. Figure 18 In the diagram, the left end 9x of the gate wiring 9 is located to the right of the left side of the electric field easing region 5a. The right end 9y of the gate wiring 9 is located to the right of the right side of the electric field easing region 5a.

[0116] exist Figure 15 In the diagram, the position of the end of the p-type electric field mitigation region 5a is schematically shown with a single-dotted line. Similarly, the position of the end of the p-type electric field mitigation region 5b is schematically shown with a single-dotted line. Additionally, the portion of the field insulating film 10 hidden beneath the gate wiring 9 is shown with a double-dotted line.

[0117] Figure 19 Showing from along Figure 15 A cross-sectional view observed along the DD direction (left-right direction). From Figure 19 The output stage element 101 shown on the left extends to the detection element 102 shown on the right, with a trench 6b provided in a left-right direction. A gate electrode 8b is buried in the trench 6b, separated by a gate insulating film 7. The upper surface of the right end of the gate electrode 8b is connected to the gate wiring 9. The side and bottom surfaces of the long side end of the trench 6b are covered by an electric field mitigation region 5a.

[0118] Figure 20 Showing from along Figure 15 A cross-sectional view observed along the EE direction in the left and right directions. From Figure 20The output stage element 101 shown on the left extends to the detection element 102 shown on the right, and a trench 6c is provided in a manner extending in the left-right direction. A gate electrode 8c is buried in the trench 6c, separated by a gate insulating film 7. The upper surface of the right end of the gate electrode 8c is connected to the gate wiring 9. The side and bottom surfaces of the ends in the long side direction of the trench 6c are in contact with the high resistivity layer 1.

[0119] According to the semiconductor device of the second embodiment, such as Figures 15-20 As shown, a gate electrode 8x orthogonal to the gate electrodes 8a-8f is provided to separate the channel formation regions 2a and 2b of the detection element 102 from the channel formation regions 2d-2f of the output stage element 101. Therefore, the long side directions of the trenches 6a-6c do not terminate at the position of the gate electrode 8x, and thus the detection element 102 does not have ends in the long side directions of the trenches 6a-6c, and therefore does not require an electric field mitigation region 5 as in the semiconductor device involved in the first comparative example.

[0120] And, as Figure 18 As shown, the detection electrode 21 of the detection element 102 is not completely surrounded by the main electrode 23 of the output stage element 101, so the source potential of the detection element 102 can be drawn out using the detection electrode 21 on the same layer as the main electrode 23, thus eliminating the need for a multi-layer wiring structure.

[0121] <First Variation>

[0122] Next, refer to Figure 21 and Figure 22 To illustrate the semiconductor device involved in the first variation of the second embodiment. Figure 21 It is a semiconductor device according to the second embodiment. Figure 16 The corresponding cross-sectional view, Figure 22 It is a semiconductor device according to the second embodiment. Figure 17 The corresponding cross-sectional view.

[0123] The difference between this and the semiconductor device according to the second embodiment is that: Figure 21 As shown, the trenches 6b to 6d near the boundary between the output stage element 101 and the detection element 102 are designated as dummy trenches for use under floating potential. No main electrode region is formed on the sidewalls of the trenches 6b to 6d. Furthermore, there is no particular limitation on the number of dummy trenches. For example, only one trench 6c can be designated as a dummy trench, or two trenches 6b and 6c, or 6c and 6d, can be designated as dummy trenches. Moreover, four or more trenches, including trench 6c, can be designated as dummy trenches.

[0124] Figure 22 The area near the ends of grooves 6a to 6f along their long sides is shown. Figure 22 In the detection element 102 shown on the left, the side and bottom surfaces near the end of the trench 6a in the long side direction are covered by a p-type electric field mitigation region 5a. Figure 22 In the output stage element 101 shown on the right, the side surfaces and bottom surfaces near the ends of trenches 6e and 6f in the long side direction are covered by p-type electric field mitigation regions 5b. The side surfaces and bottom surfaces near the ends of trenches 6b to 6d in the long side direction are not covered by electric field mitigation regions 5a and 5b. The distance D2 between electric field mitigation regions 5a and 5b is set to be greater than... Figure 21 The distance D1 shown is the width.

[0125] According to the semiconductor device of the first variation of the second embodiment, the trenches 6b to 6d near the boundary between the output stage element 101 and the detection element 102 are set as dummy trenches and set as floating potentials. As a result, when a high voltage is applied, the depletion layer extending from the pn junction of the electric field mitigation region 5a and the high resistivity layer 1 and the depletion layer extending from the pn junction of the electric field mitigation region 5b and the high resistivity layer 1 can be widened, thereby enabling the wide distance D2 between the electric field mitigation regions 5a and 5b to be depleted.

[0126] <Second Variation>

[0127] The semiconductor device involved in the second variation of the second embodiment differs from the semiconductor device involved in the second embodiment in that: Figure 23 As shown, the ends of the trenches containing the gate electrodes 8a to 8f, which are buried in the gate insulating film (not shown), are all connected in the long side direction.

[0128] The ends of the trenches containing gate electrodes 8a to 8f, which are filled with gate insulating film (not shown), are connected by connecting portions 12a to 12e along their long sides. Connecting portions 12a to 12e are structures in which gate electrodes are filled with the trenches with the gate insulating film in between. A portion of connecting portion 12b and connecting portion 12a are covered by electric field mitigation region 5a. A portion of connecting portion 12c and connecting portions 12d and 12e are covered by electric field mitigation region 5b.

[0129] The semiconductor device according to the second variation of the second embodiment has the same effect as the semiconductor device according to the second embodiment, even when all the ends of the trenches in the long side direction where the gate electrodes 8a to 8f are buried across the gate insulating film (not shown) are connected.

[0130] <Third Variation>

[0131] The semiconductor device involved in the third variation of the second embodiment differs from the semiconductor device involved in the second embodiment in that: Figure 24As shown, the positions of the ends of the channel forming regions 2a and 2b of the detection element 102 in the long side direction are not consistent with (misaligned) the positions of the ends of the channel forming regions 2f to 2h of the output stage element in the long side direction, but are offset from each other.

[0132] exist Figure 24 In the planar pattern, the positions of the lower ends of the channel formation regions 2a, 2b, and 2f-2h along their long sides are indicated by thick dotted lines. The lower ends of the channel formation regions 2a and 2b of the detection element 102 are located above the lower ends of the channel formation regions 2f-2h of the output stage element and the end 9x of the gate wiring 9. The electric field mitigation region 5a is configured to extend further into the channel formation regions 2a and 2b than the electric field mitigation region 5b. The lower ends of the channel formation regions 2a and 2b along their long sides are covered by the electric field mitigation region 5a.

[0133] The semiconductor device according to the third variation of the second embodiment achieves the same effect as the semiconductor device according to the second embodiment, even if the positions of the ends of the channel forming regions 2a and 2b of the detection element 102 in the long side direction are inconsistent (misaligned) with the positions of the ends of the channel forming regions 2f to 2h of the output stage element in the long side direction, respectively.

[0134] <Fourth Variation>

[0135] The semiconductor device involved in the fourth variation of the second embodiment differs from the semiconductor device involved in the second embodiment in that: Figure 25 As shown, the position of the end of the trench in the long side direction of the detection element 102 where the gate electrodes 8a and 8b are buried is not consistent with (misaligned) the position of the end of the trench in the long side direction of the output stage element where the gate electrodes 8c to 8f are buried, but rather they are offset.

[0136] exist Figure 25 In the planar pattern, the positions of the lower ends of the channel formation regions 2a, 2b, and 2f-2h along their long sides are indicated by thick dotted lines. The lower ends of the channel formation regions 2a and 2b of the detection element 102 are located above the lower ends of the channel formation regions 2f-2h of the output stage element and the end 9x of the gate wiring 9. The electric field mitigation region 5a is configured to extend further into the channel formation regions 2a and 2b than the electric field mitigation region 5b. The lower ends of the channel formation regions 2a and 2b along their long sides are covered by the electric field mitigation region 5a.

[0137] The end of the trench of the detection element 102 where the gate electrodes 8a and 8b are buried is positioned above the end of the trench of the output stage element where the gate electrodes 8c to 8f are buried. The end 9x of the gate wiring 9 on the side of the detection element 102 overlaps with the end of the trench of the detection element 102 on the side of the output stage element and is positioned above the end 9x of the gate wiring 9 on the side of the output stage element. Figure 25 The position on the upper side.

[0138] The semiconductor device according to the fourth variation of the second embodiment achieves the same effect as the semiconductor device according to the second embodiment, even if the position of the end of the trench in the long side direction where the gate electrodes 8a and 8b are buried in the detection element 102 is not consistent (misaligned) with the position of the end of the trench in the long side direction where the gate electrodes 8c to 8f are buried in the output stage element, it deviates from the position of the trench in the long side direction.

[0139] (Other implementation methods)

[0140] As described above, the present invention has been illustrated through first and second embodiments, but it should not be construed that the discussions and drawings, which form part of this disclosure, are intended to limit the invention. Based on this disclosure, those skilled in the art will recognize various alternative embodiments, examples, and application techniques.

[0141] For example, in the first and second embodiments, a trench-gate MOS transistor is exemplified as the output stage element 101, but it is not limited to this. For example, the output stage element 101 may also be a trench-gate IGBT. When the output stage element 101 is an IGBT, for example, as long as it is made Figure 1 n + The low resistivity layer 11 of the type is p + A semiconductor layer of this type is sufficient.

[0142] Furthermore, in the first and second embodiments, Si is used as the semiconductor substrate (1, 11), but in addition to the case of using Si, it can also be applied to the case of using semiconductor (wide bandgap semiconductor) materials such as silicon carbide (SiC), gallium nitride (GaN), diamond or aluminum nitride (AlN) with a wider bandgap than Si.

[0143] Furthermore, the structures disclosed in the first embodiment and the second embodiment can be appropriately combined without contradiction. Thus, it is self-evident that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features addressed in the appropriate claims based on the foregoing description.

Claims

1. A semiconductor device comprising an output stage element and a detection element for detecting the current of the output stage element, characterized in that, The output stage element and the detection element each include: The drift region of the first conductivity type; A second conductivity type channel forming region is disposed above the drift region; The main electrode region of the first conductivity type is disposed above the channel forming region; and A gate electrode, which is buried in a first trench adjacent to the main electrode region, the channel formation region, and the drift region, separated by a gate insulating film. in, On the planar pattern, multiple first trenches shared by the detection elements and the output stage elements extend parallel to each other. On the planar pattern, at least one second trench extending orthogonally to the plurality of first trenches separates the channel formation region of the output stage element from the channel formation region of the detection element. The output stage element is provided on only one side of the detection element along the long side of the first groove.

2. The semiconductor device according to claim 1, characterized in that, It also includes a control circuit that controls the output stage element based on the detection result of the detection element.

3. The semiconductor device according to claim 2, characterized in that, It also has: A detection electrode, which is connected to the main electrode region of the detection element; and The main electrode, which is disposed on the same layer as the detection electrode, is connected to the main electrode region of the output stage element. The detection electrode is led out to the control circuit side via wiring on the same layer as the main electrode.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The output stage element includes a portion of the first trenches at the end along the long side of the first trench. The detection element includes another portion of the first grooves, specifically the ends of the first grooves along their long sides. The semiconductor device further includes a first electric field mitigation region of a second conductivity type, which is provided in a manner that covers the end of the first trench of the output stage element, and a second electric field mitigation region of a second conductivity type, which is separated from the first electric field mitigation region and is provided in a manner that covers the end of the first trench of the detection element.

5. The semiconductor device according to claim 4, characterized in that, The end of the first trench located at the boundary between the output stage element and the detection element in the long side direction of the first trench is disposed between the first electric field mitigation region and the second electric field mitigation region.

6. The semiconductor device according to claim 4, characterized in that, The distance between the first electric field mitigation region and the second electric field mitigation region is set such that when a voltage higher than that during normal operation is applied, the depletion layer extending from the junction of the drift region of the output stage element and the first electric field mitigation region is connected to the depletion layer extending from the junction of the drift region of the detection element and the second electric field mitigation region.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The ends of the first groove are all connected.

8. A semiconductor device comprising an output stage element and a detection element for detecting the current of the output stage element, characterized in that, The output stage element and the detection element each include: The drift region of the first conductivity type; A second conductivity type channel forming region is disposed above the drift region; The main electrode region of the first conductivity type is disposed above the channel forming region; and A gate electrode, which is buried in a first trench adjacent to the main electrode region, the channel formation region, and the drift region, separated by a gate insulating film. in, On the planar pattern, multiple first trenches shared by the detection elements and the output stage elements extend parallel to each other. On the planar pattern, at least one second trench extending orthogonally to the plurality of first trenches separates the channel formation region of the output stage element from the channel formation region of the detection element. The end of the channel forming region of the detection element, opposite to the side that separates from the channel forming region of the output stage element via the second trench, is connected to the first electric field mitigation region of the second conductivity type, which has a depth greater than that of the first trench. In the long side direction of the first trench, the channel forming region of the output stage element is connected to the second electric field mitigation region of the second conductivity type, which is separate from the first electric field mitigation region and has a depth greater than that of the first trench.

9. The semiconductor device according to claim 8, characterized in that, It also includes a control circuit that controls the output stage element based on the detection result of the detection element.

10. The semiconductor device according to claim 9, characterized in that, It also has: A detection electrode, which is connected to the main electrode region of the detection element; and The main electrode, which is disposed on the same layer as the detection electrode, is connected to the main electrode region of the output stage element. The detection electrode is led out to the control circuit side via wiring on the same layer as the main electrode.

11. The semiconductor device according to any one of claims 8 to 10, characterized in that, The output stage element includes a portion of the first trenches at the end along the long side of the first trench. The detection element includes another portion of the first grooves, the end of the first groove along its long side. The first electric field mitigation region covers the end of the first trench of the detection element along its long side. The second electric field mitigation region covers the end of the first trench of the output stage element along its long side.

12. The semiconductor device according to claim 11, characterized in that, The end of the first trench located at the boundary between the output stage element and the detection element in the long side direction of the first trench is disposed between the first electric field mitigation region and the second electric field mitigation region.

13. The semiconductor device according to any one of claims 8 to 10, characterized in that, The distance between the first electric field mitigation region and the second electric field mitigation region is set such that when a voltage higher than that during normal operation is applied, the depletion layer extending from the junction of the drift region of the output stage element and the first electric field mitigation region is connected to the depletion layer extending from the junction of the drift region of the detection element and the second electric field mitigation region.

14. The semiconductor device according to any one of claims 8 to 10, characterized in that, The ends of the first groove are all connected.

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