Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes: a stacked structure having a conductive layer and an insulating layer stacked alternately with each other; a channel layer passing through the stacked structure; a ferroelectric layer surrounding a sidewall of the channel layer; a first dielectric layer surrounding a sidewall of the ferroelectric layer; and a sacrificial pattern interposed between the first dielectric layer and the insulating layer and including a material having a higher dielectric constant than the first dielectric layer.

Description

Technical Field

[0001] Various embodiments of the present invention generally relate to electronic devices, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] A non-volatile memory device retains stored data regardless of power-on / power-off conditions. Recently, an increase in the integration degree of two-dimensional non-volatile memory devices in which memory cells are formed as a single layer above a substrate has been limited. Thus, three-dimensional non-volatile memory devices in which memory cells are stacked in a vertical direction above a substrate have been proposed.

[0003] A three-dimensional non-volatile memory device may include an interlayer insulating layer and a gate electrode alternately stacked with each other and a channel layer passing therethrough, wherein memory cells are stacked along the channel layer. Various structures and manufacturing methods have been developed to improve the operation reliability of three-dimensional non-volatile memory devices. Summary of the Invention

[0004] According to an embodiment, a semiconductor device may include: a stacked structure having a conductive layer and an insulating layer alternately stacked with each other; a channel layer passing through the stacked structure; a ferroelectric layer surrounding sidewalls of the channel layer; a first dielectric layer surrounding sidewalls of the ferroelectric layer; and a sacrificial pattern interposed between the first dielectric layer and the insulating layer, the sacrificial pattern including a material having a higher dielectric constant than the first dielectric layer.

[0005] According to an embodiment, a method of manufacturing a semiconductor device may include: forming a stacked structure having a first material layer and a second material layer alternately stacked with each other; forming a first opening passing through the stacked structure, the first opening having an inner wall having a second material layer protruding further than the first material layer; forming a sacrificial layer in the first opening; forming a first dielectric layer in the sacrificial layer, the first dielectric layer having a lower dielectric constant than the sacrificial layer; forming a ferroelectric layer in the first dielectric layer; and forming a channel layer in the ferroelectric layer. Brief Description of the Drawings

[0006] Figures 1A to 1C is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure;

[0007] Figures 2A to 2C is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure;

[0008] Figure 3A and Figure 3B is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure;

[0009] Figure 4A and Figure 4Bis a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0010] Figures 5A to 5C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0011] Figures 6A to 6C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 7A and Figure 7B is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 8A and Figure 8B is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0014] Figures 9A to 9E is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0015] Figures 10A to 10C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0016] Figures 11A to 11D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0017] Figures 12A to 12C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0018] Figure 13A and Figure 13B is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0019] Figure 14 is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0020] Figure 15 is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0021] Figure 16 is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0022] Figure 17 is a diagram illustrating a memory system according to an embodiment of the present disclosure; and

[0023] Figure 18 is a diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Description

[0024] The specific structural or functional descriptions of examples of embodiments according to the concepts disclosed in this specification are merely illustrative for describing examples of embodiments according to the concepts, and examples of embodiments according to the concepts can be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0025] In the following description of embodiments, when a parameter is referred to as "predetermined", it can be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter can be set at the start of the process or algorithm, or the value of the parameter can be set during the period of executing the process or algorithm.

[0026] It will be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, without departing from the teachings of the present disclosure, a first element in some embodiments can be referred to as a second element in other embodiments.

[0027] Furthermore, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0028] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same.

[0029] Figures 1A to 1C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1B and Figure 1C illustrates Figure 1A the A-A' cross-section of

[0030] Referring to Figures 1A to 1C , the semiconductor device can include a conductive layer 11, a channel layer 15, a ferroelectric layer 14, a first dielectric pattern 17A, and an air gap AG. The semiconductor device can also include a sealing layer 12, a mask pattern 13, a gap filling layer 16, a first dielectric pattern 17B, a sacrificial pattern 18, a second dielectric layer 19, or a combination thereof.

[0031] The semiconductor device can include a stacked structure ST and a stacked conductive layer 11. According to an embodiment, the stacked structure ST can include the conductive layer 11 and the air gap AG stacked alternately with each other. The mask pattern 13 can be located above the stacked structure ST. The mask pattern 13 can include a nitride, a carbon-based material, or a combination thereof.

[0032] The conductive layer 11 may be a gate electrode of a select transistor, a memory cell, etc. The conductive layer 11 may include a metal such as tungsten or molybdenum, or a conductive material such as polysilicon or silicide. The air gap AG may be a hollow space not filled with a material layer and may be filled with air.

[0033] Each air gap AG may include a first portion P1 interposed between the conductive layers 11 and a second portion P2 protruding further toward the channel layer 15 than the conductive layer 11. In the third direction III, the second portion P2 may have a greater width than the first portion P1. The conductive layer 11 and the air gap AG may be stacked in the third direction III.

[0034] The slit SL may pass through the stacked structure ST in the third direction III. The sealing layer 12 may be formed to fill a part of the slit SL. The sealing layer 12 may include an insulating material such as an oxide.

[0035] The sealing layer 12 may include either or both of a first sealing layer 12A and a second sealing layer 12B. The first sealing layer 12A may include a first portion 12A1 formed in the slit SL and a second portion 12A2 extending into the stacked conductive layer 11. The second portion 12A2 may extend between the first dielectric patterns 17A and 17B and contact the ferroelectric layer 14. The air gap AG may be located in the second portion 12A2, respectively.

[0036] The second portion 12A2 may include a flat inner surface, an inclined inner surface, or a combination thereof. For example, when the second portion 12A2 includes an inclined inner surface, the thickness of the inner surface of the second portion 12A2 near the slit SL may be greater than the thickness of the inner surface near the channel layer 15. The second sealing layer 12B may be formed in the slit SL. The region of the air gap AG may be defined by either or both of the first sealing layer 12A and the second sealing layer 12B.

[0037] The channel layer 15 may pass through the stacked structure ST in the third direction III. A plurality of channel layers 15 may be arranged in the first direction I and the second direction II, and the second direction intersects the first direction I. The second direction II may be orthogonal to the first direction I. The third direction III may intersect the first direction I and the second direction II. According to an embodiment, the third direction III may protrude from the plane defined by the first direction I and the second direction II. The channel layer 15 may include a semiconductor material such as silicon, germanium, or polysilicon, or may include a nanostructure.

[0038] The channel layer 15 may have the following structures: a tubular structure with an open central region, a structure with a solid central region, or a combination thereof. The channel layer 15 may have an irregular inner surface, an irregular outer surface, or both an irregular inner surface and an irregular outer surface. When the inner surface or the outer surface of the channel layer 15 has an irregular structure, the channel layer 15 may have a relatively large width at a height corresponding to the conductive layer 11 and may have a relatively small width at a height corresponding to the air gap AG.

[0039] The gap filling layer 16 may be formed in the channel layer 15, and the gap filling layer 16 may include an insulating material such as an oxide or a nitride.

[0040] The ferroelectric layer 14 may be formed to surround the sidewalls of the channel layer 15. The ferroelectric layer 14 may be interposed between the channel layer 15 and the conductive layer 11 and between the channel layer 15 and the air gap AG. Additionally, the ferroelectric layer 14 may be interposed between the channel layer 15 and the mask pattern 13.

[0041] The ferroelectric layer 14 may surround the second portion P2 of the air gap AG. The ferroelectric layer 14 may include a first portion 14P1 surrounding the sidewalls of the channel layer 15 and a second portion 14P2 protruding from the first portion 14P1. The second portion 14P2 of the ferroelectric layer 14 may extend between the second portions P2 of the air gap AG.

[0042] The sidewalls of the ferroelectric layer 14 may include trenches defined between the second portions 14P2. The trenches may be located at a height corresponding to the air gap AG. Either or both of the air gap AG and the first sealing layer 12A may be located in the trenches, respectively.

[0043] The ferroelectric layer 14 may include an irregular or flat inner surface. Referring to Figure 1B , the inner surface of the ferroelectric layer 14 may be curved along the contour of the second portion P2 of the air gap AG. Referring to Figure 1C , the ferroelectric layer 14 may have a flat inner surface. The inner surface of the ferroelectric layer 14 may be an etched surface. The channel layer 15 may thus have a flat outer surface and an inner surface.

[0044] The first dielectric pattern 17A may be interposed between the ferroelectric layer 14 and the conductive layer 11. The first dielectric pattern 17B may be interposed between the ferroelectric layer 14 and the mask pattern 13. The first dielectric patterns 17A and 17B may include a material having a larger bandgap than the ferroelectric layer 14. The first dielectric patterns 17A and 17B may include an oxide. According to an embodiment, the first dielectric patterns 17A and 17B may include silicon oxide (SiO2).

[0045] Each first dielectric pattern 17A may include a first thickness T1 in a first direction I and a first length L1 in a third direction III. The conductive layer 11 may have a second thickness T2 in the third direction III. The first length L1 may have a value that is substantially the same as or less than the second thickness T2.

[0046] However, when the first thickness T1 is too small, it may be difficult to prevent gate breakdown of the memory cell. On the other hand, when the first thickness T1 is too large, the ferroelectric characteristics may deteriorate due to the depolarization field. Therefore, the first thickness T1 may be determined in consideration of gate breakdown of the memory cell and deterioration of the ferroelectric characteristics caused by the depolarization field. The first thickness T1 may be in the range from to .

[0047] The sacrificial pattern 18 may be interposed between the first dielectric pattern 17B and the mask pattern 13. The sacrificial pattern 18 may be a residue of a protective layer used during the manufacturing process. The sacrificial pattern 18 may include a material having a high etch selectivity with respect to an oxide or a nitride. The sacrificial pattern 18 may include a material having a higher dielectric constant than the first dielectric patterns 17A and 17B. The sacrificial pattern 18 may include a high-k material and may include titanium (Ti), zirconium (Zr), or hafnium (Hf). According to an embodiment, the sacrificial pattern 18 may include a high-k material doped with silicon (Si).

[0048] The second dielectric layer 19 may surround the ferroelectric layer 14. The second dielectric layer 19 may be interposed between the ferroelectric layer 14 and the first dielectric pattern 17A, between the ferroelectric layer 14 and the air gap AG, and between the ferroelectric layer 14 and the first sealing layer 12A. The second dielectric layer 19 may improve the adhesion of the ferroelectric layer 14 with respect to the first sealing layer 12A and the first dielectric patterns 17A and 17B.

[0049] The second dielectric layer 19 may include a material having a higher dielectric constant than the first dielectric patterns 17A and 17B. According to an embodiment, the second dielectric layer 19 may include a high-k material and may include SiO2, HfO2, ZrO2, La2O3, TiO2, etc. Alternatively, the second dielectric layer 19 may include a material having a larger bandgap than the ferroelectric layer 14. According to an embodiment, the second dielectric layer 19 may include SiO2.

[0050] According to the above structure, the transistor may be located at the intersection between the channel layer 15 and the conductive layer 11. The transistor may be a memory cell or a select transistor. Each memory cell may include a ferroelectric layer 14 and may store data based on the polarization state of the ferroelectric layer 14.

[0051] An air gap AG may exist between stacked memory cells. The air gap AG may protrude further toward the channel layer 15 than the conductive layer 11. Accordingly, the edge field in the spatial region between the memory cells can be effectively controlled. Interference between the memory cells and the parasitic capacitor between the stacked memory cells can be reduced.

[0052] Each memory cell may include a first dielectric pattern 17A and a second dielectric layer 19. When the first dielectric pattern 17A includes a material having a larger bandgap than the ferroelectric layer 14, the gate breakdown voltage of the memory cell can be ensured. In the same manner, when the second dielectric layer 19 includes a material having a larger bandgap than the ferroelectric layer 14, the breakdown voltage of the memory cell can be ensured.

[0053] When the second dielectric layer 19 includes a high-k material, the intensity of the electric field applied to the second dielectric layer 19 can be reduced, and the intensity of the electric field applied to the ferroelectric layer 14 can be increased. Accordingly, the voltage level of the operation voltage used during a programming operation, a read operation, or an erase operation can be reduced, and the memory window can be improved.

[0054] Figures 2A to 2C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2B and Figure 2C shows Figure 2A a B-B' cross section. Hereinafter, any repeated detailed description of the components already mentioned above will be omitted.

[0055] Referring to Figures 2A to 2C , the semiconductor device may include a conductive layer 11, a channel layer 15, a ferroelectric layer 14, a first dielectric pattern 17A, and an air gap AG. The semiconductor device may further include a sealing layer 12, a mask pattern 13, a gap filling layer 16, a first dielectric pattern 17B, a sacrificial pattern 18, a second dielectric layer 19, a third dielectric layer 20, or a combination thereof.

[0056] The third dielectric layer 20 may surround the sidewalls of the channel layer 15. The third dielectric layer 20 may be interposed between the channel layer 15 and the ferroelectric layer 14. The adhesion between the ferroelectric layer 14 and the channel layer 15 can be improved through the third dielectric layer 20.

[0057] The third dielectric layer 20 may be formed along the inner surface of the ferroelectric layer 14. Referring to Figure 2B , the inner surface of the ferroelectric layer 14 may have a profile in which the grooves of its outer surface are transferred to the inner surface. The inner surface of the ferroelectric layer 14 may be curved, and the third dielectric layer 20 may be conformally formed along the curved inner surface of the ferroelectric layer 14. Referring to Figure 2C, the ferroelectric layer 14 may have a flat inner surface. The inner surface of the ferroelectric layer 14 may be an etched surface, and the third dielectric layer 20 may be conformally formed along the flat inner surface. Accordingly, the third dielectric layer 20 or the channel layer 15 may have a flat outer surface and a flat inner surface.

[0058] Compared with the second dielectric layer 19, the third dielectric layer 20 may include substantially the same or different materials. The third dielectric layer 20 may include a material having a higher dielectric constant than the first dielectric pattern 17A. According to an embodiment, the third dielectric layer 20 may include a high-k material and may include SiO2, HfO2, ZrO2, La2O3, TiO2, etc. Alternatively, the third dielectric layer 20 may include a material having a larger bandgap than the ferroelectric layer 14. According to an embodiment, the third dielectric layer 20 may include SiO2.

[0059] According to the above structure, the memory cell may include the first dielectric pattern 17A and the second dielectric layer 19, or the first dielectric pattern 17A and the third dielectric layer 20, or the first dielectric pattern 17A, the second dielectric layer 19, and the third dielectric layer 20.

[0060] Figure 3A and Figure 3B are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3B The C-C′ cross-section is shown. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0061] Referring to Figure 3A and Figure 3B , the semiconductor device may include a conductive layer 11, a channel layer 15, a ferroelectric pattern 24A, a first dielectric pattern 17A, and an air gap AG. The semiconductor device may further include a sealing layer 12, a mask pattern 13, a gap filling layer 16, a first dielectric pattern 17B, a sacrificial pattern 18, a second dielectric pattern 19A, a second dielectric pattern 19B, a ferroelectric pattern 24B, or a combination thereof.

[0062] The ferroelectric pattern 24A may be formed to surround the sidewalls of the channel layer 15. The ferroelectric pattern 24A may be located at a height corresponding to the conductive layer 11 and may be separated from each other. The ferroelectric pattern 24B may be interposed between the channel layer 15 and the mask pattern 13.

[0063] The first dielectric pattern 17A may be interposed between the ferroelectric pattern 24A and the conductive layer 11. The first dielectric pattern 17B may be interposed between the ferroelectric pattern 24B and the mask pattern 13.

[0064] The second dielectric pattern 19A may be interposed between the ferroelectric pattern 24A and the first dielectric pattern 17A. Additionally, the second dielectric pattern 19A may extend between the ferroelectric pattern 24A and the first sealing layer 12A. The second dielectric pattern 19A may have a C-shaped cross-section such that each second dielectric pattern 19A may surround each ferroelectric pattern 24B. The second dielectric pattern 19A may be interposed only between the ferroelectric pattern 24A and the first dielectric pattern 17A. The second dielectric pattern 19A may have an I-shaped cross-section. The second dielectric pattern 19B may be interposed between the ferroelectric pattern 24B and the first dielectric pattern 17B.

[0065] The air gap AG may be interposed between the conductive layers 11 and may extend between the ferroelectric patterns 24A. The ferroelectric patterns 24A may be located between the second portions P2 of the air gap AG.

[0066] According to the above structure, the memory cells may respectively include the ferroelectric patterns 24A. When stacked memory cells share a ferroelectric layer, interference may occur between the stacked memory cells in the third direction III. For example, when programming the second memory cell after programming the first memory cell, an electric field larger than the coercive field (Ec) may be applied to the ferroelectric layer in the spatial region through the fringe field caused by the programming operation of the first memory cell. Additionally, when the second memory cell is programmed to a polarization state different from that of the first memory cell, an electric field larger than the coercive field (Ec) may be applied to the first memory cell or the ferroelectric layer in the spatial region through the fringe field caused by the programming operation of the second memory cell. As a result, the threshold voltage of the first memory cell may be changed and the programming / erasing window may be reduced. As the distance between the stacked memory cells decreases, this interference phenomenon may deteriorate. Additionally, the fringe field may make it difficult to control the ferroelectric layer in the spatial region. Thus, according to an embodiment, the ferroelectric patterns 24A may be formed by removing the ferroelectric layer in the spatial region. Since the memory cells respectively include the ferroelectric patterns 24A, interference may be reduced or prevented, and reliability may be improved.

[0067] Figure 4A and Figure 4B are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 4B Shows Figure 4A the D-D′ cross-section. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0068] Referring to Figure 4A and Figure 4B, the semiconductor device may include a conductive layer 11, a channel layer 15, a ferroelectric pattern 24A, a first dielectric pattern 17A, and an air gap AG. The semiconductor device may further include a sealing layer 12, a mask pattern 13, a gap filling layer 16, a first dielectric pattern 17B, a sacrificial pattern 18, a second dielectric pattern 19A, a second dielectric pattern 19B, a ferroelectric pattern 24B, a third dielectric layer 20, or a combination thereof.

[0069] The third dielectric layer 20 may surround the sidewalls of the channel layer 15. The third dielectric layer 20 may be interposed between the channel layer 15 and the ferroelectric patterns 24A and 24B. The third dielectric layer 20 may be interposed between the channel layer 15 and the air gap AG and between the channel layer 15 and the first sealing layer 12A. The adhesion between the ferroelectric patterns 24A and 24B and the channel layer 15 may be improved through the third dielectric layer 20. The third dielectric layer 20 may be conformally formed along the inner surfaces of the ferroelectric patterns 24A and 24B.

[0070] According to the above structure, the memory cell may include the first dielectric pattern 17A and the second dielectric pattern 19A, or the first dielectric pattern 17A and the third dielectric layer 20, or the first dielectric pattern 17A, the second dielectric pattern 19A, and the third dielectric layer 20.

[0071] Figures 5A to 5C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 5B and Figure 5C shows Figure 5A the E-E' cross-section. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0072] Referring to Figures 5A to 5C , the semiconductor device may include a stacked structure ST, a channel layer 35, a ferroelectric layer 34, a first dielectric layer 37, and a sacrificial pattern 38A. The semiconductor device may further include a gap filling layer 36, a sacrificial pattern 38B, a second dielectric layer 39, or a combination thereof.

[0073] The stacked structure ST may include a conductive layer 31 and an insulating layer 32 that are alternately stacked with each other. A mask pattern 33 may be located above the stacked structure ST. The mask pattern 33 may include a nitride, a carbon-based material, or a combination thereof.

[0074] The conductive layer 31 may be a gate electrode of a select transistor, a memory cell, etc. The conductive layer 31 may include a metal such as tungsten or molybdenum or a conductive material such as polysilicon or silicide. The insulating layer 32 may insulate the gate electrodes from each other and may include an insulating material such as an oxide or a nitride.

[0075] Each insulating layer 32 may include a first portion P1 interposed between the conductive layers 31 and a second portion P2 protruding further toward the channel layer 35 than the conductive layers 31. The second portion P2 may include a rounded edge. In the third direction III, the width of the second portion P2 may be substantially the same as, greater than, or less than the width of the first portion P1.

[0076] The channel layer 35 may pass through the stacked structure ST in the third direction III. A plurality of channel layers 35 may be arranged in the first direction I and the second direction II. The channel layer 35 may include a semiconductor material such as silicon, germanium, or polysilicon, or may include a nanostructure.

[0077] The channel layer 35 may have the following structure: a tubular structure having an open central region, a structure having a solid central region, or a combination thereof. The channel layer 35 may have an irregular inner surface, an irregular outer surface, or both an irregular inner surface and an irregular outer surface. When the inner surface or the outer surface of the channel layer 35 has irregularities, the channel layer 35 may have a relatively large width at a height corresponding to the conductive layer 31 and a relatively small width at a height corresponding to the insulating layer 32.

[0078] The gap filling layer 36 may be formed in the channel layer 35 and may include an insulating material such as an oxide or a nitride.

[0079] The ferroelectric layer 34 may be formed to surround the sidewalls of the channel layer 35. The ferroelectric layer 34 may be interposed between the channel layer 35 and the conductive layer 31 and between the channel layer 35 and the insulating layer 32. In addition, the ferroelectric layer 34 may be interposed between the channel layer 35 and the mask pattern 33.

[0080] The ferroelectric layer 34 may surround the second portion P2 of the insulating layer 32. The ferroelectric layer 34 may include a first portion 34P1 surrounding the sidewalls of the channel layer 35 and a second portion 34P2 protruding from the first portion 34P1. The second portion 34P2 of the ferroelectric layer 34 may extend between the second portions P2 of the insulating layer 32.

[0081] The sidewalls of the ferroelectric layer 34 may include grooves defined between the second portions 34P2. The grooves may be located at a height corresponding to the insulating layer 32. Each insulating layer 32 may be located in each groove. Additionally, the sacrificial patterns 38A and 38B, the first dielectric layer 37, the second dielectric layer 39, or a combination thereof may also be formed in each groove.

[0082] The ferroelectric layer 34 may include an irregular or flat inner surface. Referring to Figure 5B , the inner surface of the ferroelectric layer 34 may be curved along the contour of the second portion P2 of the insulating layer 32. Referring to Figure 5C, the ferroelectric layer 34 may have a flat inner surface. The inner surface of the ferroelectric layer 34 may be an etched surface. The channel layer 35 may thus have a flat outer surface or inner surface.

[0083] The first dielectric layer 37 may surround the sidewalls of the ferroelectric layer 34. The first dielectric layer 37 may be interposed between the ferroelectric layer 34 and the conductive layer 31, and between the ferroelectric layer 34 and the insulating layer 32. Additionally, the first dielectric layer 37 may be interposed between the ferroelectric layer 34 and the mask pattern 33.

[0084] The first dielectric layer 37 may include a material having a larger bandgap than the ferroelectric layer 34. The first dielectric layer 37 may include an oxide. According to an embodiment, the first dielectric layer 37 may include SiO2.

[0085] The sacrificial pattern 38A may be interposed between the ferroelectric layer 34 and the insulating layer 32. Each sacrificial pattern 38A may surround each second portion P2 of the insulating layer 32. The sacrificial pattern 38B may be interposed between the first dielectric layer 37 and the mask pattern 33. The sacrificial patterns 38A and 38B may be separated from each other by the conductive layer 31.

[0086] The sacrificial patterns 38A and 38B may include a material having a high etch selectivity with respect to an oxide or a nitride. The sacrificial patterns 38A and 38B may include a material having a higher dielectric constant than the first dielectric layer 37. The sacrificial patterns 38A and 38B may include a high-k material and may include titanium (Ti), zirconium (Zr), or hafnium (Hf). According to an embodiment, the sacrificial patterns 38A and 38B may include a high-k material doped with silicon (Si). The sacrificial patterns 38A and 38B may have a thickness in the range from to range.

[0087] The second dielectric layer 39 may surround the ferroelectric layer 34. The second dielectric layer 39 may be interposed between the ferroelectric layer 34 and the first dielectric layer 37. The adhesion between the ferroelectric layer 34 and the first dielectric layer 37 may be improved through the second dielectric layer 39.

[0088] The second dielectric layer 39 may include a material having a higher dielectric constant than the first dielectric layer 37. According to an embodiment, the second dielectric layer 39 may include a high-k material and may include SiO2, HfO2, ZrO2, La2O3, TiO2, etc. Alternatively, the second dielectric layer 39 may include a material having a larger bandgap than the ferroelectric layer 34. According to an embodiment, the second dielectric layer 39 may include SiO2.

[0089] According to the above structure, the insulating layer 32 can be located between the stacked memory cells, and the insulating layer 32 can protrude further toward the channel layer 35 than the conductive layer 31. The insulating layer 32 can protrude into the space region between the memory cells such that a depolarization field can be generated in the space region through the insulating layer 32. Accordingly, the polarization of the ferroelectric layer 34 in the space region can be prevented or reduced.

[0090] Each memory cell can include a first dielectric layer 37 and a second dielectric layer 39. When the first dielectric layer 37 includes a material having a larger bandgap than the ferroelectric layer 34, the gate breakdown voltage of the memory cell can be ensured. In the same manner, when the second dielectric layer 39 includes a material having a larger bandgap than the ferroelectric layer 34, the gate breakdown voltage of the memory cell can be ensured.

[0091] When the second dielectric layer 39 includes a high-k material, the intensity of the electric field applied to the second dielectric layer 39 can be reduced, and the intensity of the electric field applied to the ferroelectric layer 34 can be increased. Accordingly, the voltage level of the operation voltage used during a programming operation, a read operation, or an erase operation can be reduced, and the memory window can be improved.

[0092] Figures 6A to 6C is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 6B and Figure 6C shows Figure 6A the F-F′ cross-section. Hereinafter, any repeated detailed description of the components already mentioned above will be omitted.

[0093] Referring to Figures 6A to 6C , the semiconductor device can include a stacked structure ST, a channel layer 35, a ferroelectric layer 34, a first dielectric layer 37, and a sacrificial pattern 38A. The semiconductor device can further include a gap-fill layer 36, a sacrificial pattern 38B, a second dielectric layer 39, a third dielectric layer 40, or a combination thereof.

[0094] The third dielectric layer 40 can surround the sidewalls of the channel layer 35. The third dielectric layer 40 can be interposed between the channel layer 35 and the ferroelectric layer 34. The adhesion between the ferroelectric layer 34 and the channel layer 35 can be improved through the third dielectric layer 40.

[0095] The third dielectric layer 40 can be formed along the inner surface of the ferroelectric layer 34. Referring to Figure 6B , the inner surface of the ferroelectric layer 34 can have a profile in which the grooves of its outer wall are transferred to its inner surface. The inner surface of the ferroelectric layer 34 can be curved, and the third dielectric layer 40 can be conformally formed along the curved inner surface of the ferroelectric layer 34. Referring to Figure 6C, the ferroelectric layer 34 may have a flat inner surface. The inner surface of the ferroelectric layer 34 may be an etched surface, and the third dielectric layer 40 may be conformally formed along the flat inner surface.

[0096] Compared with the second dielectric layer 39, the third dielectric layer 40 may include substantially the same or different materials. The third dielectric layer 40 may include a material having a higher dielectric constant than the first dielectric layer 37. According to an embodiment, the third dielectric layer 40 may include a high-k material and may include SiO2, HfO2, ZrO2, La2O3, TiO2, etc. Alternatively, the third dielectric layer 40 may include a material having a larger bandgap than the ferroelectric layer 34. According to an embodiment, the third dielectric layer 40 may include SiO2.

[0097] According to the above structure, the memory cell may include the first dielectric layer 37 and the second dielectric layer 39, or the first dielectric layer 37 and the third dielectric layer 40, or the first dielectric layer 37, the second dielectric layer 39, and the third dielectric layer 40.

[0098] Figure 7A and Figure 7B are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 7B shows Figure 7A the G-G' cross-section. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0099] Referring to Figure 7A and Figure 7B , the semiconductor device may include a stacked structure ST, a channel layer 35, a ferroelectric pattern 34A, a first dielectric layer 37, and a sacrificial pattern 38A. The semiconductor device may further include a ferroelectric pattern 34B, a gap-fill layer 36, a second dielectric pattern 39A, a second dielectric pattern 39B, or a combination thereof.

[0100] The ferroelectric pattern 34A may be formed to surround the sidewalls of the channel layer 35. The ferroelectric pattern 34A may be located at a height corresponding to the conductive layer 31 and may be separated from each other. The first dielectric layer 37 may be interposed between the ferroelectric pattern 34A and the conductive layer 31 and between the channel layer 35 and the insulating layer 32. The ferroelectric pattern 34B may be interposed between the channel layer 35 and the mask pattern 33. The second dielectric pattern 39B may be interposed between the ferroelectric pattern 34B and the first dielectric layer 37.

[0101] The insulating layer 32 may be interposed between the conductive layers 31 and may extend between the ferroelectric patterns 34A. The ferroelectric patterns 34A may be respectively located between the second portions P2 of the insulating layer 32.

[0102] According to the above structure, the memory cell may include a ferroelectric pattern 34A, respectively. Although not shown, the semiconductor device may further include a third dielectric layer 40 around the sidewall of the channel layer 35 as Figures 6A to 6C shown.

[0103] Figure 8A and Figure 8B are diagrams illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 8B Shows Figure 8A the H-H' cross section. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0104] Referring to Figure 8A and Figure 8B , the semiconductor device may include a stacked structure ST, a channel layer 35, a ferroelectric layer 34, a first dielectric layer 37, and a sacrificial pattern 38A. The semiconductor device may further include a gap-fill layer 36, a sacrificial pattern 38B, a second dielectric layer 39, an air gap AG, a sealing layer 42, or a combination thereof.

[0105] The stacked structure ST may include a conductive layer 31 and an insulating layer stacked alternately with each other. The insulating layer may include an air gap AG. The insulating layer may be a part of the sealing layer 42. The slit SL may pass through the stacked structure ST in the third direction III, and the sealing layer 42 may fill at least a part of the slit SL. The sealing layer 42 may include any one or both of a first sealing layer 42A and a second sealing layer 42B. The first sealing layer 42A may fill a part of the slit SL and may extend between the stacked conductive layers 31. The second sealing layer 42B may be formed in the slit SL.

[0106] The region of the air gap AG may be defined by any one or both of the first sealing layer 42A and the second sealing layer 42B. The air gap AG may be a hollow space not filled with a material layer and may be filled with air.

[0107] Each air gap AG may include a first portion P1 and a second portion P2 inserted between the conductive layers 31, and the second portion P2 protrudes further toward the channel layer 35 than the conductive layer 31. In the third direction III, the width of the second portion P2 may be substantially the same as or greater than the width of the first portion P1.

[0108] Each sacrificial pattern 38A may respectively surround the second portion P2 of the air gap AG. The sacrificial pattern 38A may be inserted between the first dielectric layer 37 and the first sealing layer 42A.

[0109] According to the above structure, the air gap AG can be located between the stacked memory cells, and the air gap AG can protrude further toward the channel layer 35 than the conductive layer 31. Therefore, the edge field in the spatial region between the memory cells can be effectively controlled. In addition, the interference between the memory cells and the parasitic capacitor between the stacked memory cells can be reduced.

[0110] Although not shown, the semiconductor device may further include, as Figures 6A to 6C shown, a third dielectric layer 40 interposed between the channel layer 35 and the ferroelectric layer 34. Additionally, the semiconductor device may include Figure 7A and Figure 7B shown ferroelectric patterns 34A and 34B instead of the ferroelectric layer 34, or Figure 7A and Figure 7B shown second dielectric patterns 39A and 39B instead of the second dielectric layer 39.

[0111] Figures 9A to 9E is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0112] Referring to Figure 9A , a stacked structure ST can be formed. The stacked structure ST may include first material layers 51 and second material layers 52 stacked alternately. The first material layer 51 may include a material having a high etching selectivity with respect to the second material layer 52. For example, the first material layer 51 may include a sacrificial material such as nitride, and the second material layer 52 may include an insulating material such as oxide. In another example, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 52 may include an insulating material such as oxide.

[0113] A first opening OP1 may be formed to penetrate the stacked structure ST, and may include an inner wall in which the second material layer 52 protrudes further than the first material layer 51.

[0114] According to an embodiment, after a mask pattern 53 is formed on the stacked structure ST, the stacked structure ST may be etched by using the mask pattern 53 as an etching stop layer to form an opening. Then a second material may be selectively deposited on the second material layer 52 exposed through the opening. As a result, a first opening OP1 having an inner wall in which the second material layer 52 protrudes further than the first material layer 51 can be formed. The second material layer 52 may protrude further into the first opening OP1 than the sidewall of the mask pattern 53. Additionally, due to the characteristics of the deposition process, the protruding portion of the second material layer 52 may have a rounded edge.

[0115] According to an embodiment, after forming the mask pattern 53 on the stack structure ST, the stack structure ST may be etched by using the mask pattern 53 as an etch stop layer to form an opening. The first material layer 51 exposed through the opening may be selectively etched. Accordingly, a first opening OP1 having an inner wall in which the second material layer 52 protrudes further than the first material layer 51 may be formed. Accordingly, the sidewall of the second material layer 52 may be aligned with the sidewall of the mask pattern 53. The sidewall of the first material layer 51 may be separated from the first opening OP1 more than the sidewall of the mask pattern 53. Additionally, during the etching process, an electric field may be concentrated around the protruding edge of the second material layer 52 such that the edge may be rounded.

[0116] Referring Figure 9B , a sacrificial layer 58 may be formed in the first opening OP1. The sacrificial layer 58 may be conformally formed along the inner surface of the first opening OP1. The sacrificial layer 58 may be used as a protective layer in a subsequent process. The sacrificial layer 58 may include a material having a high etch selectivity with respect to the first material layer 51 and the second material layer 52. The sacrificial layer 58 may include a high-k material and may include titanium (Ti), zirconium (Zr), or hafnium (Hf). According to an embodiment, the sacrificial layer 58 may include a high-k material doped with silicon (Si).

[0117] A first dielectric layer 57 may be formed in the sacrificial layer 58, a ferroelectric layer 54 may be formed in the first dielectric layer 57, and a channel layer 55 may be formed in the ferroelectric layer 54. The ferroelectric layer 54 may include a curved or flat inner surface. However, after etching the inner surface of the ferroelectric layer 54 to a predetermined thickness, the channel layer 55 may be formed. The sacrificial layer 58 may include a material having a higher dielectric constant than the first dielectric layer 57. The first dielectric layer 57 may include a material having a larger bandgap than the ferroelectric layer 54. The first dielectric layer 57 may include an oxide such as silicon oxide (SiO2).

[0118] Before forming the ferroelectric layer 54, a second dielectric layer 59 may be formed in the first dielectric layer 57. The second dielectric layer 59 may include a material having a higher dielectric constant than the first dielectric layer 57. According to an embodiment, the second dielectric layer 59 may include a high-k material and may include SiO2, HfO2, ZrO2, La2O3, TiO2, etc. Alternatively, the second dielectric layer 59 may include a material having a larger bandgap than the ferroelectric layer 54. According to an embodiment, the second dielectric layer 59 may include SiO2.

[0119] Additionally, although not shown, before forming the channel layer 55, a third dielectric layer may be formed in the ferroelectric layer 54. The third dielectric layer may include a material having a larger bandgap than the ferroelectric layer 54 or a material having a higher dielectric constant than the first dielectric layer 57.

[0120] The gap filling layer 56 may be included in the channel layer 55. According to an embodiment, after forming the channel material in the ferroelectric layer 54, the gap filling layer 56 may be formed in the channel material. Then, the gap filling layer 56 may be partially etched, and channel material may be additionally formed in the region where the gap filling layer 56 is etched away, thereby forming the channel layer 55.

[0121] Referring to Figure 9C , the slit SL may pass through the mask pattern 53 and the stack structure ST. Subsequently, the second opening OP2 may be formed by selectively etching the first material layer 51 via the slit SL. The first material layer 51 may be etched under the condition that the first material layer 51 includes a material having a high etching selectivity with respect to the sacrificial layer 58 and the second material layer 52. Thus, the first dielectric layer 57 may be protected by the sacrificial layer 58.

[0122] Referring to Figure 9D , the sacrificial layer 58 may be selectively etched through the second opening OP2 to expose the first dielectric layer 57. As a result, a portion of the sacrificial layer 58 at a position corresponding to the second material layer 52 may be retained to form the sacrificial pattern 58A. Also, a portion of the sacrificial layer 58 at a position corresponding to the mask pattern 53 may be retained to form the sacrificial pattern 58B.

[0123] Referring to Figure 9E , the conductive layer 61 may be formed in the second opening OP2. According to an embodiment, the conductive layer 61 including a metal such as tungsten or molybdenum may be formed. Before forming the conductive layer 61, a barrier layer formed of titanium nitride, tantalum nitride, or tungsten nitride may be formed in the second opening OP2.

[0124] According to the above manufacturing method, a memory cell having a ferroelectric layer 54 may be formed. The stacked memory cells may share the ferroelectric layer 54. The second material layer 52 may be located between the stacked memory cells and may protrude further toward the channel layer 55 than the conductive layer 61.

[0125] Figures 10A to 10C is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any repeated detailed description of the components already mentioned above will be omitted.

[0126] Figures 10A to 10C is a diagram illustrating a process performed following the manufacturing process described above with reference to Figures 9A to 9E . Referring to Figure 10A, the third opening OP3 can be formed by selectively etching the second material layer 52 through the slit SL. The second material layer 52 can be etched under the condition that the second material layer 52 has a high etching selectivity with respect to the sacrificial patterns 58A and 58B and the conductive layer 61. Therefore, the first dielectric layer 57 can be protected by the sacrificial patterns 58A and 58B.

[0127] Referring to Figure 10B , the sacrificial patterns 58A and 58B can be selectively etched through the third opening OP3 to expose the first dielectric layer 57. Therefore, the sacrificial pattern 58A can be removed and the first dielectric layer 57 can be exposed. In addition, the portion of the sacrificial pattern 58B exposed through the third opening OP3 can be etched to form a sacrificial pattern 58C. The sacrificial pattern 58C can be interposed between the channel layer 54 and the mask pattern 53.

[0128] The first dielectric layer 57 can be selectively etched through the third opening OP3. The portion of the first dielectric layer 57 exposed through the third opening OP3 can be etched, and the second dielectric layer 59 or the ferroelectric layer 54 can be exposed. The portion of the first dielectric layer 57 interposed between the ferroelectric layer 54 and the conductive layer 61 can be retained to form a first dielectric pattern 57A. The portion of the first dielectric layer 57 interposed between the ferroelectric layer 54 and the mask pattern 53 can be retained to form a first dielectric pattern 57B.

[0129] When the sacrificial patterns 58A and 58B and the first dielectric layer 57 are etched, the third opening OP3 can be extended. Each extended third opening OP3′ can have a uniform width or a varying width based on its area. According to an embodiment, each extended third opening OP3′ can have a first width W1 between the first dielectric patterns 57A and a second width W2 between the conductive layers 61. The first width W1 can be greater than the second width W2.

[0130] Although not shown, the second dielectric layer 59 exposed through the third opening OP3′ can be etched. As a result, the portion of the second dielectric layer 59 exposed through the third opening OP3′ can be removed, and the second dielectric layer 59 can be retained only between the ferroelectric layer 54 and the conductive layer 61. Alternatively, the ferroelectric layer 54 and the second dielectric layer 59 exposed through the third opening OP3′ can be etched. Therefore, the ferroelectric layer 54 and the second dielectric layer 59 can be retained only between the channel layer 55 and the conductive layer 61.

[0131] Referring to Figure 10C, an air gap AG can be formed in the third opening OP3′ by sealing the third opening OP3′. According to an embodiment, by forming a sealing layer 62 in the slit SL, the air gap AG can be respectively formed in the third opening OP3′. The sealing layer 62 may include an insulating material such as an oxide. The sealing layer 62 may include a first sealing layer 62A and may also include a second sealing layer 62B.

[0132] The first sealing layer 62A can be formed along the inner surfaces of the slit SL and the third opening OP3′. The first sealing layer 62A can be interposed between the conductive layers 61 and between the first dielectric patterns 57A. The first sealing layer 62A can contact the second dielectric layer 59 or the ferroelectric layer 54.

[0133] The first sealing layer 62A can be formed by a deposition process. The first sealing layer 62A can have a uniform thickness or a thickness that varies based on its area. The first sealing layer 62A can have a relatively large thickness at the portion where the third opening OP3′ is connected to the slit SL. In each third opening OP3′, the first sealing layer 62A can have an inclined inner surface. At least some of the third opening OP3′ can be sealed by the first sealing layer 62A.

[0134] However, when there is a third opening OP3′ that is not sealed by the first sealing layer 62A, the second sealing layer 62B can be additionally formed. The second sealing layer 62B can be formed along the inner surface of the slit SL. Depending on the situation, the second sealing layer 62B can extend into the third opening OP3′.

[0135] According to the above manufacturing method, a memory cell having a ferroelectric layer 54 can be formed. Additionally, the air gap AG can be located between the stacked memory cells and can protrude further toward the channel layer 55 than the conductive layer 61.

[0136] Figures 11A to 11D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any repeated detailed descriptions of the components mentioned above will be omitted.

[0137] Referring to Figure 11A , a stacked structure ST can be formed. The stacked structure ST can include a first material layer 71 and a second material layer 72 that are alternately stacked. The first material layer 71 can include a material having a high etching selectivity with respect to the second material layer 72. The first opening OP1 can be formed to pass through the stacked structure ST and can include an inner wall where the second material layer 72 protrudes further than the first material layer 71.

[0138] Subsequently, a sacrificial layer 78 can be formed in the first opening OP1. The sacrificial layer 78 can include a material having a high etching selectivity with respect to the first material layer 71 and the second material layer 72. The first dielectric layer 77 can be formed in the sacrificial layer 78, and the ferroelectric layer 74 can be formed in the sacrificial layer 78. The sacrificial layer 78 can include a material having a higher dielectric constant than the first dielectric layer 77. The first dielectric layer 77 can include a material having a larger bandgap than the ferroelectric layer 74. The sacrificial layer 78, the first dielectric layer 77, and the ferroelectric layer 74 can also be formed on the upper surface of the mask pattern 73.

[0139] Before forming the ferroelectric layer 74, a second dielectric layer 79 can be formed in the first dielectric layer 77. The second dielectric layer 79 can include a material having a higher dielectric constant than the first dielectric layer 77. Alternatively, the second dielectric layer 79 can include a material having a larger bandgap than the ferroelectric layer 74.

[0140] Referring to Figure 11B , the ferroelectric layer 74 can be etched to form ferroelectric patterns 74A and 74B. Without using a separate mask pattern, the ferroelectric layer 74 can be etched based on a full etch-back method. The portion of the ferroelectric layer 74 that protrudes relatively into the first opening OP1 can be... The ferroelectric pattern 74A can be formed between the protruding second material layers 72. Additionally, the ferroelectric pattern 74B can be formed on the sidewalls of the mask pattern 73.

[0141] When etching the ferroelectric layer 74, the second dielectric layer 79 can be exposed. The exposed second dielectric layer 79 can be etched to form second dielectric patterns 79A and 79B. The second dielectric pattern 79A can be located between the protruding second material layers 72. The second dielectric pattern 79A can respectively surround the ferroelectric pattern 74A and can have a C-shaped cross-section. The second dielectric pattern 79B can be formed on the sidewalls of the mask pattern 73 and can be interposed between the ferroelectric pattern 74B and the first dielectric layer 77.

[0142] Although not shown, a third dielectric layer can be formed in the first opening OP1. The third dielectric layer can include a material having a larger bandgap than the ferroelectric layer 74 or a material having a higher dielectric constant than the first dielectric layer 77.

[0143] Referring to Figure 11C , a channel layer 75 and a gap-fill layer 76 can be formed in the first opening OP1. A slit SL can be formed through the mask pattern 73 and the stack structure ST. Subsequently, a second opening OP2 can be formed by selectively etching the first material layer 71 via the slit SL. The first material layer 71 can be etched under the condition that the first material layer 71 includes a material having a high etching selectivity with respect to the sacrificial layer 78 and the second material layer 72.

[0144] Referring to Figure 11D , the sacrificial patterns 78A and 78B can be formed by selectively etching the sacrificial layer 78 through the second opening OP2. As a result, the first dielectric layer 77 can be exposed. Subsequently, the conductive layer 81 can be formed in the second opening OP2.

[0145] According to the above manufacturing method, memory cells each including the ferroelectric pattern 74A can be formed.

[0146] Figures 12A to 12C FIG. is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any repeated detailed description of the components already mentioned above will be omitted.

[0147] Figures 12A to 12C FIG. is a diagram illustrating a process performed after the manufacturing process described above with reference to Figures 11A to 11D . Referring to Figure 12A , the third opening OP3 can be formed by selectively etching the second material layer 72 through the slit SL. The second material layer 72 can be etched under the condition that the second material layer 72 has a high etching selectivity with respect to the sacrificial patterns 78A and 78B and the conductive layer 81.

[0148] Referring to Figure 12B , the sacrificial patterns 78A and 78B and the first dielectric layer 77 can be etched through the third opening OP3. As a result, the channel layer 75 can be exposed, and the sacrificial pattern 78C and the first dielectric patterns 77A and 77B can be formed. As a result, the third opening OP3' can extend toward the channel layer 75.

[0149] Subsequently, the second dielectric patterns 79A and 79B, or the second dielectric patterns 79A and 79B and the ferroelectric patterns 74A and 74B can be etched through the third opening OP3'. As a result, the third opening OP3' can further extend toward the channel layer 75. In addition, even if the ferroelectric patterns 74A and 74B are not completely separated during the etching of the ferroelectric layer 74, the ferroelectric patterns 74A and 74B can be completely separated by additionally etching the ferroelectric layer 74.

[0150] Referring to Figure 12C , by forming the sealing layer 82, the air gaps AG can be formed in the third openings OP3' respectively. The sealing layer 82 can include either or both of the first sealing layer 82A and the second sealing layer 82B.

[0151] According to the above manufacturing method, memory cells each including the ferroelectric pattern 74A can be formed. In addition, the air gaps AG can be formed in the conductive layer 81 and extending between the ferroelectric patterns 74A.

[0152] Figure 13A and Figure 13B are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, any repeated detailed description of the components mentioned above will be omitted.

[0153] Figure 13A and Figure 13B are diagrams illustrating processes performed following the manufacturing process described above with reference to Figures 9A to 9E . Referring to Figure 13A , the third opening OP3 can be formed by selectively etching the second material layer 52 via the slit SL. The second material layer 52 can be etched under the condition that the second material layer 52 includes a material having a high etching selectivity with respect to the sacrificial patterns 58A and 58B and the conductive layer 61. Accordingly, the first dielectric layer 57 can be protected by the sacrificial patterns 58A and 58B.

[0154] Referring to Figure 13B , a sealing layer 62' can be formed such that air gaps AG can be formed in the third opening OP3, respectively. The sealing layer 62' can include either or both of the first sealing layer 62A' and the second sealing layer 62B'. The sacrificial patterns 58A and 58B can be etched before the sealing layer 62' is formed.

[0155] However, the processes described above with reference to Figures 11A to 11D can be performed after the manufacturing process described with reference to Figure 13A and Figure 13B . Additionally, the embodiments described in the present disclosure can be combined with each other.

[0156] Figure 14 is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0157] Referring to Figure 14 , the memory system 1000 can include a memory device 1200 configured to store data and a controller 1100 that performs communication between the memory device 1200 and the host 2000.

[0158] The host 2000 may be a device or system configured to store data in the memory system 1000 or retrieve data from the memory system 1000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. The requests may include a program request for a programming operation, a read request for a read operation, and an erase request for an erase operation. The host 2000 may communicate with the memory system 1000 by using at least one interface protocol among Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0159] The host 2000 may include at least one of a computer, a portable digital device, a tablet, a digital camera, a digital audio player, a television, a wireless communication device, or a cellular phone. However, embodiments of the disclosed technology are not limited thereto.

[0160] The controller 1100 may control the overall operation of the memory system 1000. The controller 1100 may control the memory device 1200 in response to a request from the host 2000. The controller 1100 may control the memory device 1200 at the request of the host 2000 to perform a programming operation, a read operation, and an erase operation. Alternatively, the controller 1100 may perform a background operation for improving the performance of the memory system 1000 without a request from the host 2000.

[0161] To control the operation of the memory device 1200, the controller 1100 may transmit control signals and data signals to the memory device 1200. The control signals and data signals may be transmitted to the memory device 1200 through different input / output lines. The data signals may include commands, addresses, or data. The control signals may be used to distinguish the time periods of the input data signals.

[0162] The memory device 1200 may perform a programming operation, a read operation, and an erase operation in response to the control of the controller 1100. The memory device 1200 may be a volatile memory that loses data when power is cut off or a non-volatile memory that retains data even without power supply. According to an embodiment, the memory device 1200 may be the above-described semiconductor device, which may be a flash memory device.

[0163] Upon a request from the host 2000 for a programming operation, a read operation, or an erase operation, the controller 1100 may command a device having the structure described above with reference to Figures 1A to 8B as described or by reference toFigures 9A to 13B A memory device 1200 fabricated by the described method is used to perform a programming operation, a read operation, or an erase operation. In this way, cell performance characteristics and retention characteristics can be improved.

[0164] Figure 15 FIG. is an illustration of a memory system 30000 according to an embodiment of the present disclosure.

[0165] Referring Figure 15 , the memory system 30000 can be implemented as a cellular phone, a smart phone, a tablet, a personal computer (PC), a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 that controls operations of the memory device 2200.

[0166] The controller 2100 can control data access operations of the memory device 2200 in response to control by a processor 3100. For example, programming operations, erase operations, or read operations of the memory device 2200.

[0167] In response to control by the controller 2100, data programmed into the memory device 2200 can be output through a display 3200.

[0168] A radio transceiver 3300 can exchange radio signals through an antenna ANT. For example, the radio transceiver 3300 can change a radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Thus, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the controller 2100 or the display 3200. The controller 2100 can transmit the signal processed by the processor 3100 into the memory device 2200. In addition, the radio transceiver 3300 can change a signal output from the processor 3100 into a radio signal and output the radio signal to an external device through the antenna ANT. A control signal for controlling the operation of the host or data to be processed by the processor 3100 can be input through an input device 3400, and the input device 3400 may include a pointing device such as a touchpad and a computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200 such that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0169] According to an embodiment, the controller 2100 capable of controlling operations of the memory device 2200 can be implemented as part of the processor 3100 or as a chip separate from the processor 3100.

[0170] Figure 16 FIG. is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0171] Referring to Figure 16 , the memory system 40000 may be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0172] The memory system 40000 may include a memory device 2200 and a controller 2100 that controls data processing operations of the memory device 2200.

[0173] The processor 4100 may output data stored in the memory device 2200 through the display 4300 according to data input through the input device 4200. Examples of the input device 4200 may include a pointing device such as a touchpad or a computer mouse, a keypad, or a keyboard.

[0174] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to an embodiment, the controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as a part of the processor 4100 or as a chip separate from the processor 4100.

[0175] Figure 17 FIG. is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0176] Referring to Figure 17 , the memory system 50000 may be implemented as an image processor, for example, a digital camera, a cellular phone with a digital camera, a smart phone with a digital camera, or a desktop PC with a digital camera.

[0177] The memory system 50000 may include a memory device 2200 and a controller 2100 that controls data processing operations of the memory device 2200, such as a programming operation, an erasing operation, or a reading operation.

[0178] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be transmitted to the processor 5100 or the controller 2100. In response to the control of the processor 5100, the converted digital signal may be output through the display 5300 or stored in the memory device 2200 through the controller 2100. Additionally, in response to the control of the processor 5100 or the controller 2100, data stored in the memory device 2200 may be output through the display 5300.

[0179] According to an embodiment, a controller 2100 capable of controlling the operation of a memory device 2200 may be formed as part of a processor 5100 or a chip separate from the processor 5100.

[0180] Figure 18 FIG. is an illustration of a memory system 70000 according to an embodiment of the present disclosure.

[0181] Referring Figure 18 , the memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0182] The controller 2100 may control data exchange between the memory device 2200 and the card interface 7100. According to an embodiment, the card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface.

[0183] The card interface 7100 may interface data exchange between the host 60000 and the controller 2100 according to the protocol of the host 60000. According to an embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an Inter-Chip (IC)-USB protocol. The card interface 7100 may refer to hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0184] When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, a console video game hardware, or a digital set-top box, the host interface 6200 may perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 in response to the control of the microprocessor 6100.

[0185] According to an embodiment of the present invention, a semiconductor device having a stable structure and improved reliability may be provided.

[0186] Cross-reference to related applications

[0187] This application claims priority to Korean Patent Application No. 10-2020-0087832, filed with the Korean Intellectual Property Office on July 15, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure having a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other; A channel layer passing through the stacked structure; A ferroelectric layer surrounding a sidewall of the channel layer; A first dielectric layer surrounding a sidewall of the ferroelectric layer; And A sacrificial pattern inserted between the first dielectric layer and the insulating layer, the sacrificial pattern comprising a material having a higher dielectric constant than the first dielectric layer.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of insulating layers includes a first portion inserted between the plurality of conductive layers and a second portion protruding further toward the channel layer than the conductive layer.

3. The semiconductor device according to claim 2, wherein, The second portion has a rounded edge.

4. The semiconductor device according to claim 1, wherein, The ferroelectric layer includes trenches on sidewalls of the ferroelectric layer, and Wherein the trenches are located at a height corresponding to the insulating layer.

5. The semiconductor device according to claim 1, further comprising: A second dielectric layer inserted between the first dielectric layer and the ferroelectric layer, the second dielectric layer having a material with a higher dielectric constant than the first dielectric layer.

6. The semiconductor device according to claim 1, further comprising: A second dielectric layer inserted between the first dielectric layer and the ferroelectric layer, the second dielectric layer having a material with a larger bandgap than the ferroelectric layer.

7. The semiconductor device according to claim 1, further comprising: A third dielectric layer inserted between the ferroelectric layer and the channel layer, the third dielectric layer having a material with a higher dielectric constant than the first dielectric layer.

8. The semiconductor device according to claim 1, the semiconductor device further comprising: A third dielectric layer inserted between the ferroelectric layer and the channel layer, the third dielectric layer having a material with a larger bandgap than the ferroelectric layer.

9. The semiconductor device according to claim 1, wherein, Each of the plurality of insulating layers includes air gaps.

10. The semiconductor device according to claim 1, wherein, The ferroelectric layer includes a plurality of ferroelectric patterns inserted between the channel layer and the plurality of conductive layers, and the plurality of ferroelectric patterns are separated from each other.

11. The semiconductor device according to claim 1, wherein, The first dielectric layer includes a material with a larger bandgap than the ferroelectric layer.

12. A method of manufacturing a semiconductor device, the method comprising the following steps: Forming a stacked structure having a first material layer and a second material layer stacked alternately with each other; Forming a first opening passing through the stacked structure, the first opening having an inner wall with the second material layer protruding further than the first material layer; Forming a sacrificial layer in the first opening; Forming a first dielectric layer in the sacrificial layer, the first dielectric layer having a lower dielectric constant than the sacrificial layer; Forming a ferroelectric layer in the first dielectric layer; And Forming a channel layer in the ferroelectric layer.

13. The method according to claim 12, wherein, The step of forming the first opening includes the following steps: Forming a mask pattern on the stacked structure; Etching the stacked structure by using the mask pattern as an etching barrier layer to form an opening; and Selectively etching the first material layer exposed through the opening.

14. The method according to claim 12, wherein The step of forming the first opening includes the following steps: Forming a mask pattern on the stacked structure; Etching the stacked structure by using the mask pattern as an etching barrier layer to form an opening; and Selectively deposit a second material on the second material layer exposed through the opening.

15. The method according to claim 12, the method further comprising the steps of: Form a second dielectric layer in the first dielectric layer before forming the ferroelectric layer, the second dielectric layer having a material with a higher dielectric constant than the first dielectric layer.

16. The method according to claim 12, the method further comprising the following steps: Form a second dielectric layer in the first dielectric layer before forming the ferroelectric layer, the second dielectric layer having a material with a larger bandgap than the ferroelectric layer.

17. The method according to claim 12, the method further comprising the steps of: Form a third dielectric layer in the ferroelectric layer, the third dielectric layer having a material with a higher dielectric constant than the first dielectric layer.

18. The method according to claim 12, the method further comprising the steps of: Form a third dielectric layer in the ferroelectric layer, the third dielectric layer having a material with a larger bandgap than the ferroelectric layer.

19. The method according to claim 12, the method further comprising the steps of: Form a second opening by selectively etching the first material layer; Etch the sacrificial layer through the second opening to expose the first dielectric layer; And Form a conductive layer in the second opening.

20. The method according to claim 12, the method further comprising the steps of: Form a third opening by selectively etching the second material layer; and Form an air gap in the third opening by sealing the third opening.

21. The method according to claim 20, the method further comprising the steps of: Etch the sacrificial layer through the third opening.

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