Image sensor and method of forming the same

Abstract

Various embodiments of the present disclosure are directed to image sensors having a passivation layer for reducing dark current. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap layer and the device layer and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate can be silicon, while the device layer can be germanium or include germanium. A photodetector is located in the device layer and the cap layer, and a passivation layer overlies the cap layer. The passivation layer includes a high-k dielectric material and causes formation of a dipole moment along a top surface of the cap layer. Embodiments of the present application provide image sensors and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to image sensors and methods of forming the same. Background Technology

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have become widely used, largely replacing charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly popular due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-illuminated (FSI) image sensors and back-illuminated (BSI) image sensors. Summary of the Invention

[0003] An embodiment of this application provides an image sensor, comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer and the device layer are semiconductor materials, and wherein the capping layer has a larger band gap than the device layer; a photodetector located in the device layer and the capping layer; and a passivation layer covering the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer.

[0004] Embodiments of this application provide an image sensor, comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer, the device layer, and the substrate are semiconductor materials, and wherein the device layer is a semiconductor material different from the substrate and the capping layer; a photodetector located in the device layer and the capping layer; a first dielectric layer covering and directly contacting the capping layer; and a second dielectric layer covering and directly contacting the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise oxides, and wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer.

[0005] Embodiments of this application provide a method for forming an image sensor, comprising: epitaxially growing a device layer covering a substrate; epitaxially growing a capping layer covering the device layer, wherein the capping layer has a larger band gap than the device layer; forming a photodetector in the device layer and the capping layer; and depositing a passivation layer covering the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer.

[0006] Embodiments of this application provide an image sensor having a passivation layer for reducing dark current. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1B Various cross-sectional views are shown of some embodiments of image sensors in which the passivation layer is configured to reduce dark current.

[0009] Figure 2 Show Figure 1A and Figure 1B Some embodiments of the band diagram at the interface layer of the image sensor.

[0010] Figure 3 Show Figure 1A and Figure 1B Timing diagrams of some embodiments of signals during the operation of an image sensor.

[0011] Figure 4 Show Figure 1A and Figure 1B Equivalent circuits of some embodiments of the image sensor.

[0012] Figure 5A and Figure 5B Show Figure 1A and Figure 1B Various cross-sectional views of some alternative embodiments of image sensors in which the dipole moment polarity is reversed.

[0013] Figure 6 Show Figure 5A and Figure 5B Some embodiments of the band diagram at the interface layer of the image sensor.

[0014] Figure 7 Show Figure 1A and Figure 1B The top layout of some embodiments of the image sensor.

[0015] Figure 8A and Figure 8B Show Figure 1A and Figure 1B Various cross-sectional views of some alternative embodiments of the image sensor in which the photodetector varies.

[0016] Figure 9 Show Figure 1A and Figure 1B Cross-sectional views of some alternative embodiments of an image sensor in which the interface layer is replaced by an oxide passivation layer.

[0017] Figure 10A and Figure 10B Show Figure 1A and Figure 1B Cross-sectional views of some alternative embodiments of an image sensor in which the device layer is linerbed by the substrate implantation region and the intermediate layer.

[0018] Figure 11 Show Figure 1A and Figure 1B A cross-sectional view of some alternative embodiments of an image sensor in which the bottom surface of the device layer rises above the top surface of the substrate.

[0019] Figures 12A-12C Show Figure 11 Cross-sectional views of some alternative embodiments of the image sensor.

[0020] Figure 13 Show Figure 1A and Figure 1B Enlarged cross-sectional views of some embodiments of image sensors that are back-illuminated (BSI) and three-dimensional (3D) integrated circuit (IC).

[0021] Figure 14 Show Figure 13 Cross-sectional views of some alternative embodiments of an image sensor having multiple photodetectors.

[0022] Figure 15 Show Figure 1A and Figure 1B Enlarged cross-sectional views of some embodiments of the image sensor, which is a front-illuminated (FSI) image sensor.

[0023] Figure 16 Show Figure 15 Cross-sectional views of some alternative embodiments of an image sensor having multiple photodetectors.

[0024] Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B A series of cross-sectional views are shown illustrating some embodiments of a method for forming an image sensor in which a passivation layer is configured to reduce dark current.

[0025] Figure 25 Show Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B Block diagrams of some embodiments of the method.

[0026] Figures 26-32 A series of cross-sectional views are shown of some first embodiments of a method for forming an image sensor in which a passivation layer is configured to reduce dark current and the bottom surface of the device layer is raised above the top surface of the substrate.

[0027] Figure 33 Show Figures 26-32 Block diagrams of some embodiments of the method.

[0028] Figures 34-42 A series of cross-sectional views are shown of some second embodiments of a method for forming an image sensor in which a passivation layer is configured to reduce dark current and the bottom surface of the device layer is raised above the top surface of the substrate.

[0029] Figure 43 Show Figures 34-42 Block diagrams of some embodiments of the method. Detailed Implementation

[0030] This invention provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0032] Complementary metal-oxide-semiconductor (CMOS) image sensors can be used to detect near-infrared (NIR) and infrared (IR) radiation. This is likely the case for CMOS image sensors used for time-of-flight (ToF) imaging and other suitable types of imaging. However, CMOS image sensors are typically silicon-based. Silicon has a large band gap, making it poor at absorbing NIR and IR radiation. Therefore, silicon-based CMOS image sensors may have poor quantum efficiency (QE) for NIR and IR radiation. To mitigate the poor QE, silicon-based CMOS image sensors can be replaced with CMOS image sensors based on alternative semiconductor materials with smaller band gaps than silicon. A non-limiting example of such alternative semiconductor materials is germanium.

[0033] A CMOS image sensor based on an alternative semiconductor material and used for ToF imaging may include a device layer and a capping layer. The device layer covers and is inserted on top of a semiconductor substrate, and the capping layer covers the device layer. Furthermore, the semiconductor substrate and capping layer are silicon, while the device layer is or includes an alternative semiconductor material. Two PIN diodes are located in the capping layer and the device layer, respectively, on opposite sides of the device layer. A passivation layer of silicon dioxide (e.g., SiO2) covers and directly contacts the capping layer, and contact vias extend through the passivation layer to the contact regions of the PIN diodes.

[0034] The smaller bandgap of alternative semiconductor materials enables enhanced QE. However, the smaller bandgap also leads to higher dark current, which negatively impacts the performance gains from using alternative semiconductor materials. For example, during ToF imaging, incident radiation can be measured separately using PIN diodes at different time intervals. These measurements can then be used to determine the distance to the object. Moving electrons from the dark current may accumulate on the PIN diodes, causing measurement inaccuracies and thus inaccurate distance determination.

[0035] Various embodiments of this disclosure relate to image sensors having a passivation layer for reducing dark current and methods of forming the image sensor. In some embodiments of the image sensor, a device layer covers a substrate. Furthermore, a capping layer covers the device layer. The capping layer, device layer, and substrate are semiconductor materials, and the device layer has a smaller band gap than the capping layer and substrate. For example, the capping layer and substrate may be silicon, while the device layer may be germanium or include germanium. However, it should be noted that other suitable materials are applicable in alternative embodiments. A photodetector is located within the device layer and capping layer, with the passivation layer covering the capping layer. The passivation layer comprises a high-k dielectric material and causes the formation of a dipole moment along the top surface of the capping layer.

[0036] Due to the dipole moment along the top surface of the capping layer, mobile charge carriers of the dark current (e.g., mobile electrons) may be attracted to and neutralized by the top surface of the capping layer. This, in turn, prevents the dark current from negatively impacting the performance of the photodetector. For example, when using an image sensor for ToF imaging, the photodetector may include a pair of pin junctions. As described above, the pin junctions can be located on opposite sides of the device layer and can be used to determine the distance to an object. The dipole moment attracts mobile electrons of the dark current to the pin junctions, so the dark current does not affect the measurement of the pin junctions. As a result, the measurement, and therefore the distance determination, can be more accurate.

[0037] refer to Figure 1A and Figure 1B Various cross-sectional views 100A, 100B of some embodiments of an image sensor are provided, wherein a high-k passivation layer 102 is configured to generate a dipole moment 104 above a photodetector 106 to reduce dark current. Figure 1B Corresponding to Figure 1A A magnified cross-sectional view 100B of a portion of the image sensor within frame A. The photodetector 106 is located beneath the high-k passivation layer 102 in the device layer 108 and the capping layer 110. Furthermore, the photodetector 106 includes a pair of PIN diodes 112. The PIN diodes 112 are located on opposite sides of the device layer 108 and include respective P-type contact regions 114 and N-type contact regions 116.

[0038] Device layer 108 is trenched to the top of substrate 118, and capping layer 110 separates device layer 108 from high-k passivation layer 102. Device layer 108, capping layer 110, and substrate 118 are semiconductor materials, and device layer 108 is a different semiconductor material from capping layer 110 and substrate 118. Device layer 108 may be or include germanium, silicon-germanium, some other suitable semiconductor material, or any combination thereof. Substrate 118 and capping layer 110 may be, for example, silicon and / or some other suitable semiconductor material. In some embodiments, the bulk of device layer 108 is undoped or lightly doped and / or capping layer 110 is undoped or lightly doped. In some embodiments, the bulk of substrate 104 has P-type or N-type doping. As used herein, light doping means a doping concentration of less than about 1 × 10⁻⁶. 15 atoms per cubic centimeter (e.g., cm) -3 (or some other suitable value.)

[0039] A high-k passivation layer 102 covers the capping layer 110, and an interface layer 120 is located between the high-k passivation layer 102 and the capping layer 110. The high-k passivation layer 102 is a high-k dielectric material with a dielectric constant exceeding 3.9, 10, or some other suitable value. Furthermore, during the formation of the image sensor, the high-k passivation layer 102 is deposited directly on the capping layer 110. The high-k passivation layer 102 reacts with the capping layer 110 to form the interface layer 120 between the high-k passivation layer 102 and the capping layer 110. For example, the high-k passivation layer 102 and the capping layer 110 may respectively comprise a metal oxide and silicon, such that the oxygen in the high-k passivation layer 102 reacts with the silicon in the capping layer 110 to form the interface layer 120 as silicon oxide.

[0040] Interface layer 120 is a dielectric having a different band gap and a smaller regional oxygen density than high-k passivation layer 102. Due to the different band gap, band bending occurs at the interface 122 between interface layer 120 and high-k passivation layer 102. Band bending, in turn, induces the formation of dipole moment 104 at interface 122. Furthermore, because interface layer 120 has a smaller regional oxygen density than high-k passivation layer 102, negative charges (schematically shown with a negative sign) accumulate along interface 122 in high-k passivation layer 102, while positive charges (schematically shown with a positive sign) accumulate along interface 122 in interface layer 120.

[0041] As explained in more detail below, the image sensor is used for Time-of-Flight (ToF) imaging. Radiation is emitted toward the object. The reflected radiation then strikes a photodetector 106 to generate electron-hole pairs. At different times, a PIN diode 112 collects the moving electrons of the electron-hole pairs in the N-type contact region 116. The collected electrons are then measured at different time intervals and used to determine the distance to the object. The positive charge of the dipole moment 104 draws the moving electrons 124 of the dark current in the device layer 108 away from the PIN diode 112 and neutralizes the moving electrons 124. By neutralizing the moving electrons 124, the dark current is reduced and does not accumulate at the N-type contact region 116 of the PIN diode 112. As a result, the measurement using the PIN diode 112 is more accurate, and therefore the distance determination is more precise.

[0042] Multiple contact vias 126c and multiple first-level leads 128f are stacked above the capping layer 110. The first-level leads 128f cover a high-k passivation layer 102. The contact vias 126c extend from the P-type and N-type contact regions 114 and 116, respectively, through the high-k passivation layer 102 and the interface layer 120, to the first-level leads 128f. Furthermore, the top surface of the contact vias 126c is flush with the top surface of the high-k passivation layer 102. In an alternative embodiment, the top surface of the contact vias 126c is above or below the top surface of the high-k passivation layer 102. The first-level leads 128f and the contact vias 126c may be, for example, metal and / or some other suitable conductive material.

[0043] In some embodiments, the high-k passivation layer 102 is or includes aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (HfO2), zirconium oxide (e.g., ZrO2), magnesium oxide (e.g., MgO), some other suitable high-k dielectrics, or any combination thereof. In some embodiments, the dielectric constant of the high-k passivation layer 102 is greater than that of the interface layer 120 and / or has a smaller band gap than that of the interface layer 120. In some embodiments, the thickness T of the high-k passivation layer 102 is... hkp For approximately 1-10 nanometers, approximately 1-5 nanometers, approximately 5-10 nanometers, or other suitable values. If the thickness T... hkp If the thickness T is too large (e.g., greater than about 10 nanometers or some other suitable value), the inherent defects in the high-k passivation layer 102 may lead to high leakage current, thereby offsetting the performance improvement of the dipole moment 104. On the other hand, if the thickness T... hkp If it is too small (e.g., less than about 1 nanometer or some other suitable value), the dipole moment 104 may not be formed, and therefore the performance improvement may not be obtained from the dipole moment 104.

[0044] In some embodiments, the interface layer 120 is or comprises semiconductor elements from the substrate 118 and oxygen and / or some other suitable elements from the high-k passivation layer 102. For example, the interface layer 120 may comprise silicon from the substrate 118 and oxygen from the high-k passivation layer 102. In some embodiments, the interface layer 120 is or comprises silicon dioxide (e.g., SiO2) and / or some other suitable dielectric. In some embodiments, the thickness T of the interface layer 120 is... i The nanometers are approximately 0.5–2.5 nanometers, approximately 0.5–1.5 nanometers, or approximately 1.5–2.5 nanometers, or some other suitable value.

[0045] In some embodiments, device layer 108 has a small bandgap relative to silicon, substrate 118, capping layer 110, or any combination thereof. For example, device layer 108 may be or include germanium, while capping layer 110 and substrate 118 may be silicon. In some embodiments, the small bandgap results in device layer 108 having a high absorption coefficient for NIR and / or IR radiation relative to silicon, substrate 118, capping layer 110, or any combination thereof. NIR radiation may, for example, include wavelengths of about 850-940 nm, about 850-1350 nm, about 850-1180 nm, about 1180-1350 nm, some other suitable wavelengths, or any combination thereof. IR radiation may, for example, include wavelengths of about 1.5-30 μm and / or other suitable wavelengths. In some embodiments, the small bandgap results in device layer 108 having a high QE greater than about 80% or some other suitable value for wavelengths of about 850-940 nm and for other suitable wavelengths.

[0046] In some embodiments, the height H of the device layer 108 d For approximately 2-50 micrometers, approximately 2-26 micrometers, approximately 25-50 micrometers, or some other suitable value. If the height H d If the height H is too small (e.g., less than about 2 micrometers or some other suitable value), the absorption of incident radiation by device layer 108 may be poor, and the performance of photodetector 106 may be poor. d If the size is too large (e.g., greater than about 50 micrometers or some other suitable value), the formation of the device layer 108 that is slotted into the substrate 118 may take a long time and may significantly affect manufacturing yield.

[0047] refer to Figure 2 Provided along Figure 1A and Figure 1B Some embodiments of the energy band diagram 200 of line B show a band bend 202 at the interface 122 between the high-k passivation layer 102 and the interface layer 120. As a result, the conduction band E... c The energy shifts upwards in an arc from interface 122 towards interface layer 120, resulting in a positive energy shift O1. This occurs within the valence band E.v The same situation occurs at the interface layer 120. Because the energy shift O1 is positive, the positive charge of dipole moment 104 is in the interface layer 120, while the negative charge of dipole moment 104 is in the high-k passivation layer 102. If the energy shift O1 is negative, the positive charge of dipole moment 104 is in the high-k passivation layer 102, and the negative charge of dipole moment 104 is in the interface layer 120.

[0048] In some embodiments, the capping layer 110 is silicon, the high-k passivation layer 102 is aluminum oxide (e.g., Al₂O₃), and the interface layer 120 is silicon oxide (e.g., SiO₂). In at least some of these embodiments, the energy offset O₁ is 0.57 electron volts (eV). In other embodiments, the capping layer 110 is silicon, the high-k passivation layer 102 is hafnium oxide (e.g., HfO₂), and the interface layer 120 is silicon oxide (e.g., SiO₂). In at least some of these embodiments, the energy offset O₁ is 0.31 eV. In other embodiments, different materials may be used.

[0049] refer to Figure 3 Provided Figure 1A and Figure 1B Timing diagram 300 for some embodiments of signals during the operation of an image sensor. The horizontal axis corresponds to time, while the vertical axis corresponds to signal state.

[0050] As indicated by source radiation signal 302, the source radiation is initially emitted toward the object for a duration t0. The source radiation may be emitted, for example, from or near an image sensor and / or may be emitted, for example, by a laser diode or some other suitable radiation source. The source radiation may be, for example, NIR radiation, IR radiation, or some other suitable type of radiation.

[0051] As represented by the reflected radiation signal 304, the source radiation is reflected from the object and strikes the photodetector 106 after a time Δt. As a result, the reflected radiation strikes the photodetector 106 for a duration t0.

[0052] As respectively by Figure 1A and Figure 1B The PIN1 state signal 306 and PIN2 state signal 308 of the PIN diode 112 indicate that the PIN diode 112 is in the ON state at different, non-overlapping time intervals. When the emission source radiates, the first PIN diode is in the ON state for a duration t. 0 The first PIN diode is ON immediately after emission from the source for a duration t0, and OFF otherwise. Additionally, the second PIN diode is ON immediately after emission from the source for a duration t0, and OFF otherwise.

[0053] PIN diode 112 is always ON when reverse biased, and OFF when forward biased or unbiased. In fact, the ON / OFF state of PIN diode 112 is determined by... Figure 1A and Figure 1B The bias voltage at the P-type contact region 114 is controlled. When either PIN diode 112 is ON, mobile electrons generated in response to reflected radiation accumulate in... Figure 1A and Figure 1B The corresponding region within the N-type contact region 116. Furthermore, the N-type contact region uniquely contains a parallel-coupled capacitor storing electrons collected at the N-type contact region. It should be noted that in... Figure 1A and Figure 1B The capacitor with N-type contact area 116 is not shown in the diagram.

[0054] As represented by PIN1 collection signal 310 and PIN2 collection signal 312 of PIN diode 112, respectively, PIN diode 112 collects mobile electrons generated in response to reflected radiation at different non-overlapping time intervals. When the first PIN diode is in the ON state, the first PIN diode collects a first number Q1 of electrons, while when the second PIN diode is in the ON state, the second PIN diode collects a second number Q2 of electrons. As described above, mobile electrons accumulate in... Figure 1A and Figure 1B At the N-type contact region 116, PIN1 and PIN2 collect signals 310 and 312 corresponding to the signals at the N-type contact region 116.

[0055] Given the time Δt, the distance D to the object can be determined as follows:

[0056] ,

[0057] Where c is the speed of light. However, Δt is not easily known. However, Δt can be determined from the easily known duration t0 and the first and second quantities Q1 and Q2 of electrons collected by the PIN diode 112. Specifically, Δt can be determined as follows:

[0058] .

[0059] Therefore, the distance D can be determined as follows:

[0060] .

[0061] Because the determined distance D depends on the first and second quantities Q1 and Q2, the accuracy of the determined distance D depends on the accuracy of the first and second quantities Q1 and Q2. Furthermore, if the moving electrons of the dark current migrate to... Figure 1A and Figure 1BIf the PIN diode 112 is used and collected by it, the dark current may negatively affect the accuracy of the first and second quantities Q1, Q2, and therefore may negatively affect the accuracy of the determined distance D. Since... Figure 1A and Figure 1B The dipole moment 104 in the PIN diode 112 draws dark current electrons out of the PIN diode 112. This prevents dark current electrons from being collected by the PIN diode 112, or otherwise reduces the number of dark current electrons collected by the PIN diode 112. Therefore, the dipole moment 104 reduces the impact of the dark current on the accuracy of the first and second quantities Q1, Q2, and the accuracy of determining the distance D.

[0062] refer to Figure 4 Provided Figure 1A and Figure 1B The image sensor includes an equivalent circuit 400 in some embodiments. The image sensor includes a photodetector 106 and a pair of capacitors 402. The photodetector 106 is equivalent to a pair of switches 404 and a photodiode 406 electrically coupled to a common node 408. The cathode of the photodiode 406 is electrically coupled to the common node 408, while the anode of the photodiode 406 is electrically connected to ground 410. Switches 404 are electrically coupled from the common node 408 to capacitors 402, and capacitors 402 are electrically coupled from the switches 404 to ground 410.

[0063] Switch 404 corresponds to Figure 1A and Figure 1B The PIN diode 112 is used in the circuit. When the switch is ON, the corresponding PIN diode is reverse-biased and functions entirely or partially as photodiode 406. When the switch is OFF, the corresponding PIN diode is forward-biased or unbiased and functions independently of photodiode 406. (Reference) Figure 3 The PIN1 and PIN2 status signals 306 and 308 correspond to the ON / OFF state of switch 404. Furthermore, the PIN1 and PIN2 collection signals 310 and 312 correspond to the collected mobile electrons transferred to capacitor 402.

[0064] refer to Figure 5A and Figure 5B Provided Figure 1A and Figure 1B Various cross-sectional views 500A, 500B of some alternative embodiments of the image sensor, wherein the polarity of the dipole moment 104 is reversed. Figure 5B Corresponding to Figure 5AA magnified cross-sectional view 500B of a portion of the image sensor within frame C. Due to the polarity reversal of the dipole moment 104, the negative charge of the dipole moment 104 (schematically shown by the negative sign) accumulates along interface 122 in interface layer 120, while the positive charge of the dipole moment 104 (schematically shown by the positive sign) accumulates along interface 122 in high-k passivation layer 102.

[0065] The polarity of the dipole moment 104 is reversed because the oxygen density in the region of the interface layer 120 is greater than the oxygen density in the region of the high-k passivation layer 102. In some embodiments, the interface layer 120 is or includes silicon oxide and / or some other suitable dielectric. In some embodiments, the high-k passivation layer 102 is or includes barium oxide (e.g., BaO), strontium oxide (e.g., SrO), lanthanum oxide (e.g., La2O3), yttrium oxide (e.g., Y2O3), or some other suitable high-k dielectric or any combination thereof.

[0066] In addition to reversing the polarity of the dipole moment 104, the N-type contact region 116 is also located between the P-type contact regions 114. Furthermore, compared to the P-type contact regions 114, the N-type contact regions 116 extend into the device layer 108 to a greater depth. In an alternative embodiment, the P-type contact regions 114 are located between the N-type contact regions 116, as in... Figure 1A and Figure 1B In the middle, and / or compared to the P-type contact region 114, the N-type contact region 116 extends into the device layer 108 to a smaller depth, such as in Figure 1A and Figure 1B middle.

[0067] Similar to Figure 1A and Figure 1B An image sensor is used for Time-of-Flight (ToF) imaging. Radiation is emitted toward the object. The reflected radiation then strikes a photodetector 106 to generate electron-hole pairs. At different times, a PIN diode 112 collects the moving holes of the electron-hole pairs in the P-type contact region 114. The collected holes are then measured at different time intervals and used to determine the distance to the object. The negative charge of the dipole moment 104 draws the moving holes 502 of the dark current in the device layer 108 away from the PIN diode 112 and neutralizes the moving holes 502. By neutralizing the moving holes 502, the dark current is reduced and does not accumulate at the P-type contact region 114 of the PIN diode 112. As a result, the measurement using the PIN diode 112 is more accurate, and therefore the distance determination is more precise.

[0068] refer to Figure 6 Provided along Figure 5A and Figure 5BSome embodiments of the energy band diagram 600 of line D show a band bend 602 at the interface 122 between the high-k passivation layer 102 and the interface layer 120. As a result, the conduction band E... c The energy shifts downwards from interface 122 towards interface layer 120 in an arc shape, resulting in a negative energy shift for O2. This occurs in the valence band E. v The same situation occurs at the interface layer 120. Because the energy shift O2 is negative, the negative charge of dipole moment 104 is in the interface layer 120, while the whole charge of dipole moment 104 is in the high-k passivation layer 102. If the energy shift O2 is positive, the negative charge of dipole moment 104 is in the high-k passivation layer 102, and the positive charge of dipole moment 104 is in the interface layer 120.

[0069] In some embodiments, the capping layer 110 is silicon, the high-k passivation layer 102 is yttrium oxide (e.g., Y₂O₃), and the interface layer 120 is silicon oxide (e.g., SiO₂). In at least some of these embodiments, the energy offset O₂ is -0.23 eV. In other embodiments, different materials may be used.

[0070] refer to Figure 7 A layer is provided along the interface between the capping layer 110 (shown in dashed lines) and the device layer 108. Figure 1A and Figure 1B The top layout 700 of some embodiments of the image sensor. PIN diodes 112 are located on opposite sides of device layer 108. P-type and N-type contact regions 114, 116 have a rectangular layout extending in parallel, with P-type contact region 114 located between N-type contact regions 116. In alternative embodiments, the P-type and N-type contact regions 114, 116 have some other suitable layout and / or the N-type contact region 116 is located between P-type contact regions 114.

[0071] refer to Figure 8A and Figure 8B Provided Figure 1A and Figure 1B Various cross-sectional views 800A, 800B of some alternative embodiments of the image sensor, wherein the photodetector 106 is varied.

[0072] like Figure 8A As shown in cross-sectional view 800A, the bottom surface of the capping layer 110 is raised above the top surface of the substrate 118, such that the top of the photodetector 106 is raised above the top surface of the substrate 118. In an alternative embodiment, the bottom surface of the capping layer 110 is slotted relative to the top surface of the substrate 118, and the top surface of the capping layer 110 is raised above the top surface of the substrate 118.

[0073] like Figure 8BAs shown in cross-sectional view 800B, the photodetector 106 includes a single PIN diode 112s instead of a pair of PIN diodes 112s. The single PIN diode 112s and... Figure 1A and Figure 1B The PIN diode 112 described is identical, and therefore includes a P-type contact region 114 and an N-type contact region 116. The P-type and N-type contact regions 114 and 116 are located on opposite sides of the device layer 108.

[0074] refer to Figure 9 Provided Figure 1A and Figure 1B A cross-sectional view 900 of some alternative embodiments of the image sensor shows an interface layer 120 replaced by an oxide passivation layer 902. The oxide passivation layer 902 is similar to the interface layer 120. However, unlike the interface layer 120, the oxide passivation layer 902 is deposited during the formation of the image sensor. Thus, the oxide passivation layer 902 is not formed due to the reaction between the high-k passivation layer 102 and the capping layer 110. Because the oxide passivation layer 902 is formed by deposition, its crystallinity is higher than that of the interface layer 120, resulting in reduced leakage current and enhanced performance of the photodetector 106.

[0075] The oxide passivation layer 902 is a dielectric having a different band gap and a smaller regional oxygen density than the high-k passivation layer 102. Due to the different band gap, band bending occurs at the interface 904 between the oxide passivation layer 902 and the high-k passivation layer 102. This band bending, in turn, causes the formation of a dipole moment 104 at the interface 904. Because the oxide passivation layer 902 has a smaller regional oxygen density than the high-k passivation layer 102, negative charges (illustrated with a negative sign) accumulate along the interface 904 in the high-k passivation layer 102, while positive charges (illustrated with a positive sign) accumulate along the interface 904 in the oxide passivation layer 902. In an alternative embodiment, the oxide passivation layer 902 has a higher regional oxygen density than the high-k passivation layer 102 to reverse the polarity of the dipole moment 104.

[0076] The oxide passivation layer 902 has a lower dielectric constant than the high-k passivation layer 102 and, in some embodiments, a larger band gap than the high-k passivation layer 102. In some embodiments, the oxide passivation layer 902 comprises semiconductor elements from the substrate 118 and also comprises oxygen and / or some other suitable elements from the high-k passivation layer 102. In some embodiments, the oxide passivation layer 902 is or comprises silicon dioxide (e.g., SiO2) and / or other suitable dielectrics.

[0077] In some embodiments, the thickness T of the oxide passivation layer 902 opThe values ​​are approximately 1-10 nanometers, approximately 1-5 nanometers, approximately 5-10 nanometers, or other suitable values. If the oxide passivation layer 902 is too thin (e.g., less than approximately 1 nanometer or some other suitable value), the oxide passivation layer 902 may be too thin to interact with... Figure 1A and Figure 1B Compared to effectively reducing leakage current, if the thickness T op If the value is too large (e.g., greater than about 10 nanometers or some other suitable value), the dipole moment 104 may be too far from the moving electrons 124 of the dark current to effectively attract and neutralize them. As a result, the dipole moment 104 may not effectively improve the measurement accuracy of the PIN diode 112, and therefore may not effectively improve distance determination.

[0078] refer to Figure 10A and Figure 10B Provided Figure 1A and Figure 1B Cross-sectional views 1000A and 1000B of some alternative embodiments of the image sensor, wherein device layer 108 is backed by substrate implantation region 1002 and intermediate layer 1004. Figure 10A In this configuration, the top surface of the capping layer 110 is approximately flush with the top surface of the substrate 118 (note that the substrate implantation region 1002 is the doped region of the substrate 118). Figure 10B In one embodiment, the bottom surface of the capping layer 110 is raised above the top surface of the substrate 118. In another embodiment, the bottom surface of the capping layer 110 is slotted relative to the top surface of the substrate 118, and the top surface of the capping layer 110 is raised above the top surface of the substrate 118.

[0079] As described above, substrate implantation region 1002 is a doped region of substrate 118. Furthermore, substrate implantation region 1002 has the same doping type as the bulk of substrate 118, but with a higher doping concentration. For example, both substrate implantation region 1002 and the bulk of substrate 118 can be p-type or n-type. In some embodiments, the doping concentration of substrate implantation region 1002 is approximately 1 × 10⁻⁶. 17 -5×10 18 cm -3 Greater than approximately 5 × 10 18 cm -3 Or some other suitable value.

[0080] Intermediate layer 1004 separates device layer 108 from substrate implantation region 1002. Intermediate layer 1004 is an undoped semiconductor material different from device layer 108. In an alternative embodiment, intermediate layer 1004 is a lightly doped semiconductor material, i.e., different from device layer 108, and / or with a doping concentration less than that of substrate implantation region 1002. Light doping can be, for example, less than about 1 × 10⁻⁶. 15 cm -3Or other suitable doping concentration values. The intermediate layer 1004 may be, for example, silicon and / or some other suitable semiconductor material. In some embodiments, the intermediate layer 1004 is or comprises the same semiconductor material as the substrate 118 and / or the capping layer 110. For example, the intermediate layer 1004, the substrate 118, and the capping layer 110 may be silicon, while the device layer 108 may be germanium or silicon-germanium. However, other suitable materials are also possible.

[0081] The substrate injection region 1002 reduces the number of charge carriers caused by crystal defects at the interface between the intermediate layer 1004 and the substrate 118 and / or at the interface between the intermediate layer 1004 and the device layer 108. As a result, leakage current at the first and / or second interfaces can be reduced, and the performance of the photodetector 106 can be enhanced.

[0082] Because the intermediate layer 1004 is undoped, it has a high resistance. This high resistance reduces the leakage current from device layer 108 to substrate 118. By reducing the leakage current from device layer 108 to substrate 118, the leakage current between photodetectors is reduced, and the performance of photodetector 106 is further enhanced. The high resistance can be, for example, greater than about 100 kilohms or some other suitable value. The intermediate layer 1004 further prevents dopant from the substrate implantation region 1002 from diffusing into device layer 108. For example, substrate implantation region 1002 can be p-type doped, and the intermediate layer 1004 can prevent boron or other suitable p-type dopant from diffusing into device layer 108. Dopant diffusing into device layer 108 can form a low-resistance region from substrate 118 to device layer 108, and thus can increase the leakage current between photodetectors. Because the intermediate layer 1004 prevents diffusion, the resistance from substrate 118 to device layer 108 can remain high and the leakage current can remain low.

[0083] refer to Figure 11 Provided Figure 1A and Figure 1B A cross-sectional view 1100 of some alternative embodiments of the image sensor shows that the bottom surface of device layer 108 is raised above the top surface of substrate 118. Furthermore, capping layer 110 is located on the sidewall of device layer 108, interface layer 120 is located on the sidewall of capping layer 110, and high-k passivation layer 102 is located on the sidewall of interface layer 120. Since the bottom surface of device layer 108 is raised above the top surface of substrate 118, device layer 108 and capping layer 110 can be considered as defining a mesa structure above substrate 118. Furthermore, the isolation between photodetectors is enhanced because photodetector 106 is laterally separated from photodetector 106 by high-k passivation layer 102.

[0084] refer to Figures 12A-12C Provided Figure 11Various cross-sectional figures 1200A-1200C show some alternative embodiments of the image sensor.

[0085] like Figure 12A As shown in the cross-sectional view 1200A, the interface layer 120 is... Figure 9 The oxide passivation layer 902 is replaced. (See regarding...) Figure 9 The oxide passivation layer 902 is similar to the interface layer 120. However, the oxide passivation layer 902 is deposited during the formation of the image sensor, rather than formed through a reaction between the high-k passivation layer 102 and the capping layer 110. Because the oxide passivation layer 902 is formed by deposition, its crystallinity is higher than that of the interface layer 120, resulting in reduced leakage current.

[0086] like Figure 12B and Figure 12C As shown in cross-sectional views 1200B and 1200C, the dielectric layer 1202 between photodetectors separates photodetector 106 from adjacent photodetectors. Figure 12B In the middle, the capping layer 110, the interface layer 120, and the high-k passivation layer 102 are vertically stacked and cover the dielectric layer 1202 between the photodetectors and the device layer 108. Figure 12C In this configuration, capping layer 110 is positioned to device layer 108. Interface layer 120 is located on the sidewall of capping layer 110, and high-k passivation layer 102 is located on the sidewall of interface layer 120. The photodetector inter-dielectric layer 1202 may be, for example, silicon oxide and / or some other suitable dielectric.

[0087] refer to Figure 13 Provided Figure 1A and Figure 1B Enlarged cross-sectional view 1300 of some embodiments of an image sensor, wherein the image sensor is back-illuminated (BSI) and is a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC structure 1302 and a second IC structure 1304 co-bonded at a bonding interface 1306. The first IC structure 1302 covers the second IC structure 1304 and houses a photodetector 106, while the second IC structure 1304 is located below the first IC structure 1302 and houses a plurality of logic devices 1308.

[0088] The first and second IC structures 1302 and 1304 each include a first substrate 118 and a second substrate 1310. Furthermore, the first and second IC structures 1302 and 1304 each include a first interconnect structure 1312 and a second interconnect structure 1314. The first and second interconnect structures 1312 and 1314 are located between and adjacent to the first and second substrates 118 and 1310. A photodetector 106 is located on the front side of the first substrate 118, between the first substrate 118 and the first interconnect structure 1312. A logic device 1308 is located on the front side of the second substrate 1310, between the second substrate 1310 and the second interconnect structure 1314. The first and second substrates 118 and 1310 can be, for example, bulk substrates of monocrystalline silicon or some other suitable type of substrate.

[0089] The first and second interconnect structures 1312, 1314 include multiple leads 128, multiple vias 126, and multiple pads 1316, grouped into multiple levels and alternately stacked between the first and second substrates 118, 1310. These levels correspond to different heights above the second substrate 1310. The pads 1316 are grouped into two pad levels that directly contact each other at the bonding interface 1306. The leads 128 and vias 126 are grouped into multiple lead levels and via levels, respectively, which alternately stack from the pads 1316 to the photodetector 106 and the logic device 1308, respectively. The leads 128, vias 126, and pads 1316 are conductive and may be or include copper, tungsten, aluminum, some other suitable conductive material, or any combination thereof.

[0090] The dielectric stack surrounds the lead 128, via 126, and pad 1316 between the first and second substrates 118 and 1310. A pair of bonding dielectric layers 1318 directly contact and surround the pad 1316 and the via 126 at the bonding interface 1306. An etch stop layer 1322 is adjacent to the bonding dielectric layers 1318 and further surrounds the via 126 at the pad 1316. A high-k passivation layer 102 and an interface layer 120 surround the via 126 at the photodetector 106. A pair of interconnect dielectric layers 1320 surround the lead 128 and the remaining vias 126. The etch stop layer 1322 is or comprises a different material from the interconnect dielectric layers 1320 and the bonding dielectric layers 1318.

[0091] The trench isolation structure 1324 isolates the logic device 1308. The trench isolation structure 1324 is or includes silicon oxide and / or some other suitable dielectric. The trench isolation structure 1324 can be, for example, a shallow trench isolation (STI) structure or some other suitable type of trench isolation structure.

[0092] Logic device 1308 is an insulated-gate field-effect transistor (IGFET), but may be some other suitable type of transistor. For example, logic device 1308 may be a fin field-effect transistor (FFET), a gate-all-around field-effect transistor (GAAFET), or some other suitable type of transistor. Logic device 1308 includes various wells 1326, various gate electrodes 1328, various gate dielectric layers 1330, and various pairs of source / drain regions 1332. The gate electrodes 1328 are stacked on a second substrate 1310 with the gate dielectric layers 1330, and the stack is located between the source / drain regions of the respective pairs of source / drain regions 1332. The wells 1326 are located below and around the pairs of source / drain regions 1332 in the second substrate 1310. The wells 1326 have a doping type opposite to that of the corresponding pairs of source / drain regions 1332. In some embodiments, one, some, or all of the wells 1326 have a doping type opposite to that of the bulk of the second substrate 1310. In some embodiments, one, some, or all of the wells 1326 have the same doping type as the bulk of the second substrate 1310, but with different doping concentrations. In alternative embodiments, one, some, or all of the wells 1326 are omitted.

[0093] Microlens 1334 and metal grid 1336 are stacked on the back side of first substrate 118 above first substrate 118. Metal grid 1336 has a metal grid opening 1338 covering photodetector 106 and is configured to prevent crosstalk between photodetector 106 and adjacent photodetectors. Furthermore, metal grid 1336 is surrounded by an antireflective layer 1340 and a metal grid dielectric layer 1342. Antireflective layer 1340 is located between metal grid 1336 and first substrate 118 to separate metal grid 1336 from first substrate 118, and metal grid dielectric layer 1342 fills metal grid opening 1338 and separates metal grid 1336 from microlens 1334. Microlens 1334 covers metal grid 1336 and is configured to focus incident radiation onto photodetector 106 through metal grid opening 1338.

[0094] refer to Figure 14 Provided Figure 13 Cross-sectional view 1400 of some alternative embodiments of the image sensor, wherein the image sensor has a plurality of photodetectors 106. The photodetectors 106 are all as follows: Figure 13 The counterpart in [the above figures]. In an alternative embodiment, photodetector 106 is in any of the above figures (e.g., [the figures]). Figure 10A , Figure 10B (or some other suitable accompanying drawings) are all used as their counterparts. Note that, due to Figure 14 The photodetector 106 is small in size, so its configuration (e.g., contact area) is not shown.

[0095] Multiple microlenses 1334 cover photodetector 106, and a metal grid 1336 defines multiple metal grid openings 1338. The microlenses 1334 are unique to photodetector 106 and each covers photodetector 106. Similarly, the metal grid openings 1338 are unique to photodetector 106 and each covers photodetector 106. The microlenses 1334 and the metal grid openings 1338 are respectively located in… Figure 13 They are described as their counterparts.

[0096] A pair of bonding pads 1402 are suspended above the metal grid dielectric layer 1342 and extend through the first substrate 118 to a number of leads 128. Furthermore, the bonding pads 1402 are located on opposite sides of the photodetector 106, such that the photodetector 106 is positioned between the bonding pads 1402. The bonding pads 1402 may be, for example, copper, aluminum, some other suitable metal, or any combination thereof.

[0097] An additional trench isolation structure 1404 extends into the front side of the first substrate 118, located between the first substrate 118 and the first interconnect structure 1312. The additional trench isolation structure 1404 has multiple segments located at bonding pads 1402, such that the bonding pads 1402 extend through the additional trench isolation structure 1404. The additional trench isolation structure 1404 is or includes silicon oxide and / or some other suitable dielectric. The additional trench isolation structure 1404 may be, for example, an STI structure or some other suitable type of trench isolation structure.

[0098] refer to Figure 15 Provided Figure 1A and Figure 1B A magnified cross-sectional view 1500 shows some embodiments of an image sensor, wherein the image sensor is a front-illuminated (FSI) type. Interconnect structure 1312 covers substrate 118 and photodetector 106 on the front side of substrate 118. Furthermore, interconnect structure 1312 covers logic devices (not shown) on the front side of substrate 118. The logic devices may be, for example,... Figure 13 The logic device 1308 is shown and described. The interconnect structure 1312 includes multiple leads 128 and multiple vias 126. The leads 128 and vias 126 are alternately stacked in a dielectric stack. A high-k passivation layer 102 and an interface layer 120 surround the vias 126 at the photodetector 106. An interconnect dielectric layer 1320 surrounds the leads 128 and the remaining vias 126.

[0099] Microlens 1334 and metal grid 1336 are stacked on the front side of substrate 118 above interconnect structure 1312. Furthermore, antireflective layer 1340 is located between metal grid 1336 and interconnect structure 1312, while metal grid dielectric layer 1342 fills metal grid opening 1338 and separates metal grid 1336 from microlens 1334. Microlens 1334 and metal grid are as described above. Figure 13 As stated above.

[0100] refer to Figure 16 Provided Figure 15 Cross-sectional view 1600 of some alternative embodiments of the image sensor, wherein the image sensor has a plurality of photodetectors 106. The photodetectors 106 are all as follows: Figure 15 The counterpart in [the above figures]. In an alternative embodiment, photodetector 106 is in any of the above figures (e.g., [the figures]). Figure 10A , Figure 10B (or some other suitable accompanying drawings) are all used as their counterparts. Note that, due to Figure 15 The photodetector 106 is small in size, so its configuration (e.g., contact area) is not shown.

[0101] Multiple microlenses 1334 cover photodetector 106, and a metal grid 1336 defines multiple metal grid openings 1338. The microlenses 1334 are unique to photodetector 106 and each covers photodetector 106. Similarly, the metal grid openings 1338 are unique to photodetector 106 and each covers photodetector 106. Additionally, a pair of bonding pads 1402 are suspended above a metal grid dielectric layer 1342 on the front side of substrate 118 and extend through antireflective layer 1340 and metal grid dielectric layer 1342 to some leads 128, respectively. Furthermore, the bonding pads 1402 are located on opposite sides of photodetector 106, such that photodetector 106 is located between bonding pads 1402.

[0102] refer to Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B A series of cross-sectional views 1700-2200, 2300A-2300D, 2400A, 2400B are provided for embodiments of methods for forming an image sensor, wherein a passivation layer is configured to generate a dipole moment on a photodetector to reduce dark current. Figures 23A-23D as well as Figure 24A and Figure 24B They are substitutes for each other, with the image sensors being BSI and FSI, and each derived from... Figures 17-22 Performed separately. Figures 23A-23D Show Figure 13 The formation of the image sensor in the process, and Figure 24Aand Figure 24B Show Figure 15 The formation of image sensors in [the system].

[0103] like Figure 17 As shown in cross-sectional view 1700, a first substrate 118 is patterned to form a cavity 1702. The first substrate 118 may be, for example, a bulk substrate of monocrystalline silicon or some other suitable type of substrate. In some embodiments, the first substrate 118 is undoped. In other embodiments, the first substrate 118 is doped with P-type or N-type dopants. The patterning of the cavity 1702 includes: 1) depositing a hard mask layer 1704 over the first substrate 118; 2) patterning the first substrate 118 by a photolithography / etching process; and 3) etching the first substrate 118 with the hard mask layer 1704 in place. The hard mask layer 1704 may be, for example, or comprise undoped silicate glass (USG) and / or some other suitable dielectric. In alternative embodiments, the patterning of the cavity 1702 is performed by some other suitable patterning process.

[0104] like Figure 18 As shown in cross-sectional view 1800, device layer 108 is epitaxially grown to fill cavity 1702 (see, for example, see...). Figure 17 Because device layer 108 is epitaxially grown, it grows outward from the exposed surface of the first substrate 118 within cavity 1702. Furthermore, since hard mask layer 1704 covers the first substrate 118 outside cavity 1702, device layer 108 is entirely or substantially located within cavity 1702. Device layer 108 is a different semiconductor material from the first substrate 118. For example, device layer 108 may be germanium or silicon-germanium, while the first substrate 118 may be silicon. However, in alternative embodiments, other suitable materials are also possible. In some embodiments, device layer 108 has a higher absorption coefficient for NIR and / or IR radiation than the first substrate 118. Additionally, in some embodiments, the band gap of device layer 108 is smaller than that of the first substrate 118.

[0105] like Figure 19 As shown in cross-sectional view 1900, the top surface of device layer 108 is planarized and slotted. Planarization flattens the top surface of device layer 108, and slotting creates a recess in the top surface of device layer 108 relative to the top surface of the first substrate 118. In an alternative embodiment, no slotting is performed on the top surface.

[0106] In some embodiments, planarization and grooving are performed separately. For example, chemical mechanical polishing (CMP) or some other suitable planarization process is performed, followed by etch-back or some other suitable grooving process. In alternative embodiments, planarization and grooving are performed together. For example, a sacrificial layer with a flat top surface may be formed over device layer 108. Then, etch-back can be performed on both the sacrificial layer and device layer 108 using an etchant with the same or similar etch rate.

[0107] like Figure 20 As shown in cross-sectional view 2000, capping layer 110 is epitaxially grown on and covers device layer 108. Furthermore, capping layer 110 is epitaxially grown such that it grows on device layer 108, rather than hard mask layer 1704. Therefore, capping layer 110 is positioned to device layer 108 via a self-aligned process.

[0108] The capping layer 110 is a different semiconductor material from the device layer 108 and may be, for example, silicon or some other suitable semiconductor material. In some embodiments, the capping layer 110 is the same semiconductor material as the first substrate 118 and / or is undoped. The capping layer 110 protects the device layer 108 from damage during subsequent processing. For example, a subsequent wet cleaning process may use an acid with a high etch rate to the device layer 108 but a low etch rate to the capping layer 110. Thus, the device layer 108 will suffer significant crystal damage and / or corrosion, while the capping layer 110 will not. By preventing corrosion and / or crystal damage, leakage current is reduced.

[0109] like Figure 21 As shown in cross-sectional view 2100, a photodetector 106 is formed in device layer 108 and capping layer 110. The photodetector 106 includes a pair of PIN diodes 112 located on opposite sides of device layer 108. Each PIN diode 112 includes a P-type contact region 114 and an N-type contact region 116. The P-type contact region 114 is located between the N-type contact regions 116. In an alternative embodiment, the N-type contact region 116 is located between the P-type contact regions 114. In an alternative embodiment, one of the PIN diodes 112 is omitted.

[0110] In some embodiments, the formation includes: 1) selectively performing ion implantation on the first substrate 118 to form a P-type contact region 114; and 2) selectively performing ion implantation on the first substrate 118 to form an N-type contact region 116. In other embodiments, the photodetector 106 is formed by some other suitable process.

[0111] like Figure 22As shown in cross-sectional view 2200, the hard mask layer 1704 has been removed. The removal of the hard mask layer 1704 can be performed, for example, by etching, CMP, or some other suitable removal process. In an alternative embodiment, the hard mask layer 1704 is not removed and therefore remains thereafter.

[0112] For example Figure 22 As shown in cross-sectional view 2200, a high-k passivation layer 102 is deposited directly on the capping layer 110 and the first substrate 118. The high-k passivation layer 102 is a high-k dielectric material with a dielectric constant exceeding 3.9, 10, or some other suitable value. Deposition can be performed, for example, by atomic layer deposition (ALD), vapor deposition, or some other suitable deposition process.

[0113] The high-k passivation layer 102 reacts with the capping layer 110, thereby causing an interface layer 120 to form between the high-k passivation layer 102 and the capping layer 110. For example, the high-k passivation layer 102 and the capping layer 110 may respectively comprise a metal oxide and silicon, such that the oxygen in the high-k passivation layer 102 reacts with the silicon in the capping layer 110 to form the interface layer 120 as silicon oxide. Furthermore, the high-k passivation layer 102 reacts with the first substrate 118, such that the interface layer 120 extends along the top surface of the first substrate 118. The interface layer 120 is a dielectric having a different band gap than the high-k passivation layer 102 and a smaller regional oxygen density than the high-k passivation layer 102. Due to the different band gap, band bending occurs at the interface 122 between the interface layer 120 and the high-k passivation layer 102. This band bending, in turn, causes the formation of a dipole moment 104 at the interface 122. Because the interface layer 120 has a smaller regional oxygen density than the high-k passivation layer 102, negative charges (illustrated by the minus sign) accumulate along the interface 122 in the high-k passivation layer 102, while positive charges (illustrated by the plus sign) accumulate along the interface 122 in the interface layer 120.

[0114] In some embodiments, the capping layer 110 and the first substrate 118 are silicon, the high-k passivation layer 102 is a metal oxide, and the interface layer 120 is silicon oxide. However, other suitable materials are also possible. In some embodiments, the high-k passivation layer 102 is or includes aluminum oxide (e.g., Al2O3), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), hafnium oxide (HfO2), zirconium oxide (e.g., ZrO2), magnesium oxide (e.g., MgO), some other suitable high-k dielectrics, or any combination thereof. In some embodiments, the dielectric constant of the high-k passivation layer 102 is greater than that of the interface layer 120 and / or has a smaller band gap than that of the interface layer 120.

[0115] In some embodiments, the thickness T of the high-k passivation layer 102 hkp For approximately 110 nanometers, approximately 1-5 nanometers, approximately 5-10 nanometers, or other suitable values. If the thickness T...hkp If the thickness is too large (e.g., greater than about 10 nanometers or some other suitable value), the inherent defects in the high-k passivation layer 102 may lead to high leakage current, thereby offsetting the performance improvement of the dipole moment 104. If the thickness T hkp If it is too small (e.g., less than about 1 nanometer or some other suitable value), the dipole moment 104 may not be formed, and therefore the performance improvement may not be obtained from the dipole moment 104.

[0116] In some embodiments, the interface layer 120 is or comprises semiconductor elements from the first substrate 118, and also includes oxygen and / or some other suitable elements from the high-k passivation layer 102. For example, the interface layer 120 may comprise silicon from the first substrate 118 and oxygen from the high-k passivation layer 102. In some embodiments, the interface layer 120 is or comprises silicon dioxide (e.g., SiO2) and / or some other suitable dielectric. In some embodiments, the thickness T of the interface layer 120 is... i The nanometers are approximately 0.5–2.5 nanometers, approximately 0.5–1.5 nanometers, or approximately 1.5–2.5 nanometers, or some other suitable value.

[0117] During the use of photodetector 106, radiation is emitted toward the object of interest. The radiation reflected from the object then strikes photodetector 106 to generate electron-hole pairs. At different time intervals, PIN diode 112 collects the moving electrons of the electron-hole pairs in N-type contact region 116. The collected electrons are then measured at different time intervals and used to determine the distance to the object. The positive charge of dipole moment 104 draws the moving electrons 124 of dark current in device layer 108 away from PIN diode 112 and neutralizes the moving electrons 124. By neutralizing the moving electrons 124, the dark current is reduced and does not accumulate at N-type contact region 116 of PIN diode 112. As a result, the measurement using PIN diode 112 is more accurate, and therefore the distance determination is more precise.

[0118] exist Figure 22 In the foregoing discussion, image sensing by the photodetector 106 is performed by collecting electrons. However, the photodetector 106 can alternatively perform image sensing by collecting holes. In such an embodiment, holes are collected at the P-type contact region 114. Furthermore, the polarity of the dipole moment 104 is reversed. For example, see... Figure 5A and Figure 5BThe polarity of the dipole moment 104 can be reversed, for example, by forming a high-k passivation layer 102 with a material having a regional oxygen density smaller than that of the interface layer 120. For example, the high-k passivation layer 102 can be or include barium oxide (e.g., BaO), strontium oxide (e.g., SrO), lanthanum oxide (e.g., La2O3), yttrium oxide (e.g., Y2O3), or some other suitable high-k dielectric or any combination thereof.

[0119] exist Figure 22 In the foregoing discussion, the high-k passivation layer 102 is deposited directly on the capping layer 110, and the interface layer 120 is formed through a reaction between the high-k passivation layer 102 and the capping layer 110. Then, an oxide passivation layer (e.g., see...) is applied... Figure 9 The 902 layer is directly deposited on the capping layer 110, and then the high-k passivation layer 102 is directly deposited on the oxide passivation layer. The oxide passivation layer can be deposited, for example, by thermal oxidation, vapor deposition, some other suitable deposition process, or any combination thereof.

[0120] Oxide passivation layer such as Figure 9 Furthermore, since the oxide passivation layer is formed by deposition, it has a higher crystallinity than the interface layer 120. This higher crystallinity results in reduced leakage current and enhanced performance of the photodetector 106.

[0121] like Figure 23A As shown in cross-sectional view 2300A, a first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106, thereby defining a first IC structure 1302. The first interconnect structure 1312 includes multiple leads 128, multiple vias 126, and multiple pads 1316, which are grouped into multiple levels and stacked alternately. The pads 1316 are located on top of the first interconnect structure 1312, and the leads 128 and vias 126 are stacked alternately from the pads 1316 to the photodetector 106.

[0122] A bonding dielectric layer 1318 is located on top of the first interconnect structure 1312 and surrounds the pad 1316 and via 126 at the pad 1316. An etch stop layer 1322 also surrounds the via 126 at the pad 1316. A high-k passivation layer 102 and an interface layer 120 surround the via 126 at the photodetector 106. An interconnect dielectric layer 1320 surrounds the lead 128 and the remaining vias 126.

[0123] like Figure 23B As shown in cross-sectional view 2300B, it forms as about Figure 13The second IC structure 1304 is described above. A plurality of logic devices 1308 are formed to cover the second substrate 1310, and a trench isolation structure 1324 is formed to separate the logic devices 1308. Furthermore, a second interconnect structure 1314 is formed to cover and electrically couple to the logic devices 1308.

[0124] The second interconnect structure 1314 is similar to the first interconnect structure 1312, and therefore includes multiple leads 128, multiple vias 126, and multiple pads 1316, grouped into multiple levels and stacked alternately. The pads 1316 are located on top of the second interconnect structure 1314, and the leads 128 and vias 126 are stacked alternately from the pads 1316 to the logic device 1308. A bonding dielectric layer 1318 is located on top of the second interconnect structure 1314 and surrounds the pads 1316 and vias 126 at the pads 1316. An etch stop layer 1322 also surrounds the vias 126 at the pads 1316. An interconnect dielectric layer 1320 surrounds the leads 128 and the remaining vias 126.

[0125] like Figure 23C As shown in cross-sectional view 2300C, the first IC structure 1302 is vertically flipped and bonded to the second IC structure 1304. The bonding is a hybrid bonding in which the pads 1316 of the first and second interconnect structures 1312, 1314 are in direct contact and the bonding dielectric layer 1318 of the first and second interconnect structures 1312, 1314 is in direct contact.

[0126] like Figure 23D As shown in cross-sectional view 2300D, microlens 1334 and metal grid 1336 are formed and stacked on the back side of first substrate 118 above first substrate 118. Furthermore, antireflective layer 1340 is located between metal grid 1336 and first substrate 118, while metal grid dielectric layer 1342 fills metal grid openings 1338 and separates metal grid 1336 from microlens 1334.

[0127] As mentioned above, Figures 23A-23D The image sensor is shown to be configured as a BSI. However, the image sensor can alternatively be an FSI. In such an alternative embodiment, the following description is performed. Figure 24A and Figure 24B The described action, replacing the discussion about Figures 23A-23D The aforementioned action. Therefore, in an alternative embodiment, the method can be derived from... Figures 17-22 Progressing to Figure 24A and Figure 24B (jump over Figures 23A-23D ).

[0128] like Figure 24A As shown in cross-sectional view 2400A, a first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106. (See also...) Figure 23AThe first interconnect structure 1312 is formed, but the pads 1316, bonding dielectric layer 1318, and etch stop layer 1322 are omitted. Furthermore, the interconnect dielectric layer 1320 of the first interconnect structure 1312 covers the top layer of the conductor 128.

[0129] like Figure 24B As shown in cross-sectional view 2400B, microlens 1334 and metal grid 1336 are formed and stacked on the front side of first substrate 118 above interconnect structure 1312. Furthermore, anti-reflective layer 1340 is located between metal grid 1336 and interconnect structure 1312, while metal grid dielectric layer 1342 fills metal grid openings 1338 and separates metal grid 1336 from microlens 1334.

[0130] Although various embodiments of the reference method are described Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B However, it should be understood that Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B The structure shown is not limited to this method, but can be separated from it independently. Although Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B It is described as a series of actions, but it should be understood that the order of the actions may be changed in other embodiments. Although Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0131] refer to Figure 25 Provided Figures 17-22 , Figures 23A-23D , Figure 24A and Figure 24B Block diagram 2500 shows some embodiments of the method.

[0132] At 2502, the substrate is patterned to form the cavity. See, for example, [link to example]. Figure 17 .

[0133] At position 2504, an epitaxial device layer is grown to fill the cavity. See, for example, [link to example]. Figure 18 .

[0134] At position 2506, the device layer is planarized to make the top surface of the device layer flat. For example, see... Figure 19 .

[0135] At position 2508, a capping layer is epitaxially grown to cover the device layer. See, for example, [link to example]. Figure 20 .

[0136] At position 2510, a photodetector is formed in the capping layer and the device layer. See, for example, [link to documentation]. Figure 21 .

[0137] At position 2512, a high-k passivation layer is deposited over the caprock, which induces a dipole moment along the top surface of the caprock. See, for example, [link to relevant documentation]. Figure 22 In some embodiments, the high-k passivation layer is deposited directly on the capping layer. In other embodiments, the oxide passivation layer is deposited directly on the capping layer, and the high-k passivation layer is deposited directly on the oxide passivation layer.

[0138] At position 2514, an interconnect structure covering a high-k passivation layer is formed, which is electrically coupled to a photodetector through contact vias in the high-k passivation layer. See, for example, [link to relevant documentation]. Figure 23A or Figure 24A .

[0139] At position 2516, a microlens is formed on the front or back side of the substrate, vertically aligned with the photodetector. See, for example, [link to example]. Figure 23D or Figure 24B .

[0140] Although this article will Figure 25 Block diagram 2500 illustrates and describes a series of actions or events; however, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all actions shown are used to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0141] refer to Figures 26-32 A series of cross-sectional views 2600-3200 of some first embodiments of a method for forming an image sensor are provided, wherein the bottom surface of the device layer is raised above the top surface of the substrate, and wherein a passivation layer is configured to generate a dipole moment above a photodetector in the device layer to reduce dark current. Figure 31 and Figure 32 They are substitutes for each other, with the image sensors being BSI and FSI, and each derived from... Figures 26-30 Performed separately.

[0142] like Figure 26As shown in cross-sectional view 2600, a semiconductor layer 2602 is epitaxially grown to cover the first substrate 118. The semiconductor layer 2602 is a different semiconductor material from the first substrate 118. For example, the semiconductor layer 2602 may be germanium or silicon-germanium, while the first substrate 118 may be silicon. However, in alternative embodiments, other suitable materials are also possible. In some embodiments, the semiconductor layer 2602 has a higher absorption coefficient for NIR and / or IR radiation than the first substrate 118. In some embodiments, the band gap of the semiconductor layer 2602 is smaller than that of the first substrate 118.

[0143] like Figure 27 As shown in cross-sectional view 2700, patterned semiconductor layer 2602 (e.g., see...) Figure 26 The patterning process can include, for example, 1) forming a mask over the semiconductor layer 2602; 2) etching the semiconductor layer 2602 with the mask in place; and 3) removing the mask. The mask can be, for example, a photoresist mask and / or some other suitable type of mask. In other embodiments, the patterning is performed using some other suitable process.

[0144] As by Figures 28-30 The cross-sectional diagrams 2800-3000 are shown below. The following steps are performed respectively regarding... Figures 20-22 The actions described. Figure 28 In China, such as regarding Figure 20 The capping layer 110 is epitaxially grown on and covers the device layer 108. Since the sidewalls of the device layer 108 are exposed, the capping layer 110 is also grown on the sidewalls of the device layer 108. Furthermore, epitaxial growth is performed such that the capping layer 110 is formed on the device layer 108, but not on the substrate 118. In an alternative embodiment, the capping layer 110 is also grown on the substrate 118. Figure 29 In China, such as regarding Figure 21 The photodetector 106 is formed in the device layer 108 and the capping layer 110. Figure 30 In China, such as regarding Figure 22 The high-k passivation layer 102 is deposited directly on the capping layer 110 and the first substrate 118 to form the interface layer 120. Then, an oxide passivation layer (e.g., see...) is applied... Figure 12A The high-k passivation layer 102 is deposited directly on the oxide passivation layer 110, with the 902 layer deposited directly on top of the capping layer 110. In an alternative embodiment, the polarity of the high-k passivation layer 102 is reversed (e.g., see [reference]). Figure 5A , Figure 5B and Figure 6 ).

[0145] like Figure 31 As shown in the cross-sectional view 3100, the execution regarding Figures 23A-23D The aforementioned action makes the image sensor a BSI (Browser Sensor). Specifically, as per [reference to...] Figure 23A The first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106, thereby defining the first IC structure 1302. (See also: ...) Figure 23B The second IC structure 1304 is formed. (As per...) Figure 23C The first IC structure 1302 is vertically flipped and bonded to the second IC structure 1304. (As per...) Figure 23D The microlens 1334 and the metal grid 1336 are formed to be stacked on the back side of the first substrate 118 above the first substrate 118.

[0146] Figure 31 A method for forming an image sensor as a BSI is shown. However, this method can alternatively form the image sensor as an FSI. In such an alternative embodiment, the method... Figures 26-30 Progressing to Figure 32 ,jump over Figure 31 Furthermore, in Figure 32 The execution of the relevant regulations Figure 24A and Figure 24B The actions described. Specifically, as regarding Figure 24A The first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106. Furthermore, as per [the relevant information]... Figure 24B The microlens 1334 and the metal grid 1336 are formed to be stacked on the front side of the first substrate 118 above the first interconnect structure 1312.

[0147] Although various embodiments of the reference method are described Figures 26-32 However, it should be understood that Figures 26-32 The structure shown is not limited to this method, but can be used independently of it. Although Figures 26-32 It is described as a series of actions, but it should be understood that the order of the actions may be changed in other embodiments. Although Figures 26-32 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0148] refer to Figure 33 Provided Figures 26-32 A block diagram 3300 shows some embodiments of the method.

[0149] At position 3302, a semiconductor layer is epitaxially grown over the substrate. See, for example, [link to example]. Figure 26 .

[0150] At 3304, the semiconductor layer is patterned to form the device layer. See, for example, [link to example]. Figure 27 .

[0151] At position 3306, a capping layer is epitaxially grown on the top surface and sidewalls of the device layer. See, for example, [link to documentation]. Figure 28 .

[0152] At position 3308, a photodetector is formed in the capping layer and the device layer. See, for example, [link to documentation]. Figure 29 .

[0153] At 3310, a high-k passivation layer is deposited over the caprock, which induces a dipole moment along the top surface of the caprock. See, for example, [link to relevant documentation]. Figure 30 In some embodiments, the high-k passivation layer is deposited directly on the capping layer. In other embodiments, the oxide passivation layer is deposited directly on the capping layer, and the high-k passivation layer is deposited directly on the oxide passivation layer.

[0154] At position 3312, an interconnect structure covering a high-k passivation layer is formed, which is electrically coupled to a photodetector through contact vias in the high-k passivation layer. See, for example, [link to relevant documentation]. Figure 31 or Figure 32 .

[0155] At position 3314, a microlens is formed on the front or back side of the substrate, vertically aligned with the photodetector. See, for example, [reference needed]. Figure 31 or Figure 32 .

[0156] Although this article will Figure 33 Block diagram 3300 illustrates and describes a series of actions or events; however, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all actions shown are used to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0157] refer to Figures 34-42 A series of cross-sectional views 3400-4200 of some second embodiments of a method for forming an image sensor are provided, wherein the bottom surface of the device layer is raised above the top surface of the substrate, and wherein a passivation layer is configured to generate a dipole moment above a photodetector in the device layer to reduce dark current. Figure 41 and Figure 42 They are substitutes for each other, with the image sensors being BSI and FSI, and each derived from... Figures 34-40 Performed separately.

[0158] like Figure 34As shown in cross-sectional view 3400, a photodetector inter-dielectric layer 1202 is deposited over the first substrate 118. The photodetector inter-dielectric layer 1202 may be, for example, silicon oxide and / or some other suitable dielectric. The photodetector inter-dielectric layer 1202 may be deposited, for example, by thermal oxidation, vapor deposition or some other suitable deposition process.

[0159] like Figure 35 As shown in the cross-sectional view 3500, the dielectric layer 1202 between photodetectors is patterned to form the cavity 3502. This patterning can be performed, for example, by photolithography / etching or other suitable patterning processes.

[0160] like Figures 36-40 The cross-sectional diagrams 3600-4000 are shown below. The following steps are performed respectively regarding... Figures 18-22 The actions described. Figure 36 In China, such as regarding Figure 18 The epitaxial growth filling cavity 3502 (for example, see...) Figure 35 Device layer 108. Figure 37 In China, such as regarding Figure 19 The top surface of the planarized device layer 108. However, the top surface of the device layer 108 is not slotted relative to the top surface of the photodetector inter-dielectric layer 1202. In an alternative embodiment, according to Figure 19 The slot is created on the top surface of the device layer 108, relative to the top surface of the dielectric layer 1202 between the photodetectors. Figure 38 In this process, an epitaxial capping layer 110 is grown, thus it is located on and covers the device layer 108, as per [reference to...]. Figure 20 In an alternative embodiment, the capping layer 110 is epitaxially grown, and therefore it also covers the inter-photodetector dielectric layer 1202. Figure 39 In China, such as regarding Figure 21 The photodetector 106 is formed in the device layer 108 and the capping layer 110. Figure 40 In China, such as regarding Figure 22 The high-k passivation layer 102 is deposited directly on the capping layer 110 and the first substrate 118. Then, an oxide passivation layer (e.g., see...) is applied. Figure 9 The 902) is directly deposited on the capping layer 110, and the high-k passivation layer 102 is directly deposited on the oxide passivation layer.

[0161] like Figure 41 As shown in the cross-sectional diagram 4100, the execution regarding Figures 23A-23D The aforementioned action makes the image sensor a BSI (Browser Sensor). Specifically, as per [reference to...] Figure 23A The first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106, thereby defining the first IC structure 1302. (See also: ...) Figure 23BThe second IC structure 1304 is formed. (As per...) Figure 23C The first IC structure 1302 is vertically flipped and bonded to the second IC structure 1304. (As per...) Figure 23D The microlens 1334 and the metal grid 1336 are formed to be stacked on the back side of the first substrate 118 above the first substrate 118.

[0162] Figure 41 A method for forming an image sensor as a BSI is shown. However, this method can alternatively form the image sensor as an FSI. In such an alternative embodiment, the method... Figures 34-40 Progressing to Figure 42 ,jump over Figure 41 Furthermore, in Figure 42 The execution of the relevant regulations Figure 24A and Figure 24B The actions described. Specifically, as regarding Figure 24A The first interconnect structure 1312 is formed above and electrically coupled to the photodetector 106. Furthermore, as per [the relevant information]... Figure 24B The microlens 1334 and the metal grid 1336 are formed to be stacked on the front side of the substrate 118 above the first interconnect structure 1312. Various embodiments of the reference method are described. Figures 34-42 However, it should be understood that Figures 34-42 The structure shown is not limited to this method, but can be used independently of it. Although Figures 34-42 It is described as a series of actions, but it should be understood that the order of the actions may be changed in other embodiments.

[0163] Although Figures 34-42 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0164] refer to Figure 43 Provided Figures 34-42 A block diagram 4300 shows some embodiments of the method.

[0165] At position 4302, an inter-photodetector dielectric layer is deposited above the substrate. See, for example, [link to example]. Figure 34 .

[0166] At 4304, a patterned dielectric layer between photodetectors is used to form a cavity. See, for example, [link to example]. Figure 35 .

[0167] At position 4306, an epitaxial device layer is grown to fill the cavity. See, for example, [link to example]. Figure 36 .

[0168] At 4308, the device layer is planarized to make the top surface of the device layer flat. For example, see... Figure 37 .

[0169] At position 4310, a capping layer is epitaxially grown to cover the device layer. See, for example, [link to example]. Figure 38 .

[0170] At position 4312, a photodetector is formed in the capping layer and the device layer. See, for example, [link to documentation]. Figure 39 .

[0171] At location 4314, a high-k passivation layer is deposited over the caprock, which induces a dipole moment along the top surface of the caprock. See, for example, [link to relevant documentation]. Figure 40 In some embodiments, the high-k passivation layer is deposited directly on the capping layer. In other embodiments, the oxide passivation layer is deposited directly on the capping layer, and the high-k passivation layer is deposited directly on the oxide passivation layer.

[0172] At position 4316, an interconnect structure covering a high-k passivation layer is formed, which is electrically coupled to a photodetector through contact vias in the high-k passivation layer. See, for example, [link to relevant documentation]. Figure 41 or Figure 42 .

[0173] At position 4318, a microlens is formed on the front or back side of the substrate, vertically aligned with the photodetector. See, for example, [link to example]. Figure 41 or Figure 42 .

[0174] Although this article will Figure 43 Block diagram 4300 illustrates and describes a series of actions or events; however, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, it is not required that all actions shown are used to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0175] In some embodiments, this disclosure provides an image sensor comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer and the device layer are semiconductor materials, and wherein the capping layer has a larger band gap than the device layer; a photodetector located in the device layer and the capping layer; and a passivation layer covering the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer. In some embodiments, the image sensor further comprises an interface layer located between and in direct contact with the passivation layer and the capping layer, wherein the passivation layer is a high-k dielectric material. In some embodiments, the passivation layer causes the formation of an interface layer between and in direct contact with the passivation layer and the capping layer, wherein the dipole moment spans the interface where the passivation layer and the interface layer are in direct contact. In some embodiments, the passivation layer comprises: a silicon oxide layer covering and in direct contact with the capping layer; and a high-k dielectric layer covering and in direct contact with the silicon oxide layer, wherein the dipole moment spans the interface where the high-k dielectric layer and the silicon oxide layer are in direct contact. In some embodiments, the device layer is inserted into the substrate such that the substrate is located on the sidewall of the device layer. In some embodiments, the bottom surface of the device layer is raised above the top surface of the substrate. In some embodiments, a capping layer extends from the top surface of the device layer to the sidewall of the device layer around the apex corner of the device layer and along the sidewall of the device layer. In some embodiments, the photodetector includes a pair of PIN diodes located in the capping layer and the device layer, wherein the PIN diodes are located on opposite sides of the device layer. In some embodiments, the image sensor further includes a contact via extending from the photodetector through a passivation layer, wherein the passivation layer and the contact via have flat top surfaces.

[0176] In some embodiments, this disclosure provides another image sensor, comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer, the device layer, and the substrate are semiconductor materials, and wherein the device layer is a different semiconductor material from the substrate and the capping layer; a photodetector located in the device layer and the capping layer; a first dielectric layer covering and directly contacting the capping layer; and a second dielectric layer covering and directly contacting the first dielectric layer, wherein the first and second dielectric layers comprise oxides, and wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer. In some embodiments, the first dielectric layer comprises a semiconductor element from the capping layer and further comprises an oxide from the second dielectric layer. In some embodiments, the substrate and the capping layer are silicon, and the device layer comprises germanium. In some embodiments, the first dielectric layer has a negative charge at the interface where the first and second dielectric layers directly contact, and the second dielectric layer has a positive charge at that interface. In some embodiments, the first dielectric layer has a positive charge at the interface where the first and second dielectric layers directly contact, and the second dielectric layer has a negative charge at that interface. In some embodiments, the device layer is slotted to the top of the substrate, wherein the substrate has p-type implantation regions that line the device layer. In some embodiments, the device layer has a bottom surface that rises above the top surface of the substrate, wherein a capping layer and a first dielectric layer and a second dielectric layer extend from top to bottom along the sidewalls of the device layer.

[0177] In some embodiments, this disclosure provides a method for forming an image sensor, comprising: epitaxially growing a device layer over a substrate; epitaxially growing a capping layer over the device layer, wherein the capping layer has a band gap larger than that of the device layer; forming a photodetector in the device layer and the capping layer; and depositing a passivation layer over the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer. In some embodiments, the passivation layer comprises a high-k dielectric layer, wherein the deposition of the passivation layer comprises depositing the high-k dielectric layer directly on the capping layer, thereby causing a silicon oxide interface layer to be formed between the capping layer and the high-k dielectric layer. In some embodiments, the passivation layer comprises a silicon oxide layer and a high-k dielectric layer, wherein the deposition of the passivation layer comprises: depositing the silicon oxide layer directly on the capping layer; and depositing the high-k dielectric layer directly on the silicon oxide layer. In some embodiments, the method further comprises patterning a substrate to form a cavity, wherein the device layer is epitaxially grown in the cavity.

[0178] Embodiments of this application provide an image sensor, comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer and the device layer are semiconductor materials, and wherein the capping layer has a larger band gap than the device layer; a photodetector located in the device layer and the capping layer; and a passivation layer covering the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer. In some embodiments, it further comprises: an interface layer located between the passivation layer and the capping layer and in direct contact with the passivation layer and the capping layer, wherein the passivation layer is a high-k dielectric material. In some embodiments, the passivation layer causes the formation of an interface layer between the passivation layer and the capping layer and in direct contact with the passivation layer and the capping layer, and wherein the dipole moment spans the interface where the passivation layer and the interface layer directly contact. In some embodiments, the passivation layer includes: a silicon oxide layer covering and directly contacting the capping layer; and a high-k dielectric layer covering and directly contacting the silicon oxide layer, wherein the dipole moment spans the interface where the high-k dielectric layer and the silicon oxide layer directly contact. In some embodiments, a device layer is inserted into the substrate such that the substrate is located on the sidewall of the device layer. In some embodiments, the bottom surface of the device layer is raised above the top surface of the substrate. In some embodiments, the capping layer extends from the top surface of the device layer to the sidewall of the device layer around the apex corner of the device layer and along the sidewall of the device layer. In some embodiments, the photodetector includes a pair of PIN diodes located in the capping layer and the device layer, wherein the PIN diodes are located on opposite sides of the device layer. In some embodiments, a contact via extends from the photodetector through the passivation layer, wherein the passivation layer and the contact via have flat top surfaces.

[0179] Embodiments of this application provide an image sensor, comprising: a substrate; a device layer covering the substrate; a capping layer covering the device layer, wherein the capping layer, the device layer, and the substrate are semiconductor materials, and wherein the device layer is a semiconductor material different from the substrate and the capping layer; a photodetector located in the device layer and the capping layer; a first dielectric layer covering and directly contacting the capping layer; and a second dielectric layer covering and directly contacting the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise oxides, and wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer. In some embodiments, the first dielectric layer and the substrate comprise silicon. In some embodiments, the substrate and the capping layer are silicon, and wherein the device layer comprises germanium. In some embodiments, the first dielectric layer has a negative charge at the interface where the first dielectric layer and the second dielectric layer directly contact, and wherein the second dielectric layer has a positive charge at the interface. In some embodiments, the first dielectric layer has a positive charge at the interface where the first dielectric layer and the second dielectric layer directly contact, and wherein the second dielectric layer has a negative charge at the interface. In some embodiments, the device layer is slotted to the top of the substrate, and the substrate has a p-type implantation region lining the device layer. In some embodiments, the device layer has a bottom surface that rises above the top surface of the substrate, and the capping layer, as well as the first dielectric layer and the second dielectric layer, extend from top to bottom along the sidewalls of the device layer.

[0180] Embodiments of this application provide a method for forming an image sensor, comprising: epitaxially growing a device layer over a substrate; epitaxially growing a capping layer over the device layer, wherein the capping layer has a larger band gap than the device layer; forming a photodetector in the device layer and the capping layer; and depositing a passivation layer over the capping layer, wherein the passivation layer causes a dipole moment to form along the top surface of the capping layer. In some embodiments, the passivation layer comprises a high-k dielectric layer, and wherein the deposition of the passivation layer comprises depositing the high-k dielectric layer directly on the capping layer, thereby causing a silicon oxide interface layer to be formed between the capping layer and the high-k dielectric layer. In some embodiments, the passivation layer comprises a silicon oxide layer and a high-k dielectric layer, and wherein the deposition of the passivation layer comprises: depositing the silicon oxide layer directly on the capping layer; and depositing the high-k dielectric layer directly on the silicon oxide layer. In some embodiments, the method further comprises: patterning the substrate to form a cavity, wherein the device layer is epitaxially grown in the cavity.

[0181] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An image sensor, comprising: a substrate; a device layer overlying the substrate; a cap layer overlying the device layer, wherein the cap layer and the device layer are semiconductor materials, and wherein the cap layer has a larger bandgap than the device layer; a photodetector comprising a pair of PIN diodes in the device layer and the cap layer, the pair of PIN diodes comprising a pair of contact regions of opposite conductivity types, a top surface of the cap layer being coplanar with a top surface of the pair of contact regions; and a passivation layer overlying the top surface of the cap layer, wherein the passivation layer causes a dipole moment to form along the top surface of the cap layer.

2. The image sensor of claim 1, further comprising: an interface layer between and directly contacting the passivation layer and the cap layer, wherein the passivation layer is a high-k dielectric material.

3. The image sensor of claim 1, wherein, the passivation layer causes formation of an interface layer between and directly contacting the passivation layer and the cap layer, and wherein the dipole moment spans the interface where the passivation layer and the interface layer directly contact.

4. The image sensor of claim 1, wherein, the passivation layer comprises: a silicon oxide layer overlying and directly contacting the cap layer; and a high-k dielectric layer overlying and directly contacting the silicon oxide layer, wherein the dipole moment spans the interface where the high-k dielectric layer and the silicon oxide layer directly contact.

5. The image sensor of claim 1, wherein, the device layer is inset into the substrate such that the substrate is on a sidewall of the device layer.

6. The image sensor of claim 1, wherein, a bottom surface of the device layer is elevated above a top surface of the substrate.

7. The image sensor of claim 6, wherein, the cap layer surrounds a top corner of the device layer from a top surface of the device layer to a sidewall of the device layer, and extends along the sidewall of the device layer.

8. The image sensor of claim 1, wherein, the PIN diodes are on opposite sides of the device layer, respectively.

9. The image sensor of claim 1, further comprising: a contact via extending from the photodetector through the passivation layer, wherein the passivation layer and the contact via have respective top surfaces that are planar.

10. An image sensor, comprising: a substrate; a device layer overlying the substrate; a cap layer overlying the device layer, wherein the cap layer and the device layer and the substrate are semiconductor materials, and wherein the device layer is a different semiconductor material than the substrate and the cap layer; a photodetector comprising a pair of PIN diodes in the device layer and the cap layer, the pair of PIN diodes comprising a pair of contact regions of opposite conductivity types, a top surface of the cap layer being coplanar with a top surface of the pair of contact regions; a first dielectric layer overlying and directly contacting the cap layer; and a second dielectric layer overlying and directly contacting the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise oxides, and wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer, the second dielectric layer causing a dipole moment to form along the top surface of the cap layer.

11. The image sensor of claim 10, wherein, the first dielectric layer and the substrate comprise silicon.

12. The image sensor of claim 10, wherein, the substrate and the cap layer are silicon, and wherein the device layer comprises germanium.

13. The image sensor of claim 10, wherein, The first dielectric layer has a negative charge at an interface where the first dielectric layer is in direct contact with the second dielectric layer, and wherein the second dielectric layer has a positive charge at the interface.

14. The image sensor of claim 10, wherein, The first dielectric layer has a positive charge at an interface where the first dielectric layer is in direct contact with the second dielectric layer, and wherein the second dielectric layer has a negative charge at the interface.

15. The image sensor of claim 10, wherein, The device layer is recessed to a top of the substrate, and wherein the substrate has a p-type implant region lining the device layer.

16. The image sensor of claim 10, wherein, The device layer has a bottom surface elevated above a top surface of the substrate, and wherein the cap layer and the first and second dielectric layers extend from a top to a bottom along sidewalls of the device layer.

17. A method for forming an image sensor, comprising: epitaxially growing a device layer over a substrate; epitaxially growing a cap layer over the device layer, wherein the cap layer has a larger bandgap than the device layer; forming a pair of PIN diodes of a photodetector in the device layer and the cap layer, wherein the pair of PIN diodes includes a pair of contact regions of opposite conductivity types, a top surface of the cap layer being coplanar with top surfaces of the pair of contact regions; and depositing a passivation layer over the top surface of the cap layer, wherein the passivation layer causes a dipole moment to form along the top surface of the cap layer.

18. The method of claim 17, wherein, The passivation layer includes a high-k dielectric layer, and wherein the depositing of the passivation layer includes depositing the high-k dielectric layer directly on the cap layer, thereby causing a silicon oxide interface layer to form between the cap layer and the high-k dielectric layer.

19. The method of claim 17, wherein, The passivation layer includes a silicon oxide layer and a high-k dielectric layer, and wherein the depositing of the passivation layer includes: depositing the silicon oxide layer directly on the cap layer; and depositing the high-k dielectric layer directly on the silicon oxide layer.

20. The method of claim 17, further comprising: patterning the substrate to form a cavity, wherein the device layer is epitaxially grown in the cavity.

Images