Display substrate, manufacturing method thereof, and display device

Abstract

The application discloses a display substrate and a manufacturing method thereof and a display device, and belongs to the technical field of display. The display substrate comprises a substrate and a display structure layer on the substrate. The substrate has a display area and a non-display area, and the display area comprises a target display area. The display structure layer comprises a plurality of sub-pixels, each of which comprises a light-emitting unit and a driving unit. The light-emitting unit is located in the display area, and the driving unit comprises a target functional film layer. The light-emitting unit in the target display area is a target light-emitting unit, the target driving unit of the target light-emitting unit is located in the non-display area, the target light-emitting unit and the target driving unit are electrically connected through a target connection structure, and the target connection structure comprises a first connection trace. The first connection trace is a transparent trace, and the first connection trace and the target functional film layer are of the same layer and material. The application helps to simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate, a manufacturing method thereof and a display device. BACKGROUND

[0002] Under display camera (UDC) technology refers to a technology of setting a camera between a display screen and a housing of a display device. In the UDC technology, a driving circuit of a light emitting unit in a camera corresponding area in the display screen is arranged in a non-display area of the display screen, and the light emitting unit in the camera corresponding area is connected with the driving circuit in the non-display area through a transparent connection trace, so as to drive the light emitting unit in the camera corresponding area to emit light through the driving circuit in the non-display area. SUMMARY

[0003] The present application provides a display substrate, a manufacturing method thereof and a display device. The manufacturing process of the display substrate is simplified, and the manufacturing cost of the display substrate is reduced. The technical solution is as follows:

[0004] In a first aspect, a display substrate is provided, which comprises:

[0005] A substrate substrate has a display area and a non-display area, and the display area includes a target display area;

[0006] A display structure layer is located on the substrate substrate, and the display structure layer includes a plurality of sub-pixels, the sub-pixels include a light emitting unit and a driving unit, the light emitting unit is located in the display area, and the driving unit includes a target functional film layer;

[0007] The light emitting unit in the target display area is a target light emitting unit, the target driving unit of the target light emitting unit is located in the non-display area, the target light emitting unit and the target driving unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, the target connection structure includes a first connection trace, the first connection trace is a transparent trace, and the first connection trace and the target functional film layer are of the same layer and the same material.

[0008] Optionally, the driving unit includes an oxide active layer, the target functional film layer is the oxide active layer, and the hydrogen content of a target film layer in the display substrate in contact with the first connection trace is higher than a preset threshold.

[0009] Optionally, the material of the target film layer includes at least one of an organic material and silicon nitride.

[0010] Optionally, the display structure layer comprises an interlayer structure layer between the first connection trace and the target film layer, the interlayer structure layer has a contact hole, and the target film layer contacts the first connection trace through the contact hole.

[0011] Optionally, a ratio of an overlapping area of the contact hole and the first connection trace to an area of a projection of the first connection trace on the substrate is greater than a preset ratio, and the overlapping area is an area of an overlapping region of a projection of the contact hole on the substrate and a projection of the first connection trace on the substrate.

[0012] Optionally, the interlayer structure layer has one contact hole, and a projection of the contact hole on the substrate covers a projection of the first connection trace on the substrate.

[0013] Optionally, the interlayer structure layer has a plurality of contact holes, and the plurality of contact holes are uniformly distributed in a first area of the interlayer structure layer, and the first area corresponds to the first connection trace.

[0014] Optionally, the target film layer comprises at least one of a planar layer and a passivation layer.

[0015] In the present application, the target connection structure comprises the following three implementation manners.

[0016] In a first implementation manner, the target connection structure further comprises a second connection trace and a third connection trace, and the second connection trace and the third connection trace are located in the same layer.

[0017] The second connection trace is located in the non-display area, and the second connection trace is electrically connected with the first connection trace and the target driving unit respectively.

[0018] The third connection trace is a transparent trace, the third connection trace is located in the target display area, and the third connection trace is electrically connected with the first connection trace and the target light emitting unit respectively.

[0019] In a second implementation manner, the target connection structure further comprises a second connection trace, a third connection trace and a fourth connection trace, the second connection trace and the fourth connection trace are located in the same layer, and the third connection trace is located on a side of the fourth connection trace away from the substrate.

[0020] The second connection trace is located in the non-display area, and the second connection trace is electrically connected with the first connection trace and the target driving unit respectively.

[0021] The third connection wire is a transparent wire, the third connection wire and the fourth connection wire are located in the target display area, the fourth connection wire is electrically connected with the third connection wire and the first connection wire respectively, and the third connection wire is electrically connected with the target light emitting unit.

[0022] The target light emitting unit includes an anode, and a projection of the fourth connection wire on the substrate substrate is located in a projection of the anode on the substrate substrate.

[0023] Optionally, in the first and second implementations, the target connection structure further includes a fifth connection wire.

[0024] The fifth connection wire is a transparent wire, the fifth connection wire is located in the target display area, and the fifth connection wire is located on a side of the third connection wire away from the substrate substrate.

[0025] The third connection wire is electrically connected with the target light emitting unit through the fifth connection wire.

[0026] In a third implementation, the target connection structure further includes a second connection wire,

[0027] The second connection wire is located in the non-display area, and the second connection wire is electrically connected with the first connection wire and the target drive unit respectively.

[0028] The first connection wire is electrically connected with the target light emitting unit.

[0029] In a second aspect, a manufacturing method of a display substrate is provided, and the method includes:

[0030] Providing a substrate substrate having a display area and a non-display area, the display area including a target display area;

[0031] Forming a display structure layer on the substrate substrate, the display structure layer including a plurality of sub-pixels, the sub-pixels including a light emitting unit and a drive unit, the light emitting unit being located in the display area, and the drive unit including a target functional film layer;

[0032] The light emitting unit located in the target display area is a target light emitting unit, the target drive unit of the target light emitting unit is located in the non-display area, the target light emitting unit and the target drive unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, the target connection structure includes a first connection wire, the first connection wire is a transparent wire, and the first connection wire is in the same layer and same material as the target functional film layer.

[0033] Optionally, forming a display structure layer on the substrate substrate, comprising:

[0034] forming a functional material layer on the substrate substrate;

[0035] processing the functional material layer by a one-time patterning process to obtain the target functional film layer and the first connection trace.

[0036] Optionally, the driving unit includes an oxide active layer, the target functional film layer is the oxide active layer, and a hydrogen content of the target film layer in the display substrate that contacts the first connection trace is higher than a preset threshold.

[0037] Optionally, forming a display structure layer on the substrate substrate, further comprising:

[0038] forming an interlayer structure layer on a side of the first connection trace away from the substrate substrate, the interlayer structure layer having a contact hole therein;

[0039] forming a target film layer on a side of the interlayer structure layer away from the substrate substrate, the target film layer contacting the first connection trace through the contact hole.

[0040] In the present application, the target connection structure includes three implementation manners, and correspondingly, forming a display structure layer on the substrate substrate includes the following three implementation manners.

[0041] The first implementation manner, forming a display structure layer on the substrate substrate, further comprises:

[0042] forming a second connection trace and a third connection trace on a side of the interlayer structure layer away from the substrate substrate, the second connection trace and the third connection trace being located in the same layer, the second connection trace being located in the non-display area, the third connection trace being a transparent trace, and the third connection trace being located in the target display area;

[0043] The target connection structure further includes the second connection trace and the third connection trace, the second connection trace being electrically connected with the first connection trace and the target driving unit respectively, and the third connection trace being electrically connected with the first connection trace and the target light emitting unit respectively.

[0044] The second implementation manner, forming a display structure layer on the substrate substrate, further comprises:

[0045] a second connection trace, a third connection trace and a fourth connection trace are formed on a side of the interlayer structure layer away from the substrate, the second connection trace and the fourth connection trace are located in a same layer, the third connection trace is located on a side of the fourth connection trace away from the substrate, the second connection trace is located in the non-display region, the third connection trace is a transparent trace, and the third connection trace and the fourth connection trace are both located in the target display region.

[0046] In the third implementation manner, the target connection structure further includes the fifth connection trace, and the third connection trace is electrically connected with the target light emitting unit through the fifth connection trace.

[0047] In the first implementation manner and the second implementation manner, the display structure layer is formed on the substrate, and the display structure layer further includes:

[0048] a fifth connection trace is formed on a side of the third connection trace away from the substrate, the fifth connection trace is a transparent trace, and the fifth connection trace is located in the target display region.

[0049] The target connection structure further includes the fifth connection trace, and the third connection trace is electrically connected with the target light emitting unit through the fifth connection trace.

[0050] In the third implementation manner, the display structure layer is formed on the substrate, and the display structure layer further includes:

[0051] a second connection trace is formed on a side of the interlayer structure layer away from the substrate, the second connection trace is located in the non-display region.

[0052] The target connection structure further includes the second connection trace, and the second connection trace is electrically connected with the first connection trace and the target driving unit respectively, and the first connection trace is electrically connected with the target light emitting unit.

[0053] In a third aspect, a display device is provided, and the display device includes a housing, a camera and the display substrate of the first aspect or any optional implementation manner of the first aspect.

[0054] The camera is arranged between the housing and the display substrate, and a projection of the camera on the display substrate is located in a target display region of the display substrate.

[0055] The technical scheme provided by the application has at least the following beneficial effects:

[0056] The display substrate and the manufacturing method thereof and the display device provided by the application, in the display substrate, a sub-pixel comprises a light-emitting unit and a driving unit, the driving unit comprises a target functional film layer, the display substrate comprises a display area and a target display area, a target driving unit of a target light-emitting unit in the target display area is located in a non-display area of the display substrate, and the target light-emitting unit and the target driving unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, and the target connection structure comprises a first connection trace, the first connection trace is of the same layer and the same material as the target functional film layer. Since the first connection trace is of the same layer and the same material as the target functional film layer, the first connection trace and the target functional film layer can be prepared through a one-time patterning process, which helps to reduce the number of patterning processes required to be performed in the process of manufacturing the display substrate, simplifies the manufacturing process of the display substrate, and reduces the manufacturing cost of the display substrate.

[0057] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical schemes in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0059] Figure 1 is a front view of a display substrate provided by an embodiment of the application;

[0060] Figure 2 is a cross-sectional view of a display substrate provided by an embodiment of the application;

[0061] Figure 3 is a cross-sectional view of another display substrate provided by an embodiment of the application;

[0062] Figure 4 is a cross-sectional view of still another display substrate provided by an embodiment of the application;

[0063] Figure 5 is a cross-sectional view of yet another display substrate provided by an embodiment of the application;

[0064] Figure 6 is a cross-sectional view of still another display substrate provided by an embodiment of the application;

[0065] Figure 7 is a cross-sectional view of yet another display substrate provided by an embodiment of the application;

[0066] Figure 8 is a pixel circuit diagram provided by an embodiment of the present application;

[0067] Figure 9 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the present application;

[0068] Figure 10 is a flowchart of another manufacturing method of a display substrate provided by an embodiment of the present application;

[0069] Figure 11 is a schematic diagram of sequentially forming a barrier layer, a second buffer layer, a polysilicon active layer, a second GI layer, a first gate, a second ILD layer, a second gate, a third ILD layer, and a first buffer layer on a substrate;

[0070] Figure 12 is a schematic diagram of forming a target functional film layer and a first connection trace on a side of the first buffer layer away from the substrate;

[0071] Figure 13 is a schematic diagram of sequentially forming a first GI layer, a third gate, a first ILD layer, and a source-drain layer on a side of the first connection trace away from the substrate;

[0072] Figure 14 is a schematic diagram of forming a passivation layer on a side of the source-drain layer away from the substrate;

[0073] Figure 15 is a schematic diagram of forming a target film layer on a side of an interlayer structure layer away from the substrate;

[0074] Figure 16 is a schematic diagram of forming a second connection trace and a fourth connection trace on a side of the target film layer away from the substrate;

[0075] Figure 17 is a schematic diagram of sequentially forming a second planarization layer and a third connection trace on a side of the second connection trace and the fourth connection trace away from the substrate;

[0076] Figure 18 is a schematic diagram of sequentially forming a third planarization layer and a fifth connection trace on a side of the third connection trace away from the substrate.

[0077] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. DETAILED DESCRIPTION

[0078] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0079] The UDC technology refers to a technology of arranging a camera between a display screen and a housing of a display device. In the UDC technology, the driving circuit of the light emitting unit in the camera corresponding area in the display screen is arranged in the non-display area of the display screen, and the light emitting unit in the camera corresponding area is connected with the driving circuit in the non-display area through the transparent connection wire, so as to drive the light emitting unit in the camera corresponding area to emit light through the driving circuit in the non-display area. Wherein, the main display component in the display screen is a display substrate.

[0080] For example, Figure 1 is a front view of a display substrate provided by an embodiment of the present application, which can be a display substrate in a display screen based on the UDC technology. Referring to Figure 1The display substrate includes a display area AA and a non-display area BB, the display area AA includes a first display area AA1 and a second display area AA2 located at least on one side of the first display area AA1, the first display area AA1 can be a corresponding area of a light taking module (for example, a camera, a fingerprint identification device, etc.) of the display device, the second display area AA2 accounts for a large part of the display substrate, and the first display area AA1 accounts for the remaining part, that is, the area of the second display area AA2 can be much larger than the area of the first display area AA1. The non-display area BB includes a first pixel circuit area BB1 located on the side of the first display area AA1 away from the second display area AA2, and a driving circuit of a light emitting unit (also referred to as a light emitting device) in the first display area AA1 is arranged in the first pixel circuit area BB1 and is electrically connected with the light emitting unit in the first display area AA1 through a transparent connecting line. Wherein, the resolution of the second display area AA2 can be greater than the resolution of the first display area AA1, the size of the light emitting unit located in the first display area AA1 is smaller than the size of the light emitting unit located in the second display area AA2, for example, the light emitting unit is an organic light emitting diode (OLED) light emitting unit, the size of the anode of the light emitting unit in the first display area AA1 is smaller than the size of the anode of the light emitting unit in the second display area AA2, in this way, the light transmittance of the first display area AA1 can be greater than the light transmittance of the second display area AA2, so as to facilitate the light taking module arranged below the first display area AA1 to take light through the first display area AA1. Since the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, the resolution of the second display area AA2 is greater than the resolution of the first display area AA1, and the area of the second display area AA2 is much larger than the area of the first display area AA1, therefore, a larger part of a display picture can be displayed in the second display area AA2, so the second display area AA2 can also be referred to as a main display area, and the first display area AA1 can also be referred to as an auxiliary display area. For example, the first display area AA1 is a transparent display area, and the second display area AA2 is a non-transparent display area.

[0081] Currently, in a display screen based on UDC technology, the display substrate includes a substrate, and a polyimide (PI) layer, a barrier layer, a first buffer layer, a polysilicon (p-Si) active layer, a first gate insulator (GI) layer, a first gate, a first inter-layer dielectric (ILD) layer, a second gate, a second ILD layer, a second buffer layer, an oxide active layer, a second GI layer, a third gate, a third ILD layer, a source-drain layer, a passivation (PVX) layer, a first planarization (PLN) layer, a drain connecting line, a second PLN layer, a first indium tin oxide (ITO) connecting line, a third PLN layer, a second ITO connecting line, a fourth PLN layer, a third ITO connecting line, a fifth PLN layer, an anode (AND), a pixel definition layer (PDL), a photo spacer (PS) layer, a light-emitting layer, and a cathode, which are sequentially arranged on the substrate. The source-drain layer includes a first source, a first drain, a second source, and a second drain. The first source is connected to the polysilicon active layer through a first via penetrating the third ILD layer, the second GI layer, the second buffer layer, the second ILD layer, the first ILD layer, and the first GI layer. The first drain is connected to the polysilicon active layer through a second via penetrating the third ILD layer, the second GI layer, the second buffer layer, the second ILD layer, the first ILD layer, and the first GI layer. The second source is connected to the oxide active layer through a third via penetrating the third ILD layer and the second GI layer. The second drain is connected to the oxide active layer through a fourth via penetrating the third ILD layer and the second GI layer. The drain connecting line, the first ITO connecting line, the second ITO connecting line, and the third ITO connecting line are used to electrically connect the first drain and the anode. The polysilicon active layer, the first gate, the first source, and the first drain constitute a polysilicon thin film transistor (TFT). The oxide active layer, the second gate, the second source, and the second drain constitute an oxide TFT. The anode, the light-emitting layer, and the cathode constitute a light-emitting unit. The polysilicon TFT, the oxide TFT, and the drain connecting line in the driving circuit of the light-emitting unit in the camera corresponding area are located in the non-display area. The first ITO connecting line, the second ITO connecting line, and the third ITO connecting line connect the light-emitting unit in the camera corresponding area and the polysilicon TFT in the non-display area.

[0082] The polycrystalline silicon active layer, the first gate, the second gate, the oxide active layer, the third gate, the source-drain layer, the passivation layer, the first PLN layer, the drain connecting line, the second PLN layer, the first ITO connecting line, the third PLN layer, the second ITO connecting line, the fourth PLN layer, the third ITO connecting line, the fifth PLN layer, the anode, the PDL and the PS layer in the display substrate need to be prepared by one patterning process respectively, and the first to fourth vias need to be prepared by one patterning process. Therefore, the manufacturing process of the display substrate needs at least 20 patterning processes, which leads to a complex manufacturing process of the display substrate and high manufacturing cost.

[0083] In view of the above problems existing in the process of manufacturing the display substrate, the embodiments of the present application provide a display substrate, a manufacturing method thereof and a display device. In the display substrate, a sub-pixel includes a light-emitting unit and a driving unit, the driving unit includes a target functional film layer, the display area of the display substrate includes a target display area, the target driving unit of the target light-emitting unit in the target display area is located in the non-display area of the display substrate, and the target light-emitting unit and the target driving unit are electrically connected through a target connecting structure, a part of the target connecting structure located in the target display area is a transparent structure, and the target connecting structure includes a first connecting trace, the first connecting trace is the same layer and the same material as the target functional film layer. Since the first connecting trace is the same layer and the same material as the target functional film layer, the first connecting trace and the target functional film layer can be prepared by one patterning process, which helps to reduce the number of patterning processes required to be performed in the process of manufacturing the display substrate, simplifies the manufacturing process of the display substrate, and reduces the manufacturing cost of the display substrate.

[0084] The target display area can be an under-screen light-taking area in the display substrate, and the under-screen light-taking area refers to an area in the display substrate corresponding to a light-taking module located between a display screen and a housing of a display device. For example, the target display area is an under-screen camera area, and the under-screen camera refers to a camera arranged between the display screen and the housing of the display device. Since the target light-emitting unit and the target driving unit are electrically connected through the target connecting structure, and a part of the target connecting structure located in the target display area is a transparent structure, the under-screen camera area can display, which helps to improve the screen-to-body ratio of the display screen.

[0085] The technical solutions of the embodiments of the present application will be described below with reference to the drawings.

[0086] Figure 2 is a cross-sectional view of a display substrate provided by the embodiments of the present application, for example Figure 2 may be Figure 1 is a cross-sectional view of the C-C part of the display substrate shown. Referring to Figure 2The display substrate includes a substrate 10 and a display structure layer 11 located on the substrate 10. The substrate 10 has a display area 101 and a non-display area 102, and the display area 101 includes a target display area 1011. The display structure layer 11 includes a plurality of sub-pixels ( Figure 2 (Not shown in the image), each sub-pixel includes a light-emitting unit 111 and a driving unit 112. The light-emitting unit 112 is located in the display area 101, and the driving unit 112 includes a target functional film layer 1121.

[0087] In this design, the light-emitting unit 111 located in the target display area 1011 is the target light-emitting unit 111A, and the driving unit of the target light-emitting unit 111A is the target driving unit 112A. The target driving unit 112A is located in the non-display area 102, and the target light-emitting unit 111A and the target driving unit 112A are electrically connected through the target connection structure 113. The portion of the target connection structure 113 located in the target display area 1011 is a transparent structure. The target connection structure 113 includes a first connection trace 1131, which is a transparent trace and is made of the same material as the target functional film layer 1121. That is, the first connection trace 1131 and the target functional film layer 1121 are distributed in the same layer, and the material of the first connection trace 1131 is the same as the material of the target functional film layer 1121. Therefore, the first connection trace 1131 and the target functional film layer 1121 can be fabricated in a single patterning process.

[0088] In summary, in the display substrate provided in the embodiments of the present application, the sub-pixel includes a light emitting unit and a driving unit, the driving unit includes a target functional film layer, the display substrate includes a target display area in a display area of the display substrate, a target driving unit of a target light emitting unit in the target display area is located in a non-display area of the display substrate, and the target light emitting unit and the target driving unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, and the target connection structure includes a first connection trace, which is in the same layer and of the same material as the target functional film layer. Since the first connection trace is in the same layer and of the same material as the target functional film layer, the first connection trace and the target functional film layer can be prepared through one patterning process, which helps to reduce the number of patterning processes required to be performed in the process of manufacturing the display substrate, simplify the manufacturing process of the display substrate, and reduce the manufacturing cost of the display substrate. Since the first connection trace and the target functional film layer can be prepared through one patterning process, compared with the manufacturing process of the display substrate in the related art, the manufacturing process of the display substrate in the present application can reduce one ITO process (i.e., a patterning process of forming an ITO trace), and since the first connection trace and the target functional film layer are located in the same layer, one PLN process (i.e., a patterning process of forming a PLN layer) can also be reduced, that is, compared with the current display substrate, the manufacturing process of the display substrate provided in the embodiments of the present application can reduce two patterning processes.

[0089] The display substrate can be a rigid display substrate or a flexible display substrate. Accordingly, the substrate can be a rigid substrate or a flexible substrate, for example, a glass substrate or a flexible substrate prepared by using PI. The area of the display substrate other than the target display area 1011 is a non-target display area 1012, the non-target display area 1012 is located at least one side of the target display area 1011, the non-target display area 1012 accounts for a large part of the display substrate, and the target display area 1011 accounts for the remaining part, that is, the area of the non-target display area 1012 can be much larger than the area of the target display area 1011. The resolution of the non-target display area 1012 can be greater than the resolution of the target display area 1011, and the size of the light emitting unit located in the target display area 1011 is smaller than the size of the light emitting unit located in the non-target display area 1012. The target display area 1011 can be an under-screen light taking area in the display substrate, for example, an under-screen camera area. Since the target light emitting unit 111A is located in the target display area 1011, the target driving unit 112A is located in the non-display area 102, and the part of the target connection structure located in the target display area 1011 is a transparent structure, the target display area 1011 can display, which helps to improve the screen ratio of the display screen.

[0090] In the embodiment of the present application, the driving unit 112 includes an oxide active layer, and the target functional film layer 1121 can be the oxide active layer. The hydrogen content of the target film layer in the display substrate that is in contact with the first connection trace 1131 is higher than the preset threshold, i.e., the hydrogen content of the target film layer is relatively high. Since the target functional film layer 1121 is the oxide active layer in the driving unit 112, the material of the target functional film layer 1121 is a semiconductor oxide. Since the material of the first connection trace 1131 is the same as that of the target functional film layer 1121, the material of the first connection trace 1131 is also a semiconductor oxide. Since the first connection trace 1131 is in contact with the target film layer whose hydrogen content is higher than the preset threshold, the hydrogen element in the target film layer can diffuse into the first connection trace 1131. The hydrogen element diffused into the first connection trace 1131 can reduce the oxide in the first connection trace 1131, so that the oxide in the first connection trace 1131 is hydrogenated, thereby making the first connection trace 1131 conductive, enhancing the conductivity of the first connection trace 1131, and facilitating the transmission of the driving signal in the target driving unit 112A to the target light emitting unit 111A through the first connection trace 1131 to drive the target light emitting unit 111A to emit light. In an optional embodiment, the material of the first connection trace 1131 and the material of the target functional film layer 1121 are indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO), or other semiconductor oxides, which are not limited in the embodiment of the present application. The preset threshold is any value between 3.6×10 21 ~9.68×10 21 H / cm 3 .

[0091] In an optional embodiment, the material of the target film layer includes at least one of an organic material and silicon nitride. Since the hydrogen content of the organic material and silicon nitride is usually high, the target film layer made of the organic material and silicon nitride can make the first connection trace 1131 conductive. For example, the display substrate usually includes a planarization layer and a passivation layer. The material of the planarization layer is usually an organic material (e.g., epoxy resin, acrylate, etc.) with high hydrogen content, and the material of the passivation layer is usually silicon nitride with high hydrogen content. Therefore, the target film layer in the embodiment of the present application can include at least one of the planarization layer and the passivation layer.

[0092] In an optional embodiment, the display structure layer 11 includes an interlayer structure layer located between the first connection trace 1131 and the target film layer. This interlayer structure layer has contact holes through which the target film layer contacts the first connection trace 1131, thereby conducting the first connection trace 1131 through the target film layer. The ratio of the overlapping area of ​​the contact hole and the first connection trace 1131 to the area of ​​the orthographic projection of the first connection trace 1131 onto the substrate 10 is greater than a preset ratio. This overlapping area is the area of ​​the overlapping region between the orthographic projection of the contact hole onto the substrate 10 and the orthographic projection of the first connection trace 1131 onto the substrate 10, and the preset ratio is any value between 0.33 and 1. This allows for a larger contact area between the target film layer and the first connection trace 1131, facilitating the conduction of the first connection trace 1131 by the target film layer. In one possible implementation, the interlayer structure layer has a contact hole whose orthographic projection on the substrate 10 overlaps with the orthographic projection of the first connection trace 1131 on the substrate 10, thereby allowing a larger contact area between the target film layer and the first connection trace 1131. In another possible implementation, the interlayer structure layer has multiple contact holes uniformly distributed in a first region of the interlayer structure layer, corresponding to the first connection trace 1131. This allows the target film layer to make uniform contact with the first connection trace 1131 through the multiple contact holes, resulting in a larger contact area between the target film layer and the first connection trace 1131.

[0093] Optional, Figures 3 to 7 These are cross-sectional views of five other display substrates provided in the embodiments of this application. In one possible implementation, such as... Figures 2 to 6 As shown, the film layers in the display structure layer 11 that are in contact with the first connection trace 1131 include a first planarization layer 115, a first GI layer 116, and a first buffer layer 117. The target film layer may include the first planarization layer 115. The interlayer structure layer located between the target film layer (i.e., the first planarization layer 115) and the first connection trace 1131 includes: a first GI layer 116, a first ILD layer 118, and a passivation layer 114 sequentially distributed along a direction away from the substrate 10. Figures 2 to 5 As shown, the interlayer structure (i.e., the first GI layer 116, the first ILD layer 118, and the passivation layer 114) has multiple through-holes. Figures 2 to 5 (Not shown in the text), the first planarization layer 115 (i.e., the target film layer) contacts the first connection trace 1131 through these multiple contact holes. For example... Figure 6 As shown, the interlayer structure (i.e., the first GI layer 116, the first ILD layer 118, and the passivation layer 114) has a through-hole. Figures 2 to 5 (Not marked in the text), the diameter of the contact hole is larger than... Figures 2 to 5The first flat layer 115 (i.e. the target film layer) contacts the first connection trace 1131 through a contact hole in the display structure layer 11. In another possible implementation, as shown in FIG. 1B, the film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114. Figure 7 The film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114. Figure 7 The film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114.

[0094] It should be noted that, Figures 2 to 7 The display substrate shown in FIG. 1A is merely an example of the display substrate of the present application, and in some embodiments, for the display substrate shown in FIG. 1B, Figures 2 to 5 The first flat layer 115 (i.e. the target film layer) contacts the first connection trace 1131 through a contact hole in the display structure layer 11. In another possible implementation, as shown in FIG. 1B, the film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114. Figure 6 Figure 7 The first flat layer 115 (i.e. the target film layer) contacts the first connection trace 1131 through a contact hole in the display structure layer 11. In another possible implementation, as shown in FIG. 1B, the film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114. Figures 2 to 6 The first flat layer 115 (i.e. the target film layer) contacts the first connection trace 1131 through a contact hole in the display structure layer 11. In another possible implementation, as shown in FIG. 1B, the film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114. Figure 7 The first flat layer 115 (i.e. the target film layer) contacts the first connection trace 1131 through a contact hole in the display structure layer 11. In another possible implementation, as shown in FIG. 1B, the film layer in the display structure layer 11 that contacts the first connection trace 1131 includes a passivation layer 114, a first GI layer 116, and a first buffer layer 117, and the target film layer can be the passivation layer 114.

[0095] In the embodiments of the present application, the target connection structure can be composed of multiple connection traces that are electrically connected, and in addition to the first connection trace, the target connection structure can further include one or more other connection traces. The target connection structure is introduced in three implementation manners below. Figures 2 to 7

[0096] ​​The first implementation manner is as follows: the target connection structure includes a first connection wire, a second connection wire, and a third connection wire. The second connection wire and the third connection wire are located on the same layer, and the second connection wire and the third connection wire are located on a side of the first connection wire away from the substrate. The second connection wire is located in the non-display area, and the second connection wire is electrically connected to the first connection wire and the target drive unit respectively. The third connection wire is a transparent wire, the third connection wire is located in the target display area, and the third connection wire is electrically connected to the first connection wire and the target light emitting unit respectively. In this way, the target connection structure electrically connects the target light emitting unit and the target drive unit.

[0097] For example, refer to Figure 3 , Figure 6 and Figure 7 , the target connection structure 113 includes a first connection wire 1131, a second connection wire 1132, and a third connection wire 1133. The second connection wire 1132 is located in the non-display area 102, and the second connection wire 1132 is electrically connected to the first connection wire 1131 and the target drive unit 112A respectively. The third connection wire 1133 is a transparent wire, the third connection wire 1133 is located in the target display area 1011, and the third connection wire 1133 is electrically connected to the first connection wire 1131 and the target light emitting unit 111A respectively.

[0098] As shown in Figure 3 , Figure 6 and Figure 7 , the second connection wire 1132 and the third connection wire 1133 are located on a side of the first connection wire 1131 away from the substrate 10. The display structure layer 11 includes a passivation layer 114 and a first planar layer 115 located between the second connection wire 1132 and the target drive unit 112A, and a first connection hole penetrating the passivation layer 114 and the first planar layer 115 is formed in a region corresponding to the target drive unit 112A. The second connection wire 1132 is electrically connected to the target drive unit 112A through the first connection hole. The display structure layer 11 includes a first GI layer 116, a first ILD layer 118, a passivation layer 114, and a first planar layer 115 located between the second connection wire 1132 and the first connection wire 1131. A second connection hole and a third connection hole penetrating the first GI layer 116, the first ILD layer 118, the passivation layer 114, and the first planar layer 115 are formed in a region corresponding to the first connection wire 1131. The second connection wire 1132 is electrically connected to the first connection wire 1131 through the second connection hole, and the third connection wire 1133 is electrically connected to the first connection wire 1131 through the third connection hole.

[0099] The first implementation manner takes the second connection wire and the third connection wire located on the same layer as an example, and the second connection wire and the third connection wire can also be located on different layers. For exampleFigure 2 As shown, the third connection wire 1133 is located on the side of the second connection wire 1132 away from the first connection wire 1131. The display structure layer 11 includes a first GI layer 116, a first ILD layer 118, a passivation layer 114, a first planar layer 115 and a second planar layer 119 between the third connection wire 1133 and the first connection wire 1131, and a third connection hole penetrating through air in the region of the first GI layer 116, the first ILD layer 118, the passivation layer 114, the first planar layer 115 and the second planar layer 119 corresponding to the first connection wire 1131, and the third connection wire 1133 is electrically connected to the first connection wire 1131 through the third connection hole.

[0100] The second implementation manner is as follows: the target connection structure includes a first connection wire, a second connection wire, a third connection wire and a fourth connection wire. The second connection wire and the fourth connection wire are located on the same layer, and the third connection wire is located on the side of the fourth connection wire away from the substrate. The second connection wire is located in a non-display region, and the second connection wire is electrically connected to the first connection wire and a target drive unit respectively. The third connection wire is a transparent wire, and the third connection wire and the fourth connection wire are both located in a target display region. The fourth connection wire is electrically connected to the third connection wire and the first connection wire respectively, and the third connection wire is electrically connected to a target light emitting unit. The target light emitting unit includes an anode, and the fourth connection wire is located in the projection of the anode on the substrate.

[0101] For example, refer to Figure 4The target connection structure includes a first connection trace 1131, a second connection trace 1132, a third connection trace 1133, and a fourth connection trace 1134. The second connection trace 1132 and the fourth connection trace 1134 are located on the same layer, and the third connection trace 1133 is located on the side of the fourth connection trace 1134 away from the substrate 10. The second connection trace 1132 is located in the non-display area 102, and the second connection trace 1132 is electrically connected to the first connection trace 1131 and the target drive unit 112A, respectively. The third connection trace 1133 is a transparent trace, and the third connection trace 1133 and the fourth connection trace 1134 are both located in the target display area 1011. The fourth connection trace 1134 is electrically connected to the third connection trace 1133 and the first connection trace 1131, respectively, and the third connection trace 1133 is electrically connected to the target light emitting unit 111A. The target light emitting unit 111A includes an anode 1111, and the fourth connection trace 1134 has a projection on the substrate 10 located within the projection of the anode 1111 on the substrate 10. The fourth connection trace 1134 can be a non-transparent structure. The fourth connection trace 1134 is arranged below the non-transparent anode 1111, and the projection of the fourth connection trace 1134 on the substrate 10 is located within the projection of the anode 1111 on the substrate 10. This can avoid the influence of the non-transparent fourth connection trace 1134 on the light transmission performance of the display area 101.

[0102] As Figure 4As shown, the second connection trace 1132 and the fourth connection trace 1134 are located on the side of the first connection trace 1131 away from the substrate 10, and the third connection trace 1133 is located on the side of the fourth connection trace 1134 away from the substrate 10. The display structure layer 11 includes a passivation layer 114 and a first planar layer 115 between the second connection trace 1132 and the target drive unit 112A, the first planar layer 115 and the passivation layer 114 have a first connection hole passing through the corresponding region of the target drive unit 112A, and the second connection trace 1132 is electrically connected to the target drive unit 112A through the first connection hole. The display structure layer 11 includes a first GI layer 116, a first ILD layer 118, a passivation layer 114 and a first planar layer 115 between the second connection trace 1132 and the first connection line 1131, the first GI layer 116, the first ILD layer 118, the passivation layer 114 and the first planar layer 115 have a second connection hole and a third connection hole passing through the corresponding region of the first connection line 1131, the second connection trace 1132 is electrically connected to the first connection line 1131 through the second connection hole, and the fourth connection trace 1134 is electrically connected to the first connection line 1131 through the third connection hole. The display structure layer 11 further includes a second planar layer 119 between the third connection trace 1133 and the fourth connection line 1134. The second planar layer 119 has a fourth connection hole passing through the corresponding region of the fourth connection line 1134, and the third connection trace 1133 is electrically connected to the fourth connection line 1134 through the fourth connection hole.

[0103] In optional embodiments, for the first and second implementation manners described above, the target connection structure can further include a fifth connection trace, the fifth connection trace is a transparent trace, the fifth connection trace is located in the target display area, the fifth connection trace is located on the side of the third connection trace away from the substrate, and the third connection trace can be electrically connected to the target light emitting unit through the fifth connection trace. Please refer to Figures 2 to 4 、 Figure 6 and Figure 7 The target connection structure 113 further includes a fifth connection trace 1135, the fifth connection trace 1135 is located in the target display area 1011, the fifth connection trace 1135 is located on the side of the third connection trace 1133 away from the substrate 10, and the third connection trace 1133 is electrically connected to the target light emitting unit 111A through the fifth connection trace 1135. In an optional implementation manner, as Figure 3 、 Figure 6 and Figure 7As shown, the display structure layer 11 includes a second planar layer 119 between the fifth connection trace 1135 and the third connection trace 1133. The second planar layer 119 has a fifth connection hole in a region corresponding to the third connection trace 1133, the fifth connection trace 1135 is electrically connected to the third connection trace 1133 through the fifth connection hole, and the fifth connection trace 1135 is electrically connected to the target light emitting unit 111A, so that the third connection trace 1133 is electrically connected to the target light emitting unit 111A through the fifth connection trace 1135. In another optional implementation, as shown in Figure 2 and Figure 4 As shown, the display structure layer 11 includes a third planar layer 120 between the fifth connection trace 1135 and the third connection trace 1133. The third planar layer 120 has a fifth connection hole in a region corresponding to the third connection trace 1133, the fifth connection trace 1135 is electrically connected to the third connection trace 1133 through the fifth connection hole, and the fifth connection trace 1135 is electrically connected to the target light emitting unit 111A, so that the third connection trace 1133 is electrically connected to the target light emitting unit 111A through the fifth connection trace 1135.

[0104] The third implementation: the target connection structure includes a first connection trace and a second connection trace. The second connection trace is located in a non-display region, and the second connection trace is electrically connected to the first connection trace and the target drive unit respectively. The first connection trace is electrically connected to the target light emitting unit.

[0105] For example, please refer to Figure 5 The target connection structure 113 includes a first connection trace 1131 and a second connection trace 1132. The second connection trace 1132 is located in a non-display region 102, and the second connection trace 1132 is electrically connected to the first connection trace 1131 and the target drive unit 112A respectively, and the first connection trace 1131 is electrically connected to the target light emitting unit 111A. As shown in Figure 5 The display structure layer 11 includes a passivation layer 114 and a first planar layer 115 between the second connection trace 1132 and the target drive unit 112A, and the passivation layer 114 and the first planar layer 115 have a first connection hole corresponding to the target drive unit 112A. The second connection trace 1132 is electrically connected to the target drive unit 112A through the first connection hole. The display structure layer 11 includes a first GI layer 116, a first ILD layer 118, a passivation layer 114 and a first planar layer 115 between the second connection trace 1132 and the first connection trace 1131. The first GI layer 116, the first ILD layer 118, the passivation layer 114 and the first planar layer 115 have a second connection hole corresponding to the first connection trace 1131. The second connection trace 1132 is electrically connected to the first connection trace 1131 through the second connection hole.

[0106] Optionally, in the above three implementation manners, the first connection trace 1131, the third connection trace 1133 and the fifth connection trace 1135 can all be traces made of transparent materials such as ITO. The second connection trace 1132 and the fourth connection trace 1134 can both be non-transparent traces, for example, the second connection trace 1132 and the fourth connection trace 1134 can both be metal traces made of metal materials such as aluminum. In addition, Figures 2 to 7 For example, the connection holes in different film layers can be adjusted as needed in actual applications, and the embodiments of the present application do not limit this.

[0107] In the embodiments of the present application, please continue to refer to Figures 2 to 7 The light-emitting unit 111 includes, in order away from the substrate 10, an anode 1111, a light-emitting layer 1112 and a cathode 1113. In the above first and second implementation manners, the fifth connection trace 1135 is electrically connected to the anode 1111 of the target light-emitting unit 111A. For example Figures 2 to 4 、 Figure 6 and Figure 7 The display structure layer 11 includes a fourth planar layer 121 between the anode 1111 and the fifth connection trace 1135, and the fourth planar layer 121 has an anode connection hole (not marked in Figures 2 to 4 、 Figure 6 and Figure 7 ) in the region corresponding to the fifth connection trace 1135, and the anode 1111 is electrically connected to the fifth connection trace 1135 through the anode connection hole. In the above third implementation manner, the first connection trace 1131 is electrically connected to the anode 1111 of the target light-emitting unit 111A. For example Figure 5 The display structure layer 11 includes a second planar layer 119, a first planar layer 115, a passivation layer 114, a first ILD layer 118 and a first GI layer 116 between the anode 1111 and the first connection trace 1131, and the second planar layer 119, the first planar layer 115, the passivation layer 114, the first ILD layer 118 and the first GI layer 116 have an anode connection hole passing through the gas in the region corresponding to the first connection trace 1131, and the anode 1111 is electrically connected to the first connection trace 1131 through the anode connection hole.

[0108] The display substrate of the embodiment of the present application can be a low temperature polycrystalline oxide (LTPO) display substrate, which can keep the pixel open for a long time, reduce the refresh rate of the display substrate, and thus reduce the energy consumption of the display substrate. The driving unit 112 in the LTPO display substrate can be an LTPO TFT, which is composed of an oxide TFT and a polysilicon TFT. The oxide TFT and the polysilicon TFT can be a top-gate TFT, a bottom-gate TFT or a top-bottom-gate TFT, respectively, and the types of the oxide TFT and the polysilicon TFT can be different, for example, one of the oxide TFT and the polysilicon TFT is a top-gate TFT, and the other is a top-bottom-gate TFT, which is not limited in the embodiment of the present application.

[0109] For example, the embodiment of the present application takes the oxide TFT in the driving unit 112 as a top-bottom-gate TFT and the polysilicon TFT as a top-gate TFT as an example for illustration. As shown in FIG. 1B, the driving unit 112 includes, in sequence along the direction away from the substrate 10, a polysilicon active layer 1122, a first gate 1123, a second gate 1124, an oxide active layer (i.e., a target functional film layer 1121), a third gate 1125 and a source-drain layer including a first source 1126, a first drain 1127, a second source 1128 and a second drain 1129. Figures 2 to 7 The polysilicon active layer 1122, the first gate 1123, the first source 1126 and the first drain 1127 constitute a polysilicon TFT, the second gate 1124, the oxide active layer (i.e., the target functional film layer 1121), the third gate 1125, the second source 1128 and the second drain 1129 constitute an oxide TFT, and the first source 1126 is electrically connected to the second drain 1129 (for example, the first source 1126 and the second drain 1129 are in an integrated structure), so that the polysilicon TFT is electrically connected to the oxide TFT. The second connection trace 1132 is electrically connected to the first drain 1127 in the target driving unit 112A through the first connection hole, so that the second connection trace 1132 is electrically connected to the target driving unit 112A.

[0110] As shown in FIG. 1B, the driving unit 112 includes, in sequence along the direction away from the substrate 10, a polysilicon active layer 1122, a first gate 1123, a second gate 1124, an oxide active layer (i.e., a target functional film layer 1121), a third gate 1125 and a source-drain layer including a first source 1126, a first drain 1127, a second source 1128 and a second drain 1129. Figures 2 to 7As shown, the display structure layer 11 includes: a second GI layer 122, a second ILD layer 123, a third ILD layer 124, a first buffer layer 117, a first GI layer 116, and a first ILD layer 118 distributed along a direction away from the substrate 10 between the polysilicon active layer 1122 and the source / drain layers. The second GI layer 122, the second ILD layer 123, the third ILD layer 124, the first buffer layer 117, the first GI layer 116, and the first ILD layer 118 have a first via and a second via that are connected through the substrate 10. The first source 1126 is electrically connected to the polysilicon active layer 1122 through the first via, and the first drain 1127 is electrically connected to the polysilicon active layer 1122 through the second via. A first GI layer 116 and a first ILD layer 118 are distributed along a direction away from the substrate 10 between the oxide active layer (i.e., the target functional film layer 1121) and the source / drain layers. The first GI layer 116 and the first ILD layer 118 have a third via and a fourth via that are connected in one gas. The second source 1128 is electrically connected to the oxide active layer (i.e., the target functional film layer 1121) through the third via, and the second drain 1129 is electrically connected to the oxide active layer (i.e., the target functional film layer 1121) through the fourth via. The second source 1128 is used to connect to a data line (…). Figures 2 to 7 (Not shown in the image) Electrical connection to receive data signals transmitted via the data line.

[0111] like Figures 2 to 7 As shown, the display structure layer 11 also includes a pixel definition layer 125 and a spacer layer 126. The pixel definition layer 125 is located on the side of the anode 1111 away from the substrate 10, and the pixel definition layer 125 defines a plurality of sub-pixel regions. Figures 2 to 7 (Not shown in the image), the anode 1111, the light-emitting layer 1112, and the cathode 1113 are partially superimposed in the sub-pixel region to form the light-emitting unit 111. The spacer layer 126 is located on the side of the pixel definition layer 125 away from the substrate 10, and the spacer layer 126 is used to control the thickness of the light-emitting layer 1112.

[0112] like Figures 2 to 7 As shown, the display substrate further includes a barrier layer 13 and a second buffer layer 14 located between the substrate 10 and the display structure layer 11. The second buffer layer 14 is located on the side of the barrier layer 13 away from the substrate 10. Figures 2 to 7 Taking the example of having a barrier layer and a buffer layer between the substrate 10 and the display structure layer 11, in other embodiments, there may be multiple barrier layers and multiple buffer layers between the substrate 10 and the display structure layer 11, which can be set according to actual needs.

[0113] Those skilled in the art should understand that Figures 2 to 7 This is merely an example of a display substrate provided in the embodiments of this application, and does not constitute a limitation on the structure of the display substrate. The actual display substrate may include more than [specific examples].Figures 2 to 7 More or less structures, for example, the display substrate can further include an encapsulation layer located on the side of the display structure layer away from the substrate, which encapsulates the light emitting unit in the display structure layer to avoid external water and oxygen from entering the inside of the display substrate to erode the light emitting unit. For another example, the display structure layer can further include a light shielding layer located between the oxide active layer and the substrate to shield the oxide active layer, so as to avoid the light from the substrate from entering the inside of the display substrate to affect the switching characteristics of the oxide TFT. That is, the setting of the light shielding layer can ensure the switching characteristics of the oxide TFT. In actual applications, the structure of the display substrate can be adjusted as needed, which is not limited in the embodiments of the present application.

[0114] According to the description of the foregoing embodiments, in the display substrate shown in Figure 5 Figures 2 to 4 In the display substrate shown in Figure 6 Figure 7 In the display substrate shown in Figure 2 Figure 3 Figure 6 Figure 7 In the display substrate shown in Figure 4 Figure 5 In the display substrate shown in Figure 2 Figure 3 Figure 6 Figure 7 In the display substrate shown in Figure 2 Figure 3 Figure 6 Figure 7 In the display substrate shown in Figure 2 Figure 3 Figure 6 Figure 7 In the display substrate shown in Figure 2 ​​​​​​​​​​​​​​​The display substrate shown in Figure 3 , Figure 6 and Figure 7 In the display substrate shown in Figure 2 , Figure 3 , Figure 6 and Figure 7 the manufacturing process of the display substrate is simpler and the manufacturing cost is lower.

[0115] The above embodiments mainly introduce the connection mode of the target light emitting unit 111A in the target display area 1011 and the target driving unit 112A in the non-display area 102. For the non-target display area 1012 in the display area 101, the light emitting unit 111 and the driving unit 112 of the sub-pixel in the non-target display area 1012 are both located in the non-target display area 1012, and the driving unit 112 in each sub-pixel in the non-target display area 1012 can be electrically connected to the light emitting unit 111 in the sub-pixel through a cross-layer connection structure. The cross-layer connection structure includes a connection wire located in at least one layer, and all or part of the connection wires in the cross-layer connection structure are distributed in the same layer as all or part of the connection wires in the target connection structure. The connection wires in the same layer and of the same material in the cross-layer connection structure and the target connection structure can be prepared through the same patterning process. For the sake of brevity, the connection mode of the driving unit 112 and the light emitting unit 111 in the non-target display area 1012 will not be described here.

[0116] Each sub-pixel in the display substrate can have a pixel circuit for driving the light emitting unit in the sub-pixel to emit light. The driving unit can be located in the driving circuit. For example, please refer to Figure 8 , which shows a pixel circuit diagram provided by an embodiment of the present application. As Figure 8As shown, the sub-pixel includes a light emitting unit 111 and a driving circuit 114 for driving the light emitting unit 111 to emit light, the driving circuit 113 includes a driving sub-circuit 1141, a data writing sub-circuit 1142, a threshold compensation sub-circuit 1143, a reset sub-circuit, a light emitting control sub-circuit and a storage capacitor Cst, the reset sub-circuit includes a first reset sub-circuit 1144 and a second reset sub-circuit 1145, the light emitting control sub-circuit includes a first light emitting control sub-circuit 1146 and a second light emitting control sub-circuit 1147. Among them, the first reset sub-circuit 1144 includes a first reset transistor BT1, the threshold compensation sub-circuit 1143 includes a threshold compensation transistor BT2, the driving sub-circuit 1141 includes a driving transistor BT3, the data writing sub-circuit 1142 includes a data writing transistor BT4, the first light emitting control sub-circuit 1146 includes a first light emitting control transistor BT5, the second light emitting control sub-circuit 1147 includes a second light emitting control transistor BT6, and the second reset sub-circuit 1145 includes a second reset transistor BT7. Optionally, the first reset transistor BT1 and the threshold compensation transistor BT2 are both oxide TFTs, and the data writing transistor BT4, the first light emitting control transistor BT5, the second light emitting control transistor BT6 and the second reset transistor BT7 are all polycrystalline silicon TFTs. Figures 2 to 7 The driving unit 112 in the sub-pixel 110 includes two TFTs in the driving unit 112 in the sub-pixel 110 in the prior art, and one of the two TFTs is an oxide TFT and the other TFT is a polycrystalline silicon TFT. Figure 8 The oxide TFT in the driving unit 112 in the sub-pixel 110 in the prior art can be the BT2 in the driving unit 112 in the sub-pixel 110 in the prior art. Figures 2 to 7 The polycrystalline silicon TFT in the driving unit 112 in the sub-pixel 110 in the prior art can be the BT6 in the driving unit 112 in the sub-pixel 110 in the prior art. Figure 8 The oxide TFT in the driving unit 112 in the sub-pixel 110 in the prior art can be the BT2 in the driving unit 112 in the sub-pixel 110 in the prior art. Figures 2 to 7 The polycrystalline silicon TFT in the driving unit 112 in the sub-pixel 110 in the prior art can be the BT6 in the driving unit 112 in the sub-pixel 110 in the prior art. Figure 8 The oxide TFT in the driving unit 112 in the sub-pixel 110 in the prior art can be the BT2 in the driving unit 112 in the sub-pixel 110 in the prior art.

[0117] The driving sub-circuit 1141 includes a control terminal, a first terminal and a second terminal, and is configured to control the driving current flowing through the light emitting unit 111. The control terminal of the driving sub-circuit 1141 is connected with the first node S1, the first terminal is connected with the second node S2, and the second terminal is connected with the third node S3. The data writing sub-circuit 1142 is connected with the first terminal of the driving sub-circuit 1141, the data line Vdata and the first gate scanning signal line GP, and is configured to write the data signal provided by the data line Vdata into the first terminal of the driving sub-circuit 1141 in response to the data writing control signal provided by the first gate scanning signal line GP. The threshold compensation sub-circuit 1143 is connected with the control terminal and the second terminal of the driving sub-circuit 1141, the first voltage line VDD and the second gate scanning signal line GN, and is configured to compensate the driving sub-circuit 1141 with the data signal written by the first voltage line VDD in response to the threshold compensation control signal provided by the second gate scanning signal line GN. The first reset sub-circuit 1144 is connected with the control terminal of the driving sub-circuit 1141, the initial signal line Vinit1 and the third gate scanning signal line RT, and is configured to apply the initial voltage provided by the initial signal line Vinit1 to the second terminal of the driving sub-circuit 1141 in response to the first reset control signal provided by the third gate scanning signal line RT. The second reset sub-circuit 1145 is connected with the initial signal line Vinit2 and the first gate scanning signal line GP and one end of the light emitting unit 111, and is configured to apply the initial voltage provided by the initial signal line Vinit2 to one end of the light emitting unit 111 through the fourth node S4 in response to the second reset control signal provided by the first gate scanning signal line GP. The other end of the light emitting unit 111 is connected with the second voltage line VSS. The first light emitting control sub-circuit 1146 is connected with the first voltage line VDD, the first terminal of the driving sub-circuit 1141 and the fourth gate scanning signal line E, and is configured to apply the first voltage provided by the first voltage line VDD to the first terminal of the driving sub-circuit 1141 in response to the light emitting control signal provided by the fourth gate scanning signal line E. The second light emitting control sub-circuit 1147 is connected with the second terminal of the driving sub-circuit 1141, one end of the light emitting unit 111 and the fourth gate scanning signal line E, and is configured to make the driving current be applied to one end of the light emitting unit 111 in response to the light emitting control signal provided by the fourth gate scanning signal line E.

[0118] Figure 8 The pixel circuit in the embodiments of the present application is only an example and does not limit the pixel circuit. In actual application, the pixel circuit can also have other structures, which are not limited in the present application.

[0119] In summary, in the display substrate provided by the embodiments of the present application, a sub-pixel includes a light-emitting unit and a driving unit, the driving unit includes a target functional film layer, the display substrate includes a target display area in a display area, a target driving unit of a target light-emitting unit in the target display area is located in a non-display area of the display substrate, and the target light-emitting unit and the target driving unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, and the target connection structure includes a first connection trace, which is of the same layer and material as the target functional film layer. Since the first connection trace is of the same layer and material as the target functional film layer, the first connection trace and the target functional film layer can be prepared through one patterning process, which helps to reduce the number of patterning processes required to be performed in the process of manufacturing the display substrate, simplify the manufacturing process of the display substrate, and reduce the manufacturing cost of the display substrate.

[0120] Reference is made to Figure 9 which shows a flowchart of a manufacturing method of a display substrate provided by the embodiments of the present application. The manufacturing method of the display substrate can be used to manufacture the display substrate as shown in any of Figures 2 to 7 Reference is made to Figure 9 The method can include the following steps:

[0121] In step 901, a substrate substrate is provided, which has a display area and a non-display area, and the display area includes a target display area.

[0122] The target display area can be an under-screen camera area in the display substrate.

[0123] In step 902, a display structure layer is formed on the substrate substrate, and the display structure layer includes a plurality of sub-pixels, each sub-pixel includes a light-emitting unit and a driving unit, the light-emitting unit is located in the display area, and the driving unit includes a target functional film layer. The light-emitting unit located in the target display area is a target light-emitting unit, the target driving unit of the target light-emitting unit is located in the non-display area, the target light-emitting unit and the target driving unit are electrically connected through a target connection structure, a part of the target connection structure located in the target display area is a transparent structure, the target connection structure includes a first connection trace, the first connection trace is a transparent trace, and the first connection trace is of the same layer and material as the target functional film layer.

[0124] The first connection trace and the target functional film layer are of the same layer and material, that is, the first connection trace and the target functional film layer are distributed in the same layer, and the material of the first connection trace is the same as that of the target functional film layer. The first connection trace and the target functional film layer can be prepared through one patterning process.

[0125] In summary, the manufacturing method of the display substrate provided by the embodiments of the present application has the following advantages. In the display substrate manufactured by the method, a sub-pixel includes a light-emitting unit and a driving unit, the driving unit includes a target functional film layer, the display substrate includes a target display area in a display area, a target driving unit of a target light-emitting unit in the target display area is located in a non-display area of the display substrate, and the target light-emitting unit and the target driving unit are electrically connected through a target connection structure. A part of the target connection structure located in the target display area is a transparent structure, and the target connection structure includes a first connection trace which is in the same layer and of the same material as the target functional film layer. Since the first connection trace is in the same layer and of the same material as the target functional film layer, the first connection trace and the target functional film layer can be prepared by one patterning process, which helps to reduce the number of patterning processes required to be performed in the process of manufacturing the display substrate, simplify the manufacturing process of the display substrate, and reduce the manufacturing cost of the display substrate.

[0126] Please refer to Figure 10 which shows a flowchart of another manufacturing method of a display substrate provided by the embodiments of the present application. Figure 10 The manufacturing process of the display substrate shown in Figure 4 will be described by way of example. Figure 2 、 Figures 5 to 7 and Figure 10 The manufacturing process of the display substrate shown in Figures 2 to 7 may refer to the embodiments. The method includes the following steps:

[0127] In step 1001, a substrate is provided, which has a display area and a non-display area, and the display area includes a target display area.

[0128] For example, as shown in Figure 11 , the substrate 10 has a display area 101 and a non-display area 102, the non-display area 102 is distributed around the display area 101, the display area 101 includes a target display area 1011, and the target display area 1011 is close to the non-display area 102. The target display area 1011 can be an under-screen camera area. The substrate 10 can be a rigid substrate, for example, the substrate 10 is a glass substrate, or the substrate 10 can be a flexible substrate made of a flexible material such as PI.

[0129] In step 1002, a barrier layer, a second buffer layer, a polysilicon active layer, a second GI layer, a first gate, a second ILD layer, a second gate, a third ILD layer, and a first buffer layer are sequentially formed on the substrate.

[0130] Please refer to Figure 12Fig. 10 shows a schematic diagram of the embodiment provided by the present application, which shows a schematic diagram after forming the barrier layer 13, the second buffer layer 14, the polysilicon active layer 1122, the second GI layer 122, the first gate 1123, the second ILD layer 123, the second gate 1124, the third ILD layer 124 and the first buffer layer 117 on the substrate 10 in sequence.

[0131] The material of the barrier layer 13 can be an organic material. The materials of the second buffer layer 14, the second GI layer 122, the second ILD layer 123, the third ILD layer 124 and the first buffer layer 117 can be inorganic materials such as SiOx (silicon oxide), SiNx (silicon nitride) or SiOxNy (silicon oxynitride). The material of the polysilicon active layer 1122 can be p-Si. The material of the first gate 1123 can be a metal material. The material of the second gate 1124 can be a light-shielding material, for example, the material of the second gate 1124 is a metal material.

[0132] For example, first, deposit an organic material on the display substrate 10 to obtain the barrier layer 13. Then, deposit a layer of SiOx on the side of the barrier layer 13 away from the substrate 10 to obtain the second buffer layer 14. Next, form a polysilicon material layer on the side of the second buffer layer 14 away from the substrate 10, and process the polysilicon material layer by a one-time patterning process to obtain the polysilicon active layer 1122. Then, deposit a layer of SiNx on the side of the polysilicon active layer 1122 away from the substrate 10 to obtain the second GI layer 122. Then, form a metal material layer on the side of the second GI layer 122 away from the substrate 10, and process the metal material layer by a one-time patterning process to obtain the first gate 1123. Then, deposit a layer of SiOxNy on the side of the first gate 1123 away from the substrate 10 to obtain the second ILD layer 123. Then, form a metal material layer on the side of the second ILD layer 123 away from the substrate 10, and process the metal material layer by a one-time patterning process to obtain the second gate 1124. Then, deposit a layer of SiNx on the side of the second gate 1124 away from the substrate 10 to obtain the third ILD layer 124. Finally, deposit a layer of SiOx material on the side of the third ILD layer 124 away from the substrate 10 to obtain the first buffer layer 117.

[0133] In step 1003, form a target functional film layer and a first connection trace on the side of the first buffer layer away from the substrate.

[0134] Please refer to Figure 13Fig. 12 shows a schematic diagram of the embodiment provided by the present application, which shows a schematic diagram after forming the target functional film layer 1121 and the first connection wire 1131 on the side of the first buffer layer 117 away from the substrate base plate 10. First, a functional material layer can be formed on the side of the first buffer layer 117 away from the substrate base plate 10, and then the functional material layer is processed to obtain the target functional film layer 1121 and the first connection wire 1131. The target functional film layer 1121 can be an oxide active layer, and the material of the target functional film layer 1121 can be a semiconductor oxide such as IGZO or ITZO. The orthographic projection of the target functional film layer 1121 on the substrate base plate 10 is located within the orthographic projection of the second gate 1124 on the substrate base plate 10.

[0135] In step 1004, a first GI layer, a third gate, a first ILD layer and a source-drain layer are sequentially formed on the side of the first connection wire away from the substrate base plate.

[0136] Please refer to Figure 14 Fig. 12 shows a schematic diagram of the embodiment provided by the present application, which shows a schematic diagram after forming the first GI layer 116, the third gate 1125, the first ILD layer 118 and the source-drain layer on the side of the first connection wire 1131 away from the substrate base plate 10. The source-drain layer includes a first source 1126, a first drain 1127, a second source 1128 and a second drain 1129. The first source 1126 is electrically connected to the polycrystalline silicon active layer 1122 through a first via in the second GI layer 122, the second ILD layer 123, the third ILD layer 124, the first buffer layer 117, the first GI layer 116 and the first ILD layer 118. The first drain 1127 is electrically connected to the polycrystalline silicon active layer 1122 through a second via in the second GI layer 122, the second ILD layer 123, the third ILD layer 124, the first buffer layer 117, the first GI layer 116 and the first ILD layer 118. The second source 1128 is electrically connected to the oxide active layer (i.e. the target functional film layer 1121) through a third via in the first GI layer 116 and the first ILD layer 118. The second drain 1129 is electrically connected to the oxide active layer (i.e. the target functional film layer 1121) through a fourth via in the first GI layer 116 and the first ILD layer 118. The polycrystalline silicon active layer 1122, the first gate 1123, the first source 1126 and the first drain 1127 constitute a polycrystalline silicon TFT, the second gate 1124, the oxide active layer (i.e. the target functional film layer 1121), the third gate 1125, the second source 1128 and the second drain 1129 constitute an oxide TFT, and the first source 1126 is electrically connected to the second drain 1129, so that the polycrystalline silicon TFT and the oxide TFT are electrically connected to constitute an LTPO TFT (i.e. a driving unit 112).

[0137] For example, firstly, a SiOxNy layer is deposited on the side of the first connection trace 1131 away from the substrate 10 to obtain a first GI layer 116. Then, a metal layer is formed on the side of the first GI layer 116 away from the substrate 10, and the metal layer is processed through a single patterning process to obtain a third gate 1125. Next, a SiNx layer is deposited on the side of the third gate 1125 away from the substrate 10 to obtain a first ILD layer 118. Then, through a single patterning process, a first via and a second via are formed in the second GI layer 122, the second ILD layer 123, the third ILD layer 124, the first buffer layer 117, the first GI layer 116, and the first ILD layer 118, and a third via and a fourth via are formed in the first GI layer 116 and the first ILD layer 118. Finally, a metal layer is formed on the side of the first ILD layer 118 away from the substrate 10, and the metal layer is processed through a single patterning process to obtain a source / drain layer.

[0138] In step 1005, a passivation layer is formed on the side of the source / drain layer away from the substrate. The first GI layer, the first ILD layer, and the passivation layer are stacked to form an interlayer structure layer, which has contact holes.

[0139] Please refer to Figure 15 This illustration shows a schematic diagram of a passivation layer 114 formed on the side of the source / drain layer away from the substrate 10, according to an embodiment of this application. A first GI layer 116, a first ILD layer 118, and the passivation layer 114 are stacked to form an interlayer structure layer. This interlayer structure layer has a plurality of through-holes K, which are uniformly distributed in a first region of the interlayer structure layer, corresponding to the first connection trace 1131.

[0140] For example, firstly, a SiNx layer is deposited on the side of the source / drain layer away from the substrate 10 to obtain a passivation layer 114. Then, a plurality of through-holes K are formed in the first GI layer 116, the first ILD layer 118, and the passivation layer (i.e., the interlayer structure layer) through a single patterning process.

[0141] In step 1006, a target film layer is formed on the side of the interlayer structure layer away from the substrate, and the target film layer contacts the first connection trace through a contact hole.

[0142] Please refer to Figure 15 The illustration shows a schematic diagram of a target film layer formed on the side of the interlayer structure layer away from the substrate 10, according to an embodiment of this application. Figure 15 Taking the first planarization layer 115 as an example, the first planarization layer 115 contacts the first connection trace 1131 through multiple contact holes K in the interlayer structure layer to make the first connection trace 1131 conductive. For example...Figure 16 As shown, a first connecting hole G penetrating through air is formed in the first planar layer 115 and the passivation layer 114, a second connecting hole N penetrating through air is formed in the first planar layer 115, the passivation layer 114, the first ILD layer 118 and the first GI layer 116, and a third connecting hole H is formed in the first planar layer 115, which is sleeved in the contact hole K in the interlayer structure layer.

[0143] For example, first, an epoxy material layer is formed as the first planar layer 115 on the side of the passivation layer 114 away from the substrate 10. Then, a first connecting hole G penetrating through air is formed in the first planar layer 115 and the passivation layer 114 by a one-time patterning process, a second connecting hole N penetrating through air is formed in the first planar layer 115, the passivation layer 114, the first ILD layer 118 and the first GI layer 116, and a third connecting hole H is formed in the first planar layer 115.

[0144] In step 1007a, a second connecting trace and a fourth connecting trace are formed on the side of the target film layer away from the substrate 10, the second connecting trace and the fourth connecting trace are located in the same layer, the second connecting trace is located in the non-display area, the fourth connecting trace is located in the target display area, the second connecting trace is electrically connected to the first drain through the first connecting hole, the second connecting trace is electrically connected to the first connecting trace through the second connecting hole, and the fourth connecting trace is electrically connected to the first connecting trace through the third connecting hole.

[0145] Please refer to Figure 16 which shows a schematic diagram after the second connecting trace 1132 and the fourth connecting trace 1134 are formed on the side of the target film layer (i.e. the first planar layer 115) away from the substrate 10. The second connecting trace 1132 and the fourth connecting trace 1134 are located in the same layer, the second connecting trace 1132 is located in the non-display area 102, and the fourth connecting trace 1134 is located in the target display area 1011. The second connecting trace 1132 is electrically connected to the first drain 1127 of the target drive unit 112A through the first connecting hole G, and the second connecting trace 1132 is electrically connected to the first connecting trace 1131 through the second connecting hole N, and the fourth connecting trace 1134 is electrically connected to the first connecting trace 1131 through the third connecting hole H. As shown in Figure 17 In the process of forming the second connecting trace 1132 and the fourth connecting trace 1134, a connecting trace for connecting the drive unit 112 and the light emitting unit 111 in the non-target display area 1012 in the display area 101 is also formed.

[0146] For example, a metal material layer is formed on the side of the target film layer (i.e., the first flat layer 115) away from the substrate 10, and the metal material layer is processed by a one-time patterning process to obtain the second connection trace 1132 and the fourth connection trace 1134.

[0147] In step 1008a, a second flat layer and a third connection trace are sequentially formed on the side of the second connection trace and the fourth connection trace away from the substrate 10, the third connection trace being a transparent trace, and the third connection trace being located in the target display area.

[0148] Please refer to Figure 18 which shows a schematic diagram after the second flat layer 119 and the third connection trace 1133 are sequentially formed on the side of the second connection trace 1132 and the fourth connection trace 1134 away from the substrate 10 according to an embodiment of the present application. The third connection trace 1133 is located in the target display area 1011. The second flat layer 119 has a fourth connection hole in the region corresponding to the fourth connection line 1134, and the third connection trace 1133 is electrically connected to the fourth connection line 1134 through the fourth connection hole.

[0149] For example, first, an acrylic material layer is formed on the side of the second connection trace 1132 and the fourth connection trace 1134 away from the substrate 10, and the acrylic material layer is processed by a one-time patterning process to obtain the second flat layer 119. Then, an ITO material layer is formed on the side of the second flat layer 119 away from the substrate 10, and the ITO material layer is processed by a one-time patterning process to obtain the third connection trace 1133.

[0150] In step 1009a, a third flat layer and a fifth connection trace are sequentially formed on the side of the third connection trace away from the substrate 10, the fifth connection trace being a transparent trace, and the fifth connection trace being located in the target display area.

[0151] Please refer to Figure 4 which shows a schematic diagram after the third flat layer 120 and the fifth connection trace 1135 are sequentially formed on the side of the third connection trace 1133 away from the substrate 10 according to an embodiment of the present application. The fifth connection trace 1135 is a transparent trace, and the fifth connection trace 1135 is located in the target display area 1011. The third flat layer 120 has a fifth connection hole in the region corresponding to the fourth connection line 1134, and the fifth connection trace 1135 is electrically connected to the third connection trace 1133 through the fifth connection hole. The first connection trace 1131, the second connection trace 132, the third connection trace 1133, the fourth connection trace 1134, and the fifth connection trace 1135 constitute a target connection structure 113.

[0152] For example, first, an epoxy material layer is formed on the side of the fifth connection trace 1135 away from the substrate 10, and the epoxy material layer is processed by a one-time patterning process to obtain the fourth planar layer 121. Then, an ITO material layer is formed on the side of the fourth planar layer 121 away from the substrate 10, and the ITO material layer is processed by a one-time patterning process to obtain the fifth connection trace 1135.

[0153] In step 1010a, a fourth planar layer and a light emitting unit are sequentially formed on the side of the fifth connection trace away from the substrate.

[0154] A schematic view after the fourth planar layer 121 and the light emitting unit 111 are sequentially formed on the side of the fifth connection trace 1135 away from the substrate 10 can be referred to Figure 10 . The light emitting unit 111 includes an anode 1111, a light emitting layer 1112, and a cathode 1113 sequentially formed in the direction away from the substrate 10. The anode 1111 covers the fourth connection trace 1134 on the substrate 10 in orthographic projection. The anode 1111 is electrically connected to the fifth connection trace 1135 through an anode connection hole penetrating the fourth planar layer 121.

[0155] Optionally, the fourth planar layer 121, the anode 1111, a pixel definition layer 125, a spacer layer 126, the light emitting layer 1112, and the cathode 1113 are sequentially formed on the side of the fifth connection trace 1135 away from the substrate 10, the pixel definition layer 125 defines a plurality of sub-pixel regions, the anode 1111, the light emitting layer 1112, and the cathode 1113 are stacked to form the light emitting unit 111, and the light emitting unit 111 is located in the sub-pixel region.

[0156] For example, first, an epoxy material layer is formed on the side of the fifth connection trace 1135 away from the substrate 10, and the epoxy material layer is processed by a one-time patterning process to obtain the fourth planar layer 121. Then, an ITO material layer is formed on the side of the fourth planar layer 121 away from the substrate 10, and the ITO material layer is processed by a one-time patterning process to obtain the fifth connection trace 1135.

[0157] In steps 1001 to 1010a above, the process for forming the material layer can be deposition, magnetron sputtering, thermal evaporation, or plasma-enhanced chemical vapor deposition (PECVD).

[0158] In summary, the display substrate manufacturing method provided in this application has the following advantages: In the display substrate manufactured by this method, sub-pixels include light-emitting units and driving units. The driving unit includes a target functional film layer. The display area of ​​the display substrate includes a target display area. The target driving unit of the target light-emitting unit in the target display area is located in the non-display area of ​​the display substrate. The target light-emitting unit and the target driving unit are electrically connected through a target connection structure. The portion of the target connection structure located in the target display area is a transparent structure. The target connection structure includes a first connection trace, which is in the same layer and made of the same material as the target functional film layer. Because the first connection trace and the target functional film layer are in the same layer and made of the same material, they can be fabricated in a single patterning process. This helps reduce the number of patterning processes required in the manufacturing of the display substrate, simplifying the manufacturing process and reducing the manufacturing cost of the display substrate.

[0159] It should be noted that, Figure 4 The illustrated embodiment is used for manufacturing Figure 2 The following explanation uses a display substrate as an example. During manufacturing... Figure 3 , Figures 5 to 7 as well as Figure 10 When using the display substrate shown, the above-mentioned... Figure 2 The steps of the illustrated embodiment have been adapted accordingly.

[0160] As an example of this application, in manufacturing Figure 10 When the display substrate shown is used, the above Figure 2 Steps 1007a and 1008a in the illustrated embodiment can be replaced by steps 1007b and 1008b as described below.

[0161] In step 1007b, a second connection trace is formed on the side of the target film layer away from the substrate.

[0162] The implementation process of step 1007b can be referred to step 1007a, and will not be repeated here.

[0163] In step 1008b, a second planarization layer and a third connection trace are sequentially formed on the side of the second connection trace away from the substrate.

[0164] The implementation process of step 1008b can be referenced from step 1008a. For example... Figure 2As shown, the third connection hole penetrates the second planar layer 119, the first planar layer 115, the passivation layer 114, the first ILD layer 118 and the first GI layer 116, and the third connection trace 1133 is electrically connected with the first connection line 1131 through the third connection hole.

[0165] For Figure 3 As shown in the display substrate, the first connection trace 1131, the second connection trace 1132, the third connection trace 1133 and the fifth connection trace 1135 constitute a target connection structure 113, and the target connection structure 113 electrically connects the target light emitting unit 111A and the target driving unit 112A.

[0166] As another example of the present application, in manufacturing Figure 6 、 Figure 7 and Figure 10 the display substrate, the steps 1007a to 1010a in the above-mentioned embodiment can be replaced by the following steps 1007c to 1009c. Figure 3 In step 1007c, the second connection trace and the third connection trace are formed on the side of the target film layer away from the substrate substrate, and the second connection trace and the third connection trace are located in the same layer, the second connection trace is located in the non-display area, and the third connection trace is a transparent trace, and the third connection trace is located in the target display area.

[0167] For example, referring to

[0168] 、 Figure 6 or Figure 7 , first, a metal material layer is formed on the side of the target film layer (i.e. the first planar layer 115) away from the substrate substrate 10, and the metal material layer is processed by a one-time patterning process to obtain the second connection trace 1132. Then, an ITO material layer is formed on the side of the first planar layer 115 away from the substrate substrate 10, and the ITO material layer is processed by a one-time patterning process to obtain the third connection trace 1133. Alternatively, an ITO material layer can be formed on the side of the target film layer (i.e. the first planar layer 115) away from the substrate substrate 10, and the ITO material layer is processed by a one-time patterning process to obtain the third connection trace 1133, and then a metal material layer is formed on the side of the target film layer (i.e. the first planar layer 115) away from the substrate substrate 10, and the metal material layer is processed by a one-time patterning process to obtain the second connection trace 1132. The present application does not limit the order of forming the second connection trace 1132 and the third connection trace 1133. Figure 3 In step 1008c, the second planar layer and the fifth connection trace are formed in sequence on the side of the second connection trace and the third connection trace away from the substrate substrate, and the fifth connection trace is a transparent trace, and the fifth connection trace is located in the target display area.

[0169] ​

[0170] The implementation process of step 1008c can be referred to step 1009a, and will not be repeated here.

[0171] for Figure 6 , Figure 7 and Figure 5 The display substrate shown has a target connection structure consisting of a first connection trace 1131, a second connection trace 1132, a third connection trace 1133, and a fifth connection trace 1135. The target connection structure electrically connects the target light-emitting unit 111A to the target driving unit 112A.

[0172] In step 1009c, a fourth planarization layer and a light-emitting unit are sequentially formed on the side of the fifth connection trace away from the substrate.

[0173] The implementation process of step 1008c can be referred to step 1010a, and will not be repeated here.

[0174] As another example of this application, in manufacturing Figure 10 When the display substrate shown is used, the above Figure 5 Steps 1007a to 1010a in the illustrated embodiment can be replaced by steps 1007d and 1008d as described below.

[0175] In step 1007d, a second connection trace is formed on the side of the target film layer away from the substrate, and the second connection trace is located in the non-display area.

[0176] The implementation process of step 1007d can be referred to step 1007a, and will not be repeated here.

[0177] In step 1008d, a second planarization layer and a light-emitting unit are sequentially formed on the side of the second connection trace away from the substrate.

[0178] The implementation process of step 1008d can be referred to step 1010a, and will not be repeated here.

[0179] like Figure 5 As shown, the anode connection hole penetrates the second planarization layer 119, the first planarization layer 115, the passivation layer 114, the first ILD layer 118, and the first GI layer 116. The anode 1111 of the target light-emitting unit 111A is electrically connected to the first connecting line 1131 through this anode connection hole. For ​ The display substrate shown has a target connection structure 113 formed by the first connection trace 1131 and the second connection trace 1132.

[0180] It should be noted that the one-time patterning process involved in the embodiment of the present application includes photoresist coating, exposure, development, etching and photoresist stripping. The processing of the material layer (for example, the IGZO material layer) through the one-time patterning process includes: coating a layer of photoresist on the material layer (for example, the IGZO material layer) to form a photoresist layer, exposing the photoresist layer using a mask to form a completely exposed area and a non-exposed area in the photoresist layer, then using a development process to completely remove the photoresist in the completely exposed area and completely retain the photoresist in the non-exposed area, using an etching process to etch the region corresponding to the completely exposed area of the material layer (for example, the IGZO material layer), and finally stripping the photoresist in the non-exposed area to obtain the corresponding structure (for example, the first connection trace 1131). Here, taking the positive photoresist as an example for description, when the photoresist is a negative photoresist, the process of the one-time patterning process can refer to the description in this paragraph, and the embodiment of the present application will not be described here.

[0181] The order of the steps of the manufacturing method of the display substrate provided in the embodiment of the present application can be adjusted appropriately, and the steps can be increased or decreased as appropriate. Any person skilled in the art can easily think of changes within the technical range disclosed in the present application, which should be covered within the protection scope of the present application, and therefore will not be described here.

[0182] The embodiment of the present application also provides a display device, which includes a housing, a camera and the display substrate provided in the above embodiment. The camera is arranged between the housing and the display substrate, and the orthographic projection of the camera on the display substrate is located in the target display area of the display substrate.

[0183] Optionally, the display device can be a smartphone, a tablet computer, a smart bracelet, a smart watch, a notebook computer, a digital photo frame or a navigator, or any product or component having a display function.

[0184] In the present application, the terms "first", "second", "third", "fourth" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "multiple" refers to two or more, unless otherwise explicitly limited. The term "at least one" is the same as this. The term "electrically connected" means connected and can transmit electric charge, without limiting the transmission of electric charge, for example, A and B are electrically connected, which means that A and B are connected and electric charge can be transmitted between A and B, without limiting the transmission of electric charge between A and B.

[0185] It is to be understood that the sizes of the layers and regions shown in the figures can be exaggerated for clarity of illustration. Also, it is to be understood that when a layer or element is referred to as being "on" another layer or element, it can be directly on the other layer or element or intervening layers can also be present. In addition, it is to be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements or one or more intervening layers can also be present.

[0186] The above description is merely illustrative of the exemplary embodiments of this application and is not intended to limit the scope of the application. It is recognized that modifications, equivalent substitutions, improvements, etc. not specifically enumerated herein can be resorted to by those skilled in the art and that such modifications, equivalent substitutions, improvements, etc. should be considered to fall within the scope of the application.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate substrate having a display area and a non-display area, the display area comprising a target display area; a display structure layer on the substrate substrate, the display structure layer comprising a plurality of sub-pixels, the sub-pixels comprising a light-emitting unit and a driving unit, the light-emitting unit being located in the display area, and the driving unit comprising a target functional film layer; wherein the light-emitting unit in the target display area is a target light-emitting unit, the target driving unit of the target light-emitting unit is located in the non-display area, the target light-emitting unit and the target driving unit are electrically connected through a target connection structure, part of the target connection structure in the target display area is a transparent structure, the target connection structure comprises a first connection trace, the first connection trace is a transparent trace, and the first connection trace and the target functional film layer are of the same layer and the same material; the driving unit comprises an oxide active layer, the target functional film layer is the oxide active layer, and the hydrogen content of a target film layer in the display substrate that contacts the first connection trace is higher than a preset threshold value; the display structure layer comprises an interlayer structure layer between the first connection trace and the target film layer, the interlayer structure layer has a contact hole, and the target film layer contacts the first connection trace through the contact hole; the interlayer structure layer comprises a first GI layer and a first ILD layer distributed away from the substrate substrate; and the first GI layer is in contact with the target functional film layer.

2. The display substrate of claim 1, wherein, The material of the target film layer comprises at least one of an organic material and silicon nitride.

3. The display substrate of claim 1, wherein, The ratio of the overlapping area of the contact hole and the first connection trace to the area of the orthographic projection of the first connection trace on the substrate substrate is greater than a preset ratio, and the overlapping area is the area of the overlapping region of the orthographic projection of the contact hole on the substrate substrate and the orthographic projection of the first connection trace on the substrate substrate.

4. The display substrate of claim 3, wherein: the interlayer structure layer has one contact hole, and the orthographic projection of the contact hole on the substrate substrate covers the orthographic projection of the first connection trace on the substrate substrate; or, the interlayer structure layer has a plurality of contact holes, and the plurality of contact holes are uniformly distributed in a first area of the interlayer structure layer, and the first area corresponds to the first connection trace.

5. The display substrate of any one of claims 1 to 4, wherein: the target film layer comprises at least one of a planar layer and a passivation layer.

6. The display substrate of any one of claims 1 to 4, wherein: the target connection structure further comprises a second connection trace and a third connection trace, and the second connection trace and the third connection trace are located in the same layer; the second connection trace is located in the non-display area, and the second connection trace is electrically connected to the first connection trace and the target driving unit, respectively; The third connection wire is a transparent wire, and the third connection wire is located in the target display area and is electrically connected with the first connection wire and the target light emitting unit respectively.

7. The display substrate of any one of claims 1 to 4, wherein, The target connection structure further comprises a second connection wire, a third connection wire and a fourth connection wire, the second connection wire and the fourth connection wire are located on the same layer, and the third connection wire is located on the side of the fourth connection wire away from the substrate; The second connection wire is located in the non-display area, and the second connection wire is electrically connected with the first connection wire and the target driving unit respectively; The third connection wire is a transparent wire, and the third connection wire and the fourth connection wire are located in the target display area, the fourth connection wire is electrically connected with the third connection wire and the first connection wire respectively, and the third connection wire is electrically connected with the target light emitting unit; The target light emitting unit comprises an anode, and the orthographic projection of the fourth connection wire on the substrate is located in the orthographic projection of the anode on the substrate.

8. The display substrate of claim 7, wherein, The target connection structure further comprises a fifth connection wire; The fifth connection wire is a transparent wire, and the fifth connection wire is located in the target display area and on the side of the third connection wire away from the substrate; The third connection wire is electrically connected with the target light emitting unit through the fifth connection wire.

9. The display substrate of any one of claims 1 to 4, wherein, The target connection structure further comprises a second connection wire, The second connection wire is located in the non-display area, and the second connection wire is electrically connected with the first connection wire and the target driving unit respectively; The first connection wire is electrically connected with the target light emitting unit.

10. A method for manufacturing a display substrate, characterized by, Comprising: providing a substrate, the substrate having a display area and a non-display area, the display area comprising a target display area; forming a display structure layer on the substrate, the display structure layer comprising a plurality of sub-pixels, the sub-pixels comprising a light emitting unit and a driving unit, the light emitting unit being located in the display area, and the driving unit comprising a target functional film layer; wherein the light emitting unit located in the target display area is a target light emitting unit, the target driving unit of the target light emitting unit is located in the non-display area, the target light emitting unit and the target driving unit are electrically connected through a target connection structure, the part of the target connection structure located in the target display area is a transparent structure, the target connection structure comprises a first connection wire, the first connection wire is a transparent wire, and the first connection wire is the same layer and the same material as the target functional film layer; forming a display structure layer on the substrate comprises: forming a functional material layer on the substrate; The functional material layer is processed by a one-time patterning process to obtain the target functional film layer and the first connection trace; The driving unit includes an oxide active layer, and the target functional film layer is the oxide active layer, and a hydrogen content of a target film layer in the display substrate that is in contact with the first connection trace is higher than a preset threshold value; forming a display structure layer on the substrate substrate, further comprising: forming an interlayer structure layer on a side of the first connection trace away from the substrate substrate, the interlayer structure layer having a contact hole therein; forming a target film layer on a side of the interlayer structure layer away from the substrate substrate, the target film layer being in contact with the first connection trace through the contact hole; The interlayer structure layer includes: a first GI layer and a first ILD layer distributed in a direction away from the substrate substrate; and the first GI layer is in contact with the target functional film layer.

11. The method of claim 10, wherein forming a display structure layer on the substrate substrate, further comprising: forming a second connection trace and a third connection trace on a side of the interlayer structure layer away from the substrate substrate, the second connection trace and the third connection trace being located in the same layer, the second connection trace being located in the non-display area, and the third connection trace being a transparent trace, the third connection trace being located in the target display area; The target connection structure further includes the second connection trace and the third connection trace, the second connection trace being electrically connected to the first connection trace and the target driving unit, and the third connection trace being electrically connected to the first connection trace and the target light emitting unit.

12. The method of claim 10, wherein forming a display structure layer on the substrate substrate, further comprising: forming a second connection trace, a third connection trace and a fourth connection trace on a side of the interlayer structure layer away from the substrate substrate, the second connection trace and the fourth connection trace being located in the same layer, the third connection trace being located on a side of the fourth connection trace away from the substrate substrate, the second connection trace being located in the non-display area, the third connection trace being a transparent trace, and the third connection trace and the fourth connection trace being located in the target display area; The target connection structure further includes the second connection trace, the third connection trace and the fourth connection trace, the second connection trace being electrically connected to the first connection trace and the target driving unit, the third connection trace being electrically connected to the first connection trace and the target light emitting unit, and the target light emitting unit including an anode, a projection of the fourth connection trace on the substrate substrate being located within a projection of the anode on the substrate substrate.

13. The method of claim 11 or 12, wherein forming a display structure layer on the substrate substrate, further comprising: forming a fifth connection trace on a side of the third connection trace away from the substrate substrate, the fifth connection trace being a transparent trace, and the fifth connection trace being located in the target display area; The target connection structure further includes the fifth connection trace, and the third connection trace is electrically connected with the target light emitting unit through the fifth connection trace.

14. The method of claim 10, wherein, forming a display structure layer on the substrate substrate further includes: forming a second connection trace on a side of the interlayer structure layer away from the substrate substrate, the second connection trace being located in the non-display area; The target connection structure further includes the second connection trace, and the second connection trace is electrically connected with the first connection trace and the target driving unit respectively, and the first connection trace is electrically connected with the target light emitting unit.

15. A display device comprising: including: a housing, a camera, and the display substrate according to any one of claims 1-9; The camera is arranged between the housing and the display substrate, and the orthographic projection of the camera on the display substrate is located in the target display area of the display substrate.

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