Integrally formed splitter for multipath power amplifier and method of manufacturing the same

Abstract

Aspects of the present disclosure may include a power splitter. The power splitter may include a first splitter branch having a first amplifier with passive components and a second splitter branch having a second amplifier with passive components. By configuring the first splitter branch and the second splitter branch to have similar phase delays, the first splitter branch is substantially electrically isolated from the second splitter branch. The output of the power splitter may be electrically coupled to a multi-stage amplifier. The power splitter may be fabricated on a single semiconductor die or integrally formed on the same semiconductor die with other circuitry, such as the multi-stage amplifier. Other embodiments are disclosed.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to splitters with multi-path power amplifiers and methods of making the same, which can be used with single-stage or multi-stage amplifiers, such as Doherty power amplifiers or other suitable amplifier architectures. Background Art

[0002] A typical Doherty power amplifier (PA) includes a signal splitter for receiving and dividing an input radio frequency (RF) signal, a main amplifier for amplifying the first signal from the splitter, a peaking amplifier for amplifying the second signal from the splitter, a signal combiner for combining the amplified signals from the main and peaking amplifiers, and various impedance transforming and phase delay elements for ensuring that the amplified signals are combined in phase and that the desired impedance is present at various points within the Doherty power amplifier. The signal splitter and signal combiner are typically implemented on a printed circuit board (PCB) substrate, while the main and peaking amplifiers are implemented using one or more discretely packaged devices physically coupled to the PCB substrate.

[0003] In modern wireless 4G and 5G communication systems, RF power amplifier design has become increasingly complex. Some of these systems require the PA to operate at very low power output back-off (e.g., 8 to 12 decibels (dB)) to achieve good linearity, while limiting signal compression associated with high peak-to-average power ratio signals and achieving high power-added efficiency. Doherty PA and inverted Doherty PA configurations remain popular in wireless base stations. However, a high level of integration is required to meet the stringent requirements of modern wireless standards, including providing wide instantaneous bandwidth and high efficiency. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a multi-branch splitter, comprising:

[0005] semiconductor die;

[0006] Radio frequency (RF) signal input terminal;

[0007] a first splitter branch comprising a first amplifier and a first regulating element integrally formed with the semiconductor die, wherein a first gate terminal of the first amplifier is coupled to the RF signal input terminal, and wherein a first drain terminal of the first amplifier is coupled to a first input of the first regulating element;

[0008] a second splitter branch comprising a second amplifier and a second regulating element integrally formed with the semiconductor die, wherein a second gate terminal of the second amplifier is coupled to the RF signal input terminal, and wherein a second drain terminal of the second amplifier is coupled to a second input of the second regulating element;

[0009] wherein the first splitter branch has a first combined phase delay based at least on a combination of a first phase delay of the first amplifier and a second phase delay of the first regulating element,

[0010] wherein the second splitter branch has a second combined phase delay based at least on a combination of a third phase delay of the second amplifier and a fourth phase delay of the second regulating element,

[0011] wherein the first splitter branch is substantially electrically isolated from the second splitter branch based on the first combined phase delay being substantially equal to the second combined phase delay, and

[0012] The first splitter branch and the second splitter branch are configured to split an RF signal and amplify an input power level of the RF signal according to an amplification ratio when the RF signal is applied to the RF signal input terminal.

[0013] According to one or more embodiments, the multi-branch splitter further includes an isolation impedance, wherein a first end of the isolation impedance is coupled to a first output end of the first regulating element, wherein a second end of the isolation impedance is coupled to a second output end of the second regulating element, and wherein the isolation impedance further increases the isolation between the first splitter branch and the second splitter branch.

[0014] According to one or more embodiments, the first adjustment element includes a transmission line having an electrical length that produces the second phase delay.

[0015] According to one or more embodiments, the second adjustment element includes a transmission line having an electrical length that generates the fourth phase delay.

[0016] According to one or more embodiments, the first adjustment element includes a lumped element delay circuit that generates the second phase delay.

[0017] According to one or more embodiments, the second adjustment element includes a lumped element delay circuit that generates the fourth phase delay.

[0018] According to one or more embodiments, the first combined phase delay is substantially equal to 90 degrees.

[0019] According to one or more embodiments, the second combined phase delay is substantially equal to 90 degrees.

[0020] According to one or more embodiments, a first output end of the first splitter branch is coupled to at least one peaking amplification path of a Doherty amplifier, wherein a second output end of the second splitter branch is coupled to a main amplification path of the Doherty amplifier, and wherein the semiconductor die is a single semiconductor die, and wherein the Doherty amplifier is formed integrally with the single semiconductor die.

[0021] According to one or more embodiments, the first adjustment element is further configured to substantially match a first impedance of the first drain terminal of the first amplifier, and the second adjustment element is further configured to substantially match a second impedance of the second drain terminal of the second amplifier.

[0022] According to one or more embodiments, the amplification ratio between the first splitter branch and the second splitter branch is asymmetric.

[0023] According to one or more embodiments, the amplification ratio between the first splitter branch and the second splitter branch is substantially symmetrical.

[0024] According to one or more embodiments, the multi-branch splitter further comprises:

[0025] a third splitter branch comprising a third amplifier and a third regulating element integrally formed with the semiconductor die, wherein a third gate terminal of the third amplifier is coupled to the RF signal input terminal, and wherein a third drain terminal of the third amplifier is coupled to a third input of the third regulating element,

[0026] wherein the third splitter branch has a third combined phase delay based on at least a combination of a fifth phase delay of the third amplifier and a sixth phase delay of the third regulating element,

[0027] wherein the third splitter branch is substantially electrically isolated from the first splitter branch based on the third combined phase delay being substantially equal to the first combined phase delay, and

[0028] Wherein the third splitter branch is substantially electrically isolated from the second splitter branch based on the third combined phase delay being substantially equal to the second combined phase delay.

[0029] According to a second aspect of the present invention, there is provided a multipath amplifier, comprising:

[0030] semiconductor substrates;

[0031] a first splitter branch comprising a first pre-driver amplifier integrally formed on the semiconductor substrate, wherein a first gate terminal of the first pre-driver amplifier is coupled to an RF signal input terminal;

[0032] a second splitter branch comprising a second pre-driver amplifier integrally formed on the semiconductor substrate, wherein a second gate terminal of the second pre-driver amplifier is coupled to the RF signal input terminal;

[0033] a first amplification path integrally formed on the semiconductor substrate, wherein the first amplification path is coupled to a first output of the first splitter branch;

[0034] a second amplification path integrally formed on the semiconductor substrate, wherein the second amplification path is coupled to a second output of the second splitter branch;

[0035] wherein the first splitter branch provides a first pre-amplification level of an RF signal when the RF signal is applied to the RF signal input to generate a first amplified signal supplied to the first amplification path,

[0036] wherein the second splitter branch provides a second pre-amplification level of the RF signal to generate a second amplified signal supplied to the second amplification path,

[0037] By configuring the first splitter branch and the second splitter branch to have a phase delay of approximately 90 degrees, the electrical coupling between the first splitter branch and the second splitter branch is greatly reduced.

[0038] According to one or more embodiments, the first splitter branch further includes a first regulating element, and wherein the first drain terminal of the first pre-driver amplifier is coupled to the first input of the first regulating element, wherein the first output of the first regulating element is coupled to the first amplification path, wherein the second splitter branch further includes a second regulating element, wherein the second drain terminal of the second pre-driver amplifier is coupled to the second input of the second regulating element, and wherein the second output of the second regulating element is coupled to the second amplification path.

[0039] According to one or more embodiments, the first separator branch has a first combined phase delay based at least on a combination of a first phase delay of the first pre-driver amplifier and a second phase delay of the first adjustment element, wherein the second separator branch has a second combined phase delay based at least on a combination of a third phase delay of the second pre-driver amplifier and a fourth phase delay of the second adjustment element, and wherein electrical coupling between the first separator branch and the second separator branch is substantially achieved by configuring the first combined phase delay to be substantially equal to the second combined phase delay.

[0040] According to a third invention of the present invention, there is provided a method comprising:

[0041] forming a first splitter branch on a semiconductor substrate, the first splitter branch comprising a first amplifier and a first regulating element integrally formed with the semiconductor substrate, wherein a first gate terminal of the first amplifier is coupled to an RF signal input terminal, and wherein a first drain terminal of the first amplifier is coupled to a first input of the first regulating element; and

[0042] A second splitter branch is formed on the semiconductor substrate, the second splitter branch including a second amplifier and a second regulating element integrally formed with the semiconductor substrate, wherein a second gate terminal of the second amplifier is coupled to the RF signal input terminal, and wherein a second drain terminal of the second amplifier is coupled to a second input of the second regulating element, wherein the first splitter branch is substantially electrically isolated from the second splitter branch based on the first splitter branch and the second splitter branch having substantially similar phase delays.

[0043] According to one or more embodiments, the method further comprises:

[0044] forming a first amplification path on the semiconductor substrate, the first amplification path coupled to a first output of the first regulating element; and

[0045] A second amplification path is formed on the semiconductor substrate, the second amplification path being coupled to a second output of the second regulating element.

[0046] According to one or more embodiments, the first amplification path comprises a main amplification path of a Doherty amplifier, and wherein the second amplification path comprises at least one peaking amplification path of the Doherty amplifier.

[0047] According to one or more embodiments, each of the first amplifier and the second amplifier includes a silicon-based field emission transistor (FET), a silicon-germanium (SiGe)-based FET, a gallium nitride (GaN)-based FET, a gallium arsenide (GaAs)-based FET, a gallium phosphide (GaP)-based FET, an indium phosphide (InP)-based FET, an indium antimonide (InSb)-based FET, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following drawings, wherein like reference numerals refer to like elements throughout.

[0049] Figure 1 is a simplified schematic diagram of an integrated Doherty power amplifier according to an example embodiment;

[0050] Figure 2 is a top view of a Doherty power amplifier integrated circuit (IC) according to an example embodiment;

[0051] Figure 3 is taken along line 3-3 according to an exemplary embodiment Figure 2 Cross-sectional view of the Doherty amplifier IC;

[0052] Figure 4 is a simplified schematic diagram of a power splitter according to an example embodiment;

[0053] Figure 5A According to an example embodiment Figure 4 An embodiment of a power splitter;

[0054] Figure 5B 、 5C 5D and 5E depict a method for implementing Figure 4 and an embodiment of a "transistor finger" configuration of a 5A power splitter;

[0055] Figures 5F-5G Depicted are diagrams according to example embodiments. Figure 4 and 5A Alternative embodiments of the power splitter;

[0056] Figure 5H Depicts a comparison according to an example embodiment Figure 4 and 5A A graph showing the performance of a power splitter and a passive splitter;

[0057] Figure 6 is a top view of a Doherty amplifier device encapsulated in a high power package according to an example embodiment;

[0058] Figure 7 is a top view of a packaged Doherty amplifier device coupled to a printed circuit board substrate according to an example embodiment;

[0059] Figure 8A is a flow chart of a method of making a Doherty power amplifier IC and a packaged Doherty amplifier device according to an example embodiment; and

[0060] Figure 8B is a flow chart of a method of making a power splitter IC and a packaged power splitter device according to example embodiments. DETAILED DESCRIPTION

[0061] Embodiments of the present subject matter include an integral (i.e., integrally formed in and / or on a single semiconductor die) power splitter that can be electrically coupled to the input of a multipath power amplifier (e.g., a Doherty amplifier), each path of which includes a single-stage amplifier or a multi-stage amplifier. The power splitter and the multipath amplifier can be located on different dies or can be combined on the same die. The power splitter can include multiple power splitter branches, each of which can be configured to couple to an amplification path of the multipath amplifier. Each power splitter branch can include an amplifier and an adjustment element. The adjustment element can include a transmission line, a lumped element delay circuit, or other suitable delay circuit. The amplifiers used in the power splitter branches can have symmetrical or asymmetrical gains and can be configured for a specific frequency band or frequency band range. To increase the electrical isolation between the power splitter branches, each branch can be configured to have a similar or substantially equal phase delay (e.g., 90 degrees or other suitable delay for each branch). Isolation impedances can also be added between the power splitter branches to further increase the electrical isolation between such branches.

[0062] Although the present disclosure emphasizes utilizing a power splitter with a Doherty power amplifier, it should be understood that the power splitter described below may also be used with other suitable single-path or multi-path amplifiers on the same die or separate dies. Therefore, it is contemplated that the following power splitter description is non-limiting.

[0063] The following and illustrated embodiment of the Doherty amplifier IC corresponds to a bidirectional Doherty amplifier comprising a main amplifier and one peaking amplifier. Although not explicitly shown, other embodiments may include an "N-way" Doherty power amplifier, where N>2, and where the number of peaking amplifiers is equal to N-1.

[0064] Figure 11 is a simplified schematic diagram of an integrated Doherty power amplifier 100 according to an example embodiment. Doherty amplifier 100 includes an input node 102, an output node 192, a power splitter 104 (or splitter), a main amplification path 120, a peaking amplification path 111, and a combining node structure 190. A load 196 can be coupled to combining node structure 190 (e.g., through an impedance transformer (not shown)) to receive an amplified RF signal from amplifier 100.

[0065] The Doherty power amplifier 100 is considered a "bidirectional" Doherty power amplifier, which includes a main amplifier 120 and a peaking amplifier 140. The main amplifier 120 provides amplification along a first amplification path 110, and the peaking amplifier 140 provides amplification along a second amplification path 111. Figure 1 In the embodiment depicted in FIG, the peaking amplifier 140 is “split” in that the amplification performed by the peaking amplifier 140 is actually performed by two substantially identical peaking amplifier sections 140′, 140″ (collectively referred to as peaking amplifiers 140) along two parallel and substantially identical amplification paths 111′, 111″ (collectively referred to as amplification paths 111). As shown in conjunction with FIG. Figure 2 As will be explained in greater detail, according to one embodiment, the peaking amplification paths 111 ′, 111 ″ are physically located on opposite sides of the main amplification path 110 . In other embodiments, the peaking amplifier 140 may not be “split,” and instead a single amplification path may be used for the peaking amplification path.

[0066] Although the main amplifier 120 and the peaking amplifier 140 can be of equal size (e.g., a 1:1 main-to-peak size ratio in a symmetric Doherty configuration), the main amplifier 120 and the peaking amplifier 140 can also be unequal in size (e.g., in various asymmetric Doherty configurations). In an asymmetric bidirectional Doherty amplifier configuration, the peaking power amplifier 140 is typically several times larger than the main power amplifier 120. For example, the size of the peaking power amplifier 140 can be twice that of the main power amplifier 120, such that the peaking power amplifier 140 has twice the current carrying capacity of the main power amplifier 120. Asymmetric main-to-peak amplifier size ratios other than a 1:2 ratio can also be implemented.

[0067] The power splitter 104 is configured to split the power of the input RF signal received at the input node 102 into a main portion and a peaking portion of the input signal. Because the peaking amplifier 140 is implemented using two peaking amplifier sections 140', 140", as explained above, the peaking portion of the input signal is actually composed of two peaking input signals. Therefore, the power splitter 104 is configured to split the power of the input RF signal received at the input node 102 into one main portion of the input signal and two peaking portions of the input signal. The main input signal is provided to the main amplification path 120 at the power splitter output 106, and the peaking input signal is provided to the peaking amplification paths 111', 111" at the power splitter outputs 107 and 108. During operation in a full power mode in which both the main amplifier 120 and the peaking amplifier 140 (including 140' and 140") supply current to the load 196, the power splitter 104 divides the input signal power between the amplification paths 110, 111', 111".

[0068] For example, the power splitter 104 may divide the power equally so that approximately one-third of the input signal power is provided to each path 110, 111', 111". This may be the case, for example, when the Doherty amplifier 100 has an asymmetric Doherty amplifier configuration in which the peaking amplifier 140 is approximately twice the size of the main amplifier 120 (i.e., The Doherty amplifier 100 has an asymmetric configuration with a main peak size ratio of 1:2. In the case of a 1:2 main peak size ratio, the combined size of the peaking amplifier sections 140', 140" is approximately twice the size of the main amplifier 120, which can be achieved when the size of each of the amplifiers 120, 140', 140" is approximately equal. Alternatively, the power splitter 104 can divide the power unevenly, particularly when the Doherty amplifier 100 has an asymmetric configuration other than a 1:2 main peak size ratio, or when the Doherty amplifier 100 has a symmetric configuration. In the case of a symmetric Doherty amplifier configuration, the peaking amplifier 1 The size of peaking amplifier sections 140′, 140″ is approximately equal to the size of main amplifier 120 (i.e., Doherty amplifier 100 has a symmetrical configuration with a main peak size ratio of 1:1). In the case of a 1:1 main peak size ratio, the combined size of peaking amplifier sections 140′, 140″ is approximately equal to the size of main amplifier 120, which can be achieved when the size of each of amplifiers 140′, 140″ is approximately half the size of amplifier 120. In this case, power splitter 104 can divide the power such that approximately half of the input signal power is provided to main amplification path 120 at power splitter output 106, and approximately one-quarter of the input signal power is provided to each of peaking amplification paths 111′, 111″ at power splitter outputs 107 and 108.

[0069] The power splitter 104 includes an input node 102, three branches 181, 182', 182" and three output nodes 106-108. In other embodiments, the power splitter 104 may include two branches and two output nodes (eg, Figure 5B In the embodiment shown), or more than three branches and output nodes. Each splitter branch 181, 182', 182" of the power splitter 104 includes a pre-driver amplifier and corresponding adjustment elements, which will be described below. Figures 5A-5H. The pre-driver amplifier and conditioning elements of each splitter branch 181, 182', 182" amplify the divided input RF signal supplied at the input node 102 with equal phase across the splitting branches 181, 182', 182", and the divided signals produced at the output nodes 106-108 are separately additionally amplified along the main amplification path 110 and the peaking amplification paths 111', 111". The amplified signals generated by the main amplification path 110 and the peaking amplification paths 111', 111" are then combined in phase at the combining node structure 190. Importantly, phase consistency between the main amplification path 110 and the peaking amplification paths 111', 111" is maintained across the frequency band of interest to ensure that the amplified main signal and the peaking signal arrive at the combining node structure 190 in phase and, therefore, ensure proper Doherty amplifier operation. In Figure 1 In the depicted Doherty amplifier configuration (i.e., a non-inverting Doherty configuration as described below), input phase delay circuits 109', 109" are coupled between the power splitter outputs 107 and 108 and the peaking amplifier inputs 141', 141". According to one embodiment, each input phase delay circuit 109', 109" applies a phase delay of approximately 90 degrees to the peaking input signal before it is provided to the peaking amplifier 140', 140". For example, each input phase delay circuit 109', 109" may include a quarter-wavelength transmission line, a lumped element delay circuit, or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0070] The pre-driver amplifier in each splitter branch 181, 182', 182" includes a single power transistor (e.g., composed of one or more transistor fingers). The main amplifier 120 and the peaking amplifier section 140', 140" can be configured to include a single power transistor or multiple cascaded power transistors for amplifying the RF signal conducted through the amplifiers 120, 140', 140". As used herein, the term "transistor" means a field effect transistor (FET) or another type of suitable transistor. For example, a "FET" can be a metal oxide semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), an enhancement mode or depletion mode high electron mobility transistor (HEMT), or another type of FET. According to various embodiments, each of the power transistors in the main amplifier section 120 and the peaking amplifier section 140', 140" can be implemented, for example, using a silicon-based FET (e.g., an LDMOS FET), a silicon germanium (SiGe)-based FET, or a III-V A FET (eg, a HEMT) such as a gallium nitride (GaN) FET (or another type of III-V transistor including a gallium arsenide (GaAs) FET, a gallium phosphide (GaP) FET, an indium phosphide (InP) FET, or an indium antimonide (InSb) FET).

[0071] According to one embodiment of the Doherty amplifier 100, the main amplifier 120 is a two-stage amplifier that includes a relatively low-power driver amplifier 126 and a relatively high-power final amplifier 130 connected in a cascade arrangement between a main amplifier input 121 and a main amplifier output 134. In the main amplifier cascade arrangement, the output 127 of the driver amplifier 126 is electrically coupled to the input 129 of the final amplifier 130. Similarly, each of the peaking amplifier sections 140′, 140″ is a two-stage amplifier that includes a relatively low-power driver amplifier 146′, 146″ and a relatively high-power final amplifier 150′, 150″ connected in a cascade arrangement between a peaking amplifier input 141′, 141″ and a peaking amplifier output 154′, 154″. In each peaking amplifier cascade arrangement, an output 147′, 147″ of the driver amplifier 146′, 146″ is electrically coupled to an input 149′, 149″ of the final amplifier 150′, 150″.

[0072] In other embodiments, the main amplifier 120 and the peaking amplifier sections 140', 140" may comprise single-stage amplifiers (e.g., the driver amplifiers 126, 146', 146" may be excluded). In still other embodiments, the power splitter 104 may be coupled to a Doherty amplifier 100 in which the main amplifier path and the peaking amplifier path each have Figure 1 More than two cascade-coupled amplifier stages are shown. Input impedance matching networks 122, 142', 142" (IMN) and inter-stage impedance matching networks 128, 148', 148" (ISMN) can be implemented at the input 125, 145', 145" of each driver amplifier 126, 146', 146", respectively, and between each driver amplifier 126, 146', 146" and each final amplifier 130, 150', 150". In each case, matching networks 122, 142', 142", 128, 148', 148" can incrementally increase the circuit impedance toward the load impedance. In addition to providing signal amplification of the input signal at the input node 102, each splitter branch 181, 182', 182" of the power splitter 104 may also provide a 50 ohm (or other) input impedance suitable for the input node 102 and output impedance matching characteristics that may eliminate, in whole or in part, the need for matching networks IMN 122, 141', 141" of the main amplifier 120 and peaking amplifier sections 140', 140", respectively.

[0073] During operation of the Doherty amplifier 100, the main amplifier 120 is biased to operate in Class AB mode and the peaking amplifier 140 is typically biased to operate in Class C mode. In some configurations, the peaking amplifier 140 can be biased to operate in Class B or deep Class B mode. In one embodiment, the amplifier of each splitter branch 181, 182', 182" can also be biased to operate according to the same operating class mode or a suitable operating class mode in combination with the class mode utilized by the main amplifier 120 and the peaking amplifier section 140', 140", respectively. At low power levels where the power of the input signal at node 102 is below the turn-on threshold level of the peaking amplifier 140, the amplifier 100 operates in a low power (or back-off) mode in which the main amplifier 120 is the only amplifier supplying current to the load 196. When the power of the input signal exceeds the threshold level of the peaking amplifier 140 , the amplifier 100 operates in a high power mode in which both the main amplifier 120 and the peaking amplifier 140 supply current to the load 196 .

[0074] At this point, the peaking amplifier 140 provides active load modulation at the combined node structure 190, thereby allowing the current of the main amplifier 120 to continue to increase linearly. Figure 2 As explained in more detail, in one embodiment, one or more resistor-divider gate bias circuits 170, 170', 170" (e.g., Figure 2 Resistor-divider gate bias circuits 270, 270', 270") are provided to perform gate biasing of the main amplifier 120 and the peaking amplifier 140, wherein each resistor-divider gate bias circuit 170, 170', 170" includes at least one resistor 173, 174, 173', 173", 174', 174" electrically coupled between the gate bias voltage input 170, 170', 170" and the input 125, 129, 145', 145", 149', 149" (e.g., gate terminal) of each amplifier 126, 130, 146', 146", 150', 150". Although Figure 1 Not shown, but the amplifier of each splitter branch 181, 182', 182" may utilize the same resistor-divider gate bias circuit 170, 170', 170" or other suitable resistor-divider circuit utilized by the main amplifier 120 and peaking amplifier sections 140', 140", respectively.

[0075] The Doherty amplifier 100 has a "non-inverting" load network configuration. In the non-inverting configuration, the input circuit is configured such that the input signal supplied to the peaking amplifier sections 140', 140" is delayed by 90 degrees relative to the input signal supplied to the main amplifier 120 at the center operating frequency f0 of the amplifier 100. To ensure that the main input RF signal and the peaking input RF signal arrive at the main amplifier 120 and the peaking amplifiers 140, 140" with a phase difference of approximately 90 degrees, as is essential for proper Doherty amplifier operation, the input phase delay circuits 109', 109" each apply a phase delay of approximately 90 degrees to the peaking input signal before it is provided to the peaking amplifier sections 140', 140", as described above.

[0076] To compensate for the 90-degree phase delay difference generated between the main amplification path 110 and the peaking amplification paths 111 ′, 111 ″ at the inputs of the amplifiers 120 , 140 ′, 140 ″ (i.e., to ensure that the amplified signals arrive at the combining node structure 190 in phase), the output phase delay circuit 136 is configured to apply an approximately 90-degree phase delay to the signal between the output of the main amplifier 120 and the combining node structure 190.

[0077] An alternative embodiment of the Doherty amplifier can have an "inverting" load network configuration. In this configuration, the amplifier is configured such that the input signal supplied to the main amplifier 120 is delayed by approximately 90 degrees relative to the input signal supplied to the peaking amplifier sections 140 ′, 140 ″ at the center operating frequency fo of the amplifier 100, and the output phase delay circuit is configured to apply a phase delay of approximately 90 degrees to the signal at the output between the output of the peaking amplifier sections 140 ′, 140 ″ and the combining node structure 190.

[0078] Doherty amplifier 100 is “integrated,” as that term is used herein, because at least main amplifier 120 (e.g., including driver amplifier 122 and final amplifier 130), peaking amplifier 140 (including driver amplifiers 146′, 146″ and final amplifiers 150′, 150″), and combined node structure 190 are integrally and monolithically formed on a single IC die 101 (e.g., Figure 2 In an alternative embodiment, the combined node structure 190 may be implemented separately from the IC die including the main amplifier 120 and the peaking amplifier 140. According to one embodiment, all or part of the input impedance matching networks 122, 142', 142" and the inter-stage impedance matching networks 128, 148', 148" may also be integrally and monolithically formed on the same IC die (e.g., Figure 2 In the tube core 201).

[0079] Alternatively, all or part of the input impedance matching networks 122, 142', 142" may be implemented in one or more components other than the IC die that includes the main amplifier 120 and the peaking amplifier 140. According to further embodiments, the input node 102, the power splitter 104, and the output node 192 are also integrally and monolithically formed on the same IC die as the main amplifier 120 and the peaking amplifier 140 (e.g., Figure 2 In an alternative embodiment, the input node 102 and the power splitter 104 may be implemented in one or more components distinct from the IC die that includes the main amplifier 120 and the peaking amplifier 140. According to yet another alternative embodiment, the resistor-divider bias circuits 170, 170', 170" are also integrally and monolithically formed on the same IC die (e.g., Figure 2 201), but in other embodiments the biasing may be performed by non-integrated circuits and structures.

[0080] Figure 2 is a top view of a Doherty power amplifier IC 200 (or "Dougherty IC") according to an example embodiment. Figure 2 and Figure 3 , Figure 3 It was intercepted along line 3-3 Figure 2 2 is a side cross-sectional view of a Doherty IC 200. As used herein, the terms "integrated circuit die" and "IC die" mean a single, distinct semiconductor die (or semiconductor substrate) within which one or more circuit components (e.g., transistors, passive devices, etc.) are integrally formed and / or directly physically connected to create a unitary structure.

[0081] Doherty IC 200 includes substantially the entire Doherty amplifier (eg, Figure 1 Doherty amplifier 100), wherein the semiconductor die has an input side 210 and an output side 211 that are opposite (e.g., Figure 2 The substantially rectangular periphery is defined by the bottom side and the top side (with the bottom side and the top side facing upward) and the opposite left side 212 and right side 213 extending between the input side and the output side. Figure 2 In the particular embodiment shown, Doherty amplifier IC 200 includes the following circuitry integrally and monolithically formed in and on semiconductor die 201: an input terminal 202 (eg, Figure 1 Input node 102), power splitter 204 (e.g., Figure 1 power splitter 104), input phase delay circuits 209', 209" (eg, Figure 1 Input phase delay circuit 109 ', 109"), two-stage main amplifier 220 (eg, Figure 1 The main amplifier 120 of FIG. 1 is composed of a first peaking amplifier section 240′ and a second peaking amplifier section 240″ (eg, Figure 1 The peaking amplifier sections 140', 140") of the embodiment of the present invention are divided into a peaking amplifier), an output phase delay circuit 236 (eg, Figure 1 output phase delay circuit 136), combined node structure 290 (eg, Figure 1 The combined node structure 190) and the resistor-divider bias circuit 270, 270', 270" (e.g., Figure 1 Resistor-divider bias circuit 170, 170', 170").

[0082] In various alternative embodiments, one or more of the input 202, power splitter 204, input phase delay circuits 209', 209", and / or resistor-divider gate bias circuits 270, 270', 270", may be implemented using circuitry and / or on a physically different substrate than the semiconductor die 201 in and on which the remainder of the Doherty amplifier is formed. Although Figure 2 Not shown, but the power splitter 204 may share the same resistor-divider gate bias circuits 270, 270', 270" or other suitable bias circuits utilized by the main amplifier 220 and peaking amplifier sections 240', 240", respectively.

[0083] As in Figure 3 As best seen in FIG. 2 , semiconductor die 201 includes a base semiconductor substrate 310 and a plurality of buildup layers 312 located above a top surface of base semiconductor substrate 310. In certain example embodiments, base semiconductor substrate 310 is a high-resistivity silicon substrate (e.g., a silicon substrate having a bulk resistivity in the range of approximately 1000 ohm / cm to approximately 100,000 ohm / cm or greater). Alternatively, base semiconductor substrate 310 may be a semi-insulating gallium arsenide (GaAs) substrate (e.g., a silicon substrate having a bulk resistivity of up to 10 8 ohm / cm) or another suitable high resistivity substrate. In still other alternative embodiments, the base semiconductor substrate 310 can be any of a variety of variations of a GaN substrate or other III-V semiconductor substrate.

[0084] The plurality of stacked layers 312 may include, for example, a plurality of interleaved dielectric layers, patterned conductive layers, and other conductive structures (e.g., conductive polysilicon structures). Portions of the different patterned conductive layers and structures are electrically coupled with conductive vias (e.g., via 332). Additionally, conductive through substrate vias (TSVs) (e.g., TSV 348) may provide a conductive path between the top and bottom surfaces of the base semiconductor substrate 310. The TSVs may or may not be lined with a dielectric material to insulate the TSVs from the base semiconductor substrate 310. According to one embodiment, the conductive layer 328 on the bottom surface of the base semiconductor substrate 310 serves as a ground node for the Doherty IC 200. Although Figure 3 Not shown, but as Figure 6 As indicated, when the Doherty IC 200 is ultimately packaged, the conductive layer 328 may be physically and electrically coupled to a package substrate (eg, Figure 6 flange 630) of the grounding node.

[0085] In the following description of Doherty IC 200, reference will be made to various circuits including capacitors, inductors, and / or resistors. In various embodiments, the capacitors may be, for example, integrated metal-insulator-metal (MIM) capacitors formed within buildup layer 312 and / or small chip capacitors (discrete capacitors) coupled to the top surface of die 201. The resistors may be, for example, integrated resistors (e.g., formed from polysilicon within buildup layer 312) or small discrete resistors coupled to the top surface of die 201. The inductors may be integrated spiral inductors (e.g., formed from patterned conductive layers and vias within buildup layer 312), or they may be discrete inductors or inductors formed from wire bonds or other inductive components.

[0086] exist Figure 2 and 3 In the embodiment of the present invention, each of the main amplifier 220 and the peaking amplifier sections 240', 240" includes a cascade arrangement of two power transistors, including relatively low power driver amplifier transistors 226, 246', 246" (e.g., Figure 1 driver amplifiers 126, 146', 146") and relatively high power final amplifier transistors 230, 250', 250" (e.g., Figure 1 150"). In other embodiments, the driver amplifier transistors 226, 246', 246" may be excluded, and the main amplifier 220 and peaking amplifier sections 240', 240" may include only the high power final amplifier transistors 230, 250', 250". The description herein refers to each transistor including a control terminal and two conduction terminals. For example, using terminology associated with FETs, "control terminal" refers to the gate terminal of the transistor, and the first and second conduction terminals refer to the drain and source terminals of the transistor (or vice versa). Although the following description may use terminology commonly used in connection with FET devices, the various embodiments are not limited to implementations utilizing FET devices, but are intended to also apply to implementations utilizing bipolar junction transistor (BJT) devices or other suitable types of transistors.

[0087] Each transistor 226, 246', 246", 230, 250', 250" includes a gate terminal 225, 229, 245', 245", 249', 249" (or control terminal), a drain terminal 227, 231, 247', 247", 251', 251" (or first current-carrying terminal) and an uncoded source terminal (or second current-carrying terminal). In a specific embodiment, each transistor 226, 246', 246", 230, 250', 250" is an LDMOS FET, which includes an active region disposed between the gate terminal and the drain terminal. Each active region includes a plurality of elongated, parallel-aligned and intersecting drain regions and source regions, wherein each drain region and each source region is a doped semiconductor region formed in the base semiconductor substrate 310. Due to their elongated shape, each set of adjacent drain and source regions and associated gate structures may be referred to as a "transistor finger," and each transistor 226, 246', 246", 230, 250', 250" includes multiple parallel transistor fingers within the active region of the transistor (in the FIG. Figure 2 indicated by a vertical line).

[0088] A variable conduction channel (and, in some embodiments, a drain drift region) exists between adjacent source and drain regions. A conductive (e.g., polysilicon or metal) gate structure formed on the base semiconductor substrate 310 is coupled to each gate terminal 225, 229, 245', 245", 249', 249" above the channel region and extends from each gate terminal 225, 229, 245', 245", 249', 249" along the channel region. Similarly, another conductive (e.g., polysilicon) drain structure formed on the base semiconductor substrate 310 is coupled to each drain terminal 227, 231, 247', 247", 251', 251" above the drain region and extends from each drain terminal 227, 231, 247', 247", 251', 251" along the drain region. The source region is electrically coupled to a conductive (e.g., polysilicon or metal) source contact, which in turn is coupled to a conductive TSV (e.g., TSV) extending through the base semiconductor substrate 310 to connect with the conductive layer 328 on the bottom surface of the base semiconductor substrate 310. Figure 3 During operation, a voltage applied to gate terminals 225, 229, 245', 245", 249', 249" modulates the conductivity of the variable conduction channel, thereby enabling current to flow between the source and drain regions (or ultimately between conductive layer 328 and each drain terminal 227, 231, 247', 247", 251', 251").

[0089] The circuitry integrated within and coupled to the Doherty IC 200 will now be described in greater detail. Figure 2 , is configured to receive an input RF signal for amplification at an input terminal 202 (eg, Figure 1 The input node 102 of the power splitter 204 is electrically connected to the splitter input 205 (e.g., Figure 1 Input 105). Input 202 may include, for example, a conductive bonding pad exposed at the top surface of die 201 and configured for attachment of one or more wire bonds (e.g., Figure 6 Alternatively, die 201 may be a flip-chip die, or the input terminals may be exposed on the bottom surface of die 201, in which case input terminals 202 may consist of conductive pads or other types of connections. These alternative configurations may also apply to other terminals of Doherty IC 200 (e.g., terminals 271, 271′, and 284).

[0090] Power splitter 204 (eg, Figure 1 The power splitter 104 is configured to split the power of the input RF signal received at the input terminal 205 into the main part and the peaking part of the input signal, and pre-amplify the main part and the peaking part of the input signal. Figure 1 As described, because the peaking amplifier is implemented using two peaking amplifier sections 240′, 240″, the power splitter 204 has three branches and is configured to split the power of the input RF signal received at the input terminal 202 into one main portion of the input signal and two peaking portions of the input signal. The main portion of the input signal and the peaking portion of the input signal are each pre-amplified along the three power splitter branches. Essentially, the power splitter includes the same number of branches as the number of amplification paths. Therefore, in an alternative embodiment in which the peaking amplifier is implemented using only a single amplifier path, the power splitter may include only two branches (e.g., as in Figure 5B in the embodiment of FIG.

[0091] In the embodiment shown, the main input signal is output at the power splitter output 206 (e.g., Figure 1 106) and the peaked input signal is generated at the power splitter outputs 207 and 208 (e.g., Figure 1 As previously described, the power splitter 204 can divide the power and preamplify the power equally or unequally depending on the relative sizes of the main amplifier 220 and the peaking amplifier sections 240', 240". Figure 2 In the embodiment of FIG. 1 , the main amplifier section 220 and the peaking amplifier sections 240 ′, 240 ″ are approximately equal in size (i.e., the three amplifiers 220 , 240 ′, 240 ″ have a 1:1:1 size relationship, and the Doherty amplifier is an asymmetric amplifier with a main-to-peak ratio of 1:2), and thus the power splitter 204 divides the input RF signal such that approximately one-third of the pre-amplified input signal power is produced at each power splitter output 206 - 208 . In other embodiments, the main amplifier 220 and the peaking amplifier sections 240 ′, 240 ″ may be unequal in size, in which case the power splitter 204 may produce amplified RF signals having unequal powers.

[0092] In one embodiment, input 205 has an input impedance of 50 ohms, but the input impedance may be less than or greater than 50 ohms. According to one embodiment, power splitter 204 has a Wilkinson-based design with active elements (e.g., power transistors), and power splitter 204 substantially splits and preamplifies the power of an input signal received at input 205 into three preamplified signals of equal phase at outputs 206-208.

[0093] According to one embodiment, the power splitter 204 is formed by a combination of a preamplifier transistor and a delay element coupled to passive components that are integrally formed in and / or coupled to the Doherty IC 200. In a more specific embodiment, the power splitter 204 is a three-branch splitter, where each splitter branch (e.g., Figure 4 、 5A The branches 401-403, 501-503) have a preamplifier coupled to a regulating element. The regulating element may correspond to a transmission line with a suitable electrical length, a CLC (capacitor-inductor-capacitor) topology, or a combination thereof, as will be described in more detail later. The components of the regulating element may be configured to have optimized gain, power added efficiency (PAE), and Figure 4 、 5AThe impedance and phase of the electrical isolation between the splitter branches 401-403, 501-503 of the present invention. In order to increase the electrical isolation between the splitter branches 401-403, 501-503, the power splitter 404, 504 can be configured so that each branch has an equal delay relative to another of the other branches 401-403, 501-503. In other words, when the first combined phase delay of the first branch (e.g., 401, 501) is close to the second combined phase delay of the second branch (e.g., 402, 502), the electrical isolation between the branches can be increased. The first combined delay corresponds to the sum of the first phase delay of the first amplifier (e.g., 423, 523) and the second phase delay of the first regulating element (e.g., 412, 512) of the first branch (e.g., 401, 501). Similarly, the second combined phase delay corresponds to the sum of the third phase delay of the second amplifier (eg, 439", 539") and the fourth phase delay of the second adjustment element (eg, 414", 514") of the second branch (eg, 402, 502).

[0094] In an exemplary embodiment, electrical isolation can be substantially achieved by configuring each splitter branch 401-403, 501-503 to have a combined phase delay of approximately 90 degrees. Assuming, for example, that the amplifiers of each splitter branch 401-403, 501-503 are of the same size, they have approximately the same phase delay of 55 degrees. In this illustration, each splitter branch 401-403, 501-503 can be configured to have the same phase by utilizing an adjustment element with a phase delay of 35 degrees (a total phase delay of 90 degrees for each splitter branch). Electrical isolation between the splitter branches 401-403, 501-503 can also be achieved by configuring paired splitter branches (e.g., 401 and 403; 401 and 402; 402 and 403) to have a sum at or near 180 degrees, so that each splitter branch is at least substantially out of phase with each other, and thus electrically isolated. Such summation is illustrated by the path pairs 408, 408', and 408", respectively, shown in FIG. 4. Figure 2 、 4 The power splitters 204, 404 and 504 of 5A can provide advantages over conventional power splitters having only passive components (e.g., inductors, capacitors and / or resistors) because the multi-segment topology of the power splitters 204, 404 and 504 can provide pre-amplification for single-stage or multi-stage amplifiers (e.g., Doherty amplifiers) with better broadband response than conventional single-segment power splitters.

[0095] Figure 4 and 5AAn integrated signal splitter 404, 504 (eg, Figure 1 、 2 The splitter 404, 504 includes a splitter input 405, 505 (eg, a splitter input 405, 505) configured to receive an input RF signal. Figure 1 、 2 105, 205), and coupled between the input terminals 405, 505 and the splitter output terminals 406, 506, 407, 507, 408, 508 (e.g., Figure 1 、 2 The three splitter branches 401-403, 501-503 between the outputs 106-108, 206-208).

[0096] As in Figure 4 and 5A As can be seen in the figure, each branch 401-403, 501-503 of the splitter 404, 504 may include a filter circuit (each filter circuit including, for example, an inductor 520, 530, 540 and a capacitor 522, 532, 542), a preamplifier 423, 439', 439", 523, 539', 539" and a regulating element 412, 414', 414", 512, 514', 514". Isolation resistors 452-453, 552-553 are coupled between the branches 401-403, 501-503. Figure 5A Each preamplifier 523, 539', 539" shown in FIG. 5 may correspond to one or more transistor fingers (referred to herein as transistor fingers 523, 539', 539"). Figures 5B-5E As described in more detail in the description of FIG, each transistor finger can be configured as a FET having a gate terminal, a drain terminal, and a source terminal. Within each branch 501-503, a filter circuit 519 (including inductors 520, 530, 540 and capacitors 522, 532, 542) is coupled between the splitter input terminal 405, 505 and one or more gate terminals of one or more transistor fingers corresponding to the preamplifier 523, 539', 539".

[0097] Each of the filter circuits provided by inductors 520, 530, 540 and capacitors 522, 532, 542 can function as a low-pass filter, a band-pass filter, or a high-pass filter and / or an input impedance matching circuit for a signal applied at the splitter input 505. Although not shown, the pre-driver amplifiers 423, 439', 439" can utilize a similar Figure 5A534, 536 of branch 502, or CLCs 545, 544, 546 of branch 503). It should be understood that the values ​​of the inductors 520, 530, 540 and the capacitors 522, 532, 542 of each of the filter circuits of filter 519 may vary between the filter circuits. In one embodiment, the capacitors 522, 532, 542 may be implemented solely based on the inherent capacitance of the gate terminals of the preamplifiers 523, 539', 539". In another embodiment, the capacitors 522, 532, 542 may be implemented based on the inherent capacitance of the gate terminals of the preamplifiers 523, 539', 539". Figure 5A ) is implemented by a combination of methods (not shown) to adjust the capacitance to a desired value.

[0098] In one embodiment, the adjustment elements 412, 414', 414", 512, 514', 514" are configured to take into account the phase delay and output impedance of each pre-driver amplifier 423, 439', 439", 523, 539', 539" to at least partially achieve impedance matching with the output of each pre-driver amplifier 423, 439', 439", 523, 539', 539" and equal (or substantially equal) phase at the output of the splitter branches 401-403, 501-503. Specifically, when all pre-driver amplifiers 423, 439', 439", 523, 539', 539" impart the same delay to the signals amplified by the preamplifiers, the adjustment elements 412, 414', 414", 512, 514', 514" can each also impart the same delay to those signals (which may or may not be the same as the adjustment elements 412, 414', 414", 512, 514', 514") to ensure that the cumulative delay applied by each branch 401-403, 501-503 is substantially equal. Conversely, when one or more of the pre-driver amplifiers 423, 439', 439", 523, 539', 539" impart different delays from one another, then the adjustment elements 412, 414', 414", 512, 514', 514" may impart different delays to ensure that the cumulative delay applied through each branch 401-403, 501-503 is substantially equal.

[0099] Each inductor (e.g. Figure 5A Inductors 520, 524, 530, 534, 540, 544) shown in FIG can be implemented, for example, as a stacked layer (eg, Figure 3 2. The integrated spiral inductor 520, 524, 530, 534, 540, 544 is formed by patterning a conductive layer and vias within the buildup layer 312 of the die. In alternative embodiments, some or all of the inductors 520, 524, 530, 534, 540, 544 can be implemented as discrete inductors or a wire bond array coupled to the top surface of the die 201. When the center operating frequency fo of the Doherty IC 200 is approximately 2.0 gigahertz (GHz), the inductance value of each of the inductors 520, 524, 530, 534, 540, 544 can be in the range of approximately 4 nanohenries (nH) to approximately 9 nH, although the center operating frequency and / or inductance values ​​can also be lower or higher. Other inductance values ​​and center operating frequencies fo are also contemplated by the present disclosure.

[0100] Capacitors 525, 535, 545 represent parasitic drain-source capacitances of preamplifier transistors 523, 539', 539", and are therefore not actual physical components. Instead, in various embodiments, each of capacitors 522, 526, 532, 536, 542, 546 may be a built-up layer (e.g., Figure 3 21 and / or small chip capacitors (discrete capacitors) coupled to the top surface of die 201. According to one embodiment, each capacitor 510, 526, 536, 546 is a parallel capacitor whose bottom electrode is connected using a capacitor extending through the base semiconductor substrate (e.g., Figure 3 substrate 310) to a conductive layer (eg, Figure 3 3. The capacitors 510, 522, 526, 532, 536, 542, and 546 are coupled to a ground reference by through-substrate vias (TSVs) through layer 328 of the amplifier. When the center operating frequency of the amplifier is approximately 2.0 GHz, the capacitance value of each of capacitors 510, 522, 526, 532, 536, 542, and 546 can be in the range of approximately 0.5 picofarads (pF) to approximately 1.5 pF, although the center operating frequency and / or capacitance values ​​can be lower or higher. Other capacitance values ​​and center operating frequencies f are also contemplated by the present disclosure.

[0101] Also refer to Figure 4 and 5A In one embodiment, and as will be described in more detail below, each power splitter 404, 504 also includes a plurality of resistors (e.g., Figure 4 、 5AThe resistors 452-453, 552-553 may be, for example, integrated resistors (e.g., Figure 3 、 5B 582, 587, 592, 597) or coupled to the top surface of the die 201 or substrate 582, 587, 592, 597. The resistance value of each of the resistors 452-453, 552-553 can be in the range of about 50 ohms to about 250 ohms, but lower or higher resistance values ​​are possible.

[0102] Starting at the splitter input 405, 505, a first shunt capacitor 410, 510 is electrically coupled between the input 405, 505 and the distribution nodes 409, 509 of the three branches 401-403, 501-503. Each splitter branch 401-403, 501-503 may be a three section branch with input impedance matching and / or filter sections.

[0103] although Figure 4 4. Although not shown, parallel capacitor 410 may be coupled to the input impedance matching and / or filter section in each of branches 401-403, respectively. In one embodiment, the input impedance matching and / or filter section may be included in pre-driver amplifiers 423, 439', 439". Adjustment elements 412, 414', 414" may be implemented as transmission lines having an electrical length to achieve a combined phase delay of each of splitter branches 401-403, the combined phase delay satisfying the impedance matching of the pre-driver amplifier output and the electrical isolation between paths 408, 408', 408" as previously discussed. Alternatively, as Figure 5A As shown in FIG, the adjustment elements 412, 414', 414" can be implemented with CLC circuits that provide desired impedance matching and delay to achieve gain, PAE, and electrical isolation conditions between the paths 408, 408', 408". Each adjustment element 412, 414', 414" has a first end coupled to the drain terminal of the pre-driver amplifier 423, 439', 439" and a second end coupled to the output terminals 406-408. To provide additional isolation between the splitter branches 401-403, resistors 452-453 can be coupled between the output terminals 406-408.

[0104] exist Figure 5AIn an embodiment of the present invention, the filter 519 can be implemented as an impedance matching network (in a CLC or π-type topology) that is coupled to amplifiers 523, 539', 539", respectively, which are in turn coupled to CLC circuits 512, 514', 514" connected in series between the splitter input 505 and the splitter outputs 506-508. The first section of each branch 501-503 includes a first shunt capacitor 510, a first inductor 520, 530, 540, and a second shunt capacitor 522, 532, 542 (the second shunt capacitor 522, 532, 542 may simply correspond to the inherent gate capacitance of the amplifier 523, 539', 539", or based on the gate capacitance of the amplifier 523, 539', 539". Figure 5A 515 ). Each first inductor 520, 530, 540 has a first end coupled to the input terminal 505 (or the distribution node 509) and a second end coupled to the inter-segment node 511, 513, 515. Each second shunt capacitor 522, 532, 542 is electrically coupled between the inter-segment node 511, 513, 515 and the ground reference. The second segment of each branch 501-503 includes an amplifier 523, 539', 539", which includes a control (gate) terminal coupled to the inter-segment node 511, 513, 515, a drain terminal coupled to the CLC circuit 512, 514', 514", and a source terminal coupled to the ground reference.

[0105] like Figure 5A As shown, the CLC circuit section corresponding to the regulating elements 512, 514', 514" is defined by the second parallel capacitors 525, 535, 545 coupled to the ground reference, the second inductors 524, 534, 544 coupled to the ground reference, and the third parallel capacitors 526, 536, 546. The second parallel capacitors 525, 535, 545 may simply correspond to the inherent drain capacitance of the amplifiers 523, 539', 539" or based on the capacitance of the amplifiers 523, 539', 539". Figure 5AEach second inductor 524, 534, 544 has a first end coupled to the drain terminal of the amplifier 523, 539', 539" and a second end coupled to the output terminals 506-508. Each third parallel capacitor 526, 536, 546 is electrically coupled between the output terminals 506-508 and the ground reference. According to one embodiment, the inductance value of each first inductor 520, 530, 540 is significantly greater (e.g., greater than between approximately 10% and 100%) than that of each second inductor 524, 534, 544. In alternative embodiments, the first and second inductors may have substantially the same inductance value, or the inductance value of each second inductor 524, 534, 544 may be significantly greater than that of each first inductor 520, 530, 540.

[0106] although Figure 4 and 5A A multi-section splitter 404, 504 is depicted that may include three splitter sections (CLC, amplifier, CLC) in each branch 401-403, 501-503, but alternative embodiments may include more than three (e.g., four or more) sections or less than three (e.g., two) sections in each branch 501-503. Additionally, other alternative embodiments including a single peaking amplifier may include only two branches (e.g., one branch for the main amplifier and one branch for the single peaking amplifier), such as in conjunction with Figure 5B Still other alternative embodiments including more than two peaking amplifier sections (or more than one split peaking amplifier) ​​may include more than three branches (e.g., one branch for the main amplifier and one branch for each peaking amplifier or peaking amplifier section). Figure 4 and 5A A particular integrated signal splitter configuration is depicted, but in other embodiments, other types or configurations of signal splitters may be used.

[0107] Figure 5B 、 5C , 5D, and 5E depict pre-driver amplifiers 580, 585, 590, 595 implemented using various transistor finger configurations (e.g., Figure 4 and 5A 4. In order to simplify the embodiment of the pre-driver amplifier 423, 439', 439", 523, 539', 539") of the power splitter 404, 504. Figure 4 and 5A Illustration of various configurations of pre-driver amplifiers, Figures 5B-5E Not depicted Figure 4 and5A The embodiment of the regulating element or input filter circuit shown in FIG. The regulating element or input filter circuit can be easily included in the embodiment of the regulating element or input filter circuit shown in FIG. Figures 5B-5E The pre-driver amplifier shown is on the same die as or with Figures 5B-5E The preamplifiers 580, 585, 590, and 595 are interconnected on separate dies. With this in mind, each of the preamplifiers 580, 585, 590, and 595 is integrally formed in a semiconductor substrate 582, 587, 592, and 597 (e.g., silicon, GaN, or other suitable substrates). The preamplifiers 580, 585, 590, and 595 have multiple gate manifolds, each corresponding to one or a combination of the splitter inputs. The preamplifiers 580, 585, 590, and 595 also have multiple drain manifolds, each coupled to a corresponding regulating element.

[0108] The preamplifier 580 has a drain manifold 572 corresponding to the first amplifier output ( 100 Ω ) coupled to the regulating element 512 and a drain manifold 573 . Figure 5A path 501), the regulating element 512 can be configured to couple to the main amplifier path ( Figure 5B ), the drain manifold 573 corresponds to the coupling to the regulating element 514 'or 514 "(see Figure 5A ) of the second amplifier output ( Figure 5A The regulating element 514' or 514" may be configured to couple to a peaking amplifier path (not shown). The preamplifiers 585, 590, 595 have drain manifolds 575, 576, 578, 579, 584, 586 and drain manifolds 574, 577, 583, the drain manifolds 575, 576, 578, 579, 584, 586 can correspond to the first amplifier output and the second amplifier output (paths 502 and 503 of Figure 5A) respectively coupled to the corresponding adjustment elements 514", 514', the adjustment elements 514", 514' can be configured to be coupled to the corresponding first peaking amplifier path and the second peaking amplifier path (not shown), the drain manifolds 574, 577, 583 can correspond to the third amplifier output coupled to the adjustment element 512, the adjustment element 512 can be configured to be coupled to the main amplifier path (not shown).

[0109] In some embodiments, the preamplifiers 582, 587, 592, 597 may be integrally formed in the same semiconductor substrate as the multipath amplifier to which the splitter is coupled (e.g., Figure 2In other embodiments, the preamplifiers 580, 585, 590, 595 may be formed in a separate semiconductor substrate independent of the substrate of the multipath amplifier, wherein the separate semiconductor substrate is directly coupled to the multipath amplifier semiconductor substrate or packaged as a surface mount device coupled to the multipath amplifier semiconductor substrate. Figures 5B-5E The diagram does not show Figure 4 and 5A To achieve equal phase between the splitter branches 401-403, 501-503, the regulating elements 412, 414', 414", 512, 514', 514" can be configured to couple to the transistor fingers of the regulating elements 412, 414', 414", 512, 514', 514" with appropriate phase delay and impedance matching characteristics. Figures 5B-5E The output (drain manifold) end of the transistor finger.

[0110] Figure 5B-5B Each transistor finger (555, 556, 556', 557, 558, 558', 560, 561, 561', 561", 562, 563, 563', 563") in E includes a gate terminal 511, 513, 515 (or a control terminal), a drain terminal 572', 573', 573", 574', 575', 576', 577', 578', 578", 579', 583', 584', 584", 586' (or a first current-carrying terminal), and an unnumbered and unillustrated source terminal (or a second current-carrying terminal). In a specific embodiment, each transistor finger 555, 556, 556', 557, 558, 558', 560, 561, 561', 561", 562, 563, 563 ′ and 563 ″ are both LDMOS FETs, which include an active region disposed between a gate terminal and a drain terminal. As previously described, each active region includes a plurality of elongated, parallel-aligned, and intersecting drain and source regions, wherein each drain region and each source region is a doped semiconductor region formed in a base semiconductor substrate.

[0111] A variable conduction channel (and, in some embodiments, a drain drift region) exists between adjacent source and drain regions. A conductive (e.g., polysilicon or metal) gate structure formed on a base semiconductor substrate is coupled to each gate terminal 511, 513, 515 above the channel region and extends from each gate terminal 511, 513, 515 along the channel region. Similarly, an additional conductive (e.g., polysilicon) drain structure formed over the base semiconductor substrate is coupled to each drain terminal 572′, 573′, 573″, 574′, 575′, 576′, 577′, 578′, 578″, 579′, 583′, 584′, 584″, 586′ over the drain region and extends from each drain terminal 572′, 573′, 573″, 574′, 575′, 576′, 577′, 578′, 578″, 579′, 583′, 584′, 584″, 586′ along the drain region. The source region is electrically coupled to a conductive (e.g., polysilicon or metal) source contact, which in turn is coupled to a conductive TSV extending through the base semiconductor substrate to connect with a conductive layer on the bottom surface of the base semiconductor substrate. During operation, the voltage applied to the gate terminals 511, 513, 515 modulates the conductivity of the variable conduction channel, thereby enabling current to flow between the source region and the drain region (or ultimately between the conductive layer on the bottom surface and each drain terminal 572', 573', 573", 574', 575', 576', 577', 578', 578", 579', 583', 584', 584", 586'). Figures 5B-5E In the embodiment, the gate terminals of transistor fingers 556, 556', 561, 561', 563, 563' are electrically connected together, while the gate terminals of transistor fingers 555, 557, 558, 558', 560, 561", 562, 563" are electrically isolated from each other and from transistor fingers 556, 556', 561, 561', 563, 563'.

[0112] exist Figure 5B In FIG. 5 , the drain terminal 572′ of the finger 555 is connected to the first drain manifold 572, and the drain terminals 573′, 573″ of the fingers 556 and 556′ are electrically connected to the second drain manifold 573, which is electrically isolated from the first drain manifold 572. Figure 5BIn the embodiment of FIG. 5 , each of transistor fingers 555, 556, and 556' has the same size (or length or periphery). Therefore, each of transistor fingers 555, 556, and 556' provides the same level of signal amplification. Because the drain terminals 573' and 573" of fingers 556 and 556' are electrically connected to drain manifold 573, during operation, the signal power at drain manifold 573 (which is provided to the peaking amplifier path) is approximately twice the signal power at drain manifold 572 (which is provided to the main amplifier path).

[0113] exist Figure 5C , the drain terminal 574′ of finger 557 is connected to the first drain manifold 574, and the drain terminals 575′ and 576″ of fingers 558 and 558′ are electrically connected to the second drain manifold 575 and the third drain manifold 576, which are electrically isolated from the first drain manifold 574 and each other. Figure 5C In the embodiment of FIG. 5 , each of transistor fingers 557 , 558 , and 558 ′ has the same size (or length or periphery). Thus, each of transistor fingers 557 , 558 , and 558 ′ provides the same level of signal amplification. Because drain terminals 575 ′ and 576 ′ of fingers 558 and 558 ′ are electrically connected to drain manifolds 575 and 576 , respectively, during operation, the combined signal power at drain manifolds 575 and 576 (which is provided to the corresponding peaking amplifier paths) is approximately twice the signal power at drain manifold 574 (which is provided to the main amplifier path).

[0114] exist Figure 5D , the drain terminal 577' of finger 560 is connected to a first drain manifold 577, and the drain terminals 578', 578", and 579' of fingers 561, 561', and 561" are electrically connected to a second drain manifold 578 and a third drain manifold 579, respectively, which are electrically isolated from the first drain manifold 577 and from each other. Figure 5DIn an embodiment, each of the transistor fingers 560, 561, 561', 561" has the same size (or length or periphery). Therefore, each of the transistor fingers 560, 561, 561', 561" provides the same level of signal amplification. Because the drain terminals 578', 578", 579' of the fingers 561, 561', 561" are electrically connected to the drain manifolds 578 and 579, respectively, during operation, the combined signal power at the drain manifolds 578 and 579 (the combined signal power is provided to the corresponding peaking amplifier paths) is approximately three times the signal power at the drain manifold 577 (the signal power is provided to the main amplifier path).

[0115] exist Figure 5E , the drain terminal 583' of the finger 562 is connected to the first drain manifold 583, and the drain terminals 584', 584", and 586' of the fingers 563, 563', and 563" are respectively electrically connected to the second drain manifold 584 and the third drain manifold 586, which are electrically isolated from the first drain manifold 583 and from each other. Figure 5E In an embodiment, the size and amplification of transistor fingers 562, transistor fingers 563, 563' (having the same size or length or periphery), and transistor finger 563" are different from each other. In one embodiment, the combination of transistor fingers 563, 563' is three times the size of transistor finger 562 and six times the size of transistor finger 563", thereby providing a signal amplification ratio of 6:2:1.

[0116] In an asymmetric Doherty amplifier configuration as previously described, the size of the peaking amplification path can be larger (i.e., higher current carrying capacity) than the size of the main amplification path. For example, a Doherty amplifier having a peak-to-main power ratio of 2:1 has a peaking amplification path that is twice the size of the main amplification path. To achieve a 2:1 ratio in a Doherty amplifier having a single peaking path that is twice the size of the main amplification path, the power splitters 404, 504 can be configured to use Figure 5BIn this configuration, the main splitter branch (e.g., 401-501) of the power splitter 404, 504 can utilize one or more first transistor fingers (e.g., transistor finger 555) to supply a first portion (e.g., one-third) of the input signal power to the main amplification path of the Doherty amplifier, while the peaking splitter branch (e.g., 402-502 or 403-503) of the power splitter 404, 504 can utilize one or more second transistor fingers (e.g., transistor fingers 556, 556') to supply a second portion (e.g., two-thirds) of the input signal power to the single peaking amplification path of the Doherty amplifier.

[0117] To achieve a 2:1 ratio in a Doherty amplifier having separate peaking paths that together add up to twice the size of the main amplification path, the power splitters 404, 504 may be configured using Figure 5C 1:1:1 finger transistor ratio. In this configuration, the main splitter branch (e.g., 401-501) of the power splitter 404, 504 can utilize one or more first transistor fingers (e.g., transistor finger 557) to supply a first portion (e.g., one-third) of the input signal power to the main amplification path of the Doherty amplifier. Additionally, the first peaking branch (e.g., 402-502) of the power splitter 404, 504 can utilize one or more second transistor fingers (e.g., transistor finger 558) to supply a second portion (e.g., one-third) of the input signal power to the first peaking amplification path of the Doherty amplifier, while the second peaking branch (e.g., 403-503) of the power splitter 404, 504 can utilize a single transistor finger 558' to supply one-third of the input signal power to the second peaking amplification path of the Doherty amplifier.

[0118] The power splitters 404, 504 can be used Figures 5D-5E Finger transistors of the embodiment of the present invention can be used to support other asymmetric Doherty amplifier configurations with power ratios such as 2:1:1 and 6:2:1, respectively. For example, an asymmetric Doherty amplifier can be configured with split peaking amplification paths in which one peaking amplification path is twice the size of the other peaking amplification path and twice the size of the main amplification path (thus, having a power ratio of 2:1:1). To achieve a 2:1:1 asymmetric Doherty amplifier, the main splitter branches 401, 501 of the power splitters 404, 504 can be configured with Figure 5D, to supply one-quarter of the input signal power to the main amplification path. Similarly, a first peaking splitter branch 402, 502 can be configured to use a single transistor finger 561" to supply one-quarter of the input signal power to the smaller peaking amplification path of the Doherty amplifier, while another peaking splitter branch 403, 503 can be configured to use a dual transistor finger 561, 561' (with a shared output (drain) terminal) to provide half of the input signal power to the larger peaking amplification path. Utilizing similar principles, the splitter branches 401-501, 402-502, 403-503 of the power splitter 404, 504 can be configured to use finger transistors 562, 563, 563', 563" to support an asymmetric Doherty configuration with a power ratio of 6:2:1.

[0119] Figures 5F-5G Depicted are diagrams according to example embodiments. Figure 4 and 5A An alternative embodiment of a power splitter. Figure 5F A passive Wilkinson separator 460 is incorporated at the input of the active separator 470. In this configuration, the two resistors R1 of the passive Wilkinson separator 460 are used to provide isolation between the branches 401-403 of the passive Wilkinson separator 460. The passive Wilkinson separator 460 can be configured so that path 461 has a total phase of 180 degrees (90 degrees of branch 402 plus 90 degrees of branch 403), which causes the branches 402-403 of the passive Wilkinson separator 460 to be out of phase and thus electrically isolated. Similarly, the passive Wilkinson separator 460 can be configured so that path 461 'has a total phase of 180 degrees (90 degrees of branch 402 plus 90 degrees of branch 401), which causes the branches 401 and 402 of the passive Wilkinson separator 460 to be out of phase and thus electrically isolated. Likewise, the passive Wilkinson splitter 460 can be configured such that path 461″ has a total phase of 180 degrees (90 degrees for branch 401 plus 90 degrees for branch 403), which causes branches 401 and 403 of the passive Wilkinson splitter 460 to be out of phase and, thereby, electrically isolated. The passive Wilkinson splitter 460 can also be configured to at least partially match the impedance of the input 405. The capacitors shown in the passive Wilkinson splitter 460 can represent the gate capacitance of each of the amplifiers 423, 439′, and 439″, respectively.

[0120] Turning to the active separator 470, two resistors 452-453 provide isolation between the branches 401-403 of the active separator 470. Path 408 of the active separator 470 has a total phase of 180 degrees (90 degrees for branch 402 plus 90 degrees for branch 403), which causes the branches 402-403 of the active separator 470 to be out of phase and thus electrically isolated. Similarly, path 408' has a total phase of 180 degrees (90 degrees for branch 402 plus 90 degrees for branch 401), which causes the branches 401 and 402 of the active separator 470 to be out of phase and thus electrically isolated. Likewise, path 408" has a total phase of 180 degrees (90 degrees for branch 401 plus 90 degrees for branch 403), which causes the branches 401 and 403 of the active separator 470 to be out of phase and thus electrically isolated. Figure 5F The embodiment shows a passive configuration and an active configuration Figure 4 Active splitter 470 also provides isolation between paths and improved broadband frequency response. The active splitter's tuning elements 412, 414', 414" can be configured to at least partially match the impedance of the outputs of amplifiers 423, 439', 439" and add a phase delay that achieves a 180-degree phase in paths 408, 408', 408" to maintain isolation between batches 401, 402, 403.

[0121] Go to Figure 5G In this embodiment, the gate terminals 511, 513, and 515 of amplifiers 523, 539', and 539" are electrically connected together. Capacitors 522, 532, and 542 can represent the gate capacitances of amplifiers 523, 539', and 539", respectively. Inductor 520 can represent a wire bond to a shared gate terminal. The combination of capacitor 510, inductor 520, and parallel capacitors 522, 532, 542 can form a CLC filter 519', which can be configured to match the input impedance at input 505. Figure 5G The remaining components shown in Figure 5A FIG5H depicts a comparison of Figure 4 and 5A FIG. 5 is a graph showing the performance of the power splitters 404 and 504 and the passive splitter. Figure 5H (1) shows Figure 4 and 5A The power splitter 404, 504 may be configured to have 20 dB more gain (eg, 554) than a passive splitter (eg, 552) at approximately -5 dB. Figure 5H(2) It is further shown that the power splitters 404, 504 can have electrical isolation (e.g., 558) between the output ends of the main amplification paths 401-501 and the peaking amplification paths 402-403, 502-503, which is similar to the electrical isolation (e.g., 556) of the output ends of the main path and peaking path of the passive splitter. Figure 5H (3) also shows that the input to output electrical isolation of the illustrated power splitter 404, 504 at approximately -27 dB is improved by approximately 22 dB (eg, 562) compared to the input to output electrical isolation of the passive splitter (eg, 560) at approximately -5 dB. Figure 5H (4) The power splitters 404, 504 are further shown to have electrical isolation (eg, 566) between the peaking amplification paths 402-403, 502-503 that is similar to the electrical isolation (eg, 564) between the peaking amplification paths of the passive splitter.

[0122] Reference again Figure 2 , the output 206 of the power splitter 204 (e.g., Figure 4 、 5A The outputs 406, 506 of the power splitter 204 are electrically connected to the input 221 of the main amplifier 220 through conductive paths implemented in the stacking layer 312 of the Doherty IC 200. According to one embodiment, the outputs 207, 208 of the power splitter 204 (e.g., Figure 4 、 5A The outputs 407, 507, 408, 508) are passed through the input phase delay circuits 209', 209" (e.g., Figure 1 The input phase delay circuits 109′, 109″ and additional conductive paths implemented in the stacking layer 312 of the Doherty IC 200 are electrically connected to the inputs 241′, 241″ of the peaking amplifier sections 240′, 240″. The input phase delay circuits 209′, 209″ are configured to ensure that the peaking input signals at the inputs 241′, 241″ of the peaking amplifier sections 240′, 240″ have a phase difference of approximately 90 degrees with the main input signal at the input 221 of the main amplifier 220.

[0123] In one embodiment, each of the main amplifier 220 and the peaking amplifier sections 240 ′, 240 ″ can have a substantially similar configuration. According to one embodiment, each amplifier 220 , 240 ′, 240 ″ is a two-stage amplifier that includes a relatively low-power driver amplifier 226 , 246 ′, 246 ″ (or a driver amplifier FET) and a relatively high-power final stage amplifier 230 , 250 ′, 250 ″ (or a final stage amplifier FET) connected in a cascade arrangement between the amplifier input 221 , 241 ′, 241 ″ and the combining node structure 290 .

[0124] In the main amplifier 220, the input 221 of the amplifier 220 is connected to the input impedance matching network 222 (e.g., Figure 1 The IMN 122 of the embodiment of the present invention is coupled to the input terminal 225 (e.g., gate terminal) of the driver amplifier FET 226, and the output 227 (e.g., drain terminal) of the driver amplifier FET 226 is connected to the input terminal 225 (e.g., gate terminal) of the driver amplifier FET 226 through the inter-stage impedance matching network 228 (e.g., Figure 1 The ISMN 128 of the embodiment of the present invention is electrically coupled to the input terminal 229 (e.g., the gate terminal) of the final amplifier FET 230. Similarly, in each of the peaking amplifier sections 240', 240", the input 241', 241" of the amplifier 240', 240" ... Figure 1 The IMNs 142', 142") are coupled to input terminals 245', 245" (e.g., gate terminals) of driver amplifier FETs 246', 246", and outputs 247', 247" (e.g., drain terminals) of the driver amplifier FETs 246', 246" are coupled to the input terminals 245', 245" (e.g., gate terminals) of the ...". Figure 1 The ISMNs 148′, 148″ are electrically coupled to input terminals 249′, 249″ (e.g., gate terminals) of the final amplifier FETs 250′, 250″. The source terminals of each of the FETs 226, 230, 246′, 246″, 250′, 250″ are electrically coupled to a ground reference (e.g., electrically connected to the bottom conductive layer 328 of FIG. 3 through the base semiconductor substrate 310 using TSVs).

[0125] In one embodiment, each driver amplifier FET 226, 246', 246" may be of equal size and may be configured to apply gain to a corresponding input RF signal in a range of approximately 15 decibels (dB) to approximately 25 dB when the Doherty IC 200 is operating in a high power mode (e.g., near compression), but only the driver amplifier FET 226 provides gain to its input signal when the Doherty IC 200 is operating in a low power mode. The final stage amplifier FETs 230, 250', 250" are significantly larger than the driver amplifier FETs 226, 246', 246" (e.g., at least twice as large to apply at least twice the gain). In one embodiment, each final amplifier FET 230, 250', 250" may also be of equal size, and each final amplifier FET 230, 250', 250" may be configured to apply gain to a corresponding input RF signal in the range of approximately 15 dB to approximately 25 dB when the Doherty IC 200 is operating in a high power mode (e.g., near compression), but only the final amplifier FET 230 provides gain to its input signal when the Doherty IC 200 is operating in a low power mode.

[0126] According to one embodiment, the gate bias voltage of each of the FETs 226, 230, 246', 246", 250', 250" is divided by a resistor-divider gate bias circuit 270, 270', 270" (e.g., Figure 1 The resistor-divider gate bias circuits 170, 170', 170") are provided. As previously described, for proper operation of the Doherty amplifier IC 200, the main amplifier 220 is biased to operate in Class AB mode, and the peaking amplifier sections 240', 240" are typically biased to operate in Class C mode. In some configurations, the peaking amplifier sections 240', 240" may be biased to operate in Class B or deep Class B mode. Because the biasing of the main amplifier 220 is different from the peaking amplifier sections 240', 240", the main amplifier resistor-divider gate bias circuit 270 is different from (and not electrically connected to) the peaking amplifier resistor-divider gate bias circuits 270', 270". However, because the biasing of the peaking amplifier sections 240', 240" is the same as one another, the peaking amplifier resistor-divider gate bias circuits 270', 270" may be identical and electrically connected together, as shown. Figure 2 As shown in the embodiment.

[0127] In the illustrated embodiment, the main amplifier resistor-divider gate bias circuit 270 includes an input 271, resistors 273, 274, and RF isolation circuits 275, 276. Similarly, the peaking amplifier resistor-divider gate bias circuits 270', 270" each include an input 271', resistors 273', 273", 274', 274", and RF isolation circuits 275', 275", 276', 276". In addition to the gate bias circuits 270, 270', 270", the Doherty amplifier IC 200 may also include one or more drain bias circuits 282. According to one embodiment, drain bias circuit 282 includes input terminal 284 and RF isolation circuits 286, 286', 286". The output of each of the final amplifier FETs 230, 250', 250" (ie, drain terminal 231, 251', 251") is electrically connected to a combined node structure 290 (eg, Figure 1 The combining node structure 290 is used to combine the amplified RF signals generated by each of the final amplifier FETs 230, 250', 250" into a single amplified output RF signal.

[0128] Combined node structure 290 includes an elongated conductive bond pad exposed at the top surface of die 201. According to one embodiment, the length of combined node structure 290 extends from an outer end 252' of the drain terminal 251' of the peaking amplifier final stage FET 250' to an outer end 252" of the drain terminal 251" of the peaking amplifier final stage FET 250". Figure 2 As shown in FIG, combined node structure 290 has three sections including a leftmost section electrically connected to drain terminal 251' of peaking amplifier final stage FET 250', a center section electrically connected (via wire bond 238) to drain terminal 231 of main amplifier final stage FET 230, and a rightmost section electrically connected to drain terminal 251" of peaking amplifier final stage FET 250". According to one embodiment, combined node structure 290 is a continuous conductive bond pad, but combined node structure 290 may also include discontinuous but electrically connected sections.

[0129] Desirably, the drain terminals 251′, 251″ are connected to the combined node structure 290 using a conductive path having a negligible phase delay (i.e., a phase delay as close to zero degrees as possible, such as a phase delay of 10 degrees or less), and in some embodiments, the drain terminals 251′, 251″ may be an integrally formed part of the combined node structure 290. In other words, in some embodiments, the drain terminal manifolds of the peaking amplifier final stage FETs 250′, 250″ may form part of the combined node structure 290. As previously described, the base semiconductor substrate 310 is a high-resistivity substrate, and thus, in the Doherty amplifier IC 200, the potentially high losses that would otherwise occur with relatively long transmission lines (such as in conjunction with the node structure 290) on a relatively low-resistivity substrate are significantly reduced.

[0130] As previously described, to compensate for the 90 degree phase delay difference between the main amplification path and the peaking amplification path at the inputs of amplifiers 220, 240', 240" (i.e., to ensure that the amplified signals are combined in phase at combining node structure 290), output phase delay circuit 236 (e.g., Figure 1 The output phase delay circuit 236 (e.g., the output phase delay circuit 236) is electrically coupled between the output (i.e., the drain terminal 231) of the main amplifier final stage FET 230 and the output (i.e., the drain terminals 251', 251) of the peaking amplifier final stage FETs 250', 250". Specifically, the output phase delay circuit 236 is configured to generate a phase difference substantially equal to 90 degrees (i.e., 90 degrees + / - 10 degrees) between the RF signal at the drain terminal 231 of the main amplifier final stage FET 230 and the RF signal at the drain terminals 251', 251" of the peaking amplifier final stage FETs 250', 250".

[0131] According to one embodiment, the output phase delay circuit 236 has a CLC (capacitor-inductor-capacitor) topology between the drain terminal 231 and the drain terminals 251 ′, 251 ″. The first (parallel) capacitor includes the drain-source capacitance C of the main amplifier final stage FET 230. dsM. A plurality of wire bonds 238 are electrically connected between the drain terminal 231 of the main amplifier final stage FET 230 and a combined node structure 290. More specifically, a first end of the wire bond 238 is connected to the drain terminal 231, and a second end of the wire bond 238 is connected to the combined node structure 290. The inductance in the CLC topology of the output phase delay circuit 236 is provided by the series combination of the wire bonds 238 and the portion of the combined node structure 290 that extends between the landing point of the wire bond 238 on the structure 290 and the drain terminals 251 ′, 251 ″ of the peaking amplifier final stage FETs 250 ′, 250 ″. According to one embodiment, the series combination of the wire bonds 238 and those portions of the combined node structure 290 has a combined inductance of about 0.8 nH to about 1.2 nH at a center operating frequency of about 2.0 GHz, although the center frequency and / or combined inductance can also be lower or higher.

[0132] Finally, the second (parallel) capacitance in the CLC topology of the output phase delay circuit 236 is approximately equal to the combined drain-source capacitance C of the peaking amplifier final stage FETs 250', 250". dsP Subtract the shunt inductance (e.g. Figure 7 The parallel inductor 750) compensates the C dsP In summary, the 90-degree phase difference between the drain terminal 231 and the drain terminals 251', 251" is provided by the output phase delay circuit 236 having a CLC topology, wherein the topology includes a first parallel capacitor (composed of C dsM ), a series inductance (provided by wire bonds 238 and portions of combined node structure 290), and a second shunt capacitance (provided by A×C dsP Provided, where A<1.0).

[0133] The Doherty power amplifier IC 200 can be packaged and / or incorporated into a larger electrical system in various ways. For example, the Doherty IC 200 can be packaged in an overmolded package or an air cavity power device package (e.g., Figure 6 Alternatively, the Doherty IC 200 can be packaged in a surface mount package, such as a leadless package (e.g., a dual flat no-lead (DFN) or quad flat no-lead (QFN) package). In still other embodiments, the Doherty IC 200 can be mounted directly to the surface of a module or PCB substrate.

[0134] By way of example, Figure 6 is a top view of a Doherty amplifier device 600 according to an example embodiment, the Doherty amplifier device 600 including a Doherty IC 602 (eg, Figure 2The package 604 includes a plurality of conductive input signal and bias leads 610-616 and at least one output lead 620. The input signal and bias leads 610-616 are positioned on the input side of the package 604, and the at least one output lead 620 is positioned on the output side of the package 604. In one embodiment, the input side (e.g., Figure 2 The input side 210 of the device package 604 is close to and parallel to the input side of the device package 604.

[0135] Additionally, package body 604 includes a package substrate, such as conductive flange 630, to which Doherty IC 602 is physically and electrically connected (e.g., using conductive epoxy, solder, brazing, sintering, or other conductive connection methods). Finally, package body 604 includes non-conductive structural features or materials, such as molding compound and / or other insulating materials, that hold leads 610-616, 620 and flange 630 in a fixed orientation relative to one another.

[0136] Conductive connections such as conductive wire bonds 650-656 electrically connect the input signal and bias voltage bond pads (or terminals) on the die 602 to the conductive leads 610-616 on the input side of the device 600. For example, one or more first wire bonds 650 may electrically connect the input RF signal lead 610 to a terminal corresponding to an input terminal (e.g., Figure 2 The first bonding pad of the input terminal 202) and the input RF signal lead 610 can be used to transmit the input RF signal to the Doherty IC 602.

[0137] According to one embodiment, the output of the Doherty IC 602 (and more specifically, Figure 2 The combined node structure 290 of the die 602 is electrically connected to the output lead 620 via a plurality of wire bonds 670. According to one embodiment, the package body 604 is designed such that when the die 602 is coupled to the package body 604, the die 602, and more specifically, the combined node structure of the die 602, can be positioned very close to the output lead 620. Therefore, the wire bonds 670 can be relatively short. In addition, the number of wire bonds 670 can be selected to be relatively large (e.g., 20-40 wire bonds, or more or less), which makes the wire bonds 670 relatively low parasitic inductance elements. According to one embodiment, the inductance value of the wire bonds 670 is in the range of about 20 pH to about 70 pH (e.g., about 60 pH), although the inductance value can be smaller or larger. Desirably, the wire bonds 670 are designed such that the inductance value of the wire bonds 670 is as low as possible.

[0138] In some embodiments, the leads 610-616, 620 and the flange 630 may form part of a lead frame. To complete the overmolded package during device fabrication, after attaching the die 602 and the wire bonds 650-656, 670, the die 602, the inner ends of the leads 610-616, 620, the wire bonds 650-656, 670, and the upper and side surfaces of the flange 630 may be sealed (in a non-conductive (e.g., plastic) molding compound 640, 642. Figure 6 6, 620 project from the perimeter of the device 600 and the top surface of the device 600. The bottom surface of the device 600 is defined in part by the molding compound 640 and in part by the bottom surface of the flange 630. Thus, when properly coupled to a system substrate (e.g., Figure 7 PCB 710), the flange 630 can serve (e.g., by Figure 3 The bottom conductive layer 328 of the device 600 serves to deliver the ground reference to the die 602 and may also act as a heat sink for the device 600.

[0139] In a similar but different embodiment, having Figure 6 The leads 610-616, 620 of the configuration shown in FIG can be replaced with the pads of a leadless package. The flange 630 and pads can again form a leadframe to which the die 602 and wire bonds 650-656, 670 are attached, and the assembly can again be sealed with a non-conductive molding compound to form a leadless surface mount device (e.g., a DFN or QFN device).

[0140] In other embodiments, the package 604 can be an air cavity package. In this embodiment, the flange 630 can have a larger perimeter that is equal to or approximately equal to the perimeter of the device 600. A non-conductive insulator (e.g., ceramic, plastic, or another material) having a frame shape can be attached to the top surface of the flange, leads 610-616, 620 can be placed on the non-conductive insulator, wire bonds 650-656, 670 can be attached, and a cap (not shown) can be placed over the frame opening to enclose the internal components of the device 600 in the air cavity.

[0141] Ultimately, the Doherty amplifier arrangement 600 is incorporated into a larger electrical system (e.g., a power transmitter array in a cellular base station). Figure 7 As shown in FIG, the Doherty amplifier device 720 (eg, Figure 6 The device 600) can be incorporated into the amplifier system 700.

[0142] In one embodiment, the amplifier system 700 includes a single-layer or multi-layer PCB 710 and a plurality of components coupled to the PCB 710. For example, the amplifier system 700 may include conductive coins 715 (or other features) exposed on the top and bottom surfaces of the PCB 710, and Doherty amplifier devices 720 (e.g., Figure 6 More specifically, the bottom surface of the Doherty amplifier device 720 (e.g., Figure 6 The bottom of the flange 630 of the amplifier system 700 can be physically and electrically connected to the top surface of the conductive coin 715. The conductive coin 715 can, in turn, be electrically connected to the system ground, and the bottom surface of the coin 715 can be connected to the system heat sink. Thus, the conductive coin 715 can serve as a ground reference and a heat sink for the amplifier system 700.

[0143] In a typical configuration, the amplifier system 700 includes an input RF connector 701 and an output RF connector 702, each configured to receive an input RF signal from an RF signal source and generate an amplified output RF signal for transmission (e.g., via a cellular antenna coupled to the connector 702). One or more bias voltage connectors 703, 704 may be used to receive a DC bias voltage from one or more voltage sources.

[0144] Additionally, amplifier system 700 includes a plurality of conductive paths and features 730-736 electrically coupled between connectors 701-703 and Doherty amplifier device 720. Conductive paths and features 730-736 may be formed from patterned portions of the top conductive layer, the bottom conductive layer, and / or one or more inner conductive layers of PCB 710, if included.

[0145] The first conductive path 730 electrically connects the input RF connector 701 to the input RF signal lead 722 (eg, Figure 6 During operation of the system 700, the input RF signal received by the input RF connector 701 is transmitted to the input RF signal lead 722 via the first conductive path 730. Similarly, the second conductive path 731 electrically connects the output RF connector 702 to the output RF signal lead 728 (e.g., Figure 6 During operation of the system 700 , the amplified RF signal generated by the Doherty amplifier device 720 is transmitted to the output RF connector 702 via the second conductive path 731 .

[0146] Additional conductive paths 732, 733, 734 electrically connect the bias voltage connector 703 to a plurality of bias voltage leads 724 (eg, Figure 6 During operation of system 700, multiple drain and gate DC bias voltages are delivered to bias voltage leads 724 via conductive paths 732-734. On the output side, conductive path 735 electrically connects bias voltage connector 704 to output RF signal lead 728 (e.g., directly or via path 731, as shown). Figure 7 During operation of system 700, the drain DC bias voltage of the final amplifier is transmitted to output RF signal lead 728 through bias voltage connector 704, conductive path 735, and output RF signal lead 728.

[0147] According to one embodiment, amplifier system 700 further includes a shunt inductor 750 electrically coupled between output RF signal lead 728 and further conductive feature 736. Shunt inductor 750 can be, for example, a discrete inductor having a first end coupled to output RF signal lead 728 (e.g., directly or via path 731, as shown in FIG7 ) and a second end coupled to conductive feature 736, which in turn is electrically coupled to system ground. In one embodiment, shunt inductor 750 is configured to at least partially absorb the drain-source capacitance of one or more peaking amplifier final stage transistors (e.g., Figure 2 The drain-source capacitance C of the peaking amplifier final stage FETs 250' and 250" dsP In an alternative embodiment, all or a portion of the shunt inductance provided by shunt inductor 750 may instead be provided by designing an optimized conductive path 735 between bias voltage connector 704 and output RF signal lead 728, in which case shunt inductor 750 may be omitted. Although conventional asymmetric Doherty amplifier systems may include a shunt inductor for this purpose, the shunt inductor typically needs to be implemented inside the amplifier package (e.g., inside device 720). However, according to various embodiments, the output wire bonds (e.g., Figure 6 The relatively low inductance of the wire bonds 670 enables the shunt inductor to be moved outside the amplifier package. This can reduce the amplifier package size while also facilitating easier tuning of the system 700, as the size of the shunt inductor 750 can be modified without redesigning the Doherty amplifier arrangement 720.

[0148] Figure 8A is a manufacturing method for a Doherty power amplifier IC (e.g., Figure 2Doherty IC200), packaged Doherty amplifier devices (e.g., Figure 6 600) and a Doherty amplifier system (e.g., Figure 7 In block 802, the method may form an amplifier die (e.g., Figure 2 Starting with die 201 ), the amplifier die includes integrally formed main amplifier transistors (eg, Figure 2 FETs 226, 230), peaking amplifier transistors (e.g., Figure 2 FETs 246', 246", 250', 250") and combined node structures (e.g., Figure 2 290). Additionally, forming the amplifier die may include integrally forming a pre-driver amplifier transistor (e.g., Figure 4 、 5A Amplifiers 423, 439', 439", 523, 539', 539") of the power splitter (e.g., Figure 2 Splitter 204), matching network (eg, Figure 2 IMN 222, 242', 242", ISMN 228, 248', 248"), bias circuit (e.g., Figure 2 In alternative embodiments, some of the circuits and components in the previous sentence (eg, power splitter 204) may be implemented on a substrate other than the amplifier die.

[0149] In block 804, the main amplifier final stage transistors (e.g., Figure 2 FET 230) output terminal (e.g., Figure 2 The drain terminal 231 of Figure 2 The combined node structure 290) completes the Doherty amplifier IC (e.g., Figure 2 For example, a Doherty amplifier IC 200 may be provided with wire bonds having a predetermined length, height, and number (e.g., Figure 2 The connections are made using wire bonds 238 of the embodiment to produce a desired phase delay (e.g., 90 degrees) between the main amplifier output and the peaking amplifier output.

[0150] Then, in block 806, the Doherty amplifier IC (e.g., Figure 2As previously mentioned, the Doherty amplifier IC can be packaged in an overmolded package or an air cavity power package. Alternatively, the Doherty amplifier IC can be attached to a system substrate (e.g., a module or PCB substrate) in bare die form. When packaged in an overmolded package (e.g., Figure 6 604), the Doherty amplifier IC can be connected to the conductive flange of the lead frame, wire bonding (e.g., Figure 6 Wire bonds 650-656, 670) can be coupled between the input, output, and bias leads of the lead frame and appropriate bond pads of the Doherty amplifier IC, and the flange, leads, and Doherty amplifier IC can be encapsulated in the molding compound. When packaged in an air cavity package, an insulator frame can be attached to the top surface of the conductive flange, the Doherty amplifier IC can be connected to the top surface of the flange in the frame opening, the input, output, and bias leads can be connected to the top surface of the insulator frame, and the wire bonds (e.g., Figure 6 Wire bonds 650-656, 670) can be coupled between the input, output, and bias leads and appropriate bond pads of the Doherty amplifier IC, and a cap can be applied over the flange, insulator frame, leads, wire bonds, and Doherty amplifier IC to enclose the Doherty amplifier IC in the air cavity.

[0151] In block 808, the Doherty amplifier device (e.g., Figure 6 The device 600) (or in some embodiments, a bare die) is attached to a system substrate, such as a PCB (e.g., Figure 7 PCB 710) to complete the amplifier system (e.g., Figure 7 More specifically, the bottom surface of the Doherty amplifier device can be connected to a conductive coin (e.g., Figure 7 coin 715) to provide a ground reference and heat sink for the device, and can connect the input, output, and bias leads of the device to corresponding conductive paths of the system substrate (e.g., Figure 7 Path 730-734).

[0152] According to one embodiment, in block 810, additional components may be coupled to the system substrate (e.g., Figure 7 PCB 710) to complete the amplifier system. For example, as previously described, by coupling the inductor to the conductive features of the system substrate (e.g., Figure 7 path 731 and feature 736), a discrete inductor (e.g., Figure 7 The inductor 750 is coupled to the output lead of the Doherty amplifier device (e.g., Figure 7728) and a ground reference. Additionally, a metal cover or shield connected to the ground plane of the PCB may be used to fully or partially cover the components of PCB 710 to provide electrical isolation from other devices in other systems. The method may then end.

[0153] Figure 8B is a manufacturing method for a power splitter IC (e.g., Figure 1 The power separator 104, Figure 2 Power separator 204, Figure 4 Power splitter 404, Figure 5A In block 822, the method may begin by forming a power splitter die including an integrally formed input matching network (e.g., Figure 5A 519, the integrally formed input matching network may be optional), a pre-driver amplifier transistor (eg, Figure 4 、 5A FETs 423, 439', 439", 523, 539', 539"), regulating elements (e.g., Figure 4 、 5A transmission lines or CLCs 412, 414', 414", 512, 514', 514") and isolation resistors (e.g., Figure 4 、 5A 452-453, 552-553). Additionally, forming the power splitter die may include integrally forming bias circuitry coupled to the pre-driver amplifier transistors 423, 439', 439", 523, 539', 539". In alternative embodiments, some of the circuits and components (e.g., the input matching network) may be implemented on a different substrate than the power splitter die.

[0154] In block 824, the power splitter IC (e.g., Figure 4 、 5A power splitter ICs 404, 504) to produce electrically isolated splitter branches (e.g., Figure 4 、 5A401-403, 501-503) of the desired generated branch phase (e.g., 90 degrees). In box 826, the power splitter IC can then be packaged. Similar to the Doherty amplifier IC, the power splitter IC can be packaged in an overmolded package or an air cavity power package. Alternatively, the power splitter IC can be attached to a system substrate (e.g., a module or PCB substrate) in the form of a bare die. When packaged in an overmolded package, the power splitter IC can be connected to the conductive flange of the lead frame, wire bonds can be coupled between the input, output and bias leads of the lead frame and the appropriate bonding pads of the power splitter IC, and the flange, leads and power splitter IC can be sealed in the molding material. When packaged in an air cavity package, an insulator frame can be attached to the top surface of the conductive flange, the power splitter IC can be connected to the top surface of the flange in the frame opening, the input, output and bias leads can be connected to the top surface of the insulator frame, wire bonds can be coupled between the input, output and bias leads and appropriate bonding pads of the power splitter IC, and a lid can be applied over the flange, insulator frame, leads, wire bonds and power splitter IC to enclose the power splitter IC in the air cavity.

[0155] The power splitter system can be completed by attaching the power splitter device (or in some embodiments, the bare die) to a system substrate such as a PCB in block 828. More specifically, the bottom surface of the power splitter device can be connected to a conductive coin to provide a ground reference and heat sink for the device, and the input, output, and bias leads of the device can be connected to corresponding conductive paths of the system substrate.

[0156] According to one embodiment, additional components may be coupled to the power splitter system substrate in block 830. For example, the output of the power splitter system substrate may be coupled to a single-stage or multi-stage amplifier, such as a Doherty amplifier device that does not have an integrally formed power splitter. The method may then end.

[0157] Embodiments of a power splitter may include a power amplifier and a corresponding adjustment element. The power splitter may be located on a single die or combined with a multipath amplifier (e.g., a Doherty amplifier) ​​on the same die. The power splitter may include multiple power splitter branches, each of which may be configured to couple to the input of the multipath amplifier. Each power splitter branch includes a pre-driver amplifier and an adjustment element. In order to achieve the desired phase delay and impedance matching characteristics for coupling to the pre-driver amplifier output, the adjustment element may include a transmission line with a suitable electrical length, a lumped element delay circuit, a combination of the two, or other suitable delay circuits. In addition, the adjustment element may also be configured to provide impedance matching characteristics for coupling to the input path of the multipath amplifier device. The pre-driver amplifier of each splitter branch may be a single-stage amplifier or a multi-stage amplifier, which may be configured to couple to a single-stage amplifier path or a multi-stage amplifier path of a multipath amplifier device (e.g., a Doherty amplifier device).

[0158] The pre-driver amplifier in each power splitter branch can have symmetrical or asymmetrical gain relative to the pre-driver amplifier of other splitter branches. In addition, each pre-driver amplifier in each power splitter branch can be configured for a specific frequency band, or the scope of frequency band can be identical or different with the frequency band or frequency band range of the pre-driver amplifier of other splitter branches. In addition, each pre-driver amplifier can be configured with an input filter circuit and / or a matching network circuit for being coupled to the RF input source. In order to increase the electrical isolation between the power splitter branches, each branch can be configured to have similar or substantially equal phase delay (for example, 90 degrees or other suitable delays). Isolation impedance can also be added between the power splitter branches to increase the electrical isolation between this type of branches in addition.

[0159] Embodiments of a multi-branch splitter may include a semiconductor die, a radio frequency (RF) signal input, a first splitter branch, and a second splitter branch. Embodiments of the first splitter branch may include a first amplifier and a first regulating element integrally formed with the semiconductor die. A first gate terminal of the first amplifier may be coupled to the RF signal input, and a first drain terminal of the first amplifier may be coupled to a first input of the first regulating element. The second splitter branch may include a second amplifier and a second regulating element integrally formed with the semiconductor die. A second gate terminal of the second amplifier may be coupled to the RF signal input, and a second drain terminal of the second amplifier may be coupled to a second input of the second regulating element. The first splitter branch has a first combined phase delay based on at least a combination of a first phase delay of the first amplifier and a second phase delay of the first regulating element. The second splitter branch has a second combined phase delay based on at least a combination of a third phase delay of the second amplifier and a fourth phase delay of the second regulating element. The first splitter branch is substantially electrically isolated from the second splitter branch based on the first combined phase delay being substantially equal to the second combined phase delay. In one embodiment, the first combined phase delay may be substantially equal to the second combined phase delay when the phase offset between the first and second combined phase delays is + / -10% or less. The present disclosure contemplates other phase offset ranges that may be less than or greater than + / - 10%. In one embodiment, the first splitter branch and the second splitter branch may be configured to split the RF signal and amplify the input power level of the RF signal when the RF signal is applied to the RF signal input according to an amplification ratio that may be symmetrical or asymmetrical.

[0160] An embodiment of a multipath amplifier may include a semiconductor substrate, a first splitter branch, a second splitter branch, and a first amplification path and a second amplification path. The first splitter branch may include a first pre-driver amplifier integrally formed on the semiconductor substrate. A first gate terminal of the first pre-driver amplifier may be coupled to an RF signal input. The second splitter branch may include a second pre-driver amplifier integrally formed on the semiconductor substrate. A second gate terminal of the second pre-driver amplifier may be coupled to the RF signal input. The first amplification path may be integrally formed on the semiconductor substrate and may be further coupled to a first output of the first splitter branch. The second amplification path may be integrally formed on the semiconductor substrate and may be coupled to a second output of the second splitter branch. In one embodiment, when an RF signal is applied to the RF signal input, the first splitter branch may provide a first pre-amplification level of the RF signal to generate a first amplified signal supplied to the first amplification path. The second splitter branch may provide a second pre-amplification level of the RF signal to generate a second amplified signal supplied to the second amplification path. By configuring the first splitter branch and the second splitter branch to have similar phase delays, electrical coupling between the first splitter branch and the second splitter branch may be significantly reduced. In one embodiment, a similar phase delay can be achieved when the phase offset between the first splitter branch and the second splitter branch is + / - 10% or less.This disclosure contemplates other phase offset ranges that may be less than or greater than + / - 10%.

[0161] In one embodiment, a power splitter can be manufactured according to a method. The method may include forming a first splitter branch and a second splitter branch on a semiconductor substrate. The first splitter branch may include a first amplifier and a first regulating element integrally formed with the semiconductor substrate. A first gate terminal of the first amplifier may be coupled to an RF signal input, and a first drain terminal of the first amplifier may be coupled to a first input of the first regulating element. The second splitter branch may include a second amplifier and a second regulating element integrally formed with the semiconductor substrate. A second gate terminal of the second amplifier may be coupled to the RF signal input, and a second drain terminal of the second amplifier may be coupled to a second input of the second regulating element. Based on the first splitter branch and the second splitter branch having substantially similar phase delays, the first splitter branch is substantially electrically isolated from the second splitter branch. In one embodiment, substantially similar phase delays can be achieved when the phase offset between the first splitter branch and the second splitter branch is + / -10% or less. The present disclosure contemplates other phase offset ranges that may be less than or greater than + / -10%.

[0162] The connecting lines shown in the various drawings included herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of this theme. In addition, some terms may also be used for reference only and are therefore not intended to be restrictive in this article, and the numerical terms of the terms "first", "second" and other such structures do not imply sequence or order unless context clearly indicates.

[0163] As used herein, a "node" refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise differentiated, even if the signals are received or output at a common node).

[0164] The foregoing description refers to elements, nodes, or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element is directly, and not necessarily mechanically, joined to another element (or is in direct communication with another element). Similarly, unless expressly stated otherwise, "coupled" means that one element is directly or indirectly, and not necessarily mechanically joined to another element (or is in direct or indirect communication with another element, either electrically or otherwise). Thus, although the schematic diagrams shown in the accompanying drawings depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in the embodiments of the depicted subject matter.

[0165] As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or example is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

[0166] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it will be understood that there are a large number of variations. It will also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing one or more of the described embodiments to those skilled in the art. It will be understood that various changes may be made to the function and arrangement of elements without departing from the scope defined by the claims, including known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. A multi-branch separator, characterized in that: include: semiconductor die; Radio frequency RF signal input terminal; first and second splitter outputs; a first splitter branch comprising a first amplifier and a first regulating element integrally formed with the semiconductor die and coupled in series, wherein the first amplifier comprises a first field effect transistor (FET) formed from one or more elongated first transistor fingers, a first gate terminal of the first amplifier coupled to the RF signal input, and wherein a first drain terminal of the first amplifier is coupled to the first splitter output; a second splitter branch comprising a second amplifier and a second regulating element integrally formed with the semiconductor die and coupled in series, wherein the second amplifier comprises a second field effect transistor (FET) formed by one or more elongated second transistor fingers in parallel with the first transistor fingers, a second gate terminal of the second amplifier coupled to the RF signal input, and wherein a second drain terminal of the second amplifier is coupled to the second splitter output; wherein the first splitter branch has a first combined phase delay based at least on a combination of a first phase delay of the first amplifier and a second phase delay of the first regulating element, wherein the second splitter branch has a second combined phase delay based at least on a combination of a third phase delay of the second amplifier and a fourth phase delay of the second regulating element, and The first splitter branch and the second splitter branch are configured to split an RF signal and amplify an input power level of the RF signal according to an amplification ratio when the RF signal is applied to the RF signal input terminal.

2. The multi-branch separator according to claim 1, characterized in that: Also included is an isolation impedance, wherein a first end of the isolation impedance is coupled to a first output end of the first regulating element, wherein a second end of the isolation impedance is coupled to a second output end of the second regulating element, and wherein the isolation impedance increases isolation between the first splitter branch and the second splitter branch.

3. The multi-branch separator according to claim 1, characterized in that: The first adjustment element includes a transmission line having an electrical length that produces the second phase delay.

4. The multi-branch separator according to claim 3, characterized in that: The second adjustment element includes a transmission line having an electrical length that produces the fourth phase delay.

5. The multi-branch separator according to claim 1, characterized in that: The first adjustment element includes a lumped element delay circuit that produces the second phase delay.

6. The multi-branch separator according to claim 5, characterized in that: The second adjustment element includes a lumped element delay circuit that produces the fourth phase delay.

7. The multi-branch separator according to claim 1, characterized in that: The first combined phase delay is equal to 90 degrees.

8. The multi-branch separator according to claim 7, characterized in that: The second combined phase delay is equal to 90 degrees.

9. A method for manufacturing a separator, characterized in that: include: forming a first splitter branch on a semiconductor substrate, the first splitter branch comprising a first amplifier and a first regulating element integrally formed with the semiconductor substrate and coupled in series, wherein the first amplifier comprises a first field effect transistor (FET) formed by one or more elongated first transistor fingers, a first gate terminal of the first amplifier is coupled to an RF signal input terminal, wherein a first drain terminal of the first amplifier is coupled to a first splitter output terminal, and wherein the first splitter branch has a first combined phase delay based on at least a combination of a first phase delay of the first amplifier and a second phase delay of the first regulating element; and a second splitter branch formed on the semiconductor substrate, the second splitter branch comprising a second amplifier and a second regulating element integrally formed with the semiconductor substrate and coupled in series, wherein the second amplifier comprises a second field effect transistor (FET) formed by one or more elongated second transistor fingers in parallel with the first transistor fingers, a second gate terminal of the second amplifier is coupled to the RF signal input terminal, wherein a second drain terminal of the second amplifier is coupled to a second splitter output terminal, and wherein the second splitter branch has a second combined phase delay based on at least a combination of a third phase delay of the second amplifier and a fourth phase delay of the second regulating element, and The first splitter branch and the second splitter branch are configured to split an RF signal and amplify an input power level of the RF signal according to an amplification ratio when the RF signal is applied to the RF signal input terminal.

Images