Transistor semiconductor chip with increased active area

Abstract

A transistor semiconductor chip includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is above the drift layer. The first metallization layer is above the first dielectric layer, such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is above the first metallization layer. The second metallization layer is above the second dielectric layer, such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor chip is configured to selectively conduct current between the first contact pad and a third contact pad based on a signal provided at the second contact pad.

Description

Technical Field

[0001] The present disclosure relates to transistor devices, and in particular, to vertical transistor semiconductor chips with increased active area. Background Art

[0002] Power transistor devices are used to selectively transmit high currents and block high voltages. As defined herein, a power transistor device is a device configured to conduct a current of at least 0.5A in a forward conduction operating mode and to block a voltage of at least 100V in a blocking operating mode. Examples of power transistor devices include field effect transistors (FETs), metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), and insulated gate bipolar junction transistors (IGBTs). Power transistor devices are provided by one or more power transistor semiconductor chips. Power transistor semiconductor chips are typically provided as vertical transistor devices including a device region surrounded by an edge termination region. The device region refers to the area of ​​the power transistor semiconductor chip including one or more implants, i.e., electrically coupled to one or more electrodes for providing the selective current conduction and voltage blocking capabilities of the device. The edge termination region is provided to reduce the concentration of the electric field at the edge of the power transistor semiconductor chip and thereby prevent breakdown at low reverse voltages. The device region forms the active portion of the power transistor semiconductor chip, while the edge termination region forms the passive portion of the power transistor semiconductor chip. As defined herein, an area of ​​a semiconductor chip is "active" if that area of ​​the semiconductor chip is responsible for carrying current in the device when the device is in a conduction mode (e.g., the first or third quadrant of operation). Generally, because the total active area is directly proportional to the current carrying capacity, it is desirable to maximize the total active area of ​​a power transistor semiconductor chip. However, due to design constraints of conventional power transistor semiconductor chips, the portion of the device area dedicated to active area is limited. Accordingly, there is a need for power semiconductor chips with increased active area in their device area. Summary of the Invention

[0003] In one example, a transistor semiconductor chip includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is above the drift layer. The first metallization layer is above the first dielectric layer, such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is above the first metallization layer. The second metallization layer is above the second dielectric layer, such that at least a portion of the second metallization layer provides a second contact pad. The first plurality of electrodes are above a first plurality of regions in the drift layer and coupled to the first metallization layer. The second plurality of electrodes are above a second plurality of regions in the drift layer and coupled to the second metallization layer. The first plurality of regions and the second plurality of regions are configured such that the transistor semiconductor chip is configured to selectively conduct current between the first contact pad and a third contact pad based on a signal provided at the second contact pad. By providing the second metallization layer above the second dielectric layer, the total active area of ​​the transistor semiconductor chip can be increased.

[0004] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred examples in association with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0006] Figure 1 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0007] Figure 2 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0008] Figure 3 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0009] Figure 4 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0010] Figure 5 is a cross-sectional view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0011] Figure 6 is a cross-sectional view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0012] 7A to 7C is a graph showing performance of a transistor semiconductor chip according to various embodiments of the present disclosure.

[0013] Figure 8 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0014] Figure 9 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0015] Figure 10 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0016] Figure 11 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0017] Figure 12 is a top view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0018] Figure 13 is a cross-sectional view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0019] Figure 14 is a cross-sectional view of a transistor semiconductor chip according to one embodiment of the present disclosure.

[0020] Figure 15 is a cross-sectional view of a transistor semiconductor chip according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and illustrate the best mode for implementing the embodiments. When reading the following description in light of the accompanying drawings, those skilled in the art should understand the concepts of the present disclosure and recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0022] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0023] It should be understood that when an element such as a layer, region, or substrate is referred to as "on" another element or extends "onto" another element, it can be directly on another element or directly extend to another element or there can be an intermediate element. On the contrary, when an element is referred to as "directly on" another element or extends "directly onto" another element, there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "over" another element or extends "over" another element, it can be directly above another element or extend to directly above another element or there can be an intermediate element. On the contrary, when an element is referred to as "directly over" another element or extends to "directly over" another element, there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element or there can be an intermediate element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0024] As shown in the figures, relative terms such as "below" or "above", or "upper" or "lower", or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region. It will be understood that these terms, as well as those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0025] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that when used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or combinations thereof.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technical field and should not be interpreted in an idealized or excessive form of meaning, unless expressly defined herein.

[0027] Figure 1 A top view of a transistor semiconductor chip 10 according to one embodiment of the present disclosure is shown. For illustrative purposes, the transistor semiconductor chip 10 is a vertical metal oxide semiconductor field effect transistor (MOSFET) device including a passivation layer 12 having openings for a gate contact pad 14 and a plurality of source contact pads 16. The transistor semiconductor chip 10 is a vertical power device in which a drain contact pad (not shown) is located on the back side of the device. The gate contact pad 14 and the source contact pad 16 can be provided as a surface for coupling the transistor semiconductor chip 10 to an external circuit. Accordingly, the gate contact pad 14 and the source contact pad 16 can have a minimum size so that they are reliably connected. In one embodiment, the minimum size of the gate contact pad 14 and each source contact pad 16 is 0.4 mm 2 In various embodiments, the minimum size of the gate contact pad 14 and each source contact pad 16 may be 0.5 mm. 2 , 0.6mm 2 , 0.7mm 2 , 0.8mm 2 , 0.9mm 2 , and up to 1.0mm 2 .

[0028] Figure 2 A top view of a transistor semiconductor chip 10 is shown with the passivation layer 12 removed. Beneath the passivation layer 12 are a gate metal layer 18, a gate via bar 20 coupled to the gate metal layer 18, and a source metal layer 22. As discussed in more detail below, the gate metal layer 18, the gate via bar 20, and the source metal layer 22 are provided by the same metallization layer, and thus, the source metal layer 22 must include an opening 24 to accommodate the entire area of ​​the gate metal layer 18 and the gate via bar 20 as shown. Figure 2Also shown are a device region 26 and an edge termination region 28 of the transistor semiconductor chip 10. As discussed above, the device region 26 is a region of the transistor semiconductor chip 10 that includes one or more implants electrically coupled to one or more electrodes for providing the device's selective current conduction and voltage blocking capabilities. The edge termination region 28 is configured to reduce the concentration of electric fields at the edges of the transistor semiconductor chip 10 and thereby prevent breakdown at low reverse voltages.

[0029] Figure 3 A top view of a transistor semiconductor chip 10 is shown with the gate metal layer 18, gate via bars 20, source metal layer 22, and a number of other layers (discussed below) removed. Beneath these layers are a plurality of source regions 30 separated by a plurality of gate regions 32. The source regions 30 may be provided as regions having a different doping type and / or doping concentration than the drift layer in which they are located (e.g., via an epitaxial process separate from the drift layer or by implantation of the drift layer), while the gate regions 32 may be provided as regions in which the doping type and / or doping concentration of the drift layer is relatively unchanged or changed by different amounts. Figure 3 As shown in FIG, the gate region 32 is provided as a strip, however, it can also be Figure 4 The grid shown includes a gate region 32 . In order to provide the primary functionality of the transistor semiconductor chip 10 , the gate contact pad 14 must be in electrical contact with the gate region 32 , while the source contact pad 16 must be in electrical contact with the source region 30 .

[0030] Figure 5 A cross-sectional view of a portion of a transistor semiconductor chip 10 according to one embodiment of the present disclosure is shown. The transistor semiconductor chip 10 includes a substrate 34 and a drift layer 36 over the substrate 34. A plurality of implants 38 in the surface of the drift layer 36 provide a source region 30, while a plurality of non-implanted regions between the implants 38 provide a gate region 32. A plurality of gate electrodes 40 are disposed on the gate region 32 such that each gate electrode 40 extends between the implants 38 disposed on either side of the gate region 32. Each gate electrode 40 is separated from the surface of the drift layer 36 by an oxide layer 42. A plurality of source electrodes 44 are disposed on the source region 30 such that each source electrode 44 contacts a different implant 38. A gate metal layer 18 is disposed on the surface of the drift layer 36 such that the gate metal layer 18 is separated from the surface of the drift layer 36 by the oxide layer 42 and is coupled to the gate metal layer 18. Figure 5Each gate electrode 40 is formed on a plane not shown in the figure. In order to keep the gate electrodes 40 electrically isolated from the source electrodes 44, a dielectric layer 46 is provided over the gate electrodes 40. The source electrodes 44 are exposed at the surface of the dielectric layer 46. The source metal layer 22 is provided on the dielectric layer 46 so as to contact the source electrodes 44. The drain metal layer 48 is provided on the substrate 34 opposite to the drift layer 36.

[0031] like Figure 2 and Figure 5 As shown in , the source metal layer 22 and the gate metal layer 18 are arranged in a single metallization step (i.e., as a single metal layer that is appropriately patterned) within the device area 26 of the transistor semiconductor chip 10. This means that the source metal layer 22 and the gate metal layer 18 are arranged on the same surface / plane of the transistor semiconductor chip 10. Accordingly, the source metal layer 22 cannot overlap with the gate metal layer 18 and, instead, must include an opening for the gate metal layer 18. Due to the size constraints of the gate metal layer 18 (e.g., the minimum contact pad size for wire bonding), the footprint of the source metal layer 22 is thereby limited to within the device area 26 of the transistor semiconductor chip 10. As shown in Figure 5 As shown in FIG, the area below the source metal layer 22 is an active area where the drift layer 36 carries current from the source metal layer 22 to the drain metal layer 48. Because the drift layer 18 below the gate metal layer 18 cannot carry current, the area below the gate metal layer 18 is an inactive area. Accordingly, for a chip of a given size, the total active area of ​​the device region 26 and, thereby, the total current carrying capacity of the transistor semiconductor chip 10 may be limited.

[0032] Accordingly, Figure 6 A cross-sectional view of a transistor semiconductor chip 10 is shown according to additional embodiments of the present disclosure. Figure 6 The transistor semiconductor chip 10 shown in FIG. Figure 5 , but further includes an additional dielectric layer 50 above the dielectric layer 46. Specifically, the gate electrode 40 and the source electrode 44 are disposed on the surface of the drift layer 36, the dielectric layer 46 is disposed above the gate electrode 40 and the source electrode 44, so that the gate electrode 40 is electrically isolated from the source electrode 44 and the source electrode 44 is exposed at the surface of the dielectric layer 46, the source metal layer 22 is disposed above the dielectric layer 46, the additional dielectric layer 50 is disposed above the dielectric layer 46 and the source metal layer 22, and the gate metal layer 18 is disposed above the additional dielectric layer 50. The gate metal layer 18 is electrically coupled to the gate electrode 40 (connected to the gate electrode 40) via one or more vias 52 extending through the dielectric layer 46 and the additional dielectric layer 50. Figure 6). As shown, providing an additional dielectric layer 50 allows at least a portion of the gate metal layer 18 to overlap with the source metal layer 22. The one or more vias 52 are very small compared to the total area of ​​the gate metal layer 18. Accordingly, only very small openings are required in the source metal layer 22, and the total area covered by the source metal layer 22 is thereby increased. As discussed above, because the area below the source metal layer 22 is the active area of ​​the transistor semiconductor chip 10, this effectively increases the total active area and thereby increases the current carrying capacity of the transistor semiconductor chip. In fact, the total passive area of ​​the device region 26 of the transistor semiconductor chip 10 may be less than the total area of ​​the gate metal layer 18, and in some embodiments not previously implemented, less than the total area of ​​the gate contact pads 14.

[0033] For a given size, increasing the active area of ​​the transistor semiconductor chip 10 allows an increase in current carrying capacity. Alternatively, increasing the active area of ​​the transistor semiconductor chip 10 allows the size of the chip to be reduced without sacrificing current carrying capacity. This in turn allows additional chips to be provided for a given wafer when manufacturing the transistor semiconductor chip 10. Although the examples discussed herein primarily relate to transistor semiconductor chips 10 that provide MOSFET devices, the principles described herein are equally applicable to transistor semiconductor chips 10 that provide field effect transistor (FET) devices, bipolar junction transistor (BJT) devices, insulated gate bipolar transistor (IGBT) devices, or any other type of vertical transistor device with two or more top-level contacts. With this in mind, the gate contact pads 14 may be collectively referred to as first contact pads, the source contact pads 16 may be collectively referred to as second contact pads, the source metal layer 22 may be collectively referred to as a first metallization layer, the gate metal layer 18 may be collectively referred to as a second metallization layer, the source regions 30 may be collectively referred to as a first group of regions, and the gate regions may be collectively referred to as a second group of regions.

[0034] In one embodiment, the substrate 34 and the drift layer 36 are silicon carbide. The use of silicon carbide for the substrate 34 and the drift layer 36 can significantly increase the performance of the transistor semiconductor chip 10 when compared to conventional material systems such as silicon. Although not shown, the implant 38 can include several different implant regions as needed to provide selective current conduction and voltage blocking capabilities of the transistor semiconductor chip 10. The dielectric layer 46 and the additional dielectric layer 50 can include, for example, one or more layers of Al2O3 and SiO2 in an alternating manner. In other embodiments, the dielectric layer 46 and the additional dielectric layer 50 can include, for example, one or more layers of Si3N4 and SiO2 in an alternating manner. Generally, the dielectric layer 46 and the additional dielectric layer 50 can include any suitable dielectric material (e.g., a material having a wide bandgap (>~5 eV) and a relatively low dielectric constant). The dielectric layer 46 and the additional dielectric layer 50 can include the same or different materials. Additional passivation layers comprising Si3N4, Al2O3, AlN, SiO2, or any other suitable material may be interleaved with dielectric layer 46 and additional dielectric layer 50 as needed to prevent interaction between the materials. In various embodiments, passivation layer 12 may comprise Si3N4, Al2O3, AlN, SiO2, or any other suitable material.

[0035] Figure 7A 2 is a graph showing the improvement in the current carrying capacity of the transistor semiconductor chip 10 due to the movement of the gate metal layer 18 above the source metal layer 22. The solid line shows the improvement in the current carrying capacity of the transistor semiconductor chip 10 without the improvement. Figure 5 The relationship between the current carrying capacity and the size of the transistor semiconductor chip 10 in the case of the layout of the contact pads shown in FIG. The dotted line shows the relationship between the current carrying capacity of the transistor semiconductor chip 10 and the size of the transistor semiconductor chip 10 in the case of the layout of the contact pads shown in FIG. Figure 6 The same relationship between the improvements discussed above is shown. The graph assumes a constant rated blocking voltage (e.g., 1200 V). As shown, an improvement in the current carrying capacity of the transistor semiconductor chip 10 is achieved regardless of the chip size. As discussed above, this is due to the increase in the active area of ​​the device region 26.

[0036] Figure 7B 2 is a graph further illustrating the improvement in the current carrying capacity of the transistor semiconductor chip 10 due to the movement of the gate metal layer 18 above the source metal layer 22. The graph shows the percentage increase in the current carrying capacity of the transistor semiconductor chip 10 (compared to the percentage increase in the current carrying capacity of the transistor semiconductor chip 10 without the gate metal layer 18). Figure 5) and current rating. As shown, the percentage increase in current capacity of transistor semiconductor chip 10 has an inverse relationship with the current rating of transistor semiconductor chip 10. This is because as the current rating of transistor semiconductor chip 10 increases, its overall size also increases. Accordingly, the active area created as a result of moving gate metal layer 18 above source metal layer 22 makes up a smaller percentage of the total active area of ​​the device, thereby reducing the percentage increase in current carrying capacity seen by using these improvements. Figure 7B It is shown that the greatest improvement in device performance due to the improvements discussed herein is seen at lower current ratings.

[0037] Figure 7C 2 is a graph further illustrating the improvement in the current carrying capacity of the transistor semiconductor chip 10 due to the movement of the gate metal layer 18 above the source metal layer 22. The graph shows the percentage increase in the current carrying capacity of the transistor semiconductor chip 10 (compared to the percentage increase in the current carrying capacity of the transistor semiconductor chip 10 without the gate metal layer 18). Figure 5 ) versus voltage rating for the transistor semiconductor chip 10 with the improvements shown in FIG. As shown, the percentage increase in current carrying capacity of the transistor semiconductor chip 10 is positively correlated with the voltage rating of the transistor semiconductor chip 10. The graph shown assumes a constant size of the transistor semiconductor chip 10. The relationship between the percentage increase in current carrying capacity and the voltage rating stems from the fact that as the voltage rating of the transistor semiconductor chip 10 increases, the size of the edge termination region 28 also increases. Accordingly, the size of the device area 26 decreases, so that the active area resulting from the movement of the gate metal layer 18 above the source metal layer 22 represents a greater percentage of the total active area of ​​the device, thereby increasing the percentage increase in current carrying capacity seen by using these improvements. Figure 7C It is shown that the greatest improvement in device performance for a given chip size is seen at higher voltage ratings.

[0038] Figure 8 FIG. 1 shows a top view of a transistor semiconductor chip 10 according to an embodiment of the present disclosure. Specifically, Figure 8 The transistor semiconductor chip 10 is shown with the gate metal layer 18 and the additional dielectric layer 50 removed. The source metal layer 22 is exposed below the additional dielectric layer 50. Figure 8In the illustrated embodiment, the gate via bar 20 is still present. A first dashed box 54 illustrates the region on which the gate metal layer 18 is disposed. This region may correspond to the boundary of the gate contact pad 14 or may extend beyond the boundary of the gate contact pad 14. In other words, the entire gate metal layer 18 may be exposed as the gate contact pad 14 by the passivation layer 12, or a portion of the gate metal layer 18 may be covered by the passivation layer 12, such that only a portion of the gate metal layer 18 constitutes the gate contact pad 14. As shown, a portion of the gate metal layer 18 overlaps the gate via bar 20, thereby allowing the gate contact pad 14 to contact the gate electrode 40 coupled to the gate via bar. A second dashed box 56A and a third dashed box 56B illustrate the region of the source contact pad 16. The gate via bar 20 is still located on the surface of the drift layer 36, and therefore, the source metal layer 22 is still required to have an opening 58 sized to accommodate the gate via bar 20. However, the overall size of the gate via bar 20 must be smaller than that of a conventional gate contact pad. Accordingly, the size of the active area within the device region 26 of the transistor semiconductor chip 10 can be significantly increased.

[0039] Figure 9 FIG. 1 shows a top view of a transistor semiconductor chip 10 according to an additional embodiment of the present disclosure. Specifically, Figure 9 The transistor semiconductor chip 10 is shown with the gate metal layer 18 and the additional dielectric layer 50 removed. The source metal layer 22 is exposed below the additional dielectric layer 50. Figure 9 In the illustrated embodiment, the gate via bars 20 are removed and replaced with a plurality of gate contact vias 60, extending through the dielectric layer 46 and the additional dielectric layer 50 to contact one or more underlying gate electrodes 40 and, in turn, couple to one another on the surface of the drift layer 36 (e.g., in the grid configuration shown above). A first dashed box 54 illustrates the area on which the gate metal layer 18 is disposed. As shown, a portion of the gate metal layer 18 overlaps with the gate contact vias 60, thereby connecting the gate contact pad 14 to the gate electrode 40. A second dashed box 56A and a third dashed box 56B illustrate the area of ​​the source contact pad 16. The gate contact vias 60 can have an even smaller area than the gate via bars 20. Accordingly, the overall size of the openings 60 in the source metal layer 22 that accommodate the connection from the gate contact pad 14 to the gate electrode 40 can be made even smaller, thereby further increasing the active area within the device region 26 of the transistor semiconductor chip 10.

[0040] As the connection size between the gate contact pad 14 and the underlying gate electrode 40 decreases, the gate resistance of the transistor semiconductor chip 10 may increase. Accordingly, the size and shape of the gate contact pad 14, the gate metal layer 18, and the number and placement of the gate contact vias 60 may be arranged to minimize the gate resistance of the transistor semiconductor chip 10 while minimizing the gate resistance of the transistor semiconductor chip 10. Figure 10 and Figure 11 The active portion of the device area 26 shown in FIG is maximized. Figure 10 and Figure 11 In FIG, the first dashed box 54 represents the placement of the gate metal layer 18 above the gate contact via 60. As discussed above, the gate contact pad 14 may correspond to all or a subset of the gate metal layer 18. The second dashed box 56A and the third dashed box 56B again represent the area of ​​the source contact pad 16. Figure 11 In FIG. 5 , a fourth dotted line frame 56C and a fifth dotted line frame 56D represent additional areas where the source contact pad 16 may be provided.

[0041] In addition to maximizing the active portion of the device region 26 of the transistor semiconductor chip 10, the additional dielectric layer 50 may also be used to provide additional features. Figure 12 FIG. 1 shows a top view of a transistor semiconductor chip 10 according to an embodiment of the present disclosure. Specifically, Figure 12 The transistor semiconductor chip 10 is shown with the passivation layer 12 removed. Below the passivation layer 12 is an additional dielectric layer 50, through which the gate contact pad 14 and the source contact pad 16 are exposed. In addition to these contact pads, a plurality of sensor contact pads 62 are provided on the additional dielectric layer 50. The sensor contact pads 62 are coupled to sensors 64, which can be any type of sensor, for example, a temperature sensor, a strain sensor, or a current sensor. The sensors 64 can also be located on the surface of the additional dielectric layer 50 or can be located further below the layer stack, such as on the dielectric layer 46, on the drift layer 36, or even in the drift layer 36. If the sensors 64 are located in the drift layer 36, they can reduce the total active area of ​​the device region 26. However, compared to the size of the device region 26, the sensors 64 are typically very small and thus the reduction in the active area of ​​the device region 26 caused by the sensors in the drift layer 36 is very small. Typically, sensor contact pads 62 are much larger than sensors 64 themselves, and because sensor contact pads 62 can be located above source metal layer 22, the active area of ​​device region 26 is minimally impacted by incorporating one or more sensors into transistor semiconductor die 10. In some embodiments, sensor contact pads 62 can be formed by the same metallization layer (i.e., in the same metallization step) as gate metal layer 18.

[0042] Figure 13 A cross-sectional view of a transistor semiconductor chip 10 is shown according to one embodiment of the present disclosure. Figure 13 The transistor semiconductor chip 10 shown in FIG. Figure 6, but shows the sensor contact pads 62 on the surface of the additional dielectric layer 50. Since the sensor 64 can be located behind the sensor contact pads 62 on the additional dielectric layer 50, Figure 13 The sensor 64 is not shown.

[0043] Figure 14 A cross-sectional view of a transistor semiconductor chip 10 is shown according to additional embodiments of the present disclosure. Figure 14 The transistor semiconductor chip 10 shown in FIG. Figure 13 , but the sensor contact pad 62 is coupled to a sensor 64 located in the drift layer 36 through a sensor contact via 66. The sensor 64 can include one or more implanted regions in the drift layer 36, so that the sensor 64 can be any type of semiconductor device. The sensor 64 can be used to measure temperature, stress, current, voltage, or any other desired parameter. As discussed above, the sensor contact pad 62 generally requires a larger area to implement than the sensor 64 and the sensor contact via 66. Providing the sensor contact pad 62 on the additional dielectric layer 50 allows the sensor contact pad 62 to at least partially overlap with the source metal layer 22, thereby reducing the impact of providing the sensor 64 in the transistor semiconductor chip 10 on the active area of ​​its device region 26. Although the sensor 64 is shown in the drift layer 36, the sensor 64 can be located anywhere above or below the drift layer 36 and can be coupled using any number of vias and intermediate metal layers without departing from the principles of the present disclosure.

[0044] Figure 15 FIG2 shows a cross-sectional view of a transistor semiconductor chip 10 according to an additional embodiment of the present disclosure. Figure 6, but further includes a first intermediate layer 68A between the dielectric layer 46 and the additional dielectric layer 50 and a second intermediate layer 68B between the additional dielectric layer 50 and the gate metal layer 18. The first intermediate layer 68A and the second intermediate layer 68B can reduce the chemical interaction between the dielectric layer 46, the additional dielectric layer 50, the gate metal layer 18, and the source metal layer 22. This is important because the additional dielectric layer 50 may require a densification anneal to obtain good dielectric properties. The first intermediate layer 68A and the second intermediate layer 68B can include Si3N4, Al2O3, AlN, SiO2, a variation thereof, or any other suitable material. As discussed above, the dielectric layer 46 and the additional dielectric layer 50 can include SiO2 or any other suitable material. As shown, the second intermediate layer 68B can be provided after the openings for the one or more vias 52 are made. Accordingly, a second intermediate layer 68B may be provided along the edges of the one or more vias 52 such that the second intermediate layer 68B reduces chemical interactions between the metal of the one or more vias 52, the dielectric layer 46, and the additional dielectric layer 50. The one or more vias 52 may include a single conductive metal that is the same as or different from the gate metal layer 18, or may include a stack of different metals that form a chemical or diffusion barrier along the walls of the one or more vias 52 as desired.

[0045] Figure 15 Also shown is a passivation layer 12 over the gate metal layer 18. The passivation layer 12 may protect the transistor semiconductor chip 10 from the surrounding environment. The passivation layer 12 may include Si2N4, Al2O3, SiO2, alternating layers thereof, or any other suitable material.

[0046] The transistor semiconductor chip 10 may be a power transistor chip configured to conduct a current of at least 0.5 A in a forward conduction operating mode and to block a voltage of at least 100 V in a blocking operating mode. In various embodiments, the transistor semiconductor chip 10 may be configured to conduct at least 1.0 A, at least 2.0 A, at least 3.0 A, at least 4.0 A, at least 5.0 A, at least 6.0 A, at least 7.0 A, at least 8.0 A, at least 9.0 A, and at least 10.0 A in the forward conduction operating mode. The transistor semiconductor chip 10 may be configured to block at least 250 V, at least 500 V, at least 750 V, at least 1 kV, at least 1.5 kV, and at least 2.0 kV in the blocking operating mode.

[0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims.

Claims

1. A transistor semiconductor chip, comprising: Drift layer; ●a first dielectric layer on the drift layer; a first metallization layer on the first dielectric layer, wherein at least a portion of the first metallization layer provides a first contact pad; a second dielectric layer on the first metallization layer; a gate metallization layer on the second dielectric layer, such that at least a portion of the gate metallization layer provides a gate contact pad; a first plurality of electrodes electrically coupled to the first metallization layer and covered by the first dielectric layer; a plurality of gate electrodes electrically coupled to the gate metallization layer such that the transistor semiconductor chip is configured to selectively conduct current between the first and third contact pads based on a signal provided at the gate contact pad; at least one gate contact via extending through the first dielectric layer and the second dielectric layer to electrically connect the gate contact pad to the plurality of gate electrodes; ● edge termination area; and • a device region within the edge termination region, wherein a total inactive area within the device region is less than an area of ​​the gate contact pad.

2. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip is configured to conduct a current greater than 0.5 A between the first contact pad and the third contact pad in a forward conduction operating mode and to block a voltage greater than 100 V between the first contact pad and the third contact pad in a blocking operating mode.

3. The transistor semiconductor chip according to claim 1, wherein: The drift layer includes silicon carbide.

4. The transistor semiconductor chip according to claim 1 , further comprising: A passivation layer is above the gate metallization layer, such that the first contact pad and the gate contact pad are exposed through the passivation layer.

5. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip is a metal oxide semiconductor field effect transistor MOSFET.

6. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip is an insulated gate bipolar transistor IGBT.

7. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip is a bipolar junction transistor.

8. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip provides a vertical transistor device such that the third contact pad is opposite to the drift layer from the first contact pad and the gate contact pad.

9. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip provides a lateral transistor device such that the third contact pad is on the first dielectric layer adjacent to the first contact pad.

10. The transistor semiconductor chip according to claim 1, further comprising: One or more sensor contact pads are on the second dielectric layer.

11. The transistor semiconductor chip according to claim 10, wherein: One or more of the sensor contact pads are coupled to a sensor on the second dielectric layer.

12. The transistor semiconductor chip according to claim 11, wherein: The sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.

13. The transistor semiconductor chip according to claim 10, wherein: One or more of the sensor contact pads are coupled to a sensor in the drift layer through the first dielectric layer and the second dielectric layer by one or more vias.

14. The transistor semiconductor chip according to claim 13, wherein: The sensor is one or more of a temperature sensor, a strain sensor, and a current sensor.

15. The transistor semiconductor chip according to claim 10, wherein: At least a portion of one or more of the sensor contact pads overlaps the first metallization layer.

16. The transistor semiconductor chip according to claim 10, wherein: The area of ​​the first contact pad is at least 0.4 mm 2 .

17. The transistor semiconductor chip according to claim 1, wherein: At least a portion of the gate metallization layer overlaps the first metallization layer.

18. The transistor semiconductor chip according to claim 1, wherein: The first dielectric layer and the second dielectric layer include one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 .

19. The transistor semiconductor chip according to claim 18, wherein: The first dielectric layer has a different composition than the second dielectric layer.

20. The transistor semiconductor chip according to claim 1, further comprising: An intermediate layer is between the first dielectric layer and the second dielectric layer, such that the intermediate layer is between the first metallization layer and the second dielectric layer.

21. The transistor semiconductor chip according to claim 20, wherein: The first dielectric layer, the second dielectric layer, and the intermediate layer include one or more of SiO2, Al2O3, and Si3N4; and The intermediate layer has a different composition than the first dielectric layer and the second dielectric layer.

22. The transistor semiconductor chip according to claim 20, further comprising: An intermediate layer is added between the second dielectric layer and the gate metallization layer.

23. The transistor semiconductor chip according to claim 22, wherein: the first dielectric layer, the second dielectric layer, the intermediate layer, and the additional intermediate layer comprise one or more of SiO 2 , Al 2 O 3 , and Si 3 N 4 ; and The intermediate layer and the additional intermediate layer have a different composition than the first dielectric layer and the second dielectric layer.

24. The transistor semiconductor chip according to claim 1, wherein: The transistor semiconductor chip is a vertical transistor device.

25. A transistor semiconductor chip, comprising: Source contact pad, gate contact pad, and drain contact pad; Sensor contact pads; a device region comprising one or more regions coupled to one or more of the source contact pad, the gate contact pad, and the drain contact pad, such that the transistor semiconductor chip is configured to selectively conduct current between the source contact pad and the drain contact pad based on a signal provided at the gate contact pad, wherein: The source contact pad and the gate contact pad are located on the same side of the transistor semiconductor chip; and The total passive area within the device region is less than the area of ​​the gate contact pad; and • an edge termination region, wherein the device region is within the edge termination region, • wherein the sensor contact pad is coplanar with the gate contact pad.

26. The transistor semiconductor chip according to claim 25, wherein: The area of ​​the source contact pad is at least 0.4 mm 2 .

27. The transistor semiconductor chip according to claim 25, wherein: The transistor semiconductor chip is configured to conduct a current greater than 0.5 A between the source contact pad and the drain contact pad in a forward conduction operating mode and to block a voltage greater than 100 V between the source contact pad and the drain contact pad in a blocking operating mode.

28. The transistor semiconductor chip according to claim 25, wherein: The transistor semiconductor chip is a vertical semiconductor device.

29. A transistor semiconductor chip, comprising: ●Substrate; a drift layer on the substrate; one or more implanted regions in the drift layer within the device region such that vertical transistor devices are formed; A sensor integrated with the transistor semiconductor chip; a sensor contact pad electrically coupled to the sensor, wherein the total passive area within the device region is less than the area of ​​the sensor contact pad; and • an edge termination region, wherein the device region is within the edge termination region.

30. The transistor semiconductor chip according to claim 29, wherein: The sensor is one of a temperature sensor, a strain sensor, and a current sensor.

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