Three-dimensional stacked semiconductor assemblies and methods of manufacturing the same

Abstract

Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer, and a recess formed at the second side of the substrate and aligned with the metal bump. The recess exposes and enables electrical coupling of a portion of the second metallization layer to another semiconductor device package.

Description

TECHNICAL FIELD

[0001] The present technology relates to semiconductor assemblies having stackable semiconductor packages therein. More specifically, some embodiments of the present technology relate to semiconductor assemblies fabricated through a three-dimensional stacking (3DS) process. In such embodiments, the semiconductor packages are directly electrically coupled to one another without the use of through-silicon vias (TSVs). BACKGROUND

[0002] Packaged semiconductor dies including memory chips, microprocessor chips, logic chips, and imager chips typically include semiconductor dies mounted on a substrate and encased in a plastic protective covering. Individual semiconductor dies can include functional features such as memory cells, processor circuitry, imager devices, and other circuitry, as well as bond pads electrically connected to the functional features. Semiconductor manufacturers continually reduce the size of die packages to fit within the space constraints of electronic devices. One method for increasing the processing power of a semiconductor package is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically stacked packages can be electrically interconnected through the use of TSVs. One drawback of using TSVs is that it requires multiple steps to form the TSVs, and some of these steps (e.g., photolithography processes) can be time consuming and expensive. BRIEF DESCRIPTION OF DRAWINGS

[0003] Many aspects of the present technology can be better understood with reference to the accompanying drawings. The components in the drawings are not necessarily to scale. Indeed, the emphasis is on illustrating the principles of the present technology.

[0004] Figure 1 is a schematic cross-sectional view of a semiconductor device package assembly according to embodiments of the present technology.

[0005] Figures 2A to 2J is a schematic cross-sectional view illustrating a method of forming a semiconductor device package according to embodiments of the present technology.

[0006] Figure 3A and 3B is a schematic cross-sectional view illustrating a method of stacking semiconductor device packages according to embodiments of the present technology.

[0007] Figures 4A to 4D is a schematic cross-sectional view illustrating a method of processing multiple semiconductor device package assemblies according to embodiments of the present technology.

[0008] Figure 5 is a block diagram illustrating a system incorporating semiconductor assemblies according to embodiments of the present technology. DETAILED DESCRIPTION

[0009] Specific details of several embodiments of stacked semiconductor die packages and methods of manufacturing such die packages are described below. The term "semiconductor device" generally refers to a solid-state device that includes one or more semiconductor materials. A semiconductor device can include a semiconductor substrate, wafer, or die, for example, singulated from a wafer or substrate. Throughout this disclosure, semiconductor dies are generally described, but are not limited to, in the context of semiconductor devices.

[0010] The term "semiconductor device package" can refer to an arrangement in which one or more semiconductor devices are incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encloses at least one semiconductor device. A semiconductor device package can also include an interposer that carries one or more semiconductor devices and is attached to or otherwise incorporated into a casing. The term "semiconductor device package assembly" can refer to an assembly that includes multiple stacked semiconductor device packages. As used herein, the terms "vertical," "lateral," "upper," and "lower" can refer to the relative orientation or position of features in a semiconductor device or package with respect to the orientation shown in the figures. However, these terms should be broadly interpreted to include other orientations of the semiconductor device, for example, inverted or tilted orientations.

[0011] Figure 1 is a schematic cross-sectional view of a semiconductor device package assembly 100 in accordance with an embodiment of the technology. As shown, the semiconductor device package assembly 100 includes a base substrate 101 and a plurality of semiconductor device packages 103 stacked on the base substrate 101. Although the illustrated embodiment shows thirteen (13) individual stacked semiconductor device packages 103, it should be appreciated that in other embodiments, the semiconductor device package assembly 100 can include any suitable number of stacked semiconductor device packages 103.

[0012] In some embodiments, the base substrate 101 can include a base wafer having one or more semiconductor components (e.g., dies; not shown) therein. In some embodiments, the base substrate 101 can be a circuit board or other type of substrate commonly used in semiconductor device packages. As shown, the base substrate 101 has a first side 1011 (e.g., front / active side) and a second side 1013 (e.g., back / inactive side) opposite the first side 1011.

[0013] The base substrate 101 can include a passivation layer 1015 at the first side 1011 configured to protect the base substrate 101. In some embodiments, the passivation layer 1015 can include an oxidation layer, an inert layer (e.g., a layer that is unlikely to chemically react or corrode with air), or other suitable protective layer. In some embodiments, the passivation layer 1015 can include a protective film.

[0014] In some embodiments, the base substrate 101 can be further coupled to the interposer substrate by electrical couplings such as solder bumps or solder balls.

[0015] As shown, the base substrate 101 includes a plurality of metallization layers 105 (or a first set of metallization layers) located therein and configured to electrically couple to one or more semiconductor components (not shown) in the base substrate 101. In the illustrated embodiment, the metallization layers 105 can include a first metallization layer 105a, a second metallization layer 105b, and a third metallization layer 105c. In some embodiments, the first metallization layer 105a can include aluminum, or other suitable metal or conductive material. In some embodiments, the first metallization layer 105a can be implemented as an aluminum pad. In some embodiments, the second metallization layer 105b can include copper or other suitable metal or conductive material. In some embodiments, the third metallization layer 105c can include copper or other suitable metal or conductive material.

[0016] In the illustrated embodiment, the metallization layers 105 can be formed during a back end of line (BEOL) manufacturing process. When the semiconductor device packages 103 are stacked on the base substrate 101, the first metallization layer 105a can include a contact region 107 configured to contact (e.g., electrically and physically) the semiconductor device packages 103.

[0017] In the illustrated embodiment shown in FIG. 1, the semiconductor device packages 103 are stacked on the base substrate 101. In some embodiments, the semiconductor device packages 103 can be stacked on the base substrate 101 in a manner that is similar to the manner in which semiconductor device packages are stacked on a motherboard in a conventional computer system. Figure 1 In the illustrative embodiment shown in FIG. 1, the individual semiconductor device packages 103 have a first side 1031 (e.g., front / active / side) and a second side 1033 (e.g., back / inactive side) opposite the first side 1031. As shown, the individual semiconductor device packages 103 can also include a passivation layer 1035 at the first side 1031 of the semiconductor device package 103 configured to protect the semiconductor device package 103. In some embodiments, the passivation layer 1035 can include an oxide layer, an inert layer (e.g., a layer that is unlikely to chemically react or corrode with air), or other suitable protective layer. In some embodiments, the passivation layer 1035 can include a protective film.

[0018] As shown, the individual semiconductor device packages 103 can also include a dielectric layer 1037 at the second side 1033 of the semiconductor device package 103. In some embodiments, the dielectric layer 1037 can protect the semiconductor device package 103. In some embodiments, the dielectric layer 1037 can be a dielectric film.

[0019] The individual semiconductor device packages 103 can also include one or more metallization layers 109 (or a second set of metallization layers) configured to electrically couple to one or more semiconductor components (e.g., dies; not shown) in the semiconductor device package 103. In the illustrated embodiment, the metallization layers 109 can include aluminum, copper, or other suitable metal or conductive material. In some embodiments, the metallization layers 109 can be formed during a BEOL fabrication process. In some embodiments, the metallization layers 109 can include multiple metallization layers (similar to the first, second, and third metallization layers 105a, 105b, and 105c discussed above).

[0020] The semiconductor device package assembly 100 further includes a metal bump 111 at the first side 1031 of the individual semiconductor device package 103. The metal bump 111 is electrically coupled to the metallization layers 109 and configured to contact (e.g., at the contact region 107) the first metallization layer 105a of the base substrate 101. In some embodiments, the metal bump 111 can include an indium bump. In other embodiments, the metal bump 111 can include other suitable conductive material.

[0021] The individual semiconductor device package 103 has a notch 113 (or “groove”) at the second side 1033. The notch 113 is configured to enable the metallization layers 109 to contact another semiconductor device package 103 via another metal bump 115. With this arrangement, the present technology enables the base substrate 101 to be electrically coupled to the semiconductor device package 103 without using TSVs.

[0022] In some embodiments, the semiconductor device package assembly 100 can be a memory device in which the semiconductor device package 103 is a memory die (e.g., DRAM, LPDRAM, SRAM, flash memory, etc.). In some embodiments, the base substrate 101 can be a logic device, a processor, and / or another memory device.

[0023] Figures 2A to 2J is a schematic cross-sectional view of a method for fabricating a semiconductor device package 203 according to the present technology. Like reference numbers refer to like components in Figures 2A to 2J FIG. 1. Reference is made to FIG. 1 for a description of the components of the semiconductor device package 203. Figure 2Asemiconductor device package 203 has a first side 2031 (e.g., front / active side) and a second side 2033 (back / inactive side) opposite the first side 2031. The semiconductor device package 203 can have a substrate 2057 and a metallization layer 205 formed during a BEOL manufacturing process. The metallization layer 205 can include a first metallization layer 205a, a second metallization layer 205b, and a third metallization layer 205c in the substrate 2037. In some embodiments, the first metallization layer 205a can include aluminum, or other suitable metal or conductive material. In some embodiments, the first metallization layer 205a can be implemented as an aluminum pad. In some embodiments, the second metallization layer 205b can include copper or other suitable metal or conductive material. In some embodiments, the third metallization layer 205c can include copper or other suitable metal or conductive material.

[0024] In some embodiments, the semiconductor device package 203 can also have a barrier layer 217 between portions of the metallization layer 205 and the substrate 2037. In some embodiments, the barrier layer 217 is adjacent to the second metallization layer 205b. In some embodiments, the barrier layer 217 can be made of a metal such as tantalum. In some embodiments, the second metallization layer 205b can include copper, and the barrier layer 217 made of tantalum can protect the second metallization layer 205b from diffusion or damage.

[0025] As shown in Figure 2A , the semiconductor device package 203 includes a passivation layer 2035 at the first side 2031 of the semiconductor device package 203 configured to protect the semiconductor device package 203. In some embodiments, the passivation layer 2035 can include an oxidation layer, an inert layer (e.g., a layer that is unlikely to chemically react or corrode with air), or other suitable protective layer. In some embodiments, the passivation layer 2035 can include a protective film. The semiconductor device package 203 can also include a contact area 207 on the first metallization layer 205a at the first side 2031.

[0026] Referring to Figure 2B , the semiconductor device package 203 can also include a metal bump 211 on the contact area 207. The metal bump 211 is electrically coupled to the metallization layer 205 and configured to electrically contact a metallization layer of another semiconductor device package (see, e.g., Figure 1 ). In some embodiments, the metal bump 211 can include an indium bump. In other embodiments, the metal bump 211 can include other suitable conductive material.

[0027] In some embodiments, the metal bumps 211 can have a vertical dimension VD of approximately 10 to 20 pm. In some embodiments, the vertical dimension VD can be approximately 15 pm. In some embodiments, the metal bumps 211 can be formed by an electroplating process. In some embodiments, the metal bumps 211 can be formed by having seed material in the contact regions 207 of the first metallization layer 205a. The seed material can facilitate the formation of the metal bumps 211 on the first metallization layer 205a. In some embodiments, the metal bumps 211 can be formed by an inkjet process. In other embodiments, the metal bumps 211 can be formed by other suitable methods. In some embodiments, the metal bumps 211 can be subjected to a low temperature anneal.

[0028] Figure 2C The semiconductor device package 203 is shown after it has been coupled to a carrier 215 by a bonding layer 213. The carrier 215 is configured to hold and support the semiconductor device package 203 during the manufacturing process described below with reference to Figures 2D to 2J In some embodiments, the carrier 215 can be a reusable carrier (e.g., a glass carrier). In some embodiments, the carrier 215 can be a non-reusable carrier (e.g., a silicon or plastic carrier). In some embodiments, the bonding layer 213 can be a release tape (e.g., gas sensitive or temperature sensitive). In such embodiments, the bonding layer 213 can dissolve and thus release the semiconductor device package 203 from the carrier 215 in response to a laser or a specific type of gas. Related embodiments are discussed below with reference to Figure 3A In some embodiments, the bonding layer 213 can be an adhesive layer or other suitable bonding material.

[0029] Figure 2D The semiconductor device package 203 is shown after the substrate 2037 has been thinned. With reference to Figure 2D , the semiconductor device package 203 can be thinned such that a depth D between the thinned surface 219 and the first side 2031 of the semiconductor device package 203 is approximately 10 pm (e.g., not including the depth of the passivation layer 2035). In some embodiments, the depth D can be in the range of 5 pm to 30 pm. In some embodiments, the semiconductor device package 203 can be thinned such that the depth D is no more than 30 pm, 25 pm, 20 pm, 15 pm, 10 pm, or 5 pm.

[0030] By thinning the substrate 2037 to this extent, the metallization layer 205 of the semiconductor device package 203 can access and electrically couple to other metallization layers or semiconductor components of another semiconductor device package without using TSVs. Generally, to form TSVs in a semiconductor structure, the minimum depth of the semiconductor structure that can be thinned is about 50 pm. Thus, the improved method provided by the present technology is advantageous at least because the method can fabricate and stack semiconductor device packages having a smaller depth (or vertical dimension) without the processing steps of forming TSVs. This is particularly advantageous for fabricating compact semiconductor devices or packages.

[0031] Figure 2E A process of forming a first photoresist layer 221 (or first photo pattern mask) on the second side 2033 (back / non-active side) of the semiconductor device package 203 is illustrated. As shown, the first photoresist layer 221 is formed with a plurality of openings 223 (only three - a first opening 223a, a second opening 223b, and a third opening 223c are shown in the figure). Figure 2E As shown, the first opening 223a and the third opening 223c are formed on opposite sides of the semiconductor device package 203. The first opening 223a and the third opening 223c can be used to singulate or “cut” the semiconductor device package 203 later in the process. The second opening 223b is aligned with at least a portion of the metal layer 205.

[0032] Figure 2F The semiconductor device package 203 after openings 226 have been formed through the first opening 223a and the third opening 223c to expose the passivation layer 2035 is illustrated. The openings 226 can be formed by etching the substrate 2037 of the semiconductor device package 203. In the same process, a recess 225 (e.g., a trench 225) can be formed in the substrate 2037 through the second opening 223b (e.g., the second opening 223b extends in a direction towards the first side 2031 of the semiconductor device package 203). The recess 225 can be another opening that exposes the barrier layer 217. As shown, the trench 225 is formed with sloped sidewalls (at both the left and right sides of the trench 225, as shown in the figure), which can facilitate coupling or positioning of a metal bump of another semiconductor device package to the metallization layer 205. Figure 2F The recess 225 can be formed in the same etching process as the openings 226.

[0033] Figure 2GThe semiconductor device package 203 is shown after the first photoresist layer 221 has been removed and a dielectric layer 227 has been formed on the second side 2033 of the semiconductor device package 203. In some embodiments, the dielectric layer 227 can be formed by a chemical vapor deposition (CVD) process. In some embodiments, the dielectric layer 227 can be formed by using tetraethyl orthosilicate (TEOS) in a CVD process. In some embodiments, the dielectric layer 227 can be formed by a spin-on process. In some embodiments, the dielectric layer 227 can be a dielectric film.

[0034] As shown in Figure 2H and 2I A second photoresist layer 229 (or second photo pattern mask) can be formed on the second side 2033 (back / non-active side) of the semiconductor device package 203, as shown in Figure 2H In the embodiment shown in Figure 2I The dielectric layer 227 and the barrier layer 217 within the opening 231 are removed to expose the third metallization layer 205c through the opening 2133. In some embodiments, the barrier layer 217 is not removed. Factors to consider whether to remove the barrier layer 217 include, for example, the types of materials used in the barrier layer 217, the third metallization layer 205c, and the metal bump 211.

[0035] Figure 2J The semiconductor package 203 is shown after the second photoresist layer 229 has been removed. The notch 225 has a lateral dimension LI that is greater than the lateral dimension L2 of the metal bump 211. Thus, the sidewalls 225a of the notch 225 and the sidewall portions 227a of the dielectric layer 227 are spaced apart from the sidewalls 211a of the metal bump 211. Figure 2J The semiconductor device package 203 shown in

[0036] Figure 3A and 3B A method for stacking semiconductor device packages 203 according to embodiments of the present technology is described. As shown in Figure 3A The semiconductor device package 203 is coupled to or picked up by a bond tip 301. In some embodiments, the bond tip 301 can be a flip chip tool or other suitable device. The bond tip 301 is configured to temporarily hold the semiconductor device package 203 so that it can be stacked on a base substrate 101.

[0037] Figure 3B A stage (b) is shown after the bond layer 213 has been removed by a laser or gas to separate the semiconductor device package 203 from the carrier 215. Figure 3A). When the semiconductor device package 203 is stacked on the base substrate 101, the metal bumps 211 are aligned with and coupled to the contact regions 107 of the base substrate 101. Thus, the metal bumps 211 are electrically coupled to the metallization layer 105 in the base substrate 101. With this arrangement, the metallization layer 205 of the semiconductor device package 203 can be electrically coupled to the metallization layer 105 in the base substrate 101 without TSVs. This is advantageous because it eliminates the need to form deep vias in the substrate 2037, to line the substrate 2037 with dielectric and / or barrier layers, and to electroplate conductive material into the lined vias when forming TSVs.

[0038] Also as shown in Figure 3B Before the semiconductor device package 203 is stacked on the base substrate 101, a die attach material 303 can be located between the semiconductor device package 203 and the base substrate 101. The die attach material 303 can bond the semiconductor device package 203 to the base substrate 101. In some embodiments, the die attach material 303 can include a polymer, such as a B-stage polymer (e.g., an epoxy film that has been thermally cured). In some embodiments, the die attach material 303 can include a non-conductive film (NCF) or a non-conductive paste (NCP). In some embodiments, the die attach material 303 can be spray dispensed or laminated onto the base substrate 101.

[0039] Figures 4A to 4D A method of processing a plurality of semiconductor device package assemblies 401 is illustrated in accordance with an embodiment of the technology. In Figure 4A The plurality of semiconductor device package assemblies 401 are carried by a temporary carrier 403. Each of the plurality of semiconductor device package assemblies 401 includes a base substrate (e.g., base substrate 101) and a plurality of semiconductor device packages (e.g., semiconductor device packages 103 or 203). As shown, the backside of the semiconductor device packages of the plurality of semiconductor device package assemblies 401 are coupled to the temporary carrier 403. The plurality of semiconductor device package assemblies 401 are spaced apart so that the plurality of semiconductor device package assemblies 401 can be later separated during a singulation process.

[0040] Figure 4B The assemblies are shown after the plurality of semiconductor device package assemblies 401 have been covered by an encapsulation material 405. In some embodiments, the encapsulation material 405 can include a resin, a plastic, a silicon, an oxide, a polymer, or other suitable dielectric material.

[0041] Figure 4C The assemblies are shown after the temporary carrier 403 has been separated from the plurality of semiconductor device package assemblies 401. In Figure 4C The plurality of semiconductor device package assemblies 401 covered by the encapsulation material 405 are singulated from the temporary carrier 403.Figure 4B Inverted.

[0042] Figure 4D The assembly is shown after the polymer layer 407 has been formed over the plurality of semiconductor device package assemblies 401. The method can include forming a redistribution layer 409 using the polymer layer 407. The redistribution layer 409 is electrically coupled to the metallization layer (e.g., metallization layer 105 or 205) in the individual semiconductor device package assemblies 401. In some embodiments, the redistribution layer 409 can include copper or other suitable conductive material.

[0043] As shown in Figure 4D A plurality of connectors 411 can be formed on and electrically coupled to the redistribution layer 409. The connectors 411 are further electrically coupled to the metallization layer of the semiconductor device package and the base substrate in the individual semiconductor device package assemblies 401. In some embodiments, the connectors 411 can be ball grid array (BGA) connectors. In some embodiments, the connectors 411 can include solder balls, pads, or other suitable connection devices. The plurality of semiconductor device package assemblies 401 can then be "singulated" or separated by cutting through the encapsulation material 405 at the locations indicated by the dashed lines. Figure 4D

[0044] Any of the semiconductor devices having the features described above in reference to Figures 1 to 4D may be incorporated into any of a large number of larger and / or more complex systems, representative examples of which are the systems 500 schematically shown in Figure 5 The systems 500 can include a processor 501, a memory 503 (e.g., SRAM, DRAM, flash, and / or other memory devices), input / output devices 505, and / or other subsystems or components 507. The semiconductor assemblies, devices, and device packages described above in reference to Figures 1 to 4D may be included in Figure 5 ​Any of the elements shown in the middle. The resulting system 500 can be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 500 include, without limitation, computers and / or other data processors such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 500 include lamps, cameras, vehicles, etc. With respect to these and other examples, system 500 can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communications network. Accordingly, the components of system 500 can include local and / or remote memory storage devices and any of a wide variety of suitable computer readable media.

[0045] The present disclosure is not intended to be exhaustive or to limit the techniques to the precise forms disclosed. While specific embodiments are disclosed in this document, changes and modifications can be suggested to one skilled in the art, and it is intended that the application technology encompass such changes and modifications as falling within the scope of the techniques. In some instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the techniques. Although the steps of a method can be presented in a particular order, alternative embodiments can perform the steps in a different order. Similarly, certain aspects of the techniques disclosed in the context of a particular embodiment can be combined or removed and other embodiments can include additional aspects not disclosed in the context of a particular embodiment. Moreover, although advantages associated with certain embodiments of the techniques can be disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the techniques. Accordingly, the disclosure and associated techniques can encompass a wide variety of embodiments.

[0046] Throughout this disclosure, unless the context clearly indicates otherwise, the singular terms “a,” “an,” and “the” may include multiple references. Similarly, unless the word “or” is explicitly limited to meaning only a single item other than those in a list having two or more items, its use in such a list should be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Furthermore, the term “comprising” throughout the document means to include at least one or more of the described features, without excluding any larger number of the same features and / or other features of additional types. References herein to “an embodiment,” “some embodiments,” or similar expressions mean that a particular feature, structure, operation, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. Therefore, the appearance of such phrases or expressions herein does not necessarily refer to the same embodiment. Moreover, various particular features, structures, operations, or characteristics may be combined in one or more embodiments in any suitable manner.

[0047] As will be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the scope of the invention. The invention is not limited to the appended claims.

Claims

1. A semiconductor device package comprising: A substrate having an active side and an active side opposite to the active side, the substrate comprising A first metallization layer is located on the active side; A second metallization layer, which is at least partially embedded in the substrate and directly electrically coupled to the first metallization layer without the use of through-silicon vias (TSVs), wherein The non-active side of the substrate includes a recess that exposes a portion of the second metallization layer to provide a direct electrical connection between an external device and the second metallization layer. and A metal bump protrudes from the active side, is directly aligned with the groove, and is electrically coupled to the first metallization layer.

2. The semiconductor device package of claim 1, wherein the substrate has a depth of no more than 15 µm.

3. The semiconductor device package of claim 1, wherein the substrate has a depth of no more than 10 µm.

4. The semiconductor device package of claim 1, wherein the substrate has a depth of no more than 5 µm.

5. The semiconductor device package of claim 1, wherein the semiconductor device package is a first semiconductor device package, and wherein when a second semiconductor device package is attached to the non-active side, the metal bumps are configured to electrically couple circuitry on the active side of the first semiconductor device package to the second semiconductor device package without using through-silicon vias (TSVs).

6. The semiconductor device package of claim 1, wherein the metal bump is a first metal bump, the first metallization layer and the second metallization layer are configured to provide one or more electrical connections through the substrate at a thickness measured between opposing surfaces, and an exposed portion of the second metallization layer is configured to be directly attached to a second metal bump, the second metal bump being electrically coupled to a second semiconductor device package.

7. The semiconductor device package of claim 1, further comprising a passivation layer located on the active side of the substrate.

8. The semiconductor device package of claim 1, wherein the metal bump comprises an indium metal bump.

9. The semiconductor device package of claim 1, wherein the first metallization layer comprises aluminum.

10. The semiconductor device package of claim 1, wherein the second metallization layer comprises copper.

11. The semiconductor device package of claim 1, further comprising a third metallization layer located between the first and second metallization layers and electrically coupled to the first and second metallization layers.

12. The semiconductor device package of claim 11, wherein the third metallization layer comprises copper.

13. A semiconductor device package comprising: A substrate having an active side and an active side opposite to the active side, the substrate comprising A first metallization layer is located on the active side; A second metallization layer, which is at least partially embedded in the substrate and electrically coupled to the first metallization layer without the use of a through-silicon via (TSV), wherein The non-active side of the substrate includes a recess that exposes a portion of the second metallization layer to provide external electrical connectivity. A metal bump protrudes from the active side, is directly aligned with the groove, and is electrically coupled to the first metallization layer; A dielectric layer formed on the non-active side of the substrate, the dielectric layer having dielectric openings inside the groove and above the exposed portion of the second metallization layer; and A barrier layer is located between the dielectric layer and the second metallization layer, the barrier layer including a barrier opening above an exposed portion of the second metallization layer.

14. The semiconductor device package of claim 13, wherein the barrier layer comprises tantalum.

15. A semiconductor device package assembly comprising: A substrate having a first side and a second side opposite to the first side, the substrate having a first set of metallization layers at the first side, the first set of metallization layers having a contact region; and At least one semiconductor device package stacked on the substrate, each of the at least one semiconductor device package having Active side and passive side; The second metallization layer is located on the active side, wherein... A portion of the second group of metallization layers is exposed through the groove on the active side, and the second group of metallization layers is directly electrically coupled to the first group of metallization layers without using a through-silicon via (TSV). and Metal bumps are located within the grooves and are electrically coupled to the second set of metallization layers; The metal bumps are electrically coupled to the first set of metallization layers at the contact area; and The at least one semiconductor device package has a depth of no more than 30 µm.

16. The semiconductor device package assembly of claim 15, wherein the depth does not exceed 20 µm.

17. The semiconductor device package assembly of claim 15, wherein the at least one semiconductor device package is a first semiconductor device package, and wherein the metal bump is a first metal bump, and wherein the recess of the first semiconductor device package is configured to receive a second metal bump of a second semiconductor device package such that the second metal bump is electrically coupled to the second set of metallization layers of the first semiconductor device package without using a TSV.

18. A method for manufacturing a semiconductor device package, comprising: A substrate having an active side and an active side opposite to the active side is formed; A first and a second metallization layer are formed in the substrate at the active side, the first and second metallization layers being separated at least over a portion of the thickness of the substrate and electrically coupled to each other without using a through-silicon via (TSV). Metal bumps are formed that are electrically coupled to the first metallization layer; and The substrate is thinned to a depth of no more than 30 µm by removing a portion of the non-active portion; A groove is formed on the surface of the remaining non-active portion of the substrate, and the groove is directly aligned with the metal bump. and A portion of the second metallization layer is exposed through the groove, wherein the exposed portion is configured to provide a direct connection to external circuitry.

19. The method of claim 18, wherein the semiconductor device package is a first semiconductor device package, and wherein the metal bump is a first metal bump, and wherein the method further comprises: A second metal bump of the second semiconductor device package is positioned in the groove such that the second metal bump is electrically coupled to the first and second metallization layers of the first semiconductor device package, without using a TSV.

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