Register mapping method, processor, chip and electronic device

Abstract

Embodiments of the present application provide a register mapping method, processor, chip, and electronic device, wherein the method includes: determining a target bit width actually used by an architectural register corresponding to a current instruction; determining an idle register area whose bit width matches the target bit width from a physical register stack; wherein the physical register stack includes multiple groups of physical registers, the register areas being unit areas in the physical registers used for register mapping, and the register areas corresponding to different groups of physical registers having different bit widths; determining a target register area based on the idle register area, and allocating the target register area to the architectural register. Embodiments of the present application can improve resource utilization of physical registers when mapping physical registers to architectural registers.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and specifically to a register mapping method, a processor, a chip, and an electronic device. Background Art

[0002] Physical registers in a processor require register mapping before use. Specifically, based on the processor's instruction set architecture, during the register renaming phase, the processor must assign physical registers to architectural registers specified in the instruction set architecture. This process is called register mapping. However, the resource utilization efficiency of physical registers during register mapping currently needs to be improved. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a register mapping method, a processor, a chip, and an electronic device to improve the resource utilization efficiency of physical registers when performing register mapping.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0005] In a first aspect, an embodiment of the present application provides a register mapping method, comprising:

[0006] Determine the target bit width actually used by the architecture register corresponding to the current instruction;

[0007] Determining, from a physical register file, an idle register region whose bit width matches the target bit width; wherein the physical register file includes multiple groups of physical registers, the register region is a unit region in the physical register for register mapping, and the register regions corresponding to different groups of physical registers have different bit widths;

[0008] A target register region is determined based on the free register region, and the target register region is allocated to the architectural register.

[0009] In a second aspect, an embodiment of the present application provides a processor, including:

[0010] The decode unit is used to determine the target bit width of the architectural register used by the current instruction;

[0011] a renaming unit, configured to determine, from a physical register file, a free register region whose bit width matches the target bit width; determine a target register region based on the free register region, and allocate the target register region to the architectural register;

[0012] A physical register stack includes multiple groups of physical registers, the register area is a unit area in the physical register for register mapping, and the bit widths of the register areas corresponding to different groups of physical registers are different.

[0013] In a third aspect, an embodiment of the present application provides a chip comprising the processor as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device comprising the chip as described in the third aspect above.

[0015] The register mapping method provided in the embodiment of the present application can set the physical register stack to multiple groups of physical registers, and the unit areas (called register areas) used for register mapping in different groups of physical registers have different bit widths, so that the physical register stack can provide register areas of different bit widths for register mapping, providing a basis for accurately matching the target bit width actually used by the architecture register. Based on this, the embodiment of the present application can determine the target bit width actually used by the architecture register corresponding to the current instruction during the processor processing the current instruction; thereby, based on the target bit width, determine the free register area whose bit width matches the target bit width from the physical register stack; that is, based on the register areas of different bit widths provided by the physical register stack, the embodiment of the present application can determine from the physical register stack a free register area whose bit width is the same as the target bit width, or a free register area whose bit width is greater than the target bit width but can be further divided to obtain the target bit width, or a plurality of free register areas whose bit width can be merged to obtain the target bit width, etc. Furthermore, embodiments of the present application can determine a target register region based on the free register region, so that the bit width of the target register is exactly the target bit width used by the architectural register. By allocating the target register region to the architectural register, a physical register region corresponding to the target bit width actually used can be allocated to the architectural register during the register mapping process, thereby maximizing the utilization of physical register resources. It can be seen that embodiments of the present application can allocate a target register region corresponding to the target bit width actually used by the architectural register to the architectural register, thereby improving the resource utilization of the physical register. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0017] Figure 1 This is an architectural diagram of the processor provided in an embodiment of the present application.

[0018] Figure 2 This is an example diagram of the use of vector registers and operation mask registers provided in an embodiment of the present application.

[0019] Figure 3A This is an example diagram of dividing the physical register file provided in an embodiment of the present application.

[0020] Figure 3B Another example diagram of dividing a physical register file provided in an embodiment of the present application.

[0021] Figure 4 A flowchart of a register mapping method provided in an embodiment of the present application.

[0022] Figure 5 An optional flowchart for determining a target register area provided in an embodiment of the present application.

[0023] Figure 6 Another optional flowchart for determining the target register area provided in an embodiment of the present application.

[0024] Figure 7 This is an example diagram of the reading results of the renaming table provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] The processor is the computing and control core of the computer system. For example, the central processing unit (CPU), various complex instruction set computing (CISC) processors, various reduced instruction set computing (RISC) processors, various very long instruction word (VLIW) processors, etc. The processor is generally set to operate in a pipeline. Figure 1 1 shows a schematic diagram of the architecture of the processor 100. Figure 1 As shown, the processor 100 may include: an instruction fetch unit 101 , a decoding unit 102 , an execution unit 103 , a rename table 104 , a physical register file 105 and a rename unit 106 .

[0027] The instruction fetch unit 101 may fetch instructions according to an instruction fetch instruction, for example, fetch instructions from an instruction cache according to an instruction fetch instruction predicted by a branch prediction unit of a processor front end.

[0028] The decoding unit 102 can decode and parse the instructions obtained by the instruction fetch unit 101. The instructions decoded by the decoding unit 102 can be the operation information that can be executed by the machine after parsing the instruction, such as the machine-executable uop (microinstruction) formed by parsing the OpCode (operation code), operands and control fields of the instruction. In addition, the decoding unit 102 decodes the current instruction according to the instruction set architecture setting, obtains the specific operation (addition, subtraction, etc.) performed by the subsequent execution unit in the OpCode of the instruction, obtains the architecture registers where the source operand and destination operand of the instruction are stored, and other required information. After being decoded by the decoding unit 102, the instruction can be expanded into the format required by the processor. At this time, the decoded instruction can carry multiple attributes, such as opcode, operand, etc.

[0029] Execution unit 103 performs operations based on the decoded instruction and generates an execution result. Based on the source and destination operands decoded by decoding unit 102, execution unit 103 determines the physical register number corresponding to the architectural register, in conjunction with the entry in rename table 104. Based on the physical register number, execution unit 103 retrieves the actual stored data from physical register file 105 to obtain a real-time stored result. The real-time stored result is then written back to the physical register corresponding to the destination register.

[0030] The renaming unit 106 is used to modify the mapping relationship between architectural registers and physical registers in the renaming table 104. Based on the source and destination operands decoded by the decoding unit 102 and the architectural registers stored therein, the renaming unit 106 reads the remaining physical registers in the physical register file 105 to obtain a mapping relationship between the architectural registers and the actual allocated physical registers. The renaming unit 106 writes the mapping relationship to the renaming table 104 and simultaneously marks the physical register in the physical register file as occupied to prevent confusion caused by repeated use during subsequent renaming instructions.

[0031] It should be noted that the renaming table 104 can record the mapping relationship between the actual allocated physical registers and the architectural registers. The renaming unit 106 can re-establish or modify the mapping relationship between the physical registers in the physical register file 105 and the architectural registers by changing the mapping relationship in the renaming table 104. It should be noted that the architectural registers are the registers specified in the instruction set architecture and are also the registers that programmers can use when using assembly language, while the physical registers are the actual hardware resources in the processor.

[0032] It needs to be further explained that Figure 1The illustrated instruction fetch unit 101, decode unit 102, execution unit 103, physical register file 105, and rename unit 106 may be logic circuit units in the processor 100. In addition, it is understood that Figure 1 Only some optional structures of the processor 100 are shown by way of example. The processor 100 may also include other possible devices. For example, the processor may also include other circuit devices that are not necessary for understanding the contents disclosed in the embodiments of the present application. Since other circuit devices are not necessary for understanding the contents disclosed in the embodiments of the present application, the embodiments of the present application will not be described in detail.

[0033] At the architectural level, the instruction set often sets the bit width of the physical register to the maximum bit width of the architectural register. Therefore, when performing register mapping, the renaming unit 106 directly allocates the entire physical register with the maximum bit width to the architectural register. However, the data bit width actually used by the architectural register often does not reach the maximum bit width, which results in unused bit widths in the physical register and waste of physical register resources. To more clearly illustrate the above problem, the following example uses the allocation of physical registers to operation mask registers as an example, where the operation mask register is a register used to perform operations on the data stored in the vector register. It should be noted that physical registers can be divided into vector registers for storing operation data and operation mask registers for storing operation masks during register mapping. During register mapping, the physical registers need to be mapped to the corresponding architectural registers.

[0034] When running instructions (such as single instruction multiple data (SMID) instructions), the processor saves multiple sets of data in vector registers, performs operations on multiple sets of data at the same time using vector registers, and indicates the operations to be performed and the masked operations on the multiple sets of data through the operation mask register. Figure 2 This figure shows an example of the use of vector registers and operation mask registers. Figure 2 , vector register X contains 4 groups of data (Ax, Bx, Cx, Dx), and vector register Y contains 4 groups of data (Ay, By, Cy, Dy). Assume that the data stored in vector registers X and vector registers Y are added, and in some special program semantics, it is not desired to perform the addition operation on all data in the vector registers (for example, adding a restriction that only negative numbers are added), then a multi-bit operation mask for operation control can be stored in the operation mask register.

[0035] Each bit of the operation mask stored in the operation mask register can be set to correspond to each set of data stored in the vector registers X and Y, thereby indicating the data in the vector registers X and Y that are to be added and masked. Figure 2As shown in the figure, when the value of a certain bit of the operation mask in the operation mask register is 1, it means that the data of the corresponding group in the vector register performs an addition operation. When the value of a certain bit of the operation mask in the operation mask register is 0, it means that the data of the corresponding group in the vector register masks the addition operation. Figure 2 Taking the value of the operation mask in the operation mask register as 1010 as an example, based on the values ​​of the first and third bits of the operation mask being 1, the first and third groups of data in the vector registers X and Y are added. Based on the values ​​of the second and fourth bits of the operation mask being 0, the second and fourth groups of data in the vector registers X and Y are masked for the addition operation, thereby obtaining the operation result (Ax+Ay, Bz, Cx+Cy, Dz), where Bz and Dz represent registers that retain the register values ​​before the addition instruction is executed.

[0036] As can be seen, when vector registers X and Y contain 4 groups of data, the operation mask in the operation mask register is also 4 bits. In other words, the bit width used to store the operation mask in the operation mask register corresponds to the number of data groups stored in the vector register, that is, the number of effective mask bits in the operation mask register corresponds to the number of data groups stored in the vector register.

[0037] The operation mask register, used by the processor to store operation control data, requires a physical register to be allocated during the register renaming phase. However, to ensure compatibility with all possible operation mask bit counts for the operation mask register, the instruction set architecture often sets the bit width of the operation mask register to the maximum number of data groups that a vector register can store. This means that a physical register with a corresponding bit width is allocated to the operation mask register based on the maximum number of data groups that the vector register can store. This approach can easily lead to unused bit widths in the physical register allocated to the operation mask register if the actual number of mask bits used by the operation mask register is not the maximum number of data groups that the vector register can store, resulting in a waste of physical register resources.

[0038] For example, in the Intel AVX512 instruction set, vector registers can have bit widths of 128, 256, or 512 bits, while the width of each data group can be 8, 16, 32, or 64 bits. Therefore, the maximum number of data groups in a vector register is 512 / 8 = 64, and the minimum is 128 / 64 = 2. If physical registers with corresponding bit widths are uniformly allocated to the operation mask registers based on the maximum number of data groups stored in the vector register (64), the bit width of the physical registers allocated to the operation mask registers will be uniformly 64 bits. However, if the actual number of mask bits in the operation mask register is less than 64 bits, the allocated physical registers will have unused high-order bits, resulting in a waste of physical register resources.

[0039] In other words, when the high bits of a physical register are not needed, allocating a physical register with the maximum upper limit width to an architectural register, as per the architectural design of the instruction set, results in significant waste. Furthermore, from a power consumption perspective, when the actual data width used by the architectural register is less than the maximum upper limit width, but data with the maximum upper limit width is still transmitted, invalid data is redundantly transmitted, resulting in additional power consumption. On the other hand, when the actual data width used by the architectural register is less than the maximum upper limit width, but the physical register with the maximum upper limit width is still occupied, the unused bits in the physical register cannot be used by other instructions, wasting the physical register area.

[0040] As can be seen from the above, the resource utilization efficiency of physical registers needs to be improved during register mapping. Therefore, the embodiments of the present application provide a novel register mapping solution that can allocate physical registers with corresponding bit widths to architectural registers based on the target bit width actually used by the architectural registers, thereby improving the resource utilization of physical registers.

[0041] Based on the above ideas, the embodiment of the present application does not directly allocate a complete physical register with a maximum upper limit bit width to an architectural register. Instead, the physical register is divided into register regions with different bit widths, and the register region is used as the unit region for register mapping in the physical register, thereby reducing the situation of directly mapping a complete physical register with a maximum upper limit bit width to an architectural register. This enables the embodiment of the present application to be compatible with various bit width requirements of the architectural register in actual use through register regions with different bit widths. Based on this, the embodiment of the present application can divide the register region of the physical register stack 105, Figure 3A FIG. 1 shows an example diagram of partitioning the physical register file 105. Figure 3A , the physical register stack 105 may include: multiple groups of physical registers 31 to 3n, where n is the number of groups of physical registers, which can be set according to actual conditions. A group of physical registers may have multiple physical registers, and a physical register uses a register area as a unit area for register mapping, rather than using the entire physical register for register mapping, and the bit widths of the register areas in different groups of physical registers are different, that is, different groups of physical registers use unit areas of different bit widths for register mapping. Figure 3AAs shown, the first group of physical registers 31 includes multiple register regions 310, and the first group of physical registers 31 performs register mapping using register region 310 as a unit region. The second group of physical registers 32 includes multiple register regions 320, and the second group of physical registers 32 performs register mapping using register region 320 as a unit region. Similarly, the nth group of physical registers 3n includes multiple register regions 3n0, and the nth group of physical registers 3n performs register mapping using register region 3n0 as a unit region. In the multiple groups of physical registers 31 to 3n, the bit width of the register region used for register mapping in each group of physical registers is different. For example, register regions 310 to 3n0 are the unit regions used for register mapping in the multiple groups of physical registers 31 to 3n, and the bit widths of register regions 310 to 3n0 are different.

[0042] In some embodiments, the bit width of the register region corresponding to a group of physical registers is compatible with a required bit width of an architectural register, and the architectural register has multiple required bit widths. For example, during the actual execution of a program, the architectural register may actually use n required bit widths. In this case, the embodiment of the present application may divide the physical register file 105 into n groups of physical registers 31 to 3n based on the n required bit widths of the architectural registers, and the bit width of the register region used for register mapping by a group of physical registers corresponds to one required bit width of the architectural register. In one example, assuming that the required bit widths actually used by the architectural registers are 64 bits, 32 bits, 16 bits, and 8 bits, respectively, the physical register file 105 may be divided into four groups of physical registers based on these four required bit widths. The bit width of the register region used for register mapping by a group of physical registers corresponds to one required bit width of the architectural register. For example, the physical register file 105 may be divided into four groups of physical registers whose register region bit widths are 64 bits, 32 bits, 16 bits, and 8 bits.

[0043] In some further embodiments, the required bit width of the architectural register during actual use may include the maximum bit width of the physical register (e.g., 64 bits), and at least one sub-bit width divided by the maximum bit width (e.g., 32 bits, 16 bits, and 8 bits divided by 64 bits). Based on this, when the physical register stack is divided into multiple groups of physical registers, the embodiment of the present application may divide the sub-bit widths from large to small according to the group order of the multiple groups of physical registers, starting from the maximum bit width of the physical registers, thereby dividing the register areas of each group of physical registers, thereby obtaining multiple groups of physical registers with different bit widths of register areas. In other words, the bit widths of the register areas corresponding to different groups of physical registers can be divided from large to small according to the group order of the multiple groups of physical registers, starting from the maximum bit width.

[0044] In one example, the physical register file 105 is divided into four groups of physical registers with bit widths of 64 bits, 32 bits, 16 bits, and 8 bits. Figure 3B Another example diagram of partitioning the physical register file 105 is shown. Figure 3B As shown, the physical register file 105 has 64 physical registers numbered 0-63, and the bit width of each physical register is 64 bits (in this example, assuming that 64 bits is the maximum upper limit bit width of the physical register). Therefore, when the physical register file 105 is divided, the physical registers numbered 0-15 are used as the first group of physical registers, and the physical registers numbered 0-15 remain unchanged and are still register mapped based on the 64-bit width of the entire physical register. That is, the physical registers numbered 0-15 are register mapped based on the 64-bit wide register area. The physical registers numbered 16-31 are used as the second group of physical registers. In the physical registers numbered 16-31, one 64-bit physical register is divided into two 32-bit register areas, thereby obtaining 32 32-bit wide register areas. That is, the physical registers numbered 16-31 are register mapped based on the 32-bit wide register area. The physical registers numbered 32-47 serve as the third group of physical registers. Within these physical registers, a 64-bit physical register is divided into four 16-bit register regions, resulting in 64 16-bit register regions. In other words, the physical registers numbered 32-47 are register mapped using 16-bit register regions as units. The physical registers numbered 48-63 serve as the fourth group of physical registers. Within these physical registers, a 64-bit physical register is divided into eight 8-bit register regions, resulting in 128 8-bit register regions. In other words, the physical registers numbered 48-63 are register mapped using 8-bit register regions as units. That is to say, the bit width of the unit area of ​​register mapping for the physical registers numbered 0-15 is 64 bits, the bit width of the unit area of ​​register mapping for the physical registers numbered 16-31 is 32 bits, the bit width of the unit area of ​​register mapping for the physical registers numbered 32-47 is 16 bits, and the bit width of the unit area of ​​register mapping for the physical registers numbered 48-63 is 8 bits.

[0045] It should be noted that dividing a physical register into multiple register regions, for example, dividing a 64-bit physical register into two 32-bit register regions, does not mean dividing the physical register into multiple register regions in hardware. Instead, it means adjusting the bit width range that instructions read from the physical register, so that the physical register can have different bit width ranges that are read by instructions, thereby achieving the division of the physical register into multiple register regions with different bit width ranges. For example, dividing a 64-bit physical register into two 32-bit register regions can be achieved by adjusting instructions to read the lower 32-bit range and the upper 32-bit range of the physical register respectively, thereby dividing the physical register into two 32-bit wide register regions, the lower 32 bits and the upper 32 bits.

[0046] Based on the division of the physical register stack into multiple groups of physical registers, and the different groups of physical registers having different bit widths of register regions used for register mapping, embodiments of the present application can flexibly allocate register regions that match the target bit width actually used to the architecture registers based on the register regions of different bit widths in the physical register stack, so that the bit width of the register region mapped to the architecture register adapts to the target bit width actually used by the architecture register, thereby maximizing the utilization of the register region of the physical registers, thereby achieving the effect of improving the resource utilization of the physical registers.

[0047] In some embodiments, Figure 4 The flowchart of the register mapping method provided by the embodiment of the present application is shown as an example. It should be noted that the flowchart is shown for the purpose of facilitating the understanding of the disclosed content of the embodiment of the present application, and the embodiment of the present application is not limited to Figure 4 Reference Figure 4 , the process of the register mapping method may include the following steps.

[0048] Step S410: Determine the target bit width actually used by the architecture register corresponding to the current instruction.

[0049] The current instruction may be the instruction currently being processed by the pipeline operation of the processor. In some embodiments, S410 may be executed in the decoding stage of the processor. As an optional implementation, after the current instruction is fetched by the instruction fetch unit, it may be decoded and parsed by the decoding unit. The embodiment of the present application may obtain the attribute information of the architecture register operated by the current instruction based on the decoding and parsing result of the current instruction, thereby determining the target bit width actually used by the architecture register corresponding to the current instruction based on the attribute information. It should be noted that the architecture register corresponding to the current instruction may be the architecture register operated by the current instruction, or it may be a register associated with the architecture register operated by the current instruction.

[0050] Taking the operation mask register corresponding to the architecture register corresponding to the current instruction as an example, when determining the target bit width actually used by the operation mask register, the embodiment of the present application can obtain the attribute information of the vector register operated by the current instruction (such as a SIMD instruction) by parsing the OpCode of the current instruction, and thereby determine the target bit width actually used by the architecture register associated with the vector register based on the attribute information.

[0051] As an optional implementation, the embodiment of the present application can determine the actual number of data groups that the vector register stores data during the processing of the current instruction through the attribute information of the vector register, thereby using the actual number of data groups as the number of mask bits actually used by the architecture register to obtain the target bit width actually used by the architecture register. In one example, the attribute information of the vector register can include the vector register width and the data width of each group of data stored in the vector register. The embodiment of the present application can obtain the vector register width of the vector register operated by the current instruction and the data width of each group of data stored in the vector register by parsing the OpCode of the current instruction, thereby calculating the actual number of data groups of data stored in the vector register (the actual number of data groups of the vector register = the vector register width ÷ the data width of each group of data stored in the vector register), and determine the calculated actual number of data groups as the target bit width actually used by the operation mask register.

[0052] Step S411 : Determine, from the physical register file, an idle register area whose bit width matches the target bit width.

[0053] In some embodiments, S411 can be executed in the register renaming stage of the processor. As an optional implementation, the target bit width actually used by the architectural register obtained in the decoding stage can be passed backward in the pipeline operation of the processor, so that in the register renaming stage, the renaming unit can obtain the target bit width; further, the renaming unit can determine the idle register area whose bit width matches the target bit width from the physical register stack with register areas of different bit widths based on the divided physical register stack described above. It should be noted that the idle state of the register area refers to the state in which the register area is not occupied and can be allocated for use.

[0054] In some embodiments, the bit width of the idle register area determined in step S411 may be the same as the target bit width. For example, when the physical register stack is divided into multiple groups of physical registers, and the bit widths of the register areas of each group of physical registers are different, an embodiment of the present application may determine a target group of physical registers whose register area has the same bit width as the target bit width from the physical register stack, thereby determining an idle register area whose bit width is the same as the target bit width from the target group of physical registers when there is an idle register area in the target group of physical registers. In one example, assuming that the target bit width is 32 bits, a physical register group whose register area in the physical register stack has a bit width of 32 bits may be used as the target group of physical registers, thereby an embodiment of the present application may determine an idle register area whose bit width is 32 bits when there is an idle register area in the target group of physical registers.

[0055] When possible, there may be no idle register area in the target group physical registers (the bit width of the register area is the same as the target bit width). In this case, the embodiment of the present application can wait for the occupied register area in the target group physical register to be released, and then select an idle register area from the released register area as the idle register area.

[0056] Example, combined Figure 3B As shown, when the target bit width is 64 bits, the bit width of the register area of ​​the first group of physical register groups corresponding to numbers 0-15 in the physical register stack is 64 bits. Therefore, the physical registers numbered 0-15 are used as the target group physical registers. In the embodiment of the present application, it can be determined whether there is a register area in the first group of physical register groups corresponding to numbers 0-15 in an idle state. If so, the register area in the idle state is determined to be the idle register area; if not, the idle register area is selected from the released register areas after the occupied register areas in the first group of physical register groups corresponding to numbers 0-15 are released.

[0057] In other embodiments, the bit width of the idle register region may be different from the target bit width. For example, the bit width of the idle register region is greater than the target bit width, but can be further divided to obtain the target bit width. For another example, the bit width of the idle register region is less than the target bit width, but the bit widths of multiple idle register regions can be combined to obtain the target bit width. As an optional implementation, the embodiment of the present application can, when there is no idle register region in the target group of physical registers (the bit width of the register region is the same as the target bit width), determine an alternative group of physical registers with an idle register region in other groups of physical registers whose register region has a bit width greater than or less than the target bit width, thereby using the idle register region in the alternative group of physical registers with a bit width greater than the target bit width, or the multiple register regions with an idle bit width less than the target bit width, as the idle register region.

[0058] For example, when the target group of physical registers does not have an idle register region, the embodiment of the present application may search for an idle register region in other groups of physical registers in the physical register stack in the direction of increasing bit width of the register region, and use the group of physical registers with the idle register region found first as the candidate group of physical registers. For another example, when the target group of physical registers does not have an idle register region, the embodiment of the present application may search for an idle register region in other groups of physical registers in the physical register stack in the direction of decreasing bit width of the register region, and use the group of physical registers with multiple idle register regions found first, whose bit widths can be combined to obtain the target bit width, as the candidate group of physical registers.

[0059] In one example, assuming that the target bit width is 32 bits and there is no idle register region in the target group physical registers whose register region in the physical register file has a bit width of 32, then an embodiment of the present application may search for an idle register region in the physical register group whose register region has a bit width of 64 bits as the idle register region. In other examples, when there is no idle register region in the target group physical registers whose register region has a bit width of 32 bits, an embodiment of the present application may first search for an idle register region in the physical register group whose register region has a bit width of 16 bits. If no idle register region is found, or if an idle register region is found but the idle register region cannot be merged to form a 32-bit register region, then an embodiment of the present application may search for an idle register region in the physical register group whose register region has a bit width of 8 bits.

[0060] Example, continue to combine Figure 3B As shown, when the target bit width is 64 bits, the physical registers numbered 0-15 in the physical register stack are used as the target group physical registers. In the embodiment of the present application, it can be determined whether there is a register area in the current idle state in the first group of physical register groups corresponding to the numbers 0-15. If not, a search is performed in the physical register groups numbered 16-31, 32-47, and 48-63. The register area with an idle state will be found first, and the register areas in the idle state can be merged to obtain a 64-bit physical register group as the candidate group physical register, thereby determining the idle register area from the candidate group physical registers.

[0061] Step S412: Determine a target register region based on the free register region, and allocate the target register region to an architectural register.

[0062] In some embodiments, if the bit width of an idle register area is the same as the target bit width, then the idle register area can be used as the target register area. If the bit width of an idle register area is greater than the target bit width, then the embodiment of the present application needs to further divide the idle register area, for example, using the target bit width as a unit, dividing an idle register area into multiple register areas with the same bit width as the target bit width, thereby using the divided register area as the target register area. If the bit width of an idle register area is less than the target bit width, then the embodiment of the present application needs to merge the multiple idle register areas into a register area with the same bit width as the target bit width after determining the multiple idle register areas, thereby using the merged register area as the target register area.

[0063] For example, the architecture register may be an operation mask register. In other examples, the architecture register may also be a vector register. Of course, the architecture register may also have other forms in the embodiments of the present application, and the embodiments of the present application are not limited to this.

[0064] The register mapping method provided in the embodiment of the present application can set the physical register stack to multiple groups of physical registers, and the unit areas (called register areas) used for register mapping in different groups of physical registers have different bit widths, so that the physical register stack can provide register areas of different bit widths for register mapping, providing a basis for accurately matching the target bit width actually used by the architecture register. Based on this, the embodiment of the present application can determine the target bit width actually used by the architecture register corresponding to the current instruction during the processor processing the current instruction; thereby, based on the target bit width, determine the free register area whose bit width matches the target bit width from the physical register stack; that is, based on the register areas of different bit widths provided by the physical register stack, the embodiment of the present application can determine from the physical register stack a free register area whose bit width is the same as the target bit width, or a free register area whose bit width is greater than the target bit width but can be further divided to obtain the target bit width, or a plurality of free register areas whose bit width can be merged to obtain the target bit width, etc. Furthermore, embodiments of the present application can determine a target register region based on the free register region, so that the bit width of the target register is exactly the target bit width used by the architectural register. By allocating the target register region to the architectural register, a physical register region corresponding to the target bit width actually used can be allocated to the architectural register during the register mapping process, thereby maximizing the utilization of physical register resources. It can be seen that embodiments of the present application can allocate a target register region corresponding to the target bit width actually used by the architectural register to the architectural register, thereby improving the resource utilization of the physical register.

[0065] In order to achieve the mapping between architectural registers and physical registers, it is necessary to determine the free register area that matches the target bit width from the physical register stack, and then determine the target register area based on the free register area, and assign the target register area to the architectural register. Figure 5 An optional flow chart for determining the target register area according to an embodiment of the present application is shown in FIG. Figure 5 , the process may include the following steps.

[0066] Step S521 : Determine a target group of physical registers whose bit width of the register region is the same as the target bit width.

[0067] In some embodiments, the embodiment of the present application can determine a target group of physical registers whose bit width of the register region is the same as the target bit width from multiple groups of physical registers divided by the physical register file. Figure 3B When the target bit width is 32 bits, the target group of physical registers with the same target bit width may be the second group of physical registers corresponding to numbers 16-31 of the register region with a bit width of 32 bits.

[0068] Step S522 , determining whether there is an idle register area in the target group of physical registers; if so, executing step S523 ; otherwise, executing step S524 .

[0069] Step S523: Determine the register area in the idle state as an idle register area.

[0070] Step S524 : Wait for the occupied register area in the target group physical registers to be released, and select a register area in an idle state from the released register areas as an idle register area.

[0071] Step S525: Use the free register area as the target register area.

[0072] In the process of determining the free register region, in an embodiment of the present application, if the target group physical register has a free register region, the free register region is directly used as the free register region, and then the free register region is used as the target register region. If the target group physical register currently does not have a free register region, the occupied register region in the target group physical register can be released, and then a free register region is selected from the released register region as the free register region, and then the free register region is used as the target register region.

[0073] As another optional implementation method for determining the target register area in an embodiment of the present application, when there is no idle register area in the target group physical registers, the embodiment of the present application can search for the alternative group physical registers in the physical register stack, and determine the idle register area from the alternative group physical registers, and further divide or merge the idle register areas in the alternative group physical registers to obtain the target register area. Figure 6 Another optional flow chart for determining the target register area for the embodiment of the present application. Figure 6 , the process may include the following steps.

[0074] Step S631 : Determine a target group of physical registers whose bit width of the register region is the same as the target bit width.

[0075] Step S632: Determine whether there is an idle register area in the target group of physical registers. If so, execute step S633; if not, execute step S634.

[0076] Step S633: Determine the register area in the idle state as an idle register area and use it as the target register area.

[0077] Step S634: Determine a candidate group of physical registers from the multiple groups of physical registers.

[0078] In an embodiment of the present application, when a target group of physical registers currently does not have a register region in an idle state, an alternative group of physical registers can be determined from multiple groups of physical registers, wherein the alternative group of physical registers is a physical register group whose bit width of a register region in a physical register file can form a target bit width and which has a register region in an idle state.

[0079] It should be noted that the candidate group of physical registers can be selected from a physical register group whose register region has a bit width greater than the target bit width, or from a physical register group whose register region has a bit width less than the target bit width. As an optional implementation, when there is currently no idle register region in the target group of physical registers, the embodiment of the present application can search for the candidate group of physical registers whose register region has an idle register region first among the physical registers whose register region has a bit width greater than the target bit width, in the direction of increasing bit width of the register region; or, search for the candidate group of physical registers whose register region has an idle register region first among the physical registers whose register region has a bit width less than the target bit width, in the direction of decreasing bit width of the register region.

[0080] Step S635 : If the bit width of the idle register region of the candidate group of physical registers is smaller than the target bit width, multiple idle register regions in the candidate group of physical registers are merged, and the merged register region is determined as the target register region.

[0081] Step S636: If the bit width of the register region of the candidate group of physical registers is greater than the target bit width, the register region of the candidate group of physical registers is divided to obtain a target register region having the same bit width as the target bit width.

[0082] When the bit width of the register region of the candidate group of physical registers is greater than the target bit width, embodiments of the present application may further divide the bit width of the register region of the candidate group of physical registers, thereby obtaining register regions with the same bit width as the target bit width, and then use the divided register regions as the target register regions. As an optional implementation, embodiments of the present application may divide the register regions selected from the candidate group of physical registers into register regions such that the bit width of the divided register regions is the same as the target bit width; and determine the divided register regions as the target register regions.

[0083] For example, assuming that the target bit width is 32 bits, if an alternative group of physical registers is found in the direction of increasing bit width of the register area, and the bit width of the register area corresponding to the alternative group of physical registers is 64 bits, then the embodiment of the present application can divide the 64-bit free register area in the alternative group of physical registers into two 32-bit wide free register areas, so that one of the 32-bit register areas can be used as the target register area, and the other 32-bit register area can be occupied by other instructions, thereby realizing efficient utilization of physical register resources.

[0084] When the bit width of a register region of the candidate group of physical registers is smaller than the target bit width, embodiments of the present application may merge the bit widths of multiple idle register regions in the candidate group of physical registers, thereby merging to obtain a register region with the same bit width as the target bit width. As an optional implementation, embodiments of the present application may merge multiple idle register regions selected from the candidate group of physical registers, such that the bit width of the merged register region is the same as the target bit width; and the merged register region is determined as the target register region.

[0085] For example, assuming that the target bit width is 32 bits, if an alternative group of physical registers is found in the direction of decreasing bit width of the register area, and the bit width of the register area corresponding to the found alternative group of physical registers is 16 bits, then the two 16-bit wide free register areas in the alternative group of physical registers can be merged into a 32-bit wide register area, and the merged register area can be used as the target register area.

[0086] That is, when the bit width of the register region of the candidate group of physical registers is greater than the target bit width, the register region of the candidate group of physical registers may be divided so that the bit width corresponding to the divided register region is equal to the target bit width; when the bit width of the register region of the candidate group of physical registers is less than the target bit width, the register region of the candidate group of physical registers may be merged so that the bit width corresponding to the merged register region is equal to the target bit width. Furthermore, in embodiments of the present application, the register region of the candidate group of physical registers may be further divided or merged as the target register region, thereby flexibly integrating the resources in the physical registers and improving the resource utilization efficiency of the physical registers.

[0087] Furthermore, if the target group of physical registers does not have an idle register region, then a register region with a bit width selected from the multiple groups of physical registers can be formed into an alternative group of physical registers with the target bit width. In this case, if the alternative group of physical registers also does not have an idle register region, the system can wait until an occupied register region in the target group of physical registers or the alternative group of physical registers is released, and then select an idle register region from the released register region as the idle register region. In some embodiments, whether an occupied register region in the target group of physical registers or the alternative group of physical registers is released, the idle register region can be determined based on the released register region, and the target register region can be determined based on the idle register region.

[0088] After determining the target register area, the embodiment of the present application can assign it to the architectural register in the renaming stage to achieve mapping between the architectural register and the target register area in the physical register. The mapping relationship between the architectural register and the target register area can be stored in the renaming table.

[0089] Figure 7 This is an optional example diagram of a renaming table read result in an embodiment of the present application. The renaming table is used to record the mapping relationship between the target register area and the architectural register. In some embodiments, the renaming table can be set with the physical register number corresponding to the target register area, the architectural register number, and the read identifier of the target register area.

[0090] refer to Figure 7 , the reading result of the renaming table can be as shown in the figure, and accordingly, the reading result includes at least the number of the physical register, the number of the architectural register, and the read identifier of the target register area. In some embodiments, the reading result of the renaming table may also include information such as the target bit width and whether it is the last renaming table entry. In an embodiment of the present application, the read identifier is used to indicate the bit width range of the target register area to read data in the physical register; the bit width range of the read data includes all bit width ranges or part of the bit width range of the physical register.

[0091] The embodiment of the present application can set a read identifier for a register area according to the number of register areas set in a physical register and the bit width range of each register area in the physical register. Figure 7 As shown, when the target bit width is 32, when a physical register is divided into two 32-bit wide register regions, there is an idle register region in the physical register numbered 15 for allocation, and the read identifier can be 01 or 10. The read identifier 01 indicates that the register is divided and the register region of the lower 32 bits of the physical register is read, and the read identifier 10 indicates that the current register is divided and the register region of the upper 32 bits of the physical register is read. In some embodiments, the renaming table includes multiple renaming table entries, and the mapping relationship between the number of an architectural register and the number of a physical register is recorded in a renaming table entry, and the number of an architectural register is mapped to the numbers of one or more physical registers through one or more renaming table entries.

[0092] When mapping an architectural register to a rename table entry, identification data may be set for the last rename table entry corresponding to the architectural register number in the rename table, so that the identification data indicates the last rename table entry corresponding to the architectural register number when searching the rename table; the last rename table entry records at least the number of the last physical register mapped to the architectural register number. The identification data may be set in the last rename table entry to distinguish the current rename table entry as the last one in the rename table.

[0093] This application provides a method for facilitating the search for a mapping relationship between an architectural register and a register region in a physical register by setting a read identifier in the renaming table, while dynamically selecting a physical architectural register of a corresponding bit width for allocation. This method also ensures accurate mapping between the architectural register and the physical register. Identification data is also provided in the renaming table entry so that, when searching the renaming table, the identification data indicates the last renaming table entry corresponding to the architectural register number, further ensuring accurate mapping between the architectural register in the renaming table and the target physical register region.

[0094] The present application also provides a processor, the structure of which can refer to Figure 1 , the processor includes at least:

[0095] The decode unit is used to determine the target bit width of the architectural register used by the current instruction;

[0096] a renaming unit, configured to determine, from a physical register file, a free register region whose bit width matches a target bit width; determine a target register region based on the free register region, and assign the target register region to an architectural register;

[0097] A physical register stack includes multiple groups of physical registers. A register region is a unit region in a physical register used for register mapping, and register regions corresponding to different groups of physical registers have different bit widths.

[0098] In some embodiments, the bit width of a register region corresponding to a group of physical registers is adapted to a required bit width of an architectural register, and the architectural register has multiple required bit widths; the multiple required bit widths include a maximum bit width of the physical register and at least one sub-bit width divided by the maximum bit width; the bit widths of register regions corresponding to different groups of physical registers are divided from large to small starting from the maximum bit width according to the group order of the multiple groups of physical registers.

[0099] In some embodiments, the renaming unit, for determining, from the physical register file, a free register region whose bit width matches the target bit width, may include:

[0100] A target group of physical registers is determined from the plurality of groups of physical registers, wherein the bit width of the register region is the same as the target bit width; and a register region in an idle state is selected from the target group of physical registers as the idle register region.

[0101] In some embodiments, the renaming unit, configured to determine the target register region based on the free register region, comprises: using the free register region as the target register region.

[0102] In some embodiments, the renaming unit is configured to select a register region in an idle state from the target group of physical registers as the idle register region, which may include:

[0103] If there is no idle register region in the target group physical register, wait for the occupied register region in the target group physical register to be released, and then select an idle register region from the released register region as the idle register region.

[0104] In some embodiments, the renaming unit, configured to determine, from a physical register file, a free register region whose bit width matches the target bit width, may include:

[0105] A target group of physical registers having a register region with the same bit width as a target bit width is determined from multiple groups of physical registers; if the target group of physical registers currently does not have a register region in an idle state, an alternative group of physical registers having a register region in an idle state is determined to form the target bit width from the multiple groups of physical registers; and an idle register region is selected from the alternative group of physical registers as the idle register region.

[0106] In some embodiments, the renaming unit is configured to determine the bit width of a register region from multiple groups of physical registers to form a target bit width, and the candidate group of physical registers for the register region having an idle state may include: searching, in a direction of increasing bit width of the register region, for the candidate group of physical registers for the register region having an idle state first among the physical registers of the register region having a bit width greater than the target bit width.

[0107] In some embodiments, the renaming unit is used to determine the target register area based on the free register area, including: dividing the register area in the free state selected from the candidate group of physical registers into register areas so that the bit width of the divided register area is the same as the target bit width; and determining the divided register area as the target register area.

[0108] In some embodiments, the renaming unit is configured to determine the bit width of a register region from multiple groups of physical registers to form a target bit width, and the candidate group of physical registers for the register region having an idle state may include: searching, in a direction of decreasing bit width of the register region, for the candidate group of physical registers for the register region having an idle state first among the physical registers of the register region having a bit width smaller than the target bit width.

[0109] In some embodiments, the renaming unit, for determining the target register region based on the free register region, may include: merging multiple free register regions selected from the candidate group of physical registers so that the bit width of the merged register region is the same as the target bit width; and determining the merged register region as the target register region.

[0110] In some embodiments, the renaming unit may also be used to:

[0111] If the target group of physical registers currently does not have an idle register area, and the bit widths of the register areas in the multiple groups of physical registers form the target bit width of the alternative group of physical registers. After the occupied register area in the target group of physical registers or the alternative group of physical registers is released, an idle register area is selected from the released register area as the idle register area.

[0112] In some embodiments, the renaming unit is configured to allocate the target register region to the architectural register, comprising: establishing a mapping relationship between the target register region and the architectural register in the renaming table.

[0113] In some embodiments, the renaming unit is configured to establish a mapping relationship between a target register region and an architectural register in a renaming table, and the mapping relationship between the target register region and the architectural register may include:

[0114] Establishing a mapping relationship between the physical register number corresponding to the target register area and the architectural register number in the renaming table, and setting a read flag for the target register area;

[0115] The read identifier is used to indicate the bit width range of the target register region for reading data in the physical register; the bit width range includes all bit width ranges or part of the bit width range of the physical register.

[0116] In some embodiments, the renaming table includes multiple renaming table entries, a mapping relationship between an architectural register number and a physical register number is recorded in one renaming table entry, and an architectural register number is mapped to one or more physical register numbers through one or more renaming table entries; further, the renaming unit may also be used to:

[0117] Determine the last rename table entry corresponding to the number of the architectural register, and set identification data for the last rename table entry in the rename table so that the identification data can be used to indicate the last rename table entry corresponding to the number of the architectural register when searching the rename table; the last rename table entry at least records the number of the last physical register mapped to the number of the architectural register.

[0118] The present application also provides a chip in an embodiment, which may include the processor core described above. The functions of the hardware components in the processor core may refer to the description of the corresponding parts above.

[0119] An embodiment of the present application also provides an electronic device, which may include the above-mentioned chip; the electronic device may be a terminal device or a cloud server device.

[0120] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0121] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A register mapping method, characterized in that: include: Determine the target bit width actually used by the architecture register corresponding to the current instruction; Determining, from a physical register file, an idle register region whose bit width matches the target bit width; wherein the physical register file includes multiple groups of physical registers, one group of physical registers includes multiple physical registers, and one physical register uses a register region as a unit region of register mapping, the register region being a unit region used for register mapping in the physical register, and register regions corresponding to different groups of physical registers have different bit widths; the bit width of the register region corresponding to one group of physical registers is compatible with a required bit width of an architecture register, the architecture register has multiple required bit widths, and the physical register file is divided into multiple groups of physical registers based on the multiple required bit widths of the architecture register; A target register region is determined based on the free register region, and the target register region is allocated to the architectural register.

2. The register mapping method according to claim 1, wherein: The multiple required bit widths include a maximum bit width of the physical register and at least one sub-bit width divided by the maximum bit width; the bit widths of the register areas corresponding to different groups of physical registers are divided from large to small starting from the maximum bit width according to the group order of the multiple groups of physical registers.

3. The register mapping method according to claim 1, wherein: Determining a free register area whose bit width matches the target bit width from the physical register file includes: Determine a target group of physical registers from the plurality of groups of physical registers, wherein the bit width of the register region is the same as the target bit width; Selecting an idle register area from the target group of physical registers as the idle register area; Determining the target register area based on the free register area includes: The free register area is used as the target register area.

4. The register mapping method according to claim 3, wherein: The selecting an idle register area from the target group of physical registers as the idle register area includes: If the target group of physical registers currently does not have an idle register area, wait until the occupied register area in the target group of physical registers is released, and then select an idle register area from the released register areas as the idle register area.

5. The register mapping method according to claim 1, wherein: Determining a free register area whose bit width matches the target bit width from the physical register file includes: Determine a target group of physical registers from the plurality of groups of physical registers, wherein the bit width of the register region is the same as the target bit width; If the target group of physical registers currently does not have a register region in an idle state, determining a bit width of a register region from the multiple groups of physical registers to form the target bit width, and an alternative group of physical registers has a register region in an idle state; A register region in an idle state is selected from the candidate group of physical registers as the idle register region.

6. The register mapping method according to claim 5, wherein: The step of determining the bit width of a register region from the plurality of groups of physical registers to form the target bit width, wherein a candidate group of physical registers having an idle register region includes: Searching, in the physical registers of the register region whose bit width is greater than the target bit width, for the candidate group of physical registers of the register region that is first in an idle state, in the direction of increasing bit width of the register region; Determining the target register area based on the free register area includes: The register area in the idle state selected from the candidate group of physical registers is divided into register areas so that the bit width of the divided register area is the same as the target bit width; and the divided register area is determined as the target register area.

7. The register mapping method according to claim 5, wherein: The step of determining the bit width of a register region from the plurality of groups of physical registers to form the target bit width, wherein a candidate group of physical registers having an idle register region includes: Searching, in a direction of decreasing bit widths of the register regions, for a candidate group of physical registers of the register region that is first in an idle state among the physical registers of the register region whose bit widths are smaller than the target bit width; Determining the target register area based on the free register area includes: Merging a plurality of idle register regions selected from the candidate group of physical registers so that the bit width of the merged register region is the same as the target bit width; and determining the merged register region as the target register region.

8. The register mapping method according to claim 5, wherein: Also includes: If the target group of physical registers currently does not have an idle register area, and the alternative group of physical registers whose register area bit widths form the target bit width also does not have an idle register area, then wait until the occupied register area in the target group of physical registers or the alternative group of physical registers is released, and then select an idle register area from the released register area as the idle register area.

9. The register mapping method according to any one of claims 1 to 8, wherein: Allocating the target register region to the architectural registers comprises: A mapping relationship between the target register area and the architecture register is established in a renaming table.

10. The register mapping method according to claim 9, wherein: The establishing of the mapping relationship between the target register area and the architecture register in the renaming table includes: Establishing a mapping relationship between the physical register number corresponding to the target register area and the architectural register number in the renaming table, and setting a read flag of the target register area; The read identifier is used to indicate a bit width range of data read from the target register region in the physical register; the bit width range includes the entire bit width range or a portion of the bit width range of the physical register.

11. The register mapping method according to claim 10, wherein: The renaming table includes a plurality of renaming table entries, a mapping relationship between an architectural register number and a physical register number is recorded in one renaming table entry, and an architectural register number is mapped to one or more physical register numbers through one or more renaming table entries; the method further includes: Determine the last rename table entry corresponding to the number of the architecture register, and set identification data for the last rename table entry in the rename table so that the last rename table entry corresponding to the number of the architecture register is indicated by the identification data when searching the rename table; the last rename table entry at least records the number of the last physical register mapped to the number of the architecture register.

12. A processor, characterized in that: include: The decode unit is used to determine the target bit width of the architectural register used by the current instruction; a renaming unit, configured to determine, from a physical register file, a free register region whose bit width matches the target bit width; determine a target register region based on the free register region, and allocate the target register region to the architectural register; A physical register stack, wherein the physical register stack includes multiple groups of physical registers, each group of physical registers having multiple physical registers, and each physical register uses a register area as a unit area of ​​register mapping, the register area being a unit area used for register mapping in the physical register, and the register areas corresponding to different groups of physical registers having different bit widths; the bit width of the register area corresponding to a group of physical registers is adapted to a required bit width of an architecture register, the architecture register having multiple required bit widths, and the multiple groups of physical registers are obtained by dividing the physical register stack based on the multiple required bit widths of the architecture register.

13. The processor according to claim 12, wherein: The multiple required bit widths include a maximum bit width of the physical register and at least one sub-bit width divided by the maximum bit width; the bit widths of the register areas corresponding to different groups of physical registers are divided from large to small starting from the maximum bit width according to the group order of the multiple groups of physical registers.

14. A chip, characterized in that: The method comprises a processor as claimed in any one of claims 12 to 13.

15. An electronic device, characterized in that: Comprising the chip as claimed in claim 14.

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