Electronic device and method for accelerating memory access

Abstract

An electronic device includes a memory and an integrated circuit. The memory includes multiple memory pages. The integrated circuit sequentially converts multiple virtual addresses into multiple physical addresses according to a mapping table. The integrated circuit includes an address remapping unit. When the multiple physical addresses corresponding to the multiple virtual addresses are not in the same memory page in the memory, the address remapping unit pre-accesses at least one physical address among the multiple physical addresses that does not belong to the same memory page based on whether the multiple virtual addresses currently accessed in sequence exceed the pre-fetch address.

Description

Technical Field

[0001] The present invention relates to electronic devices, and in particular to electronic devices and methods for accelerating memory access. Background Art

[0002] In computer systems, the transmission efficiency and speed of direct memory access (DMA) instructions are directly related to the performance of IO devices. In systems that support hardware virtualization, the transmission of each DMA instruction requires the participation of remapping hardware to complete the conversion of virtual addresses to physical addresses. To improve efficiency, a cache is set up in the remapping hardware. Once a cache miss occurs, the remapping hardware needs to access the memory multiple times. In the existing architecture, the first DMA instruction of each 4K bytes (corresponding to the size of each memory page) may cause a cache miss. Summary of the Invention

[0003] An electronic device according to an embodiment of the present invention includes a memory and an integrated circuit. The memory includes a plurality of memory pages. The integrated circuit sequentially converts a plurality of virtual addresses into a plurality of physical addresses according to a mapping table. The integrated circuit includes an address remapping unit. When the plurality of physical addresses corresponding to the plurality of virtual addresses are not in the same memory page in the memory, at least one physical address among the plurality of physical addresses that does not belong to the same memory page is pre-accessed based on whether the plurality of virtual addresses currently being sequentially accessed exceed a pre-fetched address.

[0004] In the electronic device as described above, when the multiple virtual addresses currently accessed sequentially exceed the prefetch address, the integrated circuit outputs a remapping prefetch instruction to the address remapping unit, so that the address remapping unit stores at least one physical address among the multiple physical addresses that does not belong to the same storage page in its own cache and updates the mapping table.

[0005] In the electronic device as described above, when the address remapping unit accesses one of the multiple virtual addresses corresponding to at least one physical address that does not belong to the same storage page, the address remapping unit directly outputs the at least one physical address that does not belong to the same storage page among the multiple physical addresses stored in the cache based on the updated mapping table.

[0006] The electronic device as described above further includes a central processing unit, which accesses the memory according to the multiple physical addresses corresponding to the multiple virtual addresses.

[0007] The electronic device further includes an external device that transmits an access request instruction to the integrated circuit. When the integrated circuit receives the access request instruction, the integrated circuit transmits a remapping instruction to the address remapping unit. Both the access request instruction and the remapping instruction include the plurality of virtual addresses.

[0008] In the electronic device described above, after the address remapping unit converts the plurality of virtual addresses into the plurality of physical addresses according to the updated mapping table, the address remapping unit transmits a remapping response instruction to the integrated circuit. Upon receiving the remapping response instruction, the integrated circuit transmits a direct memory access (DMA) instruction to the central processing unit. Both the remapping response instruction and the DMA instruction include the plurality of physical addresses.

[0009] In the electronic device described above, the size of each of the plurality of memory pages of the memory is 4K bytes, and the pre-fetch address is 4K+400, 4K+600, 4K+800, 4K+a00, 4K+c00, or 4K+e00 bytes.

[0010] In the electronic device described above, the pre-fetch address is set accordingly according to the read latency of the memory.

[0011] According to an embodiment of the present invention, a method for accelerating memory access includes multiple pages, and the method includes: receiving multiple virtual addresses; converting the multiple virtual addresses into multiple physical addresses in sequence according to a mapping table; when the multiple physical addresses corresponding to the multiple virtual addresses are not in the same memory page in the memory, pre-accessing at least one physical address among the multiple physical addresses that does not belong to the same memory page according to whether the multiple virtual addresses currently accessed in sequence exceed the pre-fetch address.

[0012] The acceleration method as described above also includes: when the multiple virtual addresses currently accessed sequentially exceed the prefetch address, generating a remapping prefetch instruction; based on the remapping prefetch instruction, storing at least one physical address among the multiple physical addresses that does not belong to the same storage page in a cache, and updating the mapping table.

[0013] The acceleration method as described above also includes: when accessing one of the multiple virtual addresses corresponding to at least one physical address that does not belong to the same storage page, directly outputting at least one physical address that does not belong to the same storage page among the multiple physical addresses stored in the cache according to the updated mapping table. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the present invention.

[0015] Figure 2 For the embodiment of the present invention Figure 1 A timing waveform diagram of signals when the electronic device 100 is operating.

[0016] Figure 3 Flowchart of a method for accelerating memory access according to an embodiment of the present invention.

[0017] Figure 4 For the embodiment of the present invention Figure 3 Detailed flowchart of step S304. DETAILED DESCRIPTION

[0018] The present invention is described with reference to the accompanying drawings, in which like reference numerals throughout the drawings designate similar or identical components. The drawings are not drawn to scale and are provided solely to illustrate the present invention. Some embodiments of the invention are described below as references to illustrative applications. This means that many specific details, relationships, and methods are set forth to provide a complete understanding of the invention. However, a person having ordinary skill in the relevant art will recognize that the invention can still be practiced without one or more of the specific details or with alternative methods.

[0019] In other examples, well-known structures or operations are not described in detail to avoid obscuring the present invention. The present invention is not limited by the order of the acts or events described; some acts may occur in a different order or concurrently with other acts or events. Furthermore, not all acts or events described need to be performed in the same manner as in the prior invention.

[0020] Figure 1 FIG is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 100 includes an integrated circuit 102, a memory 104, a central processing unit 106, and an external device 108. In some embodiments, the memory 104 includes multiple memory pages, and the size of each memory page is 4K bytes. The integrated circuit 102 sequentially converts the multiple virtual addresses carried in the access request instruction 170 from the external device 108 into multiple physical addresses according to the mapping table, and transmits the converted physical addresses to the central processing unit 106 through the direct memory access (DMA) instruction 150. Thereafter, the central processing unit 106 writes or reads the multiple physical addresses in the memory 104 through the access interface 160. In another embodiment of the present invention, the integrated circuit 102 can be a north bridge chip or a chipset that integrates a north bridge chip.

[0021] Due to the limitation of the size of each memory page of the memory 104 (e.g., 4K bytes), the physical addresses (i.e., address values) included in each memory page in the memory 104 do not exceed 4K bytes. Generally speaking, the minimum unit for accessing (e.g., reading or writing) a physical address in the memory 104 is a memory page. In other words, even if the memory 104 receives (e.g., from the central processing unit 106) an access instruction for multiple physical addresses therein, as long as the multiple physical addresses are set in the same memory page in the memory 104, the central processing unit 106 only needs to access once to read out all the data in the multiple physical addresses in the same memory page in the memory 104. On the contrary, if the multiple physical addresses in the access instruction are set in different memory pages in the memory 104, the central processing unit 106 needs to access at least twice to read out the data in the multiple physical addresses in the memory 104.

[0022] In some embodiments, a mapping table within integrated circuit 102 records the correspondence between virtual addresses and physical addresses in units of memory pages of memory 104. Because virtual addresses and physical addresses of memory 104 correspond to each other (via the mapping table), the virtual address (i.e., the address value) corresponding to the physical address of each memory page in memory 104 also does not exceed 4K bytes. In some embodiments, integrated circuit 102 includes an address remapping unit 110, and address remapping unit 110 includes a cache 114. Central processing unit 106 includes a direct memory access (DMA) controller to assist central processing unit 106 in processing DMA instructions to avoid occupying computing resources of central processing unit 106.

[0023] In some embodiments, the electronic device 100 may be, for example, a laptop computer, a desktop computer, a tablet computer, a smart mobile device, or a workstation server. In some embodiments, the integrated circuit 102, the memory 104, and the central processing unit 106 are each provided within the electronic device 100 in the form of independent chips. In some embodiments, the integrated circuit 102, the memory 104, and the central processing unit 106 are provided in the same integrated chip, such as a system-on-a-chip (SoC), but the present invention is not limited thereto. The external device 108 may be any functional chip that can communicate with the central processing unit 106 (e.g., through the integrated circuit 102) via its input and output ports. In some embodiments, the memory 104 is a non-volatile memory.

[0024] like Figure 1As shown, an external device 108 transmits an access request instruction 170 containing multiple virtual addresses to the integrated circuit 102. Upon receiving the virtual addresses contained in the access request instruction 170, the integrated circuit 102 transmits a corresponding remapping instruction 130 to the address remapping unit 110. In other words, the remapping instruction 130 also carries the virtual addresses from the access request instruction 170. When the physical addresses corresponding to the virtual addresses are not in the same memory page in the memory 104, the address remapping unit 110 pre-accesses at least one physical address that does not belong to the same memory page, based on whether the currently accessed virtual address exceeds the pre-fetched address.

[0025] Figure 2 For the embodiment of the present invention Figure 1 The signal timing waveform diagram when the electronic device 100 is operating. Figure 1 , Figure 2 The timing waveforms of the clock signal (CLK), the access request instruction 170, the virtual address 170-VA, the remapping instruction 130, the virtual address 130-VA, the remapping prefetch instruction 120, the remapping reply instruction 140, the physical address 140-PA, the direct memory access (DMA) instruction 150, and the physical address 150-PA are shown. Figure 2 As shown, at time t1, external device 108 transmits an access request command 170 containing multiple virtual addresses to integrated circuit 102. Therefore, access request command 170 maintains a high voltage level from time t1 until five clock cycles after time t1. Accordingly, access request command 170 contains virtual addresses 170-VA. Virtual addresses 170-VA, for example, include virtual address 1, virtual address 2, virtual address 3, virtual address 4, and virtual address 5, sequentially arranged from time t1.

[0026] In some embodiments, virtual address 1 may be, for example, VA[x:12]+offset1[11:0], virtual address 2 may be, for example, VA[x:12]+offset2[11:0], virtual address 3 may be, for example, VA[x:12]+offset3[11:0], virtual address 4 may be, for example, VA[x:12]+offset4[11:0], and virtual address 5 may be, for example, VA[x:12]+4K+offset5[11:0]. Based on the address values ​​of virtual addresses 1-5, the physical addresses corresponding to virtual addresses 1, 2, 3, and 4 are all in the same memory page in memory 104 (because the address value is the same as VA[x:12]), for example, the first page. The physical address corresponding to virtual address 5 is in the next page of the first page corresponding to virtual addresses 1-4 (because the address value is VA[x:12]+4K), for example, the second page. Offset1[11:0], offset2[11:0], offset3[11:0], and offset4[11:0] represent the byte differences between virtual addresses 1-4 and the start byte of the first page in memory 104. Offset5[11:0] represents the byte difference between virtual address 5 and the start byte of the second page in memory 104. In simple terms, the physical addresses corresponding to virtual addresses 1-4 are located in the same memory page in memory 104, while the physical address corresponding to virtual address 5 is located in another memory page in memory 104.

[0027] After receiving the access request 170 from the external device 108, the integrated circuit 102 transmits a remapping instruction 130 to the address remapping unit 110 at time t2, time t3, and time t4, respectively. The integrated circuit 102 first determines, based on the address values ​​of virtual addresses 1-5, whether the physical addresses corresponding to virtual addresses 1-5 are all located in the same memory page of the memory 104. Therefore, the integrated circuit 102 determines that the physical addresses corresponding to virtual addresses 1-4 are located in the same memory page of the memory 104, while the physical address corresponding to virtual address 5 is located in another memory page of the memory 104. Since the integrated circuit 102 already knows that the physical addresses corresponding to virtual addresses 1-4 are located in the same memory page of the memory 104, the remapping instruction 130 transmitted at time t2 only carries virtual address 1. In other words, by accessing the memory page corresponding to the physical address corresponding to virtual address 1, the contents of the physical addresses corresponding to virtual addresses 2-4 can be obtained simultaneously.

[0028] At time t3, since the virtual address currently being accessed by the address remapping unit 110 exceeds the prefetch address, the integrated circuit 102 generates a remapping prefetch instruction 120 and transmits the remapping prefetch instruction 120 to the address remapping unit 110. The address remapping unit 110 receives the remapping prefetch instruction 120 from the integrated circuit 102. Since the physical address corresponding to virtual address 5 and the physical address corresponding to virtual addresses 1 to 4 are located in different memory pages, at time t3 Figure 2 In the waveform of virtual address 130-VA, the virtual address carried in remapping instruction 130 is virtual address 5. Therefore, the address remapping unit 110 can pre-access the physical address corresponding to virtual address 5. In other words, at time t3, the integrated circuit 102 transmits the remapping prefetch instruction 120 and the remapping instruction 130 carrying virtual address 5, allowing the address remapping unit 110 to pre-access the physical address corresponding to virtual address 5 in the memory 104.

[0029] In some embodiments, while referring to Figure 1 、 Figure 2 , the address remapping unit 110 can directly access the physical address corresponding to the virtual address 5 in the memory 104 with the assistance of the DMA controller 112 of the central processing unit 106, and the DMA controller 112 transmits the accessed data to the address remapping unit 110 through the communication interface 180. In some embodiments, the prefetch address is 4K+400, 4K+600, 4K+800, 4K+a00, 4K+c00, or 4K+e00 bytes. For example, assuming the default address is 4K+600, when Figure 2 At time t3, the virtual address being accessed by the address remapping unit 110 has an address value of 4K+700. Since the address value of the virtual address being accessed by the address remapping unit 110 exceeds the prefetch address 4K+600, the integrated circuit 102 transmits the remap prefetch instruction 120 to the address remapping unit 110. In some embodiments, the prefetch address is set accordingly based on the read latency of the memory 104.

[0030] In some embodiments, the prefetch address may be set by the system software of the electronic device 100 during startup, for example, in the BIOS, but the present invention is not limited thereto. In some embodiments, when the read latency of the memory 104 is shorter, a smaller prefetch address (e.g., 4K+400) may be set. When the read latency of the memory 104 is longer, a larger prefetch address (e.g., 4K+e00) may be set.

[0031] The address remapping unit 110 stores the physical address corresponding to the virtual address 5 in its own cache 114 and updates the mapping table. In other words, the address remapping unit 110 adds the virtual address 5 and its corresponding physical address to the original mapping table. Figure 2 At time t4, the address remapping unit 110 accesses virtual address 5. After a period of virtual address to physical address conversion time, the address remapping unit 110 outputs physical address 1 corresponding to virtual address 1 to the integrated circuit 102 via the remapping response instruction 140 at time t5. Since the physical addresses 2-4 corresponding to virtual addresses 2-4 are in the same memory page of the memory 104 as physical address 1, the data of physical addresses 2-4 does not need to be included in the remapping response instruction 140. At time t6, the address remapping unit 110 directly outputs the physical address 5 corresponding to virtual address 5, which has been stored in the cache 114, to the integrated circuit 102 via the remapping response instruction 140 based on the updated mapping table.

[0032] At time t7, the integrated circuit 102 transmits a direct memory access (DMA) instruction 150 to the central processing unit 106. Figure 2 As shown, from time point t7 to the following five clock cycles, the direct memory access instruction 150 carries a physical address 150-PA, which sequentially includes physical address 1 corresponding to virtual address 1, physical address 2 corresponding to virtual address 2, physical address 3 corresponding to virtual address 3, physical address 4 corresponding to virtual address 4, and physical address 5 corresponding to virtual address 5. In some embodiments, the address value of physical address 1 may be, for example, PA1[y:12]+offset1[11:0], the address value of physical address 2 may be, for example, PA1[y:12]+offset2[11:0], the address value of physical address 3 may be, for example, PA1[y:12]+offset3[11:0], the address value of physical address 4 may be, for example, PA1[y:12]+offset4[11:0], and the address value of physical address 5 may be, for example, PA2[y:12]+offset5[11:0].

[0033] Similarly, based on the address values ​​of physical addresses 1-5, physical addresses 1-4 are located in the same memory page of memory 104 (e.g., PA1[y:12]), while physical address 5 is located in another memory page of memory 104 (e.g., PA2[y:12]). Offset1[11:0], Offset2[11:0], Offset3[11:0], and Offset4[11:0] represent the byte difference between physical addresses 1-4 and the starting byte of the same memory page in memory 104. Offset5[11:0] represents the byte difference between physical address 5 and the starting byte of another memory page in memory 104.

[0034] At this point, the integrated circuit 102 successfully converts the virtual addresses 1-5 of the access request instruction 170 from the external device 108 into physical addresses 1-5, and transmits the physical addresses 1-5 to the central processing unit 106 via the direct memory access instruction 150, so that the central processing unit 106 can access the physical addresses 1-5 of the memory 104. Figure 2 In an embodiment, the time point (e.g., time point t3) at which the address remapping unit 110 receives the remapping prefetch instruction 120 must be earlier than the time point (e.g., time point t4) at which the address remapping unit 110 accesses the virtual address 5, otherwise a cache miss of the address remapping unit 110 will occur.

[0035] It is worth noting that in Figure 2 In the embodiment, although the address remapping unit 110 receives the remapping prefetch instruction 120 from the integrated circuit 102 at time point t3, the address remapping unit 110 does not transmit a reply instruction based on the remapping prefetch instruction 120 back to the integrated circuit 102. This is because the remapping prefetch instruction 120 is not a real instruction. Even so, the address remapping unit 110 will still store the physical address 5 corresponding to the virtual address 5 in the cache 114 in advance according to the remapping prefetch instruction 120, so that the address remapping unit 110 will not need to store the physical address 5 corresponding to the virtual address 5 in the cache 114 when accessing the virtual address 5 in the remapping instruction 130 (for example, Figure 2 At time point t4 ), the physical address 5 already stored in the cache 114 can be quickly transmitted back to the integrated circuit 102 via the remapping reply instruction 140 .

[0036] Furthermore, in some embodiments, since the remapping prefetch instruction 120 does not include actual memory address information, the system software of the electronic device 100 does not set the mapping table based on the remapping prefetch instruction 120. In other words, the system software of the electronic device 100 only sets or updates the mapping table based on the access request instruction 170, the remapping instruction 130, the remapping response instruction 140, and the direct memory access instruction 150.

[0037] Figure 3 Flowchart of a method for accelerating memory access according to an embodiment of the present invention. Figure 3 The memory access acceleration method is used to improve Figure 1 The access efficiency of the integrated circuit 102 to the memory 104 is improved. Figure 3 As shown, the memory access acceleration method of the embodiment of the present invention includes receiving a plurality of virtual addresses (step S300); converting the virtual addresses into a plurality of physical addresses in sequence according to a mapping table (step S302); and when the physical addresses corresponding to the virtual addresses are not in the same memory page in the memory, pre-accessing at least one physical address in the physical addresses that does not belong to the same memory page according to whether the virtual address currently accessed in sequence exceeds the pre-fetch address (step S304).

[0038] In some embodiments, Figure 1 The integrated circuit 102 performs Figure 2 Step S300, Figure 1 The address remapping unit 110 (or integrated circuit 102) performs Figure 2 Step S302, and Figure 1 The address remapping unit 110 executes step S304.

[0039] Figure 4 For the embodiment of the present invention Figure 3 Detailed flow chart of step S304. Figure 4 As shown, in Figure 3 In step S304, the memory access acceleration method of the embodiment of the present invention further includes generating a remapping prefetch instruction (for example, Figure 2 At time t3, a remapping prefetch instruction 120 is generated (step S400); according to the remapping prefetch instruction, at least one physical address that does not belong to the same memory page is stored in a cache, and a mapping table is updated (step S402); and when a virtual address corresponding to the at least one physical address that does not belong to the same memory page is accessed (for example, at Figure 2 At time point t4, virtual address 5 is accessed, and at least one physical address that does not belong to the same storage page among the physical addresses stored in the cache is directly output according to the updated mapping table (for example, at Figure 2 Output physical address 5 at time point t6) (step S404).

[0040] In some embodiments, Figure 1 The integrated circuit 102 performs Figure 4 Step S400, Figure 1 The address remapping unit 110 performs Figure 4Step S402 and step S404.

[0041] The electronic device 100 and memory access acceleration method of the present invention can improve the efficiency of large data transmission throughout the entire system and have the following characteristics: 1. The timing of generating the remapped prefetch instruction 120, i.e., the timing of executing the prefetch operation by the address remapping unit 110, is controllable and can be freely adjusted according to different system conditions (e.g., in conjunction with the read latency of the memory 104). 2. When an error occurs in the remapped prefetch instruction 120, the address remapping unit 110 must ignore the occurrence of the error. In other words, the address remapping unit 110 must discard the erroneous remapped prefetch instruction 120 and must not output an error report to the system software.

[0042] Although embodiments of the present invention have been described above, it should be understood that these are presented by way of example only and not limitation. Many variations of the exemplary embodiments described above may be implemented without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. Rather, the scope of the present invention is defined by the following claims and their equivalents.

[0043] Although the invention has been illustrated and described above with reference to one or more embodiments, equivalent changes and modifications will occur to others skilled in the art based on the above specification and drawings. In addition, although particular features of embodiments of the invention have been demonstrated with reference to one of the multiple embodiments, those features may be combined with one or more other features as may be desirable and useful for any known or particular application.

[0044] Unless otherwise defined, all terms used herein (including technical or scientific terms) are generally understood by persons skilled in the art to which the present invention pertains. It should be understood that these terms, as defined in commonly used dictionaries, should be interpreted in the context of the relevant art. Unless otherwise specifically defined herein, these terms are not to be interpreted in an idealized or overly formal sense.

Claims

1. An electronic device comprising: a memory including a plurality of memory pages; The integrated circuit converts the plurality of virtual addresses into a plurality of physical addresses in sequence according to the mapping table; The integrated circuit includes: The address remapping unit pre-accesses at least one physical address of the plurality of physical addresses that does not belong to the same memory page according to whether the plurality of virtual addresses currently accessed sequentially exceed the pre-fetch address when the plurality of physical addresses corresponding to the plurality of virtual addresses are not in the same memory page in the memory, When the multiple virtual addresses currently accessed sequentially exceed the prefetch address, the integrated circuit outputs a remapping prefetch instruction to the address remapping unit, so that the address remapping unit stores at least one physical address among the multiple physical addresses that does not belong to the same storage page in its own cache and updates the mapping table.

2. The electronic device according to claim 1, wherein When the address remapping unit accesses one of the multiple virtual addresses corresponding to the at least one physical address that does not belong to the same storage page, the address remapping unit directly outputs the at least one physical address that does not belong to the same storage page among the multiple physical addresses stored in the cache according to the updated mapping table. 3 . The electronic device as claimed in claim 1 , further comprising a central processing unit, configured to access the memory according to the plurality of physical addresses corresponding to the plurality of virtual addresses.

4. The electronic device as claimed in claim 3, further comprising an external device that transmits an access request instruction to the integrated circuit; when the integrated circuit receives the access request instruction, the integrated circuit transmits a remapping instruction to the address remapping unit; wherein, The access request instruction and the remapping instruction both include the plurality of virtual addresses.

5. The electronic device according to claim 4, wherein: After the address remapping unit converts the multiple virtual addresses into the multiple physical addresses according to the updated mapping table, the address remapping unit transmits a remapping response instruction to the integrated circuit; when the integrated circuit receives the remapping response instruction, the integrated circuit transmits a direct memory access instruction to the central processing unit; wherein, the remapping response instruction and the direct memory access instruction both include the multiple physical addresses.

6. The electronic device according to claim 1, wherein The size of each of the plurality of memory pages of the memory is 4K bytes; the pre-fetch address is 4K+400, 4K+600, 4K+800, 4K+a00, 4K+c00, or 4K+e00 bytes.

7. The electronic device according to claim 6, wherein: The pre-fetch address is set accordingly according to the read latency of the memory.

8. A method for accelerating memory access, wherein the memory includes a plurality of pages, the method comprising: Receive multiple virtual addresses; Converting the plurality of virtual addresses into a plurality of physical addresses in sequence according to the mapping table; When the multiple physical addresses corresponding to the multiple virtual addresses are not in the same memory page in the memory, pre-accessing at least one physical address of the multiple physical addresses that does not belong to the same memory page according to whether the multiple virtual addresses currently accessed in sequence exceed the pre-fetch address; When the plurality of virtual addresses currently accessed sequentially exceed the prefetch address, generating a remapping prefetch instruction; as well as According to the remapping prefetch instruction, the at least one physical address that does not belong to the same memory page among the plurality of physical addresses is stored in a cache, and the mapping table is updated.

9. The acceleration method according to claim 8, further comprising: When accessing one of the multiple virtual addresses corresponding to the at least one physical address that does not belong to the same storage page, the at least one physical address that does not belong to the same storage page among the multiple physical addresses stored in the cache is directly output according to the updated mapping table.

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