Matrix calculation circuit, method, electronic device and computer readable storage medium

Abstract

The embodiment of the present disclosure discloses a matrix calculation circuit, method, electronic device and computer readable storage medium. The matrix calculation circuit comprises: an instruction decoding circuit, configured to decode a matrix calculation instruction; a first data reading circuit, configured to read the first data, and read an address to read bitmap data; a control signal generation circuit, configured to generate a second data reading control signal according to the bitmap data; a second data reading circuit, configured to generate a reading address of second data according to the second data reading control signal; read the second data; and a calculation circuit, configured to calculate third data according to the first data and the second data. The matrix calculation circuit generates the reading address of the second data through the bitmap data, reduces the reading quantity and calculation quantity of the second data, and solves the technical problem of wasting bandwidth in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of processors, and more particularly to a matrix computing circuit, method, electronic device, and computer-readable storage medium. Background Technology

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. A key characteristic of the intelligent era is the increasing variety and volume of data people acquire, coupled with ever-growing demands for faster data processing. Chips are the cornerstone of task allocation, fundamentally determining our data processing capabilities. From an application perspective, chips mainly follow two paths: one is the general-purpose chip route, such as CPUs, which offer great flexibility but have relatively low effective computing power when processing algorithms in specific domains; the other is the dedicated chip route, such as TPUs, which can achieve high effective computing power in certain specific domains, but their processing capabilities are poor or even incapable of handling more general and flexible domains. Because the data in the intelligent era is diverse and massive in quantity, chips are required to possess both extremely high flexibility to handle different and rapidly evolving algorithms in various domains, and extremely strong processing capabilities to quickly process massive and rapidly increasing data volumes.

[0003] In neural network computing, convolution calculations account for the majority of the total computation. Since convolution calculations can be converted into matrix multiplication calculations, the key to improving throughput, reducing latency, and enhancing the effective computing power of chips in neural network tasks lies in improving the speed of matrix multiplication calculations.

[0004] Figure 1a This is a schematic diagram illustrating matrix multiplication in a neural network. (Example) Figure 1a As shown, M1 is the data matrix, M2 is the parameter matrix, and M is the output matrix. A row of data in M1 and a column of parameters in M2 are multiplied and added to obtain a data point in M. Many neural networks use sparse matrices for their data and / or parameter matrices, meaning the data contains a large number of zeros. To improve the computation speed of matrices, optimizations can be made for sparse matrix multiplication.

[0005] Existing optimization methods generally employ a zero-skip approach, which involves retrieving all data and parameters, and before computation, checking if the data is zero. If the data is zero, the corresponding parameter is discarded, and the calculation is skipped; if the data is non-zero, computation proceeds. In this method, all elements of the data matrix and parameter matrix are stored, such as... Figure 1bThe first data and the second data are read out one by one, the data are compared, non-zero data and parameters corresponding to the non-zero data are selected to perform operation, and finally the result is obtained.

[0006] The above scheme has the following disadvantages: 1. storage is wasted, because data equal to 0 are also stored, but the data equal to 0 are not used in calculation; 2. bandwidth is wasted, because data equal to 0 are read out, occupying bandwidth, but the data equal to 0 are not used in calculation. SUMMARY

[0007] This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it used to limit the scope of the claimed subject matter's scope.

[0008] To solve the above technical problems in the prior art, embodiments of the present disclosure provide the following technical solutions:

[0009] In a first aspect, the embodiments of the present disclosure provide a matrix calculation circuit, characterized by comprising:

[0010] An instruction decoding circuit is configured to decode a matrix calculation instruction to obtain a first address of a first matrix, a first address of a bitmap matrix, and a first address of a second matrix, wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate positions of data in the data matrix.

[0011] A first data reading circuit is configured to generate a reading address of first data according to the first address of the first matrix, and generate a reading address of bitmap data according to the first address of the bitmap matrix; read the first data according to the reading address of the first data, and read the bitmap data according to the reading address of the bitmap data.

[0012] A control signal generating circuit is configured to generate a second data reading control signal according to the bitmap data.

[0013] A second data reading circuit is configured to generate a reading address of second data according to the first address of the second matrix and the second data reading control signal; and read the second data according to the reading address of the second data.

[0014] A calculation circuit is configured to calculate third data according to the first data and the second data.

[0015] Further, the instruction decoding circuit is further configured to decode the matrix instruction to obtain a first address of a first matrix.

[0016] The control signal generation circuit is further configured to generate a third data storage control signal according to the bitmap data.

[0017] The matrix calculation circuit further comprises:

[0018] The storage address generation circuit is configured to generate a storage address of the third data according to the first address of the third matrix and the third data storage control signal.

[0019] Further, the matrix calculation circuit further comprises:

[0020] A first memory, a second memory and a third memory;

[0021] The first memory is configured to store the first data and the bitmap data, and release the first data corresponding to a read address of the first data to the calculation circuit and release the bitmap data corresponding to a read address of the bitmap data to the control signal generation circuit according to the read address.

[0022] The second memory is configured to store the second data, and release the second data to the calculation circuit according to a read address of the second data.

[0023] The third memory is configured to save the third data to a storage position indicated by the storage address of the third data according to the storage address of the third data.

[0024] Further, the control signal generation circuit is further configured to generate a first data read circuit control signal according to the bitmap data, the first data read control signal being used to control the first data read circuit to read next first data and / or control the first data read circuit to read next bitmap data.

[0025] Further, the bitmap data comprises a column number of the bitmap data in the bitmap matrix, and the control signal generation circuit is further configured to:

[0026] The second data read circuit is configured to generate a read address of the second data according to the first address of the second matrix and the column number of the bitmap data in the bitmap matrix.

[0027] Further, the bitmap data comprises a row number of the bitmap data in the bitmap matrix, and the control signal generation circuit is further configured to:

[0028] Determine whether a row in the first matrix is calculated according to the row number of the bitmap data in the bitmap matrix.

[0029] In response to the calculation being completed, an output instruction is sent to the calculation circuit.

[0030] Further, the first matrix is a compressed matrix, wherein in the compressed matrix is a one-dimensional array, and the non-zero data in the data matrix is stored in the one-dimensional array in sequence; and the bitmap matrix comprises a first value, wherein the first value is used to indicate the non-zero data in the data matrix.

[0031] In a second aspect, the embodiments of the present disclosure provide a matrix calculation method, and the method comprises the following steps.

[0032] The matrix calculation instruction is decoded to obtain a first address of a first matrix, a first address of a bitmap matrix, and a first address of a second matrix, wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate positions of data in the data matrix.

[0033] A read address of first data is generated according to the first address of the first matrix.

[0034] A read address of bitmap data is generated according to the first address of the bitmap matrix.

[0035] The first data is read according to the read address of the first data.

[0036] The bitmap data is read according to the read address of the bitmap data.

[0037] Second data read control signals are generated according to the bitmap data.

[0038] A read address of second data is generated according to the first address of the second matrix and the second data read control signals.

[0039] The second data is read according to the read address of the second data.

[0040] Third data is calculated according to the first data and the second data.

[0041] Further, the method further comprises the following steps.

[0042] The matrix calculation instruction is decoded to obtain a first address of a first matrix, a first address of a bitmap matrix, and a first address of a second matrix, wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate positions of data in the data matrix.

[0043] Third data storage control signals are generated according to the bitmap data.

[0044] A storage address of third data is generated according to the first address of the third matrix and the third data storage control information.

[0045] The third data is stored in the storage address.

[0046] In a third aspect, the embodiments of the present disclosure provide a chip, comprising the matrix calculation circuit in any of the first aspect.

[0047] In a fourth aspect, the embodiments of the present disclosure provide an electronic device, comprising a memory configured to store computer readable instructions; and one or more processors configured to execute the computer readable instructions, so that the processor implements the matrix calculation method in any of the first aspect when executed.

[0048] In a fifth aspect, the embodiments of the present disclosure provide a non-transitory computer readable storage medium, characterized in that the non-transitory computer readable storage medium stores computer instructions, the computer instructions being configured to cause a computer to execute the matrix calculation method in any of the first aspect.

[0049] In a sixth aspect, the embodiments of the present disclosure provide a computer program product, characterized in that: comprising computer instructions, when the computer instructions are executed by a computing device, the computing device can execute the matrix calculation method in any of the first aspect.

[0050] In a seventh aspect, the embodiments of the present disclosure provide a computing device, characterized in that comprising one or more chips of the third aspect.

[0051] The embodiments of the present disclosure disclose a matrix calculation circuit, method, electronic device and computer readable storage medium. The matrix calculation circuit comprises: an instruction decoding circuit configured to decode a matrix calculation instruction; a first data reading circuit configured to read the first data, and read an address to read the bitmap data; a control signal generation circuit configured to generate a second data reading control signal according to the bitmap data; a second data reading circuit configured to generate a reading address of the second data according to the second data reading control signal; read the second data; and a calculation circuit configured to calculate third data according to the first data and the second data. The above-mentioned matrix calculation circuit generates the reading address of the second data through the bitmap data, reduces the reading quantity and calculation quantity of the second data, and solves the technical problem of wasting bandwidth in the prior art.

[0052] The above description is only a summary of the technical solutions of the present disclosure. In order to enable a clearer understanding of the technical means of the present disclosure, the contents of the specification can be implemented, and in order to enable the above and other purposes, characteristics and advantages of the present disclosure to be more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0053] The above and other features, aspects and advantages of various embodiments of the present disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like elements throughout. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the embodiments of the present disclosure.

[0054] Figure 1a and 1b Prior art of the present disclosure;

[0055] Figure 2 Structure schematic diagram of matrix calculation circuit provided by embodiments of the present disclosure;

[0056] Figure 3a Storage format schematic diagram of first matrix provided by embodiments of the present disclosure;

[0057] Figure 3b An example schematic diagram of storage format of first matrix provided by embodiments of the present disclosure;

[0058] Figure 4 Storage format schematic diagram of second matrix provided by embodiments of the present disclosure;

[0059] Figure 5 Flowchart of matrix calculation method provided by embodiments of the present disclosure;

[0060] Figure 6a Schematic diagram of one application example of the present disclosure;

[0061] Figure 6b Storage format schematic diagram of first matrix in application example of the present disclosure;

[0062] Figure 6c Storage format schematic diagram of second matrix in application example of the present disclosure. DETAILED DESCRIPTION

[0063] Embodiments of the present disclosure will be described in more detail by referring to the drawings. Although certain embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein, but rather the embodiments are provided to make the present disclosure more thorough and complete. It is understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not intended to limit the scope of the present disclosure.

[0064] It is understood that each of the steps recited in the method embodiments of the present disclosure can be performed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0065] As used herein, the term "includes" and its variants are to be read to be analogous to "comprises," or "comprising." The term "based on" is to be read as "based, at least in part, on." The term "one embodiment" means "at least one embodiment." The term "another embodiment" means "at least one additional embodiment." The term "some embodiments" means "at least some embodiments." Related terms have analogous meanings.

[0066] It should be noted that the terms "first", "second", etc. mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules or units.

[0067] It should be noted that the terms "one", "multiple" mentioned in the present disclosure are illustrative and not restrictive, and those skilled in the art should understand that "one or more" should be understood unless otherwise explicitly indicated in the context.

[0068] The names of the messages or information exchanged between the plurality of devices in the embodiments of the present disclosure are only for illustrative purposes, and are not intended to limit the scope of the messages or information.

[0069] Figure 2 A schematic diagram of a matrix calculation circuit is provided for the embodiments of the present disclosure. The matrix calculation circuit 200 provided in the present embodiment comprises:

[0070] An instruction decoding circuit ID (Instruction Decoder) 201, configured to decode a matrix calculation instruction to obtain a first matrix starting address P_D, a bitmap matrix starting address P_D_map and a second matrix starting address P_W; wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate the position of data in the data matrix;

[0071] A first data reading circuit (ADI_G) 202, configured to generate a first data reading address A_Din according to the first matrix starting address P_D; generate a bitmap data reading address A_map according to the bitmap matrix starting address P_D_map; read the first data D_data according to the first data reading address A_Din, and read the bitmap data D_map according to the bitmap data reading address A_map;

[0072] A control signal generation circuit (map_P) 203, configured to generate a second data reading control signal (C_AW) according to the bitmap data D_map;

[0073] The second data reading circuit (AW_G) 204 is used to generate a second data reading address A_Win based on the first address P_W of the second matrix and the second data reading control signal; and to read the second data Win based on the second data reading address A_Win.

[0074] The calculation circuit (EX) 205 is used to calculate the third data Dout based on the first data D_data and the second data Win.

[0075] For example, the matrix calculation instruction is a matrix multiplication calculation instruction, which includes an instruction type and the storage starting address of the first matrix and the storage starting address of the second matrix participating in the instruction multiplication calculation; in one embodiment, the first data in the first matrix is ​​non-zero data in the data matrix of the neural network convolution calculation, and the second matrix is ​​the parameter matrix of the neural network convolution calculation; optionally, the first matrix and / or the second matrix is ​​a compressed matrix, wherein the compressed matrix is ​​a matrix that compresses the original matrix and only saves the non-zero data in the original matrix; optionally, the data in the compressed matrix is ​​arranged into a one-dimensional data according to the structure of an array.

[0076] Optionally, the bitmap matrix is ​​a matrix with the same dimension as the data matrix. The non-zero bitmap data in the bitmap matrix M1_map is used to indicate that the data at the position corresponding to the non-zero bitmap data in the data matrix is ​​non-zero data. That is, the non-zero bitmap data in the bitmap matrix is ​​used to indicate the non-zero data in the data matrix. For example, if the non-zero bitmap data in the bitmap matrix is ​​represented by the value 1, then the bitmap data with the value 1 in the bitmap matrix indicates that the data at the position corresponding to the value 1 in the data matrix is ​​non-zero data, and the bitmap data with the value 0 in the bitmap matrix indicates that the data at the position corresponding to the value 0 in the data matrix is ​​0.

[0077] Optionally, the matrix calculation instruction further includes the dimensions of the data matrix represented by the first matrix and the parameter matrix represented by the second matrix participating in the instruction multiplication calculation, such as the number of rows and width, and the starting address of the third matrix, wherein the third matrix is ​​the result matrix after performing calculations on the first and second matrices. It is understood that the storage starting address of the matrix and the parameters such as the number of rows and columns of the matrix in the matrix calculation instruction can be represented in the form of register addresses, and the instruction decoding circuit obtains the corresponding data from the corresponding register address.

[0078] Figure 3a This is a schematic diagram illustrating the generation of the compression matrix. (For example...) Figure 3a As shown, taking the compressed matrix of the data matrix, i.e., the first matrix, as an example, where a ijdenotes an element in the data matrix, where i∈(1, M), j∈(1, K); the first matrix is stored as a one-dimensional array in the order of row first and column second according to the subscript a ij , which is logically stored continuously. The bitmap matrix corresponds to the data matrix and is used to record the non-zero data in the data matrix. Optionally, it is of the same dimension as the data matrix, i.e., the number of rows is the same and the number of columns is also the same. The non-zero value in the bitmap matrix is used to represent the non-zero data in the data matrix. As shown in Figure 3a , let m denote the bitmap data in the bitmap matrix. When a ij ≠ 0, m ij ≠ 0. Since m ij is only an identification data, it can be represented by a small value, such as 1. At this time, each bitmap data in the bitmap matrix only needs 1 bit of storage space. The size of the bitmap matrix is much smaller than that of the data matrix. Thus, the non-zero data of the data matrix is recorded by the first matrix, and the position of the non-zero data is recorded by the bitmap matrix. The data matrix is compressed into two small matrices. It can be understood that in actual use, any other value can be used in the bitmap matrix to represent the position of the non-zero data in the data matrix, which will not be described here.

[0079] It can be understood that the same compression operation can be performed on the parameter matrix. At this time, the compressed parameter matrix is referred to as the second matrix, which will not be described here. In actual storage, the storage of all data is in units of bytes (Byte). For the bitmap matrix M1_map, the element is a bit (bit), so 1 Byte can store 8 bits, that is, one byte can store 8 elements of M1_map.

[0080] As shown in Figure 3b , an example of generating a compressed matrix is shown. As shown in Figure 3b , the data matrix M1 includes four non-zero data a, b, c, and d. The data matrix M1 is compressed into a one-dimensional data matrix M1_C including 4 bits and a bitmap matrix M1_map_c. The bitmap data corresponding to the positions of the non-zero data a, b, c, and d in the bitmap matrix M1_map_c is set to 1, and the other positions are set to 0.

[0081] In the embodiment of the present disclosure, the first data reading circuit 202 receives the first address P_D of the first matrix and the first address P_D_map of the bitmap matrix decoded by the instruction decoding circuit 201, and generates a reading address A_Din of the first data according to the first address P_D of the first matrix, and a reading address A_map of the bitmap data according to the first address P_D_map of the bitmap matrix; reads the first data D_Data according to the reading address A_Din of the first data, and reads the bitmap data D_map according to the reading address A_map of the bitmap data. As shown in Figure 3a , in one example, if it is the first reading, the first non-zero data a 11 and the first byte of the bitmap data m 11 to m 18 (in the case that the number of columns of the data matrix is at least 8). The first data reading circuit 202 updates the first address after each reading, that is, the address of the first data read this time is added to the length of the data as the first address of the next reading, and the address of the bitmap data read this time is added to the length of the data as the first address of the next reading; if each first data occupies N storage positions, then P_D n is updated to P_D n-1 +N each time, so that new first data can be read in the calculation; each bitmap data only occupies 1 bit, so 8 bitmap data are read at a time when reading the bitmap data, and therefore the reading frequency of the bitmap data is different from that of the first data, and P_D_map n is only updated to P_D_map n-1 +1 each time.

[0082] In the present disclosure, the control signal generating circuit (map_P) 203 generates a second data reading control signal (C_AW) according to the bitmap data D_map. Optionally, the second data reading control signal (C_AW) includes the position of the bitmap data corresponding to the first data in the bitmap data.

[0083] In the embodiment of the present disclosure, the second data reading circuit 204 generates a reading address A_Win of the second data according to the first address P_W of the second matrix and the position of the bitmap data; reads the second data Win according to the reading address A_Win of the second data. Optionally, the second data reading circuit 204 generates the reading address A_Win of the second data according to the first address P_W of the second matrix and the number of columns of the bitmap data, wherein the number of columns of the bitmap data indicates which column the bitmap data is in the bitmap matrix.

[0084] In one embodiment, all the elements in the second matrix are non-zero elements, in which case the second matrix is not compressed and is stored in the form of the original matrix. The logical form of the storage is shown in FIG. 6, in which P_W is the storage address of the first element b Figure 4 11 of the second matrix. The second matrix is logically stored in a continuous form and can be physically stored continuously or discontinuously, which is not limited in the present disclosure. The row address of the second matrix can be generated by the first address P_W and the number of columns of the bitmap data, and a row of second data corresponding to the number of columns of the bitmap data in the second matrix is read out for subsequent matrix calculation. When the first data changes, the bitmap data changes accordingly, and thus the number of columns of the bitmap data also changes, and the read second data changes with the number of columns of the bitmap data, thereby changing the second data used in each calculation.

[0085] In the present disclosure, the calculation circuit 205 calculates third data according to the first data and the second data. Optionally, the calculation is a multiply-add calculation, in which the calculation circuit performs a multiplication calculation on the first data and the second data obtained in the current clock cycle to obtain a multiplication calculation result, and adds the multiplication calculation result to the third data obtained in the previous clock cycle to obtain the third data in the current clock cycle. In this way, the calculation circuit 205 continuously performs multiply-add calculation until the calculation is completed.

[0086] Optionally, the calculation circuit 205 includes a plurality of calculation units, and the number of calculation units is the same as the number of columns of the second matrix. That is, when the second data reading circuit 204 reads a row of second data according to the position of the bitmap data, the row of second data can be calculated in parallel with the first data.

[0087] Optionally, the control signal generation circuit 203 is further configured to generate a first data reading circuit control signal (C_ADI) according to the bitmap data, the first data reading control signal being used to control the first data reading circuit 202 to read the next first data and / or control the first data reading circuit 202 to read the next bitmap data. The bitmap data includes the value of the bitmap data and the position of the bitmap data, in which the position of the bitmap data represents the position of the bitmap data in the bitmap matrix, i.e., the position of the first data in the data matrix.

[0088] ​Optionally, the position of the bitmap data is an indirect position, i.e. the position of the bitmap data read out is a logical position of the bitmap data, and then the position of the bitmap data in the bitmap matrix is calculated by the number of rows H_map and the number of columns W_map of the bitmap matrix and the storage position of the bitmap data; for example, assuming that the number of rows of the bitmap matrix is 4 and the number of columns is 4, the position of the 11th bitmap data in the logical storage position in the bitmap matrix is the 3rd row and the 3rd column; thus, the control signal generation circuit only needs to determine the logical storage position of the bitmap data currently processed, and the position of the bitmap data in the bitmap matrix can be determined, and in this optional embodiment, since the position of the bitmap data does not need to be stored, the storage space is saved.

[0089] Optionally, the position of the bitmap data is directly recorded in the bitmap data, i.e. the bitmap data includes the value of the bitmap data and the position (h, w) of the bitmap data in the bitmap matrix, wherein h represents the number of rows of the bitmap data in the bitmap matrix, and w represents the number of columns of the bitmap data in the bitmap matrix; in this optional embodiment, since the position of the bitmap data has been included in the bitmap data, additional storage space is required, but the calculation amount of calculating the position of the bitmap data can be saved.

[0090] For example, when the first data needs to be taken out, the bitmap data is taken out first, and when the value of the bitmap data is 1, it indicates that the first data corresponding to the bitmap data is non-0 data, and the control signal generation circuit 203 generates the first data reading circuit control signal to control the first data reading circuit to read the first data corresponding to the bitmap data; when the bitmap data is used up, for example, 1 byte of bitmap data is read, and when all 8 bitmap data are traversed, the control signal generation circuit 203 generates the first data reading circuit control signal to control the first data reading circuit to read the next bitmap data. It can be understood that in this example, the next bitmap data is 8 bitmap data of one byte.

[0091] It can be understood that the above-mentioned way of reading the first data is only an example and does not constitute a limitation on the present disclosure; for example, the control signal generation circuit can also generate a control signal to control the first data reading circuit to read the next first data according to a periodic signal every period; optionally, the next first data is read according to the feedback signal of the calculation circuit, i.e. when the calculation circuit calculates the current first data, the feedback signal is sent to the control signal generation circuit to make the first data read the next first data. Other ways of reading the first data are not described in detail.

[0092] Optionally, the position of the bitmap data also includes the row number of the bitmap data in the bitmap matrix, wherein the row number indicates which row of the bitmap data in the bitmap matrix. The control signal generation circuit 203 is further configured to: determine whether a row in the first matrix has been calculated based on the row number of the bitmap data in the bitmap matrix; and in response to the completion of the calculation, send an output instruction (C_RE) to the calculation circuit 205.

[0093] like Figure 2 As shown, the control signal generation circuit 203 receives the bitmap data and determines whether a row of the first matrix has been calculated by checking the row number of the current bitmap data. Since the data matrix and the bitmap matrix have the same dimension, a row of the bitmap matrix corresponds to a row of the data matrix. Therefore, when the row number of the bitmap data changes, it indicates that a row of the data matrix has been calculated. Thus, the row number in the bitmap data position can be used to determine whether the first data in a row of the first matrix has been calculated. For example, the row number of the current bitmap data can be determined by the logical address of the current bitmap data and the number of columns in the bitmap matrix. Let the logical address of the current bitmap data be add, which represents the position of the current bitmap data in all bitmap data in the bitmap matrix, sorted by row first and then column. Let the number of columns in the bitmap matrix be W_map, then the row number of the current bitmap data... For example, in a 4x4 bitmap data set, where the row number is first row and then column number, the row number of the 5th bitmap data is... That is, the second line.

[0094] Specifically, the judgment steps are as follows:

[0095] Compare the number of rows in the bitmap data used this time with the number of rows in the bitmap data used last time;

[0096] If they are the same, then the first data in the first row of the first matrix has not yet been calculated; or,

[0097] If they are different, then the first data in the first row of the first matrix has been calculated.

[0098] Specifically, the X-coordinate of the currently read bitmap data is compared with the X-coordinate of the previously read bitmap data. If they are the same, it means that a row of data has not been completely read; if they are different, it means that the next row of bitmap data has been read, indicating that the first row of data has already been calculated. In response to the completion of the calculation, i.e., the X-coordinate of the currently read bitmap data is different from the X-coordinate of the previously read bitmap data, an output command C_RE is sent to the calculation circuit 205, so that the calculation circuit 205 outputs the calculated third row of data.

[0099] Optionally, the control signal generation circuit 203 can also obtain the width and height of the bitmap matrix through the instruction decoding circuit, and since the matrix is stored in row-major order, the number of rows and columns of the obtained bitmap data can be obtained.

[0100] Optionally, the instruction decoding circuit 201 is further configured to decode a matrix instruction to obtain a first address of a third matrix, and the control signal generation circuit 203 is further configured to generate a third data storage control signal (C_ADO) according to the bitmap data. The matrix calculation circuit 200 further comprises a storage address generation circuit (ADO_G) 206 configured to generate a third data storage address A_Dout according to the first address P_O of the third matrix and the third data storage control signal. The third matrix is obtained after the calculation of the first matrix and the second matrix. In an example, the position of the bitmap data in the bitmap matrix is the number of rows of the bitmap data in the bitmap matrix. When the matrix calculation is a matrix multiplication calculation, the calculation circuit can obtain a row of third data in the third matrix after calculating a row of first data in the first matrix, i.e., each calculation unit in the calculation circuit 205 outputs one of the third data in a row of the third matrix. Thus, the number of rows of the bitmap data in the bitmap matrix can determine which row of the third matrix the output row of third data belongs to. As shown in Figure 2 Optionally, after receiving the output instruction C_RE sent by the control signal generation circuit 203, the storage address generation circuit 206 sends the third data storage address A_Dout.

[0101] Optionally, as shown in Figure 2 The matrix calculation circuit 200 further comprises a first storage 207, a second storage 208, and a third storage 209. The first storage 207 is configured to store the first data and the bitmap data, and release the first data corresponding to a read address of the first data to the calculation circuit 205 and release the bitmap data corresponding to a read address of the bitmap data to the control signal generation circuit 203.

[0102] The second storage 208 is configured to store the second data, and release the second data corresponding to a read address of the second data to the calculation circuit 205.

[0103] The second storage 208 is configured to store the second data, and release the second data corresponding to a read address of the second data to the calculation circuit 205.

[0104] The third memory 209 is used to save the third data to the storage location indicated by the storage address of the third data according to the storage address.

[0105] In the embodiments of the present disclosure, the first matrix, i.e., the compressed matrix of the data matrix, is stored in the first memory 207; the bitmap matrix, i.e., the matrix indicating the position of the first data, is also stored in the first memory 207; the second matrix, i.e., the parameter matrix or the compressed matrix of the parameter matrix, is stored in the second memory 208; and the third matrix, i.e., the output matrix, is stored in the third memory 209. The first memory 207, the second memory 208 and the third memory 209 can be independently accessed in parallel, so that the data reading, parameter reading, calculation and result storage can be performed in parallel, thereby improving the efficiency of matrix calculation.

[0106] It can be understood that the first data reading circuit 202 and the first memory 207 are connected by using an address bus and a data bus, wherein the address bus is used to transmit an address, and the first data reading circuit makes the first memory 207 release data to the data bus through the address circuit, and the circuit connected with the data bus can obtain the required first data or the position of the first data in the first matrix; similarly, the connection relationship between the second data reading circuit 204 and the second memory 208 is similar, and will not be described herein. The address bus of the third memory 209 is connected with the storage address generating circuit 206, and is used to transmit the storage address of the third data generated by the storage address generating circuit 206; and the data bus of the third memory 209 is connected with the calculation circuit 205, and is used to transmit the third data calculated by the calculation circuit 205.

[0107] It can be understood that in the above specific embodiments, the position of the bitmap data in the bitmap matrix (i.e., the position corresponding to the data matrix) is used to determine the second data to be read, and in the actual implementation process, the first matrix and the second matrix can also be inverted, i.e., the position of the bitmap data in the bitmap matrix corresponding to the second matrix is used to determine the first data to be read. That is, for matrix multiplication calculation, each time a second data is read, a column of first data corresponding to the second data needs to be read from the first matrix, and then the second data is read by column, so that each time a column of second data is calculated, a column of third data is obtained, and the column of third data is determined according to the column number of the bitmap data of the bitmap matrix of the second data, and a column of third data is stored according to the first address of the third data and the column number of the bitmap data. Other cases can be obtained according to the above process and the specific matrix calculation process, and will not be described herein.

[0108] Figure 5 A flowchart of the matrix calculation method provided by the embodiments of the present disclosure is shown in FIG. 8. Figure 5 As shown in FIG. 8, the method comprises the following steps:

[0109] Step S501, decode the matrix calculation instruction to obtain the first address of a first matrix, the first address of a bitmap matrix, and the first address of a second matrix, wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate the position of the non-zero data in the data matrix;

[0110] Step S502, generate a read address of first data according to the first address of the first matrix;

[0111] Step S503, generate a read address of bitmap data according to the first address of the bitmap matrix;

[0112] Step S504, read the first data according to the read address of the first data;

[0113] Step S505, read the bitmap data according to the read address of the bitmap data;

[0114] Step S506, generate a second data read control signal according to the bitmap data;

[0115] Step S507, generate a read address of second data according to the first address of the second matrix and the second data read control signal;

[0116] Step S508, read the second data according to the read address of the second data;

[0117] Step S509, calculate third data according to the first data and the second data.

[0118] Further, the matrix calculation method further comprises:

[0119] Decode the matrix calculation instruction to obtain the first address of a third matrix;

[0120] Generate a third data storage control signal according to the bitmap data

[0121] Generate a storage address of third data according to the first address of the third matrix and the third data storage control information;

[0122] Store the third data in the storage address.

[0123] The steps in the above matrix calculation method are the steps performed by the above matrix calculation circuit, and the specific execution process can be referred to the description of the matrix calculation circuit above, which will not be repeated here.

[0124] In the foregoing, although each step in the above method embodiments is described in the above order, it should be clear to those skilled in the art that the steps in the embodiments of the present disclosure do not necessarily have to be performed in the above order, but can also be performed in reverse order, in parallel, in cross order, or other order, and those skilled in the art can also add other steps on the basis of the above steps, and these obvious modifications or equivalent replacement manners should also be included in the protection scope of the present disclosure, and will not be described here.

[0125] The embodiments of the present disclosure also provide a chip, which comprises the matrix calculation circuit in any of the above embodiments.

[0126] The working process of the matrix calculation circuit in the embodiments of the present disclosure is described below in an actual application scenario. Figure 6a In this example application scenario, a data matrix M1 and a parameter matrix M2 are used to multiply to obtain an output matrix M3. M1 is a 4*4 sparse data matrix, which includes a large number of 0 elements, and M2 is a 4*2 parameter matrix, and the multiplication of the two matrices obtains a 4*2 output matrix.

[0127] In this example, all the matrix elements are FP32, that is, 32 bits represent one data, and each element in each matrix requires 32 / 8=4B of storage space. The parameter matrix includes 2 column elements, so the calculation circuit 205 can be set as a vector processing unit composed of two multiplier-adder units.

[0128] As shown in FIG. 2, the calculation circuit 205 includes a first data reading circuit 202, a second data reading circuit 204, a vector processing unit 206, and a result writing circuit 208. Figure 6b The two matrices obtained after the sparse data matrix M1 is compressed are shown in FIG. 3, that is, a first matrix M1_C stored in the first memory and a bitmap matrix M1_map_C; wherein the first matrix M1_C includes the non-0 data 1, 2, 3, and 4 in the data matrix M1, and is stored in order (i.e., row by row) in the order of row first and column second, and each element in the first matrix M1_C requires 4B to be stored. After the first data reading circuit 202 reads one first data each time, the address P_D is automatically increased by 4B to obtain the address of the next first data, that is: P_D=P_D+4. Since the data in M1_map are bit data, there are only 4 data in each row, so when storing, one row of M1_map only needs to occupy 4bit of storage space. In this way, 2 rows of M1_map can exist in one byte, thereby saving storage space. After calculating 2 rows, the address of M1_map is changed to: P_D_map=P_D_map+1.

[0129] As shown in FIG. 4, the second data reading circuit 204 reads the parameter matrix M2 from the second memory, and the vector processing unit 206 performs multiplication and addition on the data in the first matrix M1_C and the data in the parameter matrix M2 to obtain the output matrix M3. Figure 6cThe logical storage format of the second matrix, i.e. the parameter matrix, is shown, which is stored in row order. The size of the second data of each row is 2*4=8B, and the storage starting address of each row is determined by the initial address P_W of the second matrix and the row number N_r, i.e. P_W+8*N_r. Each time a row of second data is read according to P_W, and then the value of P_W is updated.

[0130] In the calculation, the initial address P_D of M1_C, the initial address P_map of M1_map_C and the initial address P_W of M2 are decoded by the instruction decoding circuit 201, then the first data reading circuit 202 reads the first first data 1 and the first two rows of data of M1_map_C from the first memory 207 according to the initial address P_D, the first value of the first two rows of bitmap data of the bitmap data indicates that there is non-zero data in the position of the data matrix corresponding to the bitmap data, i.e. the first data 1; the control signal generating circuit 203 obtains the bitmap data of the first data 1, and according to the dimension of the bitmap matrix, it can be judged that the column number of the bitmap data is 1, i.e. the first bitmap data read is 1, and through the logical position 1 of the bitmap data and the column number 4 and the row number 4 of the bitmap matrix, it can be obtained that the position of the bitmap data in the bitmap matrix is (1, 1), i.e. the first row and the first column, thereby the control signal of the second data reading circuit 204 can be generated, and the control signal contains the column number 1 of the bitmap data; the second data reading circuit 204 reads the first row of second data 1 and 2 corresponding to the column number 1 from the second memory 208 according to the initial address P_W of the second matrix and the column number 1 of the bitmap data; when the bitmap data of the first data 2 is obtained, it is judged that the logical position of the bitmap data 2 is 7, i.e. the seventh bitmap data, then according to the column number 4 and the row number 4 of the bitmap matrix, it can be obtained that the position of the bitmap data in the bitmap matrix is (2, 3), i.e. the second row and the third column, thereby the control signal of the second data reading circuit 204 can be generated, and the control signal contains the column number 3 of the bitmap data; the second data reading circuit 204 reads the third row of second data 1 and 2 corresponding to the column number 3 from the second memory 208 according to the initial address P_W of the second matrix and the column number 3 of the bitmap data, i.e. the column number of the bitmap data determines the reading address of the second data generated by the second data reading circuit 204, assuming that the column number of the bitmap data is Col, then the reading address of the second data is P_W+8*(Col-1), it is noted that in this example, in order to facilitate understanding, the column number is marked from 1, actually it can also be marked from 0, i.e. the row and column number of the first data is (0, 0), at this time, the reading address of the second data needs to be adjusted to P_W+8*Col; in summary, through the column number of the bitmap data, the second data reading circuit 204 can determine the starting address of a row of second data, and then read out the row of second data.

[0131] After the first data and a row of second data are read out, the first data is transmitted to one input port of the two multipliers, and two second data are respectively transmitted to the other input port of the two multipliers, and the multipliers perform multiplication and accumulation calculation according to the received first data and second data, and perform multiplication calculation on the first data and the second data and accumulate the result of the last multiplication and accumulation calculation to obtain third data. The calculation circuit 205 performs multiplication and accumulation calculation in the above-mentioned manner until the number of columns of the bitmap data changes, indicating that a row of first data is calculated.

[0132] For example, when the second first data 2 is read, the number of columns of the bitmap data corresponding to the second first data 2 is 3, which is different from the X coordinate 1 of the first first data 1, indicating that a row of first data in the first matrix M1_C has been calculated, at this time, the control signal generation circuit 203 generates an output instruction C_RE and sends it to the calculation circuit 205, and sends a storage control signal C_ADO to the storage address generation circuit 206; after receiving the storage control signal C_ADO, the storage address generation circuit 206 generates the storage address of a row of third data of the output matrix M3, and the calculation circuit 205 releases a row of third data to the data bus, and the third storage 209 stores a row of third data on the data bus according to the storage address of the third data. The storage address generation circuit 206 calculates the storage address of the third data according to the number of rows of the bitmap data each time a row of output calculation is completed. Each row of the output matrix M3 has 2 FP32 data, and the storage size of each row is 2*4=8B. If the first address of the output matrix storage is P_M, and the number of rows of the bitmap data is Row, then the storage address of this output row is: P_M=P_M+8*Row.

[0133] The above steps are iteratively performed until all the first data are read out, and the output matrix in the third storage is obtained, which is the matrix calculation result of the first matrix and the second matrix.

[0134] The embodiment of the disclosure provides an electronic device, including a memory configured to store computer readable instructions, and one or more processors configured to execute the computer readable instructions, so that the processor implements the matrix calculation method described in any of the embodiments when running.

[0135] The embodiment of the disclosure also provides a non-transitory computer readable storage medium, characterized in that the non-transitory computer readable storage medium stores computer instructions for causing a computer to execute the matrix calculation method described in any of the preceding embodiments.

[0136] The embodiment of the present disclosure further provides a computer program product, characterized by comprising computer instructions, when the computer instructions are executed by a computing device, the computing device can perform the matrix calculation method in any of the foregoing embodiments.

[0137] The embodiment of the present disclosure further provides a computing device, characterized by comprising the chip in any of the foregoing embodiments.

[0138] The flowcharts and block diagrams in the drawings of the present disclosure illustrate the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, a task segment or a part of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different order from that noted in the drawings. For example, two blocks represented in succession can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the function involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0139] The units involved in the embodiments of the present disclosure can be implemented in software or in hardware. In some cases, the name of the unit does not constitute a limitation on the unit itself.

[0140] The functions described above in the present disclosure can be executed at least in part by one or more hardware logic components. For example, non-limiting example types of hardware logic components that can be used include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-chips (SOCs), complex programmable logic devices (CPLDs), and so on.

[0141] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A matrix computation circuit, characterized by comprising: The matrix calculation circuit comprises: an instruction decoding circuit configured to decode a matrix calculation instruction to obtain a first address of a first matrix, a first address of a bitmap matrix, and a first address of a second matrix, wherein the first matrix is a matrix composed of non-zero data in a data matrix, and bitmap data in the bitmap matrix is used to indicate the position of data in the data matrix; a first data reading circuit configured to generate a reading address of first data according to the first address of the first matrix, and generate a reading address of bitmap data according to the first address of the bitmap matrix; reading the first data according to the reading address of the first data, and reading the bitmap data according to the reading address of the bitmap data; a control signal generating circuit configured to generate a second data reading control signal according to non-zero bitmap data in the bitmap data; a second data reading circuit configured to generate a reading address of second data according to the first address of the second matrix and the second data reading control signal; reading the second data according to the reading address of the second data; a calculation circuit configured to calculate third data according to the first data and the second data; wherein the bitmap data comprises the column number of the bitmap data in the bitmap matrix; the second data reading circuit is configured to generate the reading address of the second data according to the first address of the second matrix and the column number of the bitmap data in the bitmap matrix, so as to read a corresponding row of second data according to the column number of the bitmap data.

2. The matrix calculation circuit of claim 1, wherein: the instruction decoding circuit is further configured to decode the matrix instruction to obtain a first address of a third matrix; the control signal generating circuit is further configured to generate a third data storage control signal according to the bitmap data; the matrix calculation circuit further comprises: a storage address generating circuit configured to generate a storage address of third data according to the first address of the third matrix and the third data storage control signal.

3. The matrix calculation circuit according to claim 2, wherein the matrix calculation circuit further comprises: a first memory, a second memory, and a third memory; wherein the first memory is configured to store the first data and the bitmap data, release the first data corresponding to the reading address of the first data to the calculation circuit according to the reading address of the first data, and release the bitmap data to the control signal generating circuit according to the reading address of the bitmap data; the second memory is configured to store the second data, and release the second data to the calculation circuit according to the reading address of the second data; the third memory is configured to save the third data to a storage position indicated by the storage address of the third data according to the storage address of the third data.

4. The matrix calculation circuit of any one of claims 1-3, wherein: the control signal generating circuit is further configured to generate a first data reading circuit control signal according to the bitmap data, and the first data reading control signal is used to control the first data reading circuit to read the next first data and / or control the first data reading circuit to read the next bitmap data.

5. The matrix calculation circuit according to any one of claims 1 to 3, wherein the bitmap data comprises the row number of the bitmap data in the bitmap matrix, and the control signal generating circuit is further configured to: Determine whether a row in the first matrix has been calculated based on the number of rows in the bitmap matrix according to the bitmap data; Upon completion of the calculation, an output command is sent to the calculation circuit.

6. The matrix computation circuit according to any one of claims 1 to 3, wherein, The first matrix is ​​a compressed matrix, wherein the compressed matrix is ​​a one-dimensional array that stores non-zero data from the data matrix in sequence; the bitmap matrix contains a first value, wherein the first value is used to indicate non-zero data from the data matrix.

7. A method of matrix computation, characterized by, include: The decoding matrix calculation instruction obtains the starting address of the first matrix, the starting address of the bitmap matrix, and the starting address of the second matrix, wherein the first matrix is ​​a matrix composed of non-zero data in the data matrix, and the bitmap data in the bitmap matrix is ​​used to indicate the position of the data in the data matrix; The read address of the first data is generated based on the starting address of the first matrix; The read address of the bitmap data is generated based on the starting address of the bitmap matrix; Read the first data according to the read address of the first data; Read the bitmap data according to the read address of the bitmap data; A second data read control signal is generated based on the non-zero bitmap data in the bitmap data; The read address of the second data is generated based on the starting address of the second matrix and the second data read control signal; Read the second data according to the read address of the second data; The third data is calculated based on the first data and the second data; The bitmap data includes the number of columns of the bitmap data in the bitmap matrix; The step of generating a second data read control signal based on non-zero bitmap data in the bitmap data specifically involves generating a read address for the second data based on the starting address of the second matrix and the column number of the bitmap data in the bitmap matrix, so as to read a corresponding row of second data according to the column number of the bitmap data.

8. The matrix calculation method of claim 7, wherein, The method further includes: The decoding matrix calculation instruction yields the starting address of the third matrix; A third data storage control signal is generated based on the bitmap data; the storage address of the third data is generated based on the first address of the third matrix and the third data storage control information. The third data is stored in the storage address.

9. A chip, characterized by Includes the matrix calculation circuit as described in any one of claims 1-6.

Images