A power-saving high-refresh panel driving circuit and design method

Abstract

The invention discloses a power-saving high-refresh panel driving circuit and a design method. The circuit comprises a GIP input signal and a GIP output stage transmission signal. A VGH high level and a VGL low level are connected to a T1 device and a T7 device at the upper part of the driving circuit respectively, and the T1 device and T7 are connected to Gn‑4 and Gn+4 respectively. The T1 device and the T7 device at the upper part are connected to a Q point voltage, and the Q point voltage is connected to a T4 device and a C2 capacitor. A C1 capacitor is connected between the T2 device and the T3 device, and a CK clock signal is connected to the C1 capacitor. The T6 is connected to a C3 capacitor, and an A point voltage is connected between the C2 capacitor and the C3 capacitor. The A point voltage is connected to a T8 device and a T9 device respectively, and the T8 device is connected to Gn‑4 and Gn‑3 respectively, and the T9 device is connected to Gn+3 and Gn+4 respectively. Through a two-level coupling scheme for the Q point voltage, when the Q point voltage remains unchanged, the driving VGH high level voltage can be reduced, the driving VGH voltage can be reduced, and the panel power consumption can be effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of display devices, and in particular relates to a power-saving high-refresh panel driving circuit and a design method thereof. Background Art

[0002] For example, the Chinese patent application number CN202110274341.8 discloses a front-end processing circuit, which is coupled to the panel driving circuit and is in front of the panel driving circuit. The front-end processing circuit includes a sub-pixel rendering module and a compensation module. The sub-pixel rendering module is used to receive a first signal and perform sub-pixel rendering processing on the first signal and then output a second signal. The compensation module is respectively coupled to the sub-pixel rendering module and the panel driving circuit, and is used to perform compensation processing on the second signal and then output a third signal to the panel driving circuit.

[0003] However, the above solution has the following shortcomings:

[0004] 1. The above circuit only solves the problem that the original built-in memory of the panel driving circuit is insufficient, so the memory capacity needs to be increased. However, the display of the liquid crystal display panel is completed by controlling the pixel TFT in the surface, specifically, the horizontal gate signal controls the on and off of the TFT and the vertical source signal writes the data to be displayed, wherein the gate signal is generated by the gate driving circuit on both sides of the panel, referred to as the GIP driving circuit; as people's requirements for display quality are getting higher and higher, today's TFT-LCD panels are mainly developed in the direction of high refresh and high resolution, so the power consumption of the panel is gradually increasing. For mobile devices, power consumption is one of the most important parameters; with the increase of refresh rate, there is a lack of a GIP circuit, which can save power consumption compared with the traditional GIP circuit.

[0005] To this end, we propose a power-saving high-refresh panel driving circuit and design method to solve the problems mentioned in the above background technology. Summary of the invention

[0006] The object of the present invention is to provide a power-saving high-refresh panel driving circuit and a design method to solve the problems existing in the prior art.

[0007] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a power-saving high-refresh panel driving circuit, comprising a GIP input signal and a GIP output stage transmission signal, wherein the GIP input signal comprises a VGH high level, a VGL low level and a CK clock signal, and the GIP output stage transmission signal comprises Gn-4, Gn+4 and Gn, and the VGL low level at the bottom of the driving circuit is sequentially connected to T2 devices, T3 devices, T6 devices and T5 devices, preferably, the T2 device is connected to the T1 device and T7 device at the top of the driving circuit, and a T4 device is connected between the Q point voltage position and the T5 device, and the T4 device is connected to the CK clock signal.

[0008] The VGH high level and the VGL low level at the upper part of the driving circuit are connected to the T1 device and the T7 device respectively, and the T1 device and T7 are connected to Gn-4 and Gn+4 respectively. The T1 device and the T7 device at the upper part are connected to the Q point voltage, and the Q point voltage is connected to the T4 device and the C2 capacitor. The C1 capacitor is connected between the T2 device and the T3 device, and the C1 capacitor is connected to the CK clock signal. The T6 is connected to the C3 capacitor. Preferably, the T3 device and the T6 device are connected, the T4 device and the T5 device are connected, and Gn is connected between the T4 device and the T5 device, and Gn is connected to the C2 device.

[0009] A point voltage is connected between the C2 capacitor and the C3 capacitor, and the A point voltage is connected to the T8 device and the T9 device respectively. The T8 device is connected to Gn-4 and Gn-3 respectively, and the T9 device is connected to Gn+3 and Gn+4 respectively.

[0010] A design method for a power-saving high-refresh panel driving circuit specifically comprises the following steps:

[0011] Step 1, the driving circuit timing includes Gout n-4, Gout n-3, Q point voltage, A point voltage, Gout n, Gout n+3 and Gout n+4. When Gout n-4 is High, Q point will be charged to VGH-Vth through T1 device, and T8 device is also turned on under the action of Gout n-4, Gout n-3 is low level, and A point voltage is low level;

[0012] Step 2, the Gout n-3 is changed from low level to high level, the voltage of point A is charged from 0V to VGH-Vth, and the voltage of point Q is twice VGH-Vth;

[0013] Step three, the CK clock signal changes from a low level to a high level, the Gout n output is a VGH high level, and the T1 device, T7 device, T8 device and T9 device are in a closed state, the A point voltage is coupled to twice the VGH-Vth by the C3 capacitor, and the Q point voltage is coupled to three times the VGH-Vth by the C1 capacitor. When the CK clock signal changes from a high level to a low level, the Q point clock signal is twice VGH-Vth, and when Gout n+4 is a high level, the T7 device and the T9 device are turned on, and the Q point voltage and the A point voltage are reset to a low level.

[0014] Compared with the prior art, the beneficial effects of the present invention are: through a two-level coupling scheme for the Q point voltage, the driving VGH high-level voltage can be reduced while the Q point voltage remains unchanged. The size of the VGH high-level voltage directly affects the power consumption of the panel. By applying this GIP circuit to a high-refresh and high-resolution panel, the driving VGH voltage can be reduced, which can effectively reduce the panel power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the GIP circuit design diagram of the common 7T2C;

[0016] Figure 2 for Figure 1 Circuit driving timing diagram;

[0017] Figure 3 This is a diagram of the GIP driver design architecture of the present invention;

[0018] Figure 4 for Figure 3 Circuit driving timing diagram. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0020] Based on the common 7T2C GIP circuit design, such as Figure 1 and Figure 2 As shown:

[0021] VGH is a high level, VGL is a low level, CK is a clock signal, Gn is an output terminal, T1 to T7 are TFT devices, and C1 and C2 are capacitors.

[0022] VGH, VGL, and CK are input signals of GIP, and Gn-4, Gn+4, and Gn are level transfer signals output by GIP, which are used to control the in-plane pixel TFT.

[0023] Usually in a-Si thin film field effect transistor LCD, during the normal display driving process, GIP is opened step by step, and each line of G1~Gn control panel, the state of G1~Gn and Q point is as follows Figure 2 The timing shown;

[0024] Under this driving architecture, the charging voltage of the Q point is about twice VGH. Taking the common Q point voltage requirement of 30V as an example, the driving VGH voltage must reach 15V. As the panel develops towards high refresh and high resolution, the higher the VGH voltage, the higher the power consumption of the panel. Therefore, a new GIP architecture is proposed, which can reduce the driving VGH voltage while meeting the Q point voltage. The Q point of this GIP circuit adopts 2-level coupling. Taking the common Q point voltage requirement of 30V as an example, using this method, the VGH voltage can reach 10V, which can effectively reduce power consumption.

[0025] In order to effectively reduce the power consumption of high refresh and high resolution panels, based on the existing 7T2C structure, we came up with the following Figure 3 and Figure 4 A power-saving high-refresh panel driving circuit design is shown, including a GIP input signal and a GIP output stage transmission signal, wherein the GIP input signal includes a VGH high level, a VGL low level and a CK clock signal, and the GIP output stage transmission signal includes Gn-4, Gn+4 and Gn.

[0026] The VGL low level at the bottom of the driving circuit is connected to T2 devices, T3 devices, T6 devices and T5 devices in sequence, the T2 device is connected to T1 devices and T7 devices at the top of the driving circuit, and the T4 device is connected between the Q point voltage and the T5 device, and the T4 device is connected to the CK clock signal.

[0027] The VGH high level and VGL low level at the upper part of the driving circuit are connected to the T1 device and the T7 device respectively, and the T1 device and T7 are connected to Gn-4 and Gn+4 respectively. The T1 device and T7 device at the upper part are connected to the Q point voltage level, and the Q point voltage level is connected to the T4 device and the C2 capacitor.

[0028] A C1 capacitor is connected between the T2 device and the T3 device, a CK clock signal is connected to the C1 capacitor, the T6 is connected to the C3 capacitor, the T3 device is connected to the T6 device, the T4 device is connected to the T5 device, and a Gn is connected between the T4 device and the T5 device, and the Gn is connected to the C2 device.

[0029] A point voltage is connected between the C2 capacitor and the C3 capacitor, and the A point voltage is connected to the T8 device and the T9 device respectively. The T8 device is connected to Gn-4 and Gn-3 respectively, and the T9 device is connected to Gn+3 and Gn+4 respectively.

[0030] A design method for a power-saving high-refresh panel driving circuit specifically comprises the following steps:

[0031] Step 1, the driving circuit timing includes Gout n-4, Gout n-3, Q point voltage, A point voltage, Gout n, Gout n+3 and Gout n+4. When Gout n-4 is High, Q point will be charged to VGH-Vth through T1 device, and T8 device is also turned on under the action of Gout n-4, Gout n-3 is low level, and A point voltage is low level;

[0032] Step 2, the Gout n-3 is changed from low level to high level, the voltage of point A is charged from 0V to VGH-Vth, and the voltage of point Q is twice VGH-Vth;

[0033] Step three, the CK clock signal changes from a low level to a high level, the Gout n output is a VGH high level, and the T1 device, T7 device, T8 device and T9 device are in a closed state, the A point voltage is coupled to twice the VGH-Vth by the C3 capacitor, and the Q point voltage is coupled to three times the VGH-Vth by the C1 capacitor. When the CK clock signal changes from a high level to a low level, the Q point clock signal is twice VGH-Vth, and when Gout n+4 is a high level, the T7 device and the T9 device are turned on, and the Q point voltage and the A point voltage are reset to a low level.

[0034] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A design method for a power-saving high refresh panel driving circuit, the power-saving high refresh panel driving circuit comprises a GIP input signal and a GIP output stage transmission signal, the GIP input signal comprises a VGH high level, a VGL low level and a CK clock signal, the GIP output stage transmission signal comprises Gn-4, Gn+4 and Gn, characterized in that: The VGL low level at the bottom of the driving circuit is connected to the gates of the T2 device, the T3 device, the T6 device and the T5 device in sequence. The drain of T2 is connected to the CK clock signal via the C1 capacitor; the source of T3 is connected to the source of T6 and is connected to the voltage of point A via the C2 capacitor; The VGH high level and the VGL low level in the upper part of the driving circuit are connected to the gates of the T1 device and the T7 device respectively, and the drains of the T1 device and the T7 are connected to Gn-4 and Gn+4 respectively, the sources of the T1 device and the T7 device in the upper part are connected to the Q point voltage, the Q point voltage is connected to the source of the T4 device and the C2 capacitor, the C1 capacitor is connected between the T2 device and the T3 device, the C1 capacitor is connected to the CK clock signal, the T6 is connected to the C3 capacitor, and the A point voltage is connected between the C2 capacitor and the C3 capacitor, the A point voltage is connected to the T8 device and the T9 device respectively, the T8 device is connected to Gn-4 and Gn-3 respectively, and the T9 device is connected to Gn+3 and Gn+4 respectively; The T2 device is connected to the T1 device and the T7 device at the top of the driving circuit, and the Q point voltage is connected to the gate of the T5 device through the source of the T4 device, and the gate of the T4 device is connected to the CK clock signal; The T3 device is connected to the T6 device, the T4 device is connected to the T5 device, and Gn is connected between the T4 device and the T5 device, and Gn is connected to the C2 device; The design method specifically includes the following steps: Step 1, the driving circuit timing includes Gout n-4, Gout n-3, Q point voltage, A point voltage, Gout n, Goutn+3 and Gout n+4. When Gout n-4 is High, Q point will be charged to VGH-Vth through T1 device, and T8 device is also turned on under the action of Gout n-4, Gout n-3 is low level, and A point voltage is low level; Step 2, the Gout n-3 is changed from low level to high level, the voltage of point A is charged from 0V to VGH-Vth, and the voltage of point Q is twice VGH-Vth; Step three, the CK clock signal changes from a low level to a high level, the Gout n output is a VGH high level, and the T1 device, T7 device, T8 device and T9 device are in a closed state, the A point voltage is coupled to twice the VGH-Vth by the C3 capacitor, and the Q point voltage is coupled to three times the VGH-Vth by the C1 capacitor. When the CK clock signal changes from a high level to a low level, the Q point clock signal is twice VGH-Vth, and when Gout n+4 is a high level, the T7 device and the T9 device are turned on, and the Q point voltage and the A point voltage are reset to a low level.

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