Memory controller, control method thereof, and memory system

Abstract

A memory controller includes a plurality of channels, wherein a first channel of the plurality of channels includes a first transmitter configured to generate a first data signal to a memory module, a first pull-up variable resistor coupled between a power supply voltage and an output of the first transmitter, a first pull-down variable resistor coupled to the output of the first transmitter, and a control circuit coupled to the plurality of channels for controlling the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module. Each transmitter adjusts a voltage level of a transmitted data signal by the first pull-up variable resistor and / or the first pull-down variable resistor, such that a middle voltage level of each data signal is as close as possible to the reference voltage, thereby obtaining a more accurate logic value.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a memory controller, a control method thereof, and a memory system, and more particularly, to a memory controller, a control method thereof, and a memory system. BACKGROUND

[0002] In a dynamic random access memory (DRAM) system, there are multiple channels between a DRAM controller and a DRAM module for transmitting data signals (i.e., DQ signals). Each channel can be used for bi-directional data transmission, i.e., the DRAM controller has a transmitter and a receiver for each channel, and the DRAM module also has a transmitter and a receiver for each channel. When the DRAM controller transmits DQ signals to the DRAM module through multiple channels, the receiver of the DRAM module can use a reference voltage to determine the logic value (i.e., bit) of the DQ signal. For example, if the receiver determines that the voltage level of the DQ signal is higher than the reference voltage, the receiver can determine that the DQ signal has a logic value of “1”; if the receiver determines that the voltage level of the DQ signal is lower than the reference voltage, the receiver can determine that the DQ signal has a logic value of “0”. Ideally, the reference voltage used by the receiver should be the average of the highest voltage level and the lowest voltage level of the DQ signal. However, due to channel mismatch and semiconductor process variation, the voltage levels of multiple channels can be different, i.e., a single reference voltage is not suitable for each receiver. In addition, near-ground signaling (NGS) is widely used in modern low-power DRAM interfaces, and the DQ signal using NGS technology usually has a lower swing and a higher speed. Therefore, if the reference voltage is not suitable for some receivers, the misjudgment of the logic value will become more serious. SUMMARY

[0003] Therefore, the present disclosure provides a memory controller, a control method thereof, and a memory system to solve the above problems.

[0004] According to a first aspect of the present disclosure, a memory controller is disclosed, comprising:

[0005] a plurality of channels, wherein a first channel of the plurality of channels comprises: a first transmitter configured to generate a first data signal to a memory module; a first pull-up variable resistor coupled between a power supply voltage and an output terminal of the first transmitter; a first pull-down variable resistor coupled to the output terminal of the first transmitter; and

[0006] a control circuit coupled to the plurality of channels, configured to control the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module.

[0007] According to a second aspect of the present application, a memory system is disclosed, comprising:

[0008] a memory controller comprising a plurality of transmitters, wherein the transmitters are configured to generate a plurality of data signals respectively; and

[0009] a memory module comprising a plurality of receivers, wherein the receivers compare the plurality of data signals with a reference voltage to generate a plurality of output signals respectively;

[0010] wherein the plurality of transmitters comprises a first transmitter, the memory controller further comprises a first pull-up variable resistor coupled between a power supply voltage and an output terminal of the first transmitter, and a first pull-down variable resistor coupled to the output terminal of the first transmitter, and the memory controller further comprises a control circuit configured to control the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module.

[0011] According to a third aspect of the present application, a control method of a memory controller is disclosed, wherein the memory controller comprises a plurality of channels, a first channel of the plurality of channels comprises:

[0012] a first transmitter;

[0013] a first pull-up variable resistor coupled between a power supply voltage and an output terminal of the first transmitter; and

[0014] a first pull-down variable resistor coupled to the output terminal of the first transmitter; and

[0015] the control method comprises the following steps:

[0016] controlling the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module.

[0017] The memory controller of the present application includes a plurality of channels, wherein a first channel of the plurality of channels includes a first transmitter configured to generate a first data signal to a memory module, a first pull-up variable resistor coupled between a power supply voltage and an output of the first transmitter, a first pull-down variable resistor coupled to the output of the first transmitter, and a control circuit coupled to the plurality of channels for controlling the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module. In the dynamic random access memory controller of the present application, each transmitter output can be controlled to have a data signal with an appropriate voltage level so that the receiver of the memory module can use the same reference voltage to accurately determine the logic value of the data signal. Each transmitter of the present application adjusts the voltage level of the transmitted data signal by the first pull-up variable resistor and / or the first pull-down variable resistor so that the middle voltage level of each data signal is as close to the reference voltage as possible, thereby more accurately obtaining the logic value. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A schematic diagram of a memory system according to an embodiment of the present application.

[0019] Figure 2 Some transmitters in the memory interface circuit of a DRAM controller and some receivers in the memory interface circuit of a DRAM module are shown according to an embodiment of the present application.

[0020] Figure 3 Data signals without a voltage level adjustment mechanism and data signals with a voltage level adjustment mechanism are shown according to an embodiment of the present application.

[0021] Figure 4 Adjustment of the middle voltage level of a data signal DQ according to an embodiment of the present application is shown

[0022] Figure 5 Adjustment of the middle voltage level of a data signal DQ according to an embodiment of the present application is shown Figure 6 A schematic diagram of a transmitter and related circuitry according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In the following detailed description of embodiments of the application, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific preferred embodiments of the application. The description of these embodiments is intended to be illustrative, and not to limit the scope of the application, as defined by the appended claims, and the following detailed description is not intended to limit the scope of the application. Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. Therefore, the detailed description is not intended to limit the scope of the application as defined by the appended claims. The following detailed description is presented to enable any person skilled in the art to make and use the application. For purposes of explanation and as required by the

[0024] It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary element, component, region, layer or section discussed below could be termed a second or secondary element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0025] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly. Additionally, it will be understood that, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0026] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0027] What will be understood is that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0028] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0029] Figure 1 This is a schematic diagram of a memory system 100 according to an embodiment of the present invention. Figure 1 As shown, the memory system 100 includes a memory controller (in this embodiment, the DRAM controller 110 serves as the memory controller) and a memory module (in this embodiment, the DRAM module 120 serves as the memory module). The DRAM controller 110 includes a memory interface circuit 112 and a control circuit 114, and the DRAM module 120 includes a memory interface circuit 122, a control circuit 124, and a memory array 126. In this embodiment, the DRAM controller 110 and the DRAM module 120 are connected by multiple connection lines, which are used to transmit at least multiple bidirectional data signals DQ, bidirectional data strobe signals DQS, multiple command signals CMD, and a differential clock signal CLK.

[0030] When the memory system 100 is implemented by a DRAM system, the command signals can include at least a row address strobe, a column address strobe, and a write enable signal. In addition, Figure 1 The clock signals or command signals shown can be unidirectional or bidirectional.

[0031] In the general operation of the memory system 100, the DRAM controller 110 is arranged to receive requests from a host or processor and to transfer data signals DQ, data strobe signals DQS, command signals CMD, clock signals CLK, and clock enable signals CKE to access (or access) the DRAM module 120. In addition, the control circuit 114 within the DRAM controller 110 can include related circuits, such as processing circuits, write / read buffers, control logic, and arbiters, to perform related operations. The memory interface circuit 112 of the DRAM controller 110 is used to output data signals DQ, data strobe signals DQS, command signals CMDs, and clock signals CLK to the DRAM module 120. The memory interface circuit 122 is used to receive data signals DQ, data strobe signals DQS, command signals CMDs, and clock signals CLK from the DRAM controller 110 and output data to the DRAM controller 110 through the DQ connection line. The control circuit 124 can include a read / write controller, a row decoder, and a column decoder, and the control circuit 124 is used to receive output signals from the memory interface circuit 122 to access the memory array 126.

[0032] Figure 2 Some transmitters 212_1-212_8 within the memory interface circuit 112 and some receivers 222_1-222_8 within the memory interface circuit 122 are shown according to one embodiment of the present application. In this embodiment, Figure 2 Eight channels between the DRAM controller 110 and the DRAM module 120 are shown, which are used to transmit data signals DQ. Regarding the eight channels, the data signals DQ are transmitted through the eight channels. In addition, Figure 2The first channel is shown, transmitter 212_1 is coupled between a supply voltage VDD_TX and a reference voltage (e.g. ground voltage or ground voltage), while receiver 222_1 is coupled between a supply voltage VDD_RX and a reference voltage (e.g. ground voltage); transmitter 212_1 is configured to receive a data signal DQ1 and output it to receiver 222_1, receiver 222_1 compares data signal DQ1 with reference voltage VREF to generate an output signal Vout1, wherein if data signal DQ1 is greater than reference voltage VREF, output signal Vout1 has a higher level, indicating that data signal DQ1 has a logic value of "1"; if data signal DQ1 is lower than reference voltage VREF, the level of output signal Vout1 is lower, indicating that the logic value of data signal DQ1 is "0". Similarly, the other channels work similarly to the first channel. For example, transmitter 212_8 is coupled between supply voltage VDD_TX and ground voltage, while receiver 222_8 is coupled between supply voltage VDD_RX and ground voltage; transmitter 212_8 is configured to receive data signal DQ8 and output it to receiver 222_8, receiver 222_8 compares data signal DQ8 with reference voltage VREF to generate an output signal, wherein if data signal DQ8 is greater than reference voltage VREF, output signal Vout8 has a higher level, indicating that data signal DQ8 has a logic value of "1"; if data signal DQ8 is lower than reference voltage VREF, the level of output signal Vout8 is lower, indicating that the logic value of data signal DQ8 is "0".

[0033] As described in the prior art, due to channel mismatch and semiconductor process variation, the voltage levels of the multiple channels (i.e. the DQ signals transmitted by transmitters 212_1-212_8) can be different, i.e. a single reference voltage VREF is not suitable for each receiver 222_1-222_8. To solve this problem, in memory interface circuit 112, each transmitter 212_1-212_8 has a voltage level adjustment mechanism to adjust the voltage level of the transmitted DQ signal, so that the intermediate voltage level of each data signal DQ is as close as possible to reference voltage VREF, wherein the intermediate voltage level can be the average of the highest voltage level and the lowest voltage level of data signal DQ. Specifically, taking the first channel as an example, pull-up variable resistor R WPU [1] is connected between supply voltage VDD_TX and the output of transmitter 212_1, pull-down variable resistor R WPD[1] is connected between the ground voltage (or ground voltage) and the output of the transmitter 212_1. In one embodiment, during the operation of the memory system 100, the DRAM module 120 can calibrate the reference voltage VREF based on the training signal to determine a suitable level of the reference voltage VREF, and the DRAM module 120 can feedback the information of the reference voltage VREF to the DRAM controller 110, so that the control circuit 114 can control the pull-up variable resistance R WPU [1] and / or the pull-down variable resistance R WPD [1] to make the intermediate voltage level of the DQ1 as close to the reference voltage VREF as possible. In another embodiment, the DRAM module 120 can feedback the bit error rate or the bit error count to the DRAM controller 110, so that the control circuit 114 can control the pull-up variable resistance R WPU [1] and / or the pull-down resistance R WPD [1] has the lowest error rate or the bit error count (which also means that the intermediate voltage level of the DQ1 received by the receiver 222_1 is very close to the reference voltage VREF).

[0034] Similarly, the voltage level adjustment mechanism of the other channels is similar to that of the first channel. Take the eighth channel as an example. The pull-up variable resistance R WPU [8] is connected between the power supply voltage VDD_TX and the output of the transmitter 212_8, and the pull-down variable resistance R WPD [8] is connected between the ground voltage and the output of the transmitter 212_8. In one embodiment, during the operation of the memory system 100, the DRAM module 120 can calibrate the reference voltage VREF based on the training signal to determine a suitable level of the reference voltage VREF, and the DRAM module 120 can feedback the information of the reference voltage VREF to the DRAM controller 110, so that the control circuit 114 can control the pull-up variable resistance R WPU [8] and / or the pull-down variable resistance R WPD [8] to make the intermediate voltage level of the DQ8 as close to the reference voltage VREF as possible. In another embodiment, the DRAM module 120 can feedback the bit error rate or the bit error count to the DRAM controller 110, so that the control circuit 114 can control the pull-up variable resistance R WPU [8] and / or the pull-down resistance R WPD [8] has the lowest error rate or the bit error count (which also means that the intermediate voltage level of the DQ8 received by the receiver 222_8 is very close to the reference voltage VREF).

[0035] Figure 3Data signals without a voltage level adjustment mechanism and data signals with a voltage level adjustment mechanism are shown according to an embodiment of the present invention. (Reference) Figure 3 The upper part, if the memory interface circuit 112 does not have a voltage level adjustment mechanism (i.e., pull-up variable resistor R) WPU [1]-R WPU [8] and / or pull-down variable resistor R WPD [1]-R WPD [8] Not appearing Figure 2 In this context, the reference voltage VREF may not be suitable for determining the logic value of each data signal. For example, the intermediate voltage level of data signal DQ1 may be lower than the reference voltage VREF, the intermediate voltage level of data signal DQ2 may be higher than the reference voltage VREF, the intermediate voltage level of data signal DQ1 may be lower than the reference voltage VREF, and the intermediate voltage level of data signal DQ1 may be equal to the reference voltage VREF. Figure 3 The lower part is controlled by the pull-up variable resistor R of the control channel. WPU [1]-R WPU [8] and / or pull-down variable resistor R WPD [1]-R WPD [8] Each data signal DQ1 to DQ8 has an intermediate voltage level that is equal to or very close to the reference voltage VREF. Therefore, the reference voltage VREF is suitable for determining the logic value of each data signal DQ1 to DQ8. In addition, in this embodiment, the intermediate voltage level of data signal DQ1 is different from that of data signal DQ2 by controlling the pull-up and / or pull-down variable resistors of the control channel.

[0036] exist Figure 2 In the embodiment shown, the pull-up variable resistor R WPU [1]-R WPU [8] is a weakly-pull-high resistor, and the pull-down variable resistor R WPD [1]-R WPD [8] is a weak pull-down resistor. Therefore, the pull-up variable resistor R WPU [1]-R WPU [8] and pull-down variable resistor R WPD [1]-R WPD Each of [8] has a high resistance. Furthermore, the memory interface circuit 122 of the DRAM module 120 has an on-die termination resistor R. ODT [1]-R ODT [8] To improve impedance mismatch in transmission lines, wherein the on-chip terminating resistor R ODT [1]-R ODT[8] These are located at the input terminals of receivers 222_1-222_8, respectively. In this embodiment, the pull-up variable resistor R... WPU [1]-R WPU [8] and pull-down variable resistor R WPD [1]-R WPD The resistance of each of [8] is much higher than the terminal resistance R of each chip. ODT [1]–R ODT [8] The resistor, for example, the variable resistor R WPU [1] / R WPD The resistance of [1] is the on-chip terminating resistance R. ODT [1] Hundreds of times the resistance.

[0037] Figure 4 This illustrates the adjustment of the intermediate voltage level of a data signal DQ (e.g., each of DQ1-DQ8) according to an embodiment of the present invention, wherein the symbol R ODT It can be used to represent the terminating resistance R on each die. ODT [1]–R ODT [8], symbol R WPU This can represent each pull-up variable resistor R WPU [1]–R WPU [8], symbol R OP / R ON The output impedance of each transmitter is represented by 212_1–212_8. For example... Figure 4 As shown, assuming the data signal DQ initially has a highest voltage level VOH and a lowest voltage level 0V, then the intermediate voltage level V1 of the data signal DQ is equal to 0.5*VOH, and the output impedance R... OP / R ON The resistance value of the terminating resistor ODT on the transmitter and the die is equal to "R", and the pull-up variable resistor R is... WPU The resistance value is much greater than "R". Control circuit 114 can control the pull-up variable resistor R. WPU The resistance value is used to increase the minimum and maximum voltage levels of the data signal DQ, and the equations for increasing the minimum and maximum voltage levels are as follows:

[0038] ΔVPD=(VDD+TX)*((0.5*R) / (R WPU +0.5*R))=ΔV (1);

[0039] ΔVPU=(VDD+TX)*R / (R WPU +R))=2*ΔV (2).

[0040] Therefore, since the new highest voltage level becomes VOH+2*ΔV, and the new highest lowest voltage level becomes ΔV, the control circuit 114 can determine that the middle voltage level VI' of the data signal DQ becomes (0.5*VOH+1.5*ΔV).

[0041] Figure 5 The adjustment of the middle voltage level of the data signal DQ (e.g., each of DQ1-DQ8) is shown according to one embodiment of the present application, in which the symbol RODT can be used to represent the termination resistance R ODT [1] -R ODT [8], the symbol R WPD can be used to represent each pull-down variable resistor R WPD [1] -R WPD [8], the symbol R OP / R ON is used to represent the output impedance of each pull-down variable resistor 212_1-212_8. As shown, Figure 5 assuming that the data signal DQ initially has a highest voltage level VOH and a lowest voltage level OV, the middle voltage level VI of the data signal DQ is equal to 0.5*VOH, the output impedance ROP / RON is equal to 'R', and the resistance value of the transmitter and the termination resistance RODT on the die is equal to 'R'. The resistance value of the pull-up variable resistor R WPU is much greater than 'R'. The control circuit 114 can control the resistance value of the pull-down variable resistor R WPD to reduce the highest voltage level of the data signal DQ, and the formula for the reduction of the highest voltage level is as follows:

[0042] ΔVPU = -1*(VDD+TX)*R / (R WPD +R)) = 2*ΔV (3).

[0043] Therefore, since the new highest voltage level becomes VOH-2*ΔV, the control circuit 114 can determine that the middle voltage level VI' of the data signal DQ becomes (0.5*VOH-ΔV).

[0044] Figure 4 the resistance value of the pull-up variable resistor R WPU and the relationship of the middle voltage level of the data signal DQ, Figure 5 the resistance value of the pull-down variable resistor R WPD and the relationship of the middle voltage level of the data signal DQ, therefore, the control circuit 114 can determine the appropriate middle voltage level of the data signal DQ by controlling the resistance values of the variable resistors R WPU and R WPD .

[0045] It should be noted that, Figure 4 and Figure 5The embodiments shown are for illustrative purposes only. In other embodiments, the testing phase of the memory system 100 may have a built-in lookup table, and the control circuit 114 may refer to the reference voltage REF and the lookup table to determine the variable resistor R. WPU and R WPD The appropriate resistance value.

[0046] Figure 6 This is a schematic diagram of the transmitter and related circuits according to an embodiment of the present invention, wherein... Figure 2 Taking the transmitter 212_1 shown as an example, but... Figure 6 The structure shown can be applied to any transmitter 212_1–212_8. For example... Figure 6 As shown, transmitter 212_1 includes transistors M1-M4 and two resistors R1 and R2. The drain of transistor M1 is coupled to the power supply voltage VDD_TX, the drain of transistor M2 is coupled to the source of transistor M1, and the source of transistor M2 is coupled to the output terminal N1 through resistor R1. The source of transistor M4 is coupled to ground, the source of transistor M3 is coupled to the drain of transistor M3, and the drain of transistor M3 is coupled to the output terminal N1 through resistor R2. Transistors M1 and M4 are controlled by the driver enable signal DRV_EN, which is configured to enable transistors M1 and M4 to allow transmitter 212_1 to transmit data signals and disable transistors M1 and M4 to prevent transmitter 212_1 from transmitting data signals. Transistors M2 and M3 are controlled by pull-up signal DATA_PU[1] and pull-down signal DATA_PD[1], respectively. If transistor M2 is enabled and transistor M3 is disabled, transmitter 212_1 will output a data signal with a higher voltage level; if transistor M2 is disabled and transistor M3 is enabled, transmitter 212_1 will output a data signal with a lower voltage level.

[0047] also, Figure 6 It also includes transistors M5-M8 and multiplexers 610 and 620, wherein the source of transistor M5 is coupled to the power supply voltage VDD_TX, the source of transistor M6 is coupled to the drain of transistor M5, and the drain of transistor M6 is coupled to the output terminal N1 through a pull-up variable resistor RWPU[1]. The source of transistor M8 is coupled to the ground voltage, the source of transistor M7 is coupled to the drain of transistor M8, and the drain of transistor M7 is coupled to the output terminal N1 through a pull-down variable resistor RWPU[1]. WPD [1] Coupled to output terminal N1. In this embodiment, transistors M5 and M6 act as a switching circuit, selectively connecting the power supply voltage VDD_TX to the pull-up variable resistor R. WPU [1] Transistors M7 and M8 act as another switching circuit, selectively connecting the ground voltage to the pull-down variable resistor R. WPD[1]. The multiplexer 610 receives the dynamic mode pull-up signal DATA WPU [1] and the static mode pull-up signal OE WPU [1], and selects one of the dynamic mode pull-up signal DATA WPU [1] and the static mode pull-up signal OE WPU [1] according to the selection signal SEL to generate a first multiplexed signal to control the transistors M5 and M6; the multiplexer 620 receives the dynamic pull-down signal DATA WPD [1] and the static pull-down signal OE WPD [1], and selects one of the dynamic mode pull-down signal DATA WPD [1] and the static mode pull-down signal OE WPD [1] according to the selection signal SEL to generate a second multiplexed signal to control the transistors M7 and M8. In this embodiment, the static mode means that the transistors M5-M8 are always enabled or activated if the transmitter 212_1 is allowed to transmit the data signal DQ1 (e.g., when the output enable or activation (OE) signal of the DRAM interface is open), and the dynamic mode means that the transistors M5-M8 are enabled or activated only when the transmitter 212_1 transmits the data signal DQ1, i.e., the transistors M5-M8 are controlled to be enabled (or activated) or disabled bit by bit, wherein the dynamic mode can reduce power consumption.

[0048] In the above embodiment, all the transmitters 212_1-212_8 have the voltage level adjustment mechanism to adjust the voltage level of the data signals DQ1-DQ8, respectively. However, the present application is not limited thereto. In other embodiments, only some of the transmitters 212_1-212_8 have the voltage level adjustment mechanism, and the voltage level of the data signals outputted by the other transmitters is not controlled by the reference voltage VREF of the DRAM module 120. Such alternative design should be within the scope of the present application.

[0049] In short, in the dynamic random access memory controller of the present application, each transmitter can be controlled to output a data signal having a proper voltage level, so that the receivers of the memory module can use the same reference voltage to accurately determine the logic value of the data signal. That is, the receivers of the memory module 120 can only provide one set of adjustable reference voltage, so that all the signals (the data signals DQ1-DQ8) transmitted by the transmitters of the DRAM controller 110 will see the same reference voltage (provided by the receivers of the memory module 120). Therefore, the voltage level adjustment mechanism of the DRAM controller can improve the performance of the receivers in the DRAM module.

[0050] Those skilled in the art will readily observe that numerous modifications and changes in the described embodiments can be made without departing from the teachings of the present application. Accordingly, the above disclosure is intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

Claims

1. A memory controller, comprising: comprises a first channel of the plurality of channels, the first channel comprising: a first transmitter configured to generate a first data signal to a memory module; a first pull-up variable resistor coupled between a power voltage and an output terminal of the first transmitter; a first pull-down variable resistor coupled between the output terminal of the first transmitter and a ground voltage; and a first switch circuit coupled between the first pull-up variable resistor and the power voltage, to connect the power voltage to the first pull-up variable resistor or to disconnect the first pull-up variable resistor from the power voltage; a second switch circuit coupled between the first pull-down variable resistor and the ground voltage, to connect the ground voltage to the first pull-down variable resistor or to disconnect the first pull-down variable resistor from the ground voltage; a control circuit coupled to the plurality of channels, to control the first pull-up variable resistor and / or the first pull-down variable resistor according to a reference voltage used by the memory module; wherein the first transmitter comprises a first transistor, a second transistor and a first resistor disposed between the power voltage and the output terminal of the first transmitter, and a second resistor, a third transistor and a fourth transistor disposed between the output terminal of the first transmitter and the ground voltage; wherein the first transistor and the fourth transistor are configured to allow or prohibit the first transmitter to transmit the first data signal, and the second transistor and the third transistor are configured to control a voltage level of the first data signal to be high or low; the control circuit is configured to control the first pull-up variable resistor and / or the first pull-down variable resistor to cause an intermediate voltage level of the first data signal output by the first transmitter to be substantially equal to the reference voltage used by the memory module. a second channel of the plurality of channels comprises:

2. The memory controller of claim 1, wherein, a second transmitter configured to generate a second data signal to the memory module; a second pull-up variable resistor coupled between the power voltage and an output terminal of the second transmitter; and a second pull-down variable resistor coupled to the output terminal of the second transmitter; wherein the control circuit is further configured to control the second pull-up variable resistor and / or the second pull-down variable resistor according to the reference voltage used by the memory module. the control circuit is configured to control the second pull-up variable resistor and / or the second pull-down variable resistor to cause an intermediate voltage level of the second data signal output by the second transmitter to be substantially equal to the reference voltage used by the memory module.

3. The memory controller of claim 2, wherein, the control circuit controls the first pull-up / pull-down variable resistor and the second pull-up / pull-down variable resistor separately, such that the intermediate voltage level of the second data signal is not equal to the intermediate voltage level of the first data signal.

4. The memory controller of claim 3, wherein, the first switch circuit is controlled by a static mode pull-up signal, such that the first switch circuit is always enabled when the first transmitter is enabled.

5. The memory controller of claim 1, wherein, the first switch circuit is controlled by a dynamic mode pull-up signal, such that the first switch circuit is enabled only when the first transmitter generates the first data signal, and the control circuit enables the first switch circuit bit by bit.

6. The memory controller of claim 1, wherein, comprises a memory controller comprising a plurality of transmitters, wherein the transmitters are configured to generate a plurality of data signals respectively; and 7. A memory system, characterized by comprising: a control circuit coupled to the plurality of transmitters, to control the transmitters according to a reference voltage used by a memory module. ​ ​ A memory module includes a plurality of receivers, wherein the plurality of receivers respectively compare the plurality of data signals with a reference voltage to generate a plurality of output signals; The plurality of transmitters includes a first transmitter, wherein the first transmitter includes a first transistor, a second transistor and a first resistor disposed between a power supply voltage and an output of the first transmitter, and a second resistor, a third transistor and a fourth transistor disposed between the output of the first transmitter and a ground voltage; wherein the first transistor and the fourth transistor are used to allow or prohibit the first transmitter to transmit a first data signal of the plurality of data signals, and the second transistor and the third transistor are used to control a voltage level of the first data signal to be high or low; the memory controller further includes a first pull-up variable resistor coupled between the power supply voltage and the output of the first transmitter, a first pull-down variable resistor coupled between the output of the first transmitter and the ground voltage, a first switch circuit coupled between the first pull-up variable resistor and the power supply voltage to connect the power supply voltage to the first pull-up variable resistor or disconnect the first pull-up variable resistor from the power supply voltage, and a second switch circuit coupled between the first pull-down variable resistor and the ground voltage to connect the ground voltage to the first pull-down variable resistor or disconnect the first pull-down variable resistor from the ground voltage; and a control circuit configured to control the first pull-up variable resistor and / or the first pull-down variable resistor according to the reference voltage used by the memory module. The control circuit is configured to control the first pull-up variable resistor and / or the first pull-down variable resistor to make an intermediate voltage level of the first data signal output by the first transmitter substantially equal to the reference voltage used by the memory module.

8. A control method of a memory controller, characterized by, The memory controller includes a plurality of channels, a first channel of the plurality of channels includes: a first transmitter including a first transistor, a second transistor and a first resistor disposed between a power supply voltage and an output of the first transmitter, and a second resistor, a third transistor and a fourth transistor disposed between the output of the first transmitter and a ground voltage; wherein the first transistor and the fourth transistor are used to allow or prohibit the first transmitter to transmit a first data signal, and the second transistor and the third transistor are used to control a voltage level of the first data signal to be high or low; a first pull-up variable resistor coupled between the power supply voltage and the output of the first transmitter; and a first pull-down variable resistor coupled between the output of the first transmitter and the ground voltage; and a first switch circuit coupled between the first pull-up variable resistor and the power supply voltage to connect the power supply voltage to the first pull-up variable resistor or disconnect the first pull-up variable resistor from the power supply voltage, and a second switch circuit coupled between the first pull-down variable resistor and the ground voltage to connect the ground voltage to the first pull-down variable resistor or disconnect the first pull-down variable resistor from the ground voltage. The control method comprises the following steps. The control method is used for controlling the first pull-up variable resistor and / or the first pull-down variable resistor to make the intermediate voltage level of the first data signal output by the first transmitter substantially equal to the reference voltage used by the memory module. The control method comprises the following steps. The control method is used for controlling the first pull-up variable resistor and / or the first pull-down variable resistor to make the intermediate voltage level of the first data signal output by the first transmitter substantially equal to the reference voltage used by the memory module.

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