Power failure detection circuit and semiconductor storage device

Abstract

The present invention provides a power failure detection circuit and a semiconductor storage device, which can more accurately detect the reduction of the supply voltage. The power failure detection circuit of the present invention has: a BGR circuit, which generates a reference voltage VREF; a resistor division circuit, which generates a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on the supply voltage VCC; a first comparator, which outputs a reset signal PDDRST when detecting that VCC_DIV1 < VREF; a second comparator, which outputs a switching signal SEL when detecting that VCC_DIV2 < VREF; a charging pump circuit, which generates a boosted voltage VXX based on the supply voltage VCC; and a switching circuit, which switches the operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

Description

Technical Field

[0001] The present invention relates to a power failure detection circuit and a semiconductor storage device, and more particularly to detection of a drop in supply voltage (power failure detection). Background Art

[0002] Flash memory includes a power failure detection circuit to detect a drop in the supply voltage VCC caused by noise or peak current consumption, etc. The purpose of the power failure detection circuit is to prevent unexpected abnormal operations (e.g., programming operations or erasing operations) that may occur due to a low supply voltage VCC level. Complementary metal oxide semiconductor (CMOS) circuits or other internal circuits have a supply voltage VCC range for accurate operation.

[0003] On the other hand, the flash memory also needs to detect power-on. Therefore, the power-off detection level must satisfy the following relationship.

[0004] VLLOGIC<VPDD<VPOD<VCC range for accurate operation

[0005] VLLOGIC: The limit of the supply voltage VCC for the internal logic circuit to operate accurately

[0006] VPDD: Power-off detection level

[0007] VPOD: Power-on detection level

[0008] According to the requirements of this relationship, the flash memory needs to minimize the variation of the power-off detection level caused by the process and temperature.

[0009] Figure 1 The power failure detection circuit 10 includes: a band gap reference (BGR) circuit 20, which generates a reference voltage VREF based on a supply voltage VCC; a resistor division circuit 30, which divides the supply voltage VCC by resistors and generates an internal voltage VCC_DIV at a node N; and a comparator 40, which compares the reference voltage VREF with the internal voltage VCC_DIV and outputs a reset signal PDDRST that transitions from an H level to an L level when VCC_DIV < VREF is detected.

[0010] The BGR circuit 20 generates a reference voltage VREF that does not depend on the fluctuation of the supply voltage VCC or the operating temperature, thereby suppressing the fluctuation of the power-off detection level. When the supply voltage VCC drops to the power-off detection level, the comparator 40 detects that VCC_DIV<VREF and outputs an L-level reset signal PDDRST. The reset signal PDDRST is output to an internal circuit such as a central processing unit or a logic circuit, and the internal circuit performs a power-off action in response to the reset signal PDDRST, such as stopping the operation of the charge pump circuit or resetting the CPU or the logic circuit.

[0011] Figure 2 This is an example of an ideal operating waveform of the power failure detection circuit 10. For example, the supply voltage VCC is set to 1.8V, the reference voltage VREF of the BGR circuit 20 is set to 1.2V, and the power failure detection level is set to 1.3V. At time t1, if the supply voltage VCC drops, the internal voltage VCC_DIV drops accordingly. When the supply voltage VCC drops to 1.3V at time t2, the internal voltage VCC_DIV crosses the reference voltage VREF, that is, the comparator 40 detects that VCC_DIV < VREF, and outputs the reset signal PDDRST of the L level.

[0012] If the supply voltage VCC drops further, the BGR circuit 20 may generate a voltage lower than the desired reference voltage VREF. For example, when the reference voltage VREF is designed to generate 1.2V, if the supply voltage VCC drops to about 1.3V, the reference voltage VREF may be lower than 1.2V. In this case, even if the supply voltage VCC drops to the power-off detection level, the comparator 40 cannot detect that VCC_DIV<VREF, and a reset may not be performed properly.

[0013] This situation is shown in Figure 3 At time t1, the supply voltage VCC decreases, and the internal voltage VCC_DIV decreases accordingly. At time t2, the supply voltage VCC decreases to the power failure detection level. At time t1A earlier than time t2, if the operation of the BGR circuit 20 becomes unstable, the reference voltage VREF decreases, and at time t2, the reference voltage VREF and the internal voltage VCC_DIV do not cross, and the comparator 40 cannot detect the internal voltage VCC_DIV. As a result, the power failure of the supply voltage VCC cannot be accurately detected. Summary of the invention

[0014] The present invention is an invention for solving such conventional problems, and an object of the present invention is to provide a power failure detection circuit and a semiconductor memory device that can more accurately detect a drop in supply voltage.

[0015] The power-off detection circuit of the present invention comprises: a reference voltage generating circuit, which generates a reference voltage; an internal voltage generating circuit, which generates a first internal voltage and a second internal voltage lower than the first internal voltage based on a supply voltage; a first detection circuit, which outputs a power-off reset signal when it detects that the first internal voltage is lower than the reference voltage; a second detection circuit, which outputs a switching signal when it detects that the second internal voltage is lower than the reference voltage; a boosting circuit, which generates a boosted voltage based on the supply voltage; and a switching component, which supplies the supply voltage or the voltage of the boosting circuit to the reference voltage generating circuit based on the switching signal.

[0016] A semiconductor memory device of the present invention includes: the power-off detection circuit described above; and an execution unit that executes a power-off operation in response to a detection result of the first detection circuit of the power-off detection circuit.

[0017] According to the present invention, before the supply voltage drops to the power-off detection level, the voltage supplied to the reference voltage generating circuit is switched from the supply voltage to the voltage of the boost circuit, thereby stabilizing the operation of the reference voltage generating circuit within a certain period and suppressing the reduction of the reference voltage during this period, thereby accurately detecting the supply voltage drop to the power-off detection level. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structure representing an existing power failure detection circuit;

[0019] Figure 2 Yes means Figure 1 The ideal operating waveform of the power failure detection circuit shown;

[0020] Figure 3 Yes means Figure 1 The operating waveform of the BGR circuit of the power failure detection circuit shown in FIG. 1 when the reference voltage is reduced;

[0021] Figure 4 2 is an internal structure of a flash memory according to an embodiment of the present invention;

[0022] Figure 5 2 is a diagram showing the structure of a power failure detection circuit according to an embodiment of the present invention;

[0023] Figure 6 2 is an operational waveform showing the power failure detection circuit according to the embodiment of the present invention. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0025] Next, the embodiments of the present invention are described in detail with reference to the accompanying drawings. In a preferred embodiment, the semiconductor storage device of the present invention is a non-volatile memory such as a NAND type or NOR type flash memory, a resistance variable memory, a magnetic variable memory, or a microprocessor, a microcontroller, a logic circuit, an application-specific integrated circuit (ASIC), a processor for processing images or sounds, a processor for processing signals such as wireless signals, etc. embedded in such a non-volatile memory. In the following description, a NAND type flash memory is exemplified.

[0026] The schematic structure of the NAND flash memory of the embodiment of the present invention is shown in FIG. Figure 4 The flash memory 100 of the present embodiment is composed of the following components: a memory cell array 110, which arranges a plurality of memory cells in a matrix; an input / output buffer 120, which is connected to an external input / output terminal I / O; an address register 130, which receives address data from the input / output buffer 120; a controller 140, which receives instruction data from the input / output buffer 120 and controls each part; a word line selection circuit 150, which selects a block and a word line based on the decoding result of the row address information Ax from the address register 130; and a page buffer / sensing circuit 160, which keeps the data from the word line selection. The data read out of the page selected by the selection circuit 150, or the data to be programmed into the selected page; the column selection circuit 170 selects the column based on the decoding result of the column address information Ay from the address register 130; the power-off detection circuit 180 outputs the reset signal PDDRST when it detects that the supply voltage VCC supplied to the power terminal drops to the power-off detection level; and the internal voltage generation circuit 190 generates various voltages required for reading, programming and erasing data (programming voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

[0027] The memory cell array 110 has m blocks BLK(0), BLK(1), ..., BLK(m-1) arranged along the column direction. In one block, a plurality of NAND strings are formed, and one NAND string is formed by connecting a plurality of memory cells (for example, 64), bit line side selection transistors, and source line side selection transistors in series. The drain of the bit line side selection transistor is connected to a corresponding bit line, and the source of the source line side selection transistor is connected to a common source line. The NAND string can be formed two-dimensionally on the surface of the substrate, or three-dimensionally on the surface of the substrate. In addition, the memory cell can be a single-level cell (SLC) type that stores 1 bit (binary data), or a type that stores multiple bits.

[0028] In the read operation, a positive voltage is applied to the bit line, a voltage (e.g., 0V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5V) is applied to the non-selected word line, the bit line side selection transistor and the source line side selection transistor are turned on, and 0V is applied to the common source line. In the programming (writing) operation, a high voltage programming voltage Vpgm (15V to 20V) is applied to the selected word line, an intermediate potential (e.g., 10V) is applied to the non-selected word line, the bit line side selection transistor is turned on, the source line side selection transistor is turned off, and a potential corresponding to the data "0" or "1" is supplied to the bit line. In the erase operation, 0V is applied to the selected word line in the block, and a high voltage (e.g., 20V) is applied to the P-well.

[0029] If the power-off detection circuit 180 detects that the supply voltage VCC drops to the power-off detection level, it outputs a reset signal PDDRST that transitions from the H level to the L level to the controller 140 or other internal circuits. In response to the reset signal PDDRST, the controller 140 performs a power-off operation according to a code read from a read-only memory (ROM) / random access memory (RAM). In the power-off operation, for example, the internal circuits including the controller 140 are reset, or the charging pump circuit included in the internal voltage generating circuit 190 is stopped.

[0030] Figure 5 1 shows the internal structure of the power failure detection circuit 180. The power failure detection circuit 180 includes: a BGR circuit 200, which generates a reference voltage VREF with little variation or temperature dependency of the supply voltage VCC; a resistor division circuit 210, which generates a first internal voltage VCC_DIV1 at a node N1 based on the supply voltage VCC, and generates a second internal voltage VCC_DIV2 at a node N2 that is lower than the first internal voltage VCC_DIV1; a first comparator 220A, which compares the reference voltage VREF with the first internal voltage VCC_DIV1, and outputs a voltage VCC_DIV2 when it is detected that VREF>VCC_DIV1. A reset signal PDDRST of an L level; a second comparator 220B, which compares the reference voltage VREF with the second internal voltage VCC_DIV2 and, when detecting that VREF>VCC_DIV2, outputs a switching signal SEL that migrates from an H level to an L level; a charging pump circuit 230, which generates a boosted voltage VXX at an output node N3 based on the supply voltage VCC; and a switching circuit 240, which supplies the voltage VXX generated by the charging pump circuit 230 or the supply voltage VCC to the BGR circuit 200 based on the switching signal SEL.

[0031] The resistor division circuit 210 generates a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2. Figure 1 The internal voltage VCC_DIV shown is the same as that for setting the power failure detection level. The second internal voltage VCC_DIV2 is a voltage for detecting that the supply voltage VCC has dropped to a certain level before the supply voltage VCC drops to the power failure detection level. As described later, it is a voltage for setting a switching detection level for switching the power supply to the BGR circuit 200. The first internal voltage and the second internal voltage have a relationship of VCC_DIV2<VCC_DIV1.

[0032] In one embodiment, the charge pump circuit 230 is included in the internal voltage generating circuit 190 and operates when the flash memory 100 is in a busy state (not in a standby state). The charge pump circuit 230 generates various boosted voltages VXX according to the supply voltage VCC. For example, when the supply voltage VCC is 1.8V, a read pass voltage (e.g., 6V), a programming voltage (e.g., 16V), an erase voltage (e.g., 20V), etc. are generated. In other embodiments, the charge pump circuit 230 can also be separated from the internal voltage generating circuit 190 and specifically set in the power-off detection circuit 180. In this case, the charge pump circuit 230 can always operate regardless of whether the flash memory 100 is in a busy state.

[0033] The switching circuit 240 includes a VCC_BGR regulator 242 and a VCC_BGR conversion circuit 244. The VCC_BGR regulator 242 is connected to the node N3 of the charge pump circuit 230, and generates a voltage VCC_BGR for supplying to the BGR circuit 200 according to the voltage VXX supplied via the node N3. The voltage VCC_BGR is a voltage substantially equal to or lower than the supply voltage VCC (wherein the BGR circuit can normally generate a voltage of the reference voltage VREF). The circuit structure of the VCC_BGR regulator 242 is not particularly limited, and for example, it can be composed of a resistor division circuit or a comparator.

[0034] The VCC_BGR conversion circuit 244 receives the voltage VCC_BGR generated by the VCC_BGR regulator 242 and the supply voltage VCC, and supplies either the voltage VCC_BGR or the supply voltage VCC to the BGR circuit 200 in response to the switching signal SEL of the second comparator 220B. Specifically, when the switching signal SEL is at an H level, the VCC_BGR conversion circuit 244 supplies the supply voltage VCC to the BGR circuit 200, and when the switching signal SEL is at an L level, the VCC_BGR conversion circuit 244 supplies the voltage VCC_BGR to the BGR circuit 200.

[0035] Figure 6 The operation waveform of the power failure detection circuit of this embodiment is shown. When the supply voltage VCC is within the normal range, the switching signal SEL is at the H level, and the VCC_BGR conversion circuit 244 supplies the supply voltage VCC to the BGR circuit 200. At time t1, if the supply voltage VCC decreases, the first internal voltage VCC_DIV1 and the second internal voltage VCC_DIV2 also decrease accordingly.

[0036] At time t2, when the supply voltage VCC drops to the switching detection level, the second comparator 220B detects that VCC_DIV2<VREF and outputs a switching signal SEL that transitions from the H level to the L level. The VCC_BGR conversion circuit 244 switches the voltage supplied to the BGR circuit 200 from the supply voltage VCC to the voltage VCC_BGR generated by the VCC_BGR regulator 242 in response to the switching signal SEL.

[0037] Thereafter, even if the supply voltage VCC further decreases (indicated by the dotted line), the voltage VCC_BGR generated by the VCC_BGR regulator 242 does not immediately decrease due to the boosted voltage VXX, but maintains a certain potential for a certain period of time. By maintaining a certain potential, during this period, the BGR circuit 200 operates stably and generates the desired reference voltage VREF.

[0038] At time t3, when the supply voltage VCC drops to the power-off detection level, the comparator 220A detects that VCC_DIV1<VREF and outputs the reset signal PDDRST that changes from the H level to the L level. The flash memory 100 performs a reset operation in response to the reset signal PDDRST.

[0039] If the supply voltage VCC is within the normal range, the BGR circuit 200 generates the desired reference voltage VREF. If the supply voltage VCC decreases more, there is a concern that the reference voltage VREF may decrease. For example, when the reference voltage VREF of the BGR circuit 200 is 1.2V and the power failure detection level is set to 1.3V, if the supply voltage VCC decreases to about 1.3V, the reference voltage VREF will become lower than 1.2V. In this case, even if the supply voltage VCC decreases to the power failure detection level, the comparator 220A cannot detect that VCC_DIV1 < VREF.

[0040] In this embodiment, before the supply voltage VCC drops to the power failure detection level, the voltage VCC_BGR generated by the voltage VXX obtained by boosting the supply voltage VCC is supplied to the BGR circuit 200, thereby ensuring the stable operation of the BGR circuit 200 for a certain period of time, and during this period, suppressing the decrease of the reference voltage VREF, thereby reliably detecting that the supply voltage VCC reaches the power failure detection level. Furthermore, during the busy period, the power consumption of the flash memory is large, and the drop of the supply voltage VCC is also aggravated. Even if a part of the power of the charge pump circuit 230 is used for the power failure detection circuit 180, it is extremely small from the perspective of the overall power consumption, and there is no particular problem.

[0041] In the above embodiment, a charge pump circuit is exemplified as a circuit for boosting the supply voltage VCC, but the boost circuit may be another circuit (for example, a boost-type DC / DC converter).

[0042] Furthermore, the configuration of the switching circuit 240 shown in the above embodiment is an example, and any circuit may be used as long as it can supply either the boosted voltage VCC_BGR or the supply voltage VCC to the BGR circuit 200 based on the switching signal SEL.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power failure detection circuit, characterized in that: include: A reference voltage generating circuit generates a reference voltage; an internal voltage generating circuit that generates a first internal voltage and a second internal voltage lower than the first internal voltage based on a supply voltage; A first detection circuit outputs a power-off reset signal when detecting that the first internal voltage is lower than the reference voltage; A second detection circuit outputs a switching signal when detecting that the second internal voltage is lower than the reference voltage; a boost circuit that generates a boosted voltage based on the supply voltage; as well as a switching means for supplying the supply voltage or the voltage of the booster circuit to the reference voltage generating circuit based on the switching signal, The first detection circuit includes a first comparator that compares the first internal voltage with the reference voltage, and the second detection circuit includes a second comparator that compares the second internal voltage with the reference voltage.

2. The power failure detection circuit according to claim 1, characterized in that: When the second detection circuit detects that the second internal voltage is lower than the reference voltage, the switching means supplies the voltage of the booster circuit to the reference voltage generation circuit.

3. The power failure detection circuit according to claim 1, characterized in that: The first internal voltage defines a power-off detection level, and the second internal voltage defines a switching detection level of a voltage of the booster circuit according to the supply voltage associated with the reference voltage generation circuit.

4. The power failure detection circuit according to claim 1, characterized in that: The switching component includes: a regulator that generates a certain voltage according to the voltage of the boost circuit; and a conversion circuit that receives the voltage generated by the regulator and the supply voltage, and supplies either the certain voltage or the supply voltage to the reference voltage generating circuit based on the switching signal.

5. The power failure detection circuit according to claim 1, characterized in that: The internal voltage generating circuit includes a resistance dividing circuit.

6. The power failure detection circuit according to claim 1, characterized in that: The reference voltage generating circuit includes a bandgap reference circuit.

7. A semiconductor storage device, characterized in that: include: A power failure detection circuit as claimed in any one of claims 1 to 6; as well as An execution unit executes a power-off action in response to a detection result of the first detection circuit of the power-off detection circuit.

8. The semiconductor memory device according to claim 7, wherein: The power-off action includes resetting the internal circuit.

9. The semiconductor memory device according to claim 7, wherein: The boost circuit is a charging pump circuit that operates when reading, programming or erasing the NAND type memory cell array.

10. The semiconductor memory device according to claim 7, wherein: The power failure detection circuit operates during the busy period of the read, program or erase operation.

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