Interconnect structure with dielectric cap layer and etch stop layer stack

Abstract

The present disclosure relates to interconnect structures having a dielectric cap layer and an etch stop layer stack. A method of forming a semiconductor device includes forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack includes a plurality of etch stop layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an interconnect structure having a dielectric cap layer and an etch stop layer stack. BACKGROUND

[0002] High-density integrated circuits, such as very large scale integration (VLSI) circuits, are typically formed with multiple metal interconnects for use as a three-dimensional wiring structure. The purpose of the multiple interconnects is to properly link together densely packed devices. As the level of integration increases, the parasitic capacitance effects between the metal interconnects, which cause RC delay and crosstalk, can increase accordingly. To reduce the parasitic capacitance between the metal interconnects and increase the conduction speed, low-k dielectric materials are commonly used to form interlayer dielectric (ILD) layers and intermetal dielectric (IMD) layers.

[0003] Metal lines and vias are formed in the IMD layers. The formation process can include forming an etch stop layer over the first conductive features, and forming a low-k dielectric layer over the etch stop layer. The low-k dielectric layer and the etch stop layer are patterned to form trenches and via openings. The trenches and via openings are then filled with a conductive material, and then a planarization process is performed to remove excess conductive material, thereby forming the metal lines and vias. SUMMARY

[0004] According to one aspect of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming first conductive features in a first dielectric layer disposed over a substrate; forming a metal cap layer over upper surfaces of the first conductive features away from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

[0005] According to another aspect of the disclosure, a method of forming a semiconductor device is provided, the method comprising: forming first conductive features in a first dielectric layer disposed over a substrate, wherein a first surface of the first conductive features distal to the substrate is flush with a first surface of the first dielectric layer; selectively forming a metal cap layer on the first surface of the first conductive features; selectively forming a dielectric cap layer on the first surface of the first dielectric layer, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed of a nitride-containing dielectric material; sequentially forming a plurality of etch stop layers on the metal cap layer and the dielectric cap layer; forming a second dielectric layer on the plurality of etch stop layers; and forming second conductive features in the second dielectric layer, wherein the second conductive features extend through the plurality of etch stop layers and are electrically coupled to the respective first conductive features.

[0006] According to yet another aspect of the disclosure, a semiconductor device is provided, comprising: a substrate; a first dielectric layer over the substrate; first conductive features in the first dielectric layer; a metal cap layer on the first conductive features; a dielectric cap layer on an upper surface of the first dielectric layer distal to the substrate, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer comprises a nitride-containing dielectric material, wherein an upper surface of the metal cap layer distal to the substrate is free of the dielectric cap layer; an etch stop layer stack on the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers; a second dielectric layer on the etch stop layer stack; and second conductive features in the second dielectric layer, wherein the second conductive features extend through the etch stop layer stack and are electrically coupled to the first conductive features. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity. It should be noted that for ease of understanding, the drawings are sometimes shown with exaggerated differences between the various features.

[0008] Figures 1 to 7 Cross-sectional views of a semiconductor device at various stages of fabrication are shown in accordance with one embodiment.

[0009] Figures 8 to 10 Cross-sectional views of a semiconductor device at various stages of fabrication are shown in accordance with another embodiment.

[0010] Figure 11 A cross-sectional view of a semiconductor device is shown in accordance with another embodiment.

[0011] Figure 12 A cross-sectional view of a semiconductor device is shown in accordance with another embodiment.

[0012] Figure 13 A cross-sectional view of a semiconductor device is shown in accordance with yet another embodiment.

[0013] Figure 14 A flow diagram of a method of forming a semiconductor device is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact with each other, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact.

[0015] Furthermore, spatially relative terms (for example, "beneath", "below", "lower", "above", "upper", and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Like or similar components in different drawings can be denoted by like or similar reference numerals throughout the discussion of the specification.

[0016] According to some embodiments, an interconnect structure of a semiconductor device and a method of forming the same are provided. According to some embodiments of the present disclosure, the formation of the interconnect structure includes forming a metal cap layer over first conductive features (e.g., conductive lines) disposed in a first dielectric layer. A dielectric cap layer (which is a nitride-containing dielectric material) is selectively formed on an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer. The dielectric cap layer can be formed by a selective deposition process or by an ion implantation process. The dielectric cap layer reduces the leakage current path between adjacent conductive lines in the first dielectric layer at the interface between the first dielectric layer and a subsequently formed second dielectric layer, and improves Time-Dependent Dielectric Breakdown (TDDB) performance. Next, an etch stop layer stack including a plurality of etch stop layers (e.g., three or four etch stop layers) is formed on the dielectric cap layer and the metal cap layer. In some embodiments, the etch stop layer stack includes an aluminum nitride layer, a first aluminum oxide layer, an oxygen-doped silicon carbide (ODC) layer, and a second aluminum oxide layer formed in that order on the dielectric cap layer and the metal cap layer. The film scheme of the etch stop layer stack has various advantages. For example, the etch stop layer stack prevents copper in the first conductive features from diffusing upward into the etch stop layer and the second dielectric layer above. The upward diffusion of copper can reduce the etch rate of the second dielectric layer and the etch stop layer stack in a subsequent etch process for forming a via, and the reduced etch rate can cause the etching of the via opening to stop prematurely, resulting in a failure of electrical connection between the via and the underlying conductive line. The film scheme of the etch stop layer prevents the above-mentioned problem by preventing copper diffusion. Other advantages include better etch selectivity window and further reduced leakage current.

[0017] Figures 1 to 7 Cross-sectional views of a semiconductor device 100 at various stages of fabrication are shown in accordance with one embodiment. The semiconductor device 100 can be a device wafer that includes active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, inductors, resistors, etc.). In some embodiments, the semiconductor device 100 is an interposer wafer, which can or can not include active devices and / or passive devices. According to yet another embodiment of the present disclosure, the semiconductor device 100 is a package substrate strip, which can be a package substrate with a core therein, or can be a coreless package substrate. In the following discussion, a device wafer is used as an example of the semiconductor device 100. As those skilled in the art readily appreciate, the teachings of the present disclosure can also be applied to an interposer wafer, a package substrate, or other semiconductor structures.

[0018] As Figure 1As shown, the semiconductor device 100 includes a semiconductor substrate 101 and integrated circuit devices 103 (e.g., active devices, passive devices) formed on or in the semiconductor substrate 101 (may also be referred to as the substrate 101). The semiconductor substrate 101 can include a semiconductor material such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 101 can include other semiconductor materials, for example, germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates can also be used, for example, a multilayer substrate or a graded substrate.

[0019] In Figure 1 In the example shown, the integrated circuit devices 103 are formed on or in the semiconductor substrate 101. Example integrated circuit devices 103 include transistors (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), resistors, capacitors, diodes, etc. Any suitable method can be used to form the integrated circuit devices 103, the details of which are not discussed here.

[0020] After the integrated circuit devices 103 are formed, an interlayer dielectric (ILD) layer 107 is formed on the semiconductor substrate 101 and on the integrated circuit devices 103. The ILD layer 107 can fill spaces between gate stacks of the transistors (not shown) of the integrated circuit devices 103. According to some embodiments, the ILD layer 107 includes silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), etc. The ILD layer 107 can be formed using spin-on, flowable chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0021] Still referring to Figure 1Contact plugs 105 are formed in ILD layer 107, which electrically couple integrated circuit device 103 to overlying conductive features, such as metal lines, vias, and conductive pillars. Note that, in this disclosure, unless otherwise stated, a conductive feature is a feature that conducts electricity. According to some embodiments, contact plugs 105 are formed of a conductive material, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Formation of contact plugs 105 can include forming contact openings in ILD layer 107, forming one or more conductive materials in the contact openings, and performing a planarization process, such as chemical mechanical polishing (CMP), to level the top surfaces of contact plugs 105 with the top surface of ILD layer 107.

[0022] Next, a plurality of intermetal dielectric (IMD) layers, such as 109 and 111, are formed over ILD layer 107. IMD layers 109 and 111 can be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. According to some embodiments, IMD layers 109 and 111 are formed of a low-k dielectric material having a dielectric constant (k-value) of less than 3.0 (e.g., about 2.5, about 2.0, or even lower). IMD layers 109 and 111 can include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. As an example, formation of each of IMD layers 109 and 111 can include depositing a porogen-containing dielectric material over ILD layer 107, and then performing a curing process to drive out the porogen, thereby forming a porous IMD layer. Other suitable methods can also be used to form IMD layers 109 and 111. In an example embodiment, IMD layers 109 and 111 are formed of SiCO using a chemical vapor deposition (CVD) process, where each of IMD layers 109 and 111 (e.g., SiCO) has a thickness between about 200 Angstroms and about 600 Angstroms, and a k-value between about 2.8 and about 3.5. Oxygen concentration in IMD layers 109 and 111 can be between about 40 atomic percent (atomic %) and about 55 atomic %, carbon concentration in IMD layers 109 and 111 can be between about 5 atomic % and about 20 atomic %, and silicon concentration in IMD layers 109 and 111 can be between about 39 atomic % and about 40 atomic %.

[0023] As Figure 1As shown, a conductive feature 112 (e.g., a metal line) is formed in the IMD layer 111. In the illustrated example, the conductive feature 112 is a metal line that includes a diffusion barrier layer 113 (also referred to as a barrier layer) and a conductive material 115 (e.g., copper or a copper-containing material) over the diffusion barrier layer 113. The diffusion barrier layer 113 can include titanium, titanium nitride, tantalum, tantalum nitride, etc., and can be formed by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc. After the diffusion barrier layer 113 is formed, the conductive material 115 is formed over the diffusion barrier layer 113. The formation of the conductive feature 112 can include a single damascene process, although other suitable formation methods can also be used. The conductive feature 112 can also be referred to as a conductive line 112 or a metal line 112 hereinafter, with the understanding that the conductive feature 112 can be or include other features (e.g., a via or a conductive line with a via connected thereto). Although Figure 1 One or more IMD layers 109 are shown formed between the IMD layer 111 and the ILD layer 107, although this is merely a non-limiting example. Those skilled in the art will readily appreciate that the IMD layer 111 can be formed directly on the ILD layer 107 (e.g., a solid contact). Moreover, although not shown in FIG. 1A, one or more ILD layers can be formed between the IMD layer 111 and the ILD layer 107. Figure 1 Conductive features such as conductive lines and / or vias are formed in the IMD layer 109 to electrically couple the conductive line 112 with the integrated circuit device 103, although not shown in FIG. 1A.

[0024] Next, a metal cap layer 116 is formed (e.g., selectively formed) on the upper surface of the conductive line 112. The portion of the metal cap layer 116 on each conductive line 112 is also referred to as a metal cap 116 of the underlying conductive line 112. In some embodiments, the metal cap layer 116 is formed of a conductive material such as a metal or a metal-containing material. According to some embodiments of the present disclosure, the metal cap layer 116 is formed of cobalt (Co), CoWP, CoB, tungsten (W), tantalum (Ta), nickel (Ni), molybdenum (Mo), titanium (Ti), iron (Fe), combinations thereof, and / or alloys thereof. Suitable formation methods such as PVD, CVD, PECVD, ALD, etc. can be used to form the metal cap layer 116. For example, the thickness of the metal cap layer 116 can be between about 20 angstroms and about 40 angstroms.

[0025] In Figure 1In the example of FIG. 1, the metal cap 116 on each conductive line 112 has the same width as the conductive line 112, such that the sidewalls of the metal cap 116 are aligned (e.g., vertically aligned) with the corresponding sidewalls of the barrier layer 113 of the conductive line 112. In other embodiments, the metal cap 116 on each conductive line 112 has the same width as the conductive material 115 of the conductive line 112, such that the sidewalls of the metal cap 116 are aligned (e.g., vertically aligned) with the corresponding sidewalls of the conductive material 115.

[0026] In some embodiments, the metal cap layer 116 is formed by a selective deposition process that has a first deposition rate on the conductive lines 112 and a second deposition rate on the IMD layer 111, where the first deposition rate is higher than the second deposition rate. An etching process is performed after the selective deposition process to remove the metal cap layer 116 from the upper surface of the IMD layer 111. In another embodiment, the metal cap layer 116 is blanket-deposited over the conductive lines 112 and the IMD layer 111. Next, a patterned mask layer (e.g., a patterned photoresist layer) is formed over the metal cap layer 116, where the portions of the metal cap layer 116 over (e.g., directly over) the conductive lines 112 are covered by the patterned mask layer, and the portions of the metal cap layer 116 over (e.g., directly over) the IMD layer 111 are exposed by the pattern (e.g., openings) of the patterned mask layer. An etching process is then performed to remove the portions of the metal cap layer 116 that are exposed by the pattern of the patterned mask layer. After the etching process, the patterned mask layer is removed by a suitable process such as ashing.

[0027] Reference is now made to FIG. 2, which illustrates a cross-sectional view of the structure of FIG. 1 after the formation of the dielectric cap layer 117 over the upper surface of the IMD layer 111. Figure 2 The dielectric cap layer 117 is formed (e.g., selectively formed) on the upper surface of the IMD layer 111. In some embodiments, the dielectric cap layer 117 is a nitrogen-containing dielectric material such as SiN x , SiON x , or SiCN x , where x can be 1 or 2. The thickness of the dielectric cap layer 117 can be between about 5 Angstroms and about 50 Angstroms, or between about 10 Angstroms and about 50 Angstroms. The density of the dielectric cap layer 117 can be between about 1.5 g / cm 3 and about 3.2 g / cm 3 .

[0028] In some embodiments, the dielectric cap layer 117 is formed by a selective deposition process that has a first deposition rate on the conductive lines 112 and a second deposition rate on the IMD layer 111, where the first deposition rate is higher than the second deposition rate. An etching process is performed after the selective deposition process to remove the dielectric cap layer 117 from the upper surface of the IMD layer 111. In another embodiment, the dielectric cap layer 117 is blanket-deposited over the conductive lines 112 and the IMD layer 111. Next, a patterned mask layer (e.g., a patterned photoresist layer) is formed over the dielectric cap layer 117, where the portions of the dielectric cap layer 117 over (e.g., directly over) the conductive lines 112 are covered by the patterned mask layer, and the portions of the dielectric cap layer 117 over (e.g., directly over) the IMD layer 111 are exposed by the pattern (e.g., openings) of the patterned mask layer. An etching process is then performed to remove the portions of the dielectric cap layer 117 that are exposed by the pattern of the patterned mask layer. After the etching process, the patterned mask layer is removed by a suitable process such as ashing. Figure 2In the example of FIG. 1, the dielectric cap layer 117 is formed by a suitable deposition process, such as PECVD. In some embodiments, the PECVD process is performed using a nitrogen-containing gas source, such as N2, NH3, NO, or N2O. A carrier gas (e.g., Ar, N2, O3, or a mixture of He and O2) is used to bring the nitrogen-containing gas source into the processing chamber of the PECVD process. In some embodiments, after the dielectric cap layer 117 is formed, the nitride concentration in the dielectric cap layer 117 is between about 2 atomic % and about 10 atomic %. Other methods for forming the dielectric cap layer 117 are possible in addition to PECVD processes, and are fully intended to be included within the scope of the present disclosure. For example, embodiments of forming the dielectric cap layer 117 by an ion implantation process will be discussed below with reference to FIGS. 2A-2C. Figures 8-10

[0029] In some embodiments, during the PECVD process for forming the dielectric cap layer 117, the material of the dielectric cap layer 117 is formed on the IMD layer 111 at a first deposition rate, and on the metal cap layer 116 at a second deposition rate, where the first deposition rate is higher than the second deposition rate. After the PECVD process, an etch process can be performed to remove the material of the dielectric cap layer 117 from the upper surface of the metal cap layer 116, and the remaining portion of the material of the dielectric cap layer 117 on the upper surface of the IMD layer 111 forms the dielectric cap layer 117.

[0030] In the example of FIG. 1, the dielectric cap layer 117 is formed by a suitable deposition process, such as PECVD. In some embodiments, the PECVD process is performed using a nitrogen-containing gas source, such as N2, NH3, NO, or N2O. A carrier gas (e.g., Ar, N2, O3, or a mixture of He and O2) is used to bring the nitrogen-containing gas source into the processing chamber of the PECVD process. In some embodiments, after the dielectric cap layer 117 is formed, the nitride concentration in the dielectric cap layer 117 is between about 2 atomic % and about 10 atomic %. Other methods for forming the dielectric cap layer 117 are possible in addition to PECVD processes, and are fully intended to be included within the scope of the present disclosure. For example, embodiments of forming the dielectric cap layer 117 by an ion implantation process will be discussed below with reference to FIGS. 2A-2C. Figure 2 In the example of FIG. 1, the dielectric cap layer 117 is formed by a suitable deposition process, such as PECVD. In some embodiments, the PECVD process is performed using a nitrogen-containing gas source, such as N2, NH3, NO, or N2O. A carrier gas (e.g., Ar, N2, O3, or a mixture of He and O2) is used to bring the nitrogen-containing gas source into the processing chamber of the PECVD process. In some embodiments, after the dielectric cap layer 117 is formed, the nitride concentration in the dielectric cap layer 117 is between about 2 atomic % and about 10 atomic %. Other methods for forming the dielectric cap layer 117 are possible in addition to PECVD processes, and are fully intended to be included within the scope of the present disclosure. For example, embodiments of forming the dielectric cap layer 117 by an ion implantation process will be discussed below with reference to FIGS. 2A-2C. Figure 2 As shown, the dielectric cap layer 117 covers the upper surface 111U of the IMD layer 111, and extends continuously along the upper surface 111U of the IMD layer 111 from the conductive lines 112 to the adjacent conductive lines 112.

[0031] ​In some embodiments, by forming a dielectric cap layer 117 between adjacent conductive lines 112, leakage current paths between adjacent conductive lines 112 are reduced or avoided at the interface between the IMD layer 111 and the overlying dielectric layer (see, e.g., 127), thereby improving device performance and reducing power consumption. In addition, time-dependent dielectric breakdown (TDDB) performance of the formed device is also improved compared to a reference design without the dielectric cap layer 117. Figure 4

[0032] Next, in Figure 3 , an etch stop layer stack 118 is formed over the dielectric cap layer 117 and over the metal cap layer 116. In the example of Figure 3 , the etch stop layer stack 118 includes a plurality of etch stop layers (ESLs) 119, 121, 123, and 125. Accordingly, forming the etch stop layer stack 118 includes sequentially forming the ESLs 119, 121, 123, and 125 over the dielectric cap layer 117 and over the metal cap layer 116.

[0033] In some embodiments, the ESL 119 is formed of a metal nitride that has good adhesion to the underlying metal cap layer 116 and dielectric cap layer 117. For example, the ESL 119 can be formed of aluminum nitride (AIN), aluminum oxynitride (AINO), manganese nitride (Mn3N2), gallium nitride (GaN), aluminum gallium nitride (AlGaN), etc. In the discussion herein, the ESL 119 can alternatively be referred to as an aluminum nitride layer 119, with the understanding that the ESL 119 can be formed of other suitable materials (such as those listed above) other than aluminum nitride.

[0034] According to some embodiments, the ESL 119 is formed using a suitable formation method such as PVD, CVD, ALD, etc. Precursors used to form the ESL 119 can include a nitrogen-containing process gas such as NH3, and an aluminum-containing process gas such as trimethylaluminum (TMA) (Al2(CH3)6), etc. In an example deposition process (e.g., an ALD process), the nitrogen-containing process gas and the aluminum-containing process gas are alternately supplied to a processing chamber and then purged in each cycle of the deposition process to grow an atomic layer of aluminum nitride.

[0035] ​According to some embodiments, the ESL 119 has a thickness in a range between about 5 Angstroms and about 30 Angstroms. The thickness of the ESL 119 should be in a suitable range. If the ESL 119 is too thick (e.g., thicker than about 30 Angstroms), undercuts can be generated when etching through the ESL 119 in subsequent processes. If the ESL 119 is too thin (e.g., thinner than about 5 Angstroms), the ESL 119 can not effectively stop etching of the layers above.

[0036] During the deposition of the aluminum nitride layer 119, the temperature of the semiconductor device 100 is controlled to be in a suitable range, for example, between about 300 °C and 380 °C. It can be appreciated that the temperature of the semiconductor device 100 affects the deposition rate. If the temperature is too low (e.g., lower than about 300 °C), the deposition rate can be too low to be economically feasible for semiconductor manufacturing because it takes a long time to form the aluminum nitride layer 119. If the temperature is too high (e.g., higher than about 380 °C), the resulting aluminum nitride layer 119 is crystalline (e.g., polycrystalline), which can result in increased copper diffusion from the conductive lines 112 to the layers above. Thus, in some embodiments, the temperature of the semiconductor device 100 is selected to be in a range between about 300 °C and about 380 °C during the deposition of the aluminum nitride layer 119 to avoid the aforementioned problems.

[0037] The deposited aluminum nitride layer 119 can or can not include some crystalline structures, for example, polycrystalline structures, including grains therein. Some of the grains can be connected to each other, while other grains can be embedded in an amorphous structure. The copper in the conductive lines 112 can diffuse upward along the grain boundaries to the layers above that will be formed later. Thus, to reduce the upward diffusion of copper, after the deposition of the aluminum nitride layer 119, a treatment process (also referred to as an amorphization process) is performed to convert the polycrystalline structures (if present) in the aluminum nitride layer 119 to an amorphous structure, such that the entire aluminum nitride layer 119 is amorphous. Since the amorphous aluminum nitride layer 119 does not have grain boundaries, it has a better ability to prevent copper diffusion.

[0038] According to some embodiments of the present disclosure, a process gas including NH3, N2, or a combination thereof is used to perform the treatment process (e.g., a plasma process) for the deposited aluminum nitride layer 119. Other gases, for example, argon, can also be added. In the treatment process, the aluminum nitride layer 119 is bombarded. The bombardment destroys the crystalline structure. Moreover, in the presence of hydrogen and nitrogen atoms in the process gas (e.g., NH3), hydrogen and nitrogen can be added to the aluminum nitride layer 119. Thus, as a result of the treatment process, the aluminum nitride layer 119 can include hydrogen doped therein. According to some embodiments, after the amorphization process, the aluminum nitride layer 119 has a percentage of hydrogen atoms in a range between about 1 atomic % and about 3 atomic %.

[0039] The treatment process also has the effect of changing the aluminum-to-nitrogen atomic ratio (hereinafter referred to as the Al:N atomic ratio), which also affects whether the resulting aluminum nitride layer 119 has a crystalline structure or an amorphous structure. For example, an untreated crystalline aluminum nitride layer can have an atomic ratio Al:N close to 1 : 1. The addition of nitrogen atoms through the amorphization process changes this ratio. For example, in the case where nitrogen is used for bombardment, nitrogen atoms bond with aluminum atoms such that one aluminum atom can be cross-linked with more than one nitrogen atom, which can further bond with hydrogen atoms. As a result, it is easier to form an amorphous structure. Moreover, in the case where one aluminum atom is bonded to more than one nitrogen atom, even if the temperature in the subsequent process is high enough to perform recrystallization, recrystallization of the aluminum nitride layer 119 can be prevented. Furthermore, since the added nitrogen atoms can further bond with hydrogen atoms, hydrogen is also added to the aluminum nitride layer 119 through this treatment process.

[0040] According to some embodiments of the present disclosure, the flow rate of the NH3 gas (when used) during the treatment process is in the range of about 50 seem to about 500 seem. The flow rate of the N2 gas (when used) is in the range of about 1000 seem to about 3000 seem. The temperature of the semiconductor device 100 during the treatment process can be in the range of about 340 °C to about 400 °C.

[0041] According to some embodiments, the treatment process is or includes a plasma treatment, which can be a direct plasma process in which the plasma is generated in the same process chamber as the semiconductor device 100 is being treated. This plasma treatment process is performed using both high frequency radio frequency (HFRF) power (e.g., having a frequency of about 13.56 MHz) and low frequency radio frequency (LFRF) power (e.g., having a frequency of about 350 KHz). The HFRF power is used to ionize and generate the plasma, while the LFRF power is used to bombard the aluminum nitride layer 119 for amorphization purposes. According to some embodiments of the present disclosure, the HFRF power is in the range of about 400 watts to about 800 watts.

[0042] The LFRF power is selected to be in a suitable range. If the LFRF power is too low (e.g., below about 90 watts), nitrogen ions can not be effectively doped into the aluminum nitride layer 119. If the LFRF power is too high (e.g., above about 135 watts), it can cause severe plasma-induced damage to the layers / structures underneath the aluminum nitride layer 119. According to some embodiments of the present disclosure, the LFRF power is selected to be in the range of about 90 watts to about 135 watts to avoid the aforementioned issues.

[0043] In some embodiments, after processing, the aluminum nitride layer 119 has an atomic percentage of aluminum in a range between about 55 atomic % to about 63 atomic %, an atomic percentage of nitride in a range between about 37 atomic % to about 43 atomic %, and an atomic percentage of carbon in a range between about 0.5 atomic % to about 2 atomic %. In some embodiments, when the atomic percentages of different materials (e.g., aluminum, nitride, carbon) of the aluminum nitride layer 119 are within the above ranges, the physical properties of the aluminum nitride layer 119 can satisfy the etch selectivity capability of the etch stop layer stack 118, where the etch selectivity capability of the etch stop layer stack 118 means that in a subsequent etching process to form the trench openings 131T and via openings 131V (see, e.g., Figure 5 ) the etching process can remain anisotropic in the desired etching direction (e.g., vertically) in the etch stop layer stack 118.

[0044] Still referring to Figure 3 , the ESL 121 is formed on the ESL 119. In example embodiments, the ESL 121 is formed of aluminum oxide (AlO X , where x is the atomic ratio of oxygen to aluminum). The ESL 121 can also be formed of other materials that have high etch selectivity with respect to the underlying ESL 119 and the overlying ESL 123. The formation method of the ESL 121 includes ALD, CVD, PECVD, etc. According to some embodiments of the present disclosure, the ESL 121 is formed using precursors including a metal-containing precursor (e.g., TMA) and an oxygen-containing precursor (e.g., H2O, O3, etc.). The thickness of the ESL 121 can be in a range between about 10 angstroms to about 50 angstroms. In some embodiments, the thickness of the aluminum nitride layer 119 and the ESL 121 are determined by, e.g., the etch selectivity capability of the etch stop layer stack 118 and / or the reliability window of the formed device.

[0045] In some embodiments, after formation, the ESL 121 has an atomic percentage of aluminum in a range between about 40 atomic % to about 45 atomic %, an atomic percentage of oxygen in a range between about 55 atomic % to about 60 atomic %, and an atomic percentage of carbon in a range between about 0.5 atomic % to about 1 atomic %. In some embodiments, when the atomic percentages of different materials (e.g., aluminum, oxygen, carbon) of the ESL 121 are within the above ranges, the physical properties of the ESL 121 can satisfy the etch selectivity capability of the etch stop layer stack 118.

[0046] In some embodiments, the ESL 121 improves the etch selectivity of the etch stop layer stack 118 and helps to further reduce the leakage current between the conductive lines 112. In addition, the process used to form the aluminum nitride layer 119 and the ESL 121 can enhance the adhesion between the metal cap layer 116 and the conductive material 115 (e.g., copper), thereby reducing or avoiding problems caused by copper metal diffusion, such as copper pits formed on the copper metal lines or copper metal line openings.

[0047] Next, an ESL 123 is formed on the ESL 121. In example embodiments, the ESL 123 is formed of oxygen-doped (silicon) carbide (ODC), which is also referred to as silicon oxycarbide (SiOC). The ESL 123 can also be formed of another material, such as nitrogen-doped silicon carbide (NDC), SiC, etc. The deposition method of the ESL 123 can be CVD or another suitable method, such as ALD, PECVD, high-density plasma CVD (HDPCVD), etc. The thickness of the ESL 123 can be in a range between about 20 angstroms to about 100 angstroms.

[0048] In some embodiments, the precursors used to form the ESL 123 depend on the desired composition of the ESL 123 and can include silicon (Si), carbon (C), hydrogen (H), nitrogen (N), oxygen (O), boron (B), etc. According to some embodiments, the precursors include a gas selected from 1-methylsilane (Si(CH)H3, also referred to as 1MS), 2-methylsilane (Si(CH)2H2, also referred to as 2MS), 3-methylsilane (Si(CH)3H, also referred to as 3MS), 4-methylsilane (Si(CH)4, also referred to as 4MS), or combinations thereof. An inert gas, such as He, N2, Ar, Xe, etc., can be used as an ambient gas. If ODC is to be formed, carbon dioxide (CO2) can also be added to provide oxygen. If NDC is to be formed, NH3 can be added to provide nitrogen. In addition, the precursors can include a boron-containing gas, such as B2H6, BH3, or combinations thereof, to provide boron in the resulting ESL 123.

[0049] In addition to the precursors discussed above, one or more carbon source gases can be added to increase the carbon content in the resulting ESL 123. The carbon source gas can be a carbon rich source, meaning that the carbon atom percentage in the carbon source gas is high, for example, greater than about 10 atomic %, or greater than about 20 atomic %, or 30 atomic %. In example embodiments, the carbon source gas is a carbon containing hydrogen gas selected from C2H4, C2H6, and combinations thereof. With the additional carbon provided by the carbon source gas, the carbon percentage in the resulting ESL 123 is increased and the properties of the ESL 123 are improved. According to some embodiments, the flow rate of the carbon source gas to the flow rate of all 1Ms / 2Ms / 3Ms / 4Ms gases is greater than about 2 to 4.

[0050] According to some embodiments, the formation of the ESL 123 is performed in a chamber using, for example, PECVD, where the temperature of the semiconductor device 100 can be between about 300 °C to about 500 °C, and the chamber pressure can be between about 2 Torr to about 10 Torr. The power sources for forming the ESL 123 can include HFRF power and LFRF power. During the formation of the ESL 123, the HFRF power source can provide power between about 100 Watts to about 1000 Watts, while the LFRF power source can provide power lower than about 135 Watts, and can be as low as zero Watts (meaning no low frequency power is provided). The high frequency RF power and the LFRF power can be provided simultaneously.

[0051] In some embodiments, after formation, the ESL 123 has an oxygen atom percentage in a range between about 40 atomic % to about 50 atomic %, a silicon atom percentage in a range between about 36 atomic % to about 40 atomic %, and a carbon atom percentage in a range between about 15 atomic % to about 20 atomic %. In some embodiments, when the atomic percentages of the different materials (e.g., oxygen, silicon, carbon) of the ESL 123 are within the above ranges, the physical properties of the ESL 123 can satisfy the etch selectivity capability of the etch stop layer stack 118.

[0052] Next, an ESL 125 is formed on top of the ESL 123. In example embodiments, the ESL 125 is formed of the same material as the ESL 121, for example, aluminum oxide. The formation method, dimensions (e.g., thickness), and material composition (e.g., atomic percentages of various elements) of the ESL 125 can be the same or similar to the ESL 121, and therefore are not repeated. In example embodiments, the ESL 119 is formed of aluminum nitride, the ESL 121 is formed of aluminum oxide, the ESL 123 is formed of ODC, and the ESL 125 is formed of aluminum oxide.

[0053] Each of ESLs 121, 123, and 125 can have a polycrystalline structure or an amorphous structure, which can be achieved by adjusting the deposition temperature. Since the diffusion of copper atoms is prevented by the underlying ESL 119, it does not matter whether ESLs 121, 123, and 125 are polycrystalline or amorphous, as it does not cause upward diffusion of copper atoms.

[0054] In the example of FIG. 1, the etch stop layer stack 118 includes four ESLs (119, 121, 123, and 125). According to alternative embodiments of the present disclosure, the etch stop layer stack 118 includes three ESLs (see, e.g., ESLs 119, 123, and 125). Details of the alternative embodiments are discussed below with reference to Figure 3 Figure 11 and Figure 12 ), e.g., ESLs 119, 123, and 125. Details of the alternative embodiments are discussed below with reference to Figure 11 and Figure 12 .

[0055] Next, with reference to FIG. 1, an IMD layer 127 is formed over the etch stop layer stack 118. The IMD layer 127 can be formed using the same or similar material(s) as the IMD layer 111, by the same or similar formation process, and therefore the details are not repeated. Figure 4

[0056] Next, a mask layer 129 is formed over the IMD layer 127. In subsequent processing, a pattern is transferred onto the mask layer 129 using, e.g., photolithography and etching techniques. The mask layer 129 can then be used as a patterned mask for etching the underlying IMD layer 127. The mask layer 129 can be formed using a process such as CVD, PVD, ALD, etc., or a combination thereof, from a mask material such as silicon nitride, titanium nitride, titanium oxide, etc., or a combination thereof.

[0057] Next, in FIG. 1, the mask layer 129 is patterned, and the pattern of the mask layer 129 is transferred to the IMD layer 127, e.g., by one or more etching processes, to form openings 131. In Figure 5 Figure 5 ​​​In the example shown, each opening 131 includes a via opening 131V and a trench opening 131T above the via opening 131V. In one embodiment, to form the via opening 131V and the trench opening 131T, a first etch process (e.g., an anisotropic etch process) is performed using the patterned mask layer 129 as an etch mask to form the trench opening 131T by etching into the IMD layer 127 from the upper surface of the IMD layer 127. Once the depth of the opening 131 reaches a target depth of the trench opening 131T, the first etch process is stopped. Next, a second mask layer (not shown), such as a photoresist layer, is formed to fill the opening 131 and is formed over the upper surface of the mask layer 129. The second mask layer is then patterned, where the pattern (openings) of the second mask layer correspond to the locations of the via openings 131V. Next, a second etch process (e.g., an anisotropic etch process) is performed using the patterned second mask layer as an etch mask to form the via openings 131V. Note that the second etch process can stop at the ESL 125 (e.g., when the ESL 125 is exposed). As described in detail below, additional etch steps are performed to extend the via openings 131V through the etch stop layer stack 118 and expose the metal cap layer 116. Other methods for forming the via openings 131V and the trench openings 131T are possible in addition to the method described above, and are fully intended to be included within the scope of the present disclosure.

[0058] According to some embodiments of the present disclosure, the etching of the IMD layer 127 is performed using a process gas that includes fluorine and carbon, where the fluorine is used for etching and the carbon is used to generate a plasma that can protect the sidewalls of the resulting via openings 131V and trench openings 131T. With the appropriate ratio of fluorine and carbon, the via openings 131V and the trench openings 131T can have a desired profile (e.g., a sidewall profile). For example, the process gas used for etching includes fluorine and carbon containing gas(es) such as C4F8 and / or CF4, and a carrier gas such as N2.

[0059] In the embodiment shown, the etching of the IMD layer 127 stops at the ESL 125. Next, the ESL 125 (e.g., AIO x ) is etched, for example, by a dry etch process followed by a wet etch process. In some embodiments, the dry etch process is performed using an etch gas such as a mixture of BCl3 and Cl2. The wet etch process can be performed using, for example, phosphoric acid. Next, the ESL 123 (e.g., ODC) is etched, for example, using an etch gas that includes a fluorine and carbon containing gas such as CF4 and other gas(es) such as argon. Next, the ESL 121 (e.g., AIO x). In the illustrated embodiment, ESL 121 and ESL 125 are formed of the same material (e.g., A10 x ) and, thus, the same etching process(s) used to etch ESL 125 can again be performed to etch ESL 121. Next, ESL 119 (e.g., A1N) is etched through, for example, using a mixture of BCl3, Cl2, and argon. ESL 119 can also be etched by a wet etching process, for example, using phosphoric acid. After etching ESL 119, metal cap layer 116 is exposed.

[0060] Forming amorphous ESL 119 (e.g., A1N) has the advantage of improving the etching of the aforementioned IMD layer 127 and etch stop layer stack 118. The amorphous structure of ESL 119, which does not have grains and grain boundaries, can effectively prevent copper atoms in conductive line 112 from diffusing upward into etch stop layer stack 118 and IMD layer 127. Otherwise, if ESL 119 has a polycrystalline structure, copper can diffuse along the grain boundaries into etch stop layer stack 118 and the overlying IMD layer 127. The diffused copper can reduce the etch rate when etching ESL 119 / 121 / 123 / 125 and IMD layer 127. The reduced etch rate can cause the etching to prematurely stop inside etch stop layer stack 118 or even inside IMD layer 127 for forming via opening 131V, an effect known as under-etching of etch stop layer stack 118 and IMD layer 127. As a result of under-etching, the subsequently formed via in via opening 131V cannot electrically connect to conductive line 112, resulting in a circuit failure. The amorphization process disclosed herein ensures that ESL 119 has an amorphous structure to prevent copper diffusion and, thus, avoids the under-etching problem. As a result, the reliability and yield of the device are improved.

[0061] Next, in Figure 6 , conductive features 132 are formed in openings 131. In the illustrated example, each conductive feature 132 includes a via 138 and a conductive line 136. Each via 138 electrically couples the overlying conductive line 136 to the underlying conductive line 112.

[0062] In some embodiments, to form conductive features 132, a barrier layer 133 is formed (e.g., conformally) to line the sidewalls and bottom of openings 131. Barrier layer 133 can also be formed on mask layer 129 (see Figure 5Above the upper surface of the barrier layer 113. Next, a conductive material 135 is formed on the barrier layer 133 to fill the opening 131. The barrier layer 133 and the conductive material 135 may be the same as or similar to the barrier layer 113 and the conductive material 115, respectively, and may be formed using the same or similar (one or more) forming methods, so details will not be repeated.

[0063] After the barrier layer 133 and conductive material 135 are formed, a planarization process such as CMP is performed to remove excess portions of the barrier layer 133 and conductive material 135 from the upper surface of the IMD layer 127. In the illustrated embodiment, this planarization process also removes the mask layer 129. After the planarization process, the remaining portions of the barrier layer 133 and conductive material 135 in the via opening 131V form vias 138, and the remaining portions of the barrier layer 133 and conductive material 135 in the trench opening 131T form conductive lines 136.

[0064] Next, in Figure 7 In this process, a metal capping layer 146 is formed (e.g., selectively formed) on the upper surface of the conductive feature 132. Next, a dielectric capping layer 137 is formed on the upper surface of the IMD layer 127, and then an etch stop layer stack 148 including ESLs 139, 141, 143, and 145 is formed on the metal capping layer 146 and the dielectric capping layer 137. The metal capping layer 146 and the dielectric capping layer 137 may be formed from the same or similar materials as the metal capping layer 116 and the dielectric capping layer 117, and may be formed using the same or similar formation methods, so details will not be repeated. Furthermore, ESLs 139, 141, 143, and 145 may be formed from the same or similar materials using the same or similar formation methods as ESLs 119, 121, 123, and 125, so details will not be repeated.

[0065] Additional processes can be performed to complete the fabrication of the semiconductor device 100. For example, additional IMD layers and additional conductive features (e.g., vias, conductive lines) can be formed on the etch stop layer stack 148 to form an interconnect structure that electrically connects the integrated circuit device 103 to form functional circuitry. Furthermore, an under-bump metallization (UBM) structure can be formed on the interconnect structure, and external connectors (e.g., copper pillars and / or solder balls) can be formed on the UBM structure to provide electrical connections to the functional circuitry of the semiconductor device 100. Details are not discussed here.

[0066] Figures 8 to 10Cross-sectional views of a semiconductor device 100A at various stages of fabrication are shown in accordance with another embodiment. The semiconductor device 100A is similar to the semiconductor device 100, but the dielectric cap layer 117 is formed by a different amorphization process. Specifically, in Figure 8 the ion implantation process 120 is performed to convert an upper portion of the IMD layer 111 (e.g., the portion away from the substrate 101) into the dielectric cap layer 117.

[0067] According to some embodiments of the present disclosure, the ion implantation process is performed using a nitrogen-containing process gas such as NH3or N2O. In some embodiments, the process gas is ignited into a plasma and ions of the process gas (e.g., nitrogen ions) are implanted into the upper portion of the IMD layer 111 to convert the upper portion of the IMD layer 111 into a nitrogen-containing dielectric cap layer 117. In some embodiments, the dielectric cap layer 117 is a nitrogen-containing dielectric material such as SiN X , SiON X , or SiCN X , where x can be 1 or 2. The thickness of the dielectric cap layer 117 can be between about 5 Angstroms to about 50 Angstroms, or between about 10 Angstroms to about 50 Angstroms. The density of the dielectric cap layer 117 can be between about 1.5 g / cm 3 to about 3.2 g / cm 3 . The dielectric cap layer 117 can have a percentage of nitrogen atoms in a range between about 2 atomic % to about 10 atomic %.

[0068] In Figure 8 the example, the lower surface 117L of the dielectric cap layer 117 is closer to the substrate 101 than the upper surface 115U of the conductive material 115 of the conductive line 112. The upper surface 117U of the dielectric cap layer 117 is flush with the upper surface 115U of the conductive material 115. The upper surface 111U of the IMD layer 111 is recessed below the upper surface 115U of the conductive material 115.

[0069] Next, in Figure 9 the etch stop layer stack 118 including the ESLs 119, 121, 123, and 125 is formed over the metal cap layer 116 and the dielectric cap layer 117. The formation of the etch stop layer stack 118 is the same as or similar to the formation of the etch stop layer stack 118 in Figure 2 , so the details are not repeated. Note that the upper surface of the ESL 119 can be planar, as in Figure 9the metal cap layer 116 (e.g., directly above). For example, the portion of the upper surface of the ESL 119 that is above (e.g., directly above) the metal cap layer 116 can be curved, as indicated by dashed line 119U’. In subsequent figures, the upper surface of the ESL 119 is shown as a flat surface, it is to be understood that at least some portions of the upper surface of the ESL 119 can be non-flat (e.g., curved).

[0070] Next, processing steps that are the same or similar to those discussed above in Figures 4-7 are performed to form a semiconductor device 100A in Figure 10 . For the sake of simplicity, details are not repeated.

[0071] Figure 11 A cross-sectional view of a semiconductor device 100B according to another embodiment is shown. The semiconductor device 100B is similar to the semiconductor device 100 of Figure 7 , but Figure 11 the etch stop layer stacks 118 and 148 in include three etch stop layers, rather than four etch stop layers as in Figure 7 . Specifically, the etch stop layer stack 118 includes an ESL 119 (e.g., AlN), an ESL 123 (e.g., ODC), and an ESL 125 (e.g., AlO x ). Similarly, the etch stop layer stack 148 includes an ESL 139 (e.g., AlN), an ESL 143 (e.g., ODC), and an ESL 145 (e.g., AlO x ).

[0072] Figure 12 A cross-sectional view of a semiconductor device 100C according to another embodiment is shown. The semiconductor device 100C is similar to the semiconductor device 100A of Figure 10 , but Figure 12 the etch stop layer stacks 118 and 148 in include three etch stop layers, rather than four etch stop layers as in Figure 10 . Specifically, the etch stop layer stack 118 includes an ESL 119 (e.g., AlN), an ESL 123 (e.g., ODC), and an ESL 125 (e.g., AlO x ). Similarly, the etch stop layer stack 148 includes an ESL 139 (e.g., AlN), an ESL 143 (e.g., ODC), and an ESL 145 (e.g., AlO x ). Figure 12 The dielectric cap layers 117 and 137 of

[0073] Figure 13 A cross-sectional view of a semiconductor device 100D according to yet another embodiment is shown. The semiconductor device 100D is similar to... Figure 7 The semiconductor device 100, however, at least one of the vias 138 (e.g., the left-side via 138) is formed to be misaligned with the underlying conductive line 112 (e.g., due to mask alignment errors during manufacturing), such that a portion of the bottom surface of the via 138 extends beyond the lateral extent of the conductive line 112 (e.g., beyond the sidewall) and contacts the dielectric cap layer 117 (e.g., in solid contact). In some embodiments, leakage current between the misaligned via 138 and the conductive line 112 is reduced or avoided due to the electrical isolation provided by the dielectric cap layer 117.

[0074] The embodiments of this disclosure achieve several advantageous features. For example, the dielectric cap layer 117 reduces leakage current paths between adjacent conductive lines 112, thereby improving device performance and reducing power consumption. Furthermore, the time-varying dielectric breakdown (TDDB) performance of the device is also improved. A film scheme with etch stop layer stacks (e.g., 118, 148) provides further advantages. For example, by forming an amorphous etch stop layer 119, there are no grain boundaries in the etch stop layer 119 for copper atoms to migrate through, thus preventing copper atoms from diffusing into the overlying etch stop layer and dielectric layer (e.g., 127). Since copper atoms can cause under-etching in the dielectric layer and etch stop layer, preventing copper diffusion eliminates under-etching, and therefore improves device reliability and manufacturing yield.

[0075] Figure 14 A flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments is shown. It should be understood that... Figure 14 The embodiments shown are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 14 The various steps shown.

[0076] refer to Figure 14 At block 1010, a first conductive feature is formed in a first dielectric layer disposed on the substrate. At block 1020, a metal capping layer is formed on the upper surface of the first conductive feature, away from the substrate. At block 1030, a dielectric capping layer is selectively formed on the upper surface of the first dielectric layer and laterally adjacent to the metal capping layer, wherein the metal capping layer is exposed by the dielectric capping layer. At block 1040, an etch stop layer stack is formed on the metal capping layer and the dielectric capping layer, wherein the etch stop layer stack includes a plurality of etch stop layers.

[0077] According to embodiments of the present disclosure, a method of forming a semiconductor device includes forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature away from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack includes a plurality of etch stop layers. In one embodiment, the method further includes forming a second dielectric layer over the etch stop layer stack; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the metal cap layer. In one embodiment, forming the metal cap layer includes selectively forming a conductive material over an upper surface of the first conductive feature. In one embodiment, the dielectric cap layer is formed of a nitride-containing dielectric material. In one embodiment, the nitride-containing dielectric material is silicon nitride, silicon oxynitride, or silicon carbon nitride. In one embodiment, a thickness of the dielectric cap layer is between about 10 Angstroms and about 50 Angstroms. In one embodiment, selectively forming the dielectric cap layer includes selectively depositing the nitride-containing dielectric material over the upper surface of the first dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) process. In one embodiment, the PECVD process is performed using a precursor including N2, NH3, NO, or N2O. In one embodiment, selectively forming the dielectric cap layer includes converting an upper layer of the first dielectric layer into the dielectric cap layer by performing an ion implantation process. In one embodiment, the ion implantation process is performed using a gas source including NH3or N2O. In one embodiment, forming the etch stop layer stack includes forming an aluminum nitride layer over the metal cap layer and the dielectric cap layer; forming an oxygen-doped silicon carbide layer over the aluminum nitride layer; and forming an aluminum oxide layer over the oxygen-doped silicon carbide layer. In one embodiment, forming the etch stop layer stack further includes forming another aluminum oxide layer between the aluminum nitride layer and the oxygen-doped silicon carbide layer.

[0078] According to embodiments of the present disclosure, a method of forming a semiconductor device includes forming first conductive features in a first dielectric layer disposed over a substrate, wherein first surfaces of the first conductive features distal to the substrate are flush with a first surface of the first dielectric layer; selectively forming a metal cap layer on the first surfaces of the first conductive features; selectively forming a dielectric cap layer on the first surface of the first dielectric layer, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed of a nitride-containing dielectric material; sequentially forming a plurality of etch stop layers on the metal cap layer and the dielectric cap layer; forming a second dielectric layer on the plurality of etch stop layers; and forming second conductive features in the second dielectric layer, wherein the second conductive features extend through the plurality of etch stop layers and are electrically coupled to respective first conductive features. In one embodiment, selectively forming the dielectric cap layer includes depositing the nitride-containing dielectric material on the first surface of the first dielectric layer, but leaving an upper surface of the metal cap layer distal to the substrate free of the nitride-containing dielectric material, wherein the nitride-containing dielectric material extends continuously between adjacent first conductive features. In one embodiment, selectively forming the dielectric cap layer includes converting an upper portion of the first dielectric layer proximate to the first surface thereof into the dielectric cap layer by an ion implantation process. In one embodiment, forming the plurality of etch stop layers includes forming a first etch stop layer over the metal cap layer and the dielectric cap layer, the first etch stop layer comprising aluminum nitride; forming a second etch stop layer over the first etch stop layer, the second etch stop layer comprising oxygen-doped silicon carbide; and forming a third etch stop layer over the second etch stop layer, the third etch stop layer comprising aluminum oxide. In one embodiment, forming the second conductive features includes forming conductive lines in the second dielectric layer; and forming vias under the conductive lines, wherein upper portions of the vias are in the second dielectric layer, and lower portions of the vias extend through the plurality of etch stop layers and are electrically coupled to the first conductive features.

[0079] According to embodiments of the present disclosure, a semiconductor device includes: a substrate; a first dielectric layer over the substrate; a first conductive feature in the first dielectric layer; a metal cap layer over the first conductive feature; a dielectric cap layer over an upper surface of the first dielectric layer away from the substrate, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer comprises a nitride-containing dielectric material, wherein an upper surface of the metal cap layer away from the substrate is free of the dielectric cap layer; an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers; a second dielectric layer over the etch stop layer stack; and a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the first conductive feature. In one embodiment, the etch stop layer stack comprises: a first etch stop layer comprising aluminum nitride and over the metal cap layer and the dielectric cap layer; a second etch stop layer comprising oxygen-doped silicon carbide and over the first etch stop layer; and a third etch stop layer comprising aluminum oxide and over the second etch stop layer. In one embodiment, the second conductive feature comprises: a metal line in the second dielectric layer, wherein a lower surface of the metal line facing the substrate is spaced apart from the etch stop layer stack; and a via under the metal line and connected to the metal line, wherein the via extends through the etch stop layer stack and contacts the metal cap layer.

[0080] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or for achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize or be able to ascertain

[0081] Example 1. A method of forming a semiconductor device, the method comprising: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature away from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

[0082] Example 2. The method of example 1, further comprising: forming a second dielectric layer over the etch stop layer stack; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the metal cap layer.

[0083] Example 3. The method of example 1, wherein forming the metal cap layer comprises: selectively forming a conductive material over an upper surface of the first conductive feature.

[0084] Example 4. The method of example 1, wherein the dielectric cap layer is formed of a nitride-containing dielectric material.

[0085] Example 5. The method of example 4, wherein the nitride-containing dielectric material is silicon nitride, silicon oxynitride, or silicon carbon nitride.

[0086] Example 6. The method of example 4, wherein a thickness of the dielectric cap layer is between 10 Angstroms and 50 Angstroms.

[0087] Example 7. The method of example 4, wherein selectively forming the dielectric cap layer comprises: selectively depositing the nitride-containing dielectric material over an upper surface of the first dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0088] Example 8. The method of example 7, wherein the PECVD process is performed using a precursor comprising N2, NH3, NO, or N2O.

[0089] Example 9. The method of example 4, wherein selectively forming the dielectric cap layer comprises: converting an upper layer of the first dielectric layer into the dielectric cap layer by performing an ion implantation process.

[0090] Example 10. The method of example 9, wherein the ion implantation process is performed using a gas source comprising NH3or N2O.

[0091] Example 11. The method of example 4, wherein forming the etch stop layer stack comprises: forming an aluminum nitride layer over the metal cap layer and the dielectric cap layer; forming an oxygen-doped silicon carbide layer over the aluminum nitride layer; and forming an aluminum oxide layer over the oxygen-doped silicon carbide layer.

[0092] Example 12. The method of example 11, wherein forming the etch stop layer stack further comprises forming another aluminum oxide layer between the aluminum nitride layer and the oxygen-doped silicon carbide layer.

[0093] Example 13. A method of forming a semiconductor device, the method comprising: forming first conductive features in a first dielectric layer disposed over a substrate, wherein first surfaces of the first conductive features distal from the substrate are flush with a first surface of the first dielectric layer; selectively forming a metal cap layer on the first surfaces of the first conductive features; selectively forming a dielectric cap layer on the first surface of the first dielectric layer, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed of a nitride-containing dielectric material; sequentially forming a plurality of etch stop layers on the metal cap layer and the dielectric cap layer; forming a second dielectric layer on the plurality of etch stop layers; and forming second conductive features in the second dielectric layer, wherein the second conductive features extend through the plurality of etch stop layers and are electrically coupled to respective ones of the first conductive features.

[0094] Example 14. The method of example 13, wherein selectively forming the dielectric cap layer comprises: depositing the nitride-containing dielectric material on the first surface of the first dielectric layer, but leaving an upper surface of the metal cap layer distal from the substrate free of the nitride-containing dielectric material, wherein the nitride-containing dielectric material extends continuously between adjacent ones of the first conductive features.

[0095] Example 15. The method of example 13, wherein selectively forming the dielectric cap layer comprises: converting an upper portion of the first dielectric layer proximate to its first surface into the dielectric cap layer by an ion implantation process.

[0096] Example 16. The method of example 13, wherein forming the plurality of etch stop layers comprises: forming a first etch stop layer over the metal cap layer and the dielectric cap layer, the first etch stop layer comprising aluminum nitride; forming a second etch stop layer over the first etch stop layer, the second etch stop layer comprising oxygen-doped silicon carbide; and forming a third etch stop layer over the second etch stop layer, the third etch stop layer comprising aluminum oxide.

[0097] Example 17. The method of example 13, wherein forming the second conductive features comprises: forming conductive lines in the second dielectric layer; and forming vias under the conductive lines, wherein upper portions of the vias are in the second dielectric layer and lower portions of the vias extend through the plurality of etch stop layers and are electrically coupled to the first conductive features.

[0098] Example 18. A semiconductor device comprising: a substrate; a first dielectric layer over the substrate; a first conductive feature in the first dielectric layer; a metal cap layer over the first conductive feature; a dielectric cap layer on an upper surface of the first dielectric layer distal the substrate, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer comprises a nitride-containing dielectric material, wherein an upper surface of the metal cap layer distal the substrate is free of the dielectric cap layer; an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers; a second dielectric layer over the etch stop layer stack; and a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the first conductive feature.

[0099] Example 19. The semiconductor device of Example 18, wherein the etch stop layer stack comprises: a first etch stop layer comprising aluminum nitride and over the metal cap layer and the dielectric cap layer; a second etch stop layer comprising oxygen-doped silicon carbide and over the first etch stop layer; and a third etch stop layer comprising aluminum oxide and over the second etch stop layer.

[0100] Example 20. The semiconductor device of Example 18, wherein the second conductive feature comprises: a metal line in the second dielectric layer, wherein a lower surface of the metal line facing the substrate is spaced apart from the etch stop layer stack; and a via under the metal line and connected to the metal line, wherein the via extends through the etch stop layer stack and contacts the metal cap layer.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature away from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers; wherein forming the etch stop layer stack comprises: forming an aluminum nitride layer over the metal cap layer and the dielectric cap layer; forming a first aluminum oxide layer over the aluminum nitride layer; forming an oxygen-doped silicon carbide layer over the first aluminum oxide layer; and forming a second aluminum oxide layer over the oxygen-doped silicon carbide layer.

2. The method of claim 1, further comprising: forming a second dielectric layer over the etch stop layer stack; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the metal cap layer. forming the metal cap layer comprises selectively forming a conductive material over an upper surface of the first conductive feature.

3. The method of claim 1, wherein, the dielectric cap layer is formed from a nitride-containing dielectric material.

4. The method of claim 1, wherein, the nitride-containing dielectric material is silicon nitride, silicon oxynitride, or silicon carbon nitride.

5. The method of claim 4, wherein, a thickness of the dielectric cap layer is between 10 angstroms and 50 angstroms.

6. The method of claim 4, wherein, selectively forming the dielectric cap layer comprises selectively depositing the nitride-containing dielectric material over an upper surface of the first dielectric layer using a plasma enhanced chemical vapor deposition (PECVD) process.

7. The method of claim 4, wherein, the PECVD process is performed using a precursor comprising N2, NH3, NO, or N2O.

8. The method of claim 7, wherein, selectively forming the dielectric cap layer comprises converting an upper layer of the first dielectric layer into the dielectric cap layer by performing an ion implantation process.

9. The method of claim 4, wherein, the ion implantation process is performed using a gas source comprising NH3 or N2O.

10. The method of claim 9, wherein, 11. A method of forming a semiconductor device, the method comprising: forming a first conductive feature in a first dielectric layer disposed over a substrate, wherein a first surface of the first conductive feature away from the substrate is flush with a first surface of the first dielectric layer; selectively forming a metal cap layer on the first surface of the first conductive feature; selectively forming a dielectric cap layer on the first surface of the first dielectric layer, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed from a nitride-containing dielectric material; forming a plurality of etch stop layers sequentially on the metal cap layer and the dielectric cap layer; forming a second dielectric layer on the plurality of etch stop layers; and ​ forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the plurality of etch stop layers and is electrically coupled to the respective first conductive features; wherein forming the plurality of etch stop layers comprises: forming a first etch stop layer over the metal cap layer and the dielectric cap layer, the first etch stop layer comprising aluminum nitride; forming a second etch stop layer over the first etch stop layer, the second etch stop layer comprising aluminum oxide; forming a third etch stop layer over the second etch stop layer, the third etch stop layer comprising oxygen-doped silicon carbide; and forming a fourth etch stop layer over the third etch stop layer, the fourth etch stop layer comprising aluminum oxide.

12. The method of claim 11, wherein, selectively forming the dielectric cap layer comprises depositing the nitride- containing dielectric material on a first surface of the first dielectric layer, but leaving an upper surface of the metal cap layer distal from the substrate free of the nitride- containing dielectric material, wherein the nitride-containing dielectric material extends continuously between adjacent first conductive features.

13. The method of claim 11, wherein, selectively forming the dielectric cap layer comprises converting an upper portion of the first dielectric layer proximate to its first surface into the dielectric cap layer by an ion implantation process.

14. The method of claim 11, wherein, forming the second conductive feature comprises: forming a conductive line in the second dielectric layer; and forming a via under the conductive line, wherein an upper portion of the via is in the second dielectric layer and a lower portion of the via extends through the plurality of etch stop layers and is electrically coupled to the first conductive features.

15. A semiconductor device, comprising: a substrate; a first dielectric layer over the substrate; first conductive features in the first dielectric layer; a metal cap layer over the first conductive features; a dielectric cap layer on an upper surface of the first dielectric layer distal from the substrate, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer comprises a nitride-containing dielectric material, wherein the upper surface of the metal cap layer distal from the substrate is free of the dielectric cap layer; an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers; a second dielectric layer over the etch stop layer stack; and second conductive features in the second dielectric layer, wherein the second conductive features extend through the etch stop layer stack and are electrically coupled to the first conductive features; wherein the etch stop layer stack comprises: a first etch stop layer comprising aluminum nitride and over the metal cap layer and the dielectric cap layer; a second etch stop layer comprising aluminum oxide and over the first etch stop layer; a third etch stop layer comprising oxygen-doped silicon carbide and over the second etch stop layer; and a fourth etch stop layer comprising aluminum oxide and over the third etch stop layer.

16. The semiconductor device of claim 15, wherein, the second conductive features comprise: a metal line in the second dielectric layer, wherein a lower surface of the metal line facing the substrate is spaced apart from the etch stop layer stack; and a via under and connected to the metal line, wherein the via extends through the etch stop layer stack and contacts the metal cap layer.

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