A high integration density chip interconnection structure, packaging structure and packaging method

Abstract

The present invention belongs to the field of chip interconnection technology, and particularly relates to a chip interconnection structure, packaging structure and packaging method with high integration density. The chip interconnection structure includes an integrated bundle, which is in a bundle shape, and includes a dielectric layer and a plurality of conductive circuits. The dielectric layer is coated on the outer surface of the plurality of conductive circuits, and the conductive circuits penetrate the dielectric layer and are exposed at the two opposite end faces of the integrated bundle. The integrated bundle of the chip interconnection structure can be made separately from the chip, and the chip packaging structure encapsulated by the integrated bundle has a higher yield and reliability, which is conducive to the detection of conductive circuit defects of the integrated bundle by measuring instruments. The length of the integrated bundle is flexibly combined, has better adaptability, and can adapt to the interconnection of chips of different specifications and different processes. Compared with the interconnection structure of TSV, the distance between the conductive circuits of the integrated bundle is smaller, which reduces the length of the interconnection transmission channel, has a higher integration density, and provides a higher data transmission rate and bandwidth.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip interconnection, and in particular relates to a chip interconnection structure, a packaging structure and a packaging method with high integration density. Background Art

[0002] The current mainstream packaging technologies include wire bonding packaging, flip-chip packaging, fan-in packaging, fan-out packaging, and three-dimensional packaging based on through silicon via technology (TSV).

[0003] In three-dimensional packaging, TSV is the key technology to achieve vertical interconnection between multiple chips. TSV technology achieves vertical electrical interconnection of silicon vias by filling conductive materials such as copper, tungsten, and polysilicon, achieving high density, high electrical performance, low cost, and low power consumption, conforming to the development trend of integrated circuits. Silicon via technology is gradually replacing the current more mature wire bonding technology and is considered to be the fourth generation of packaging technology.

[0004] However, TSV often has defects such as voids, gaps and missing filling, which will lead to a series of problems such as unstable packaging performance and reduced product reliability. What's more serious is that most of these defects are concentrated inside the wafer and chip, which seriously hinders the development of 3D packaging technology.

[0005] Therefore, the existing technology needs to be improved and developed. Summary of the invention

[0006] The object of the present invention is to provide a chip interconnection structure, a packaging structure and a packaging method with high integration density, which can provide a more reliable connection mode with higher integration density.

[0007] To solve the above technical problems, in the first aspect, the present application provides a high integration density chip interconnection structure, including an integrated bundle, the integrated bundle is in a bundle shape, the integrated bundle includes a dielectric layer and a plurality of conductive lines, the dielectric layer is coated on the outer surface of the plurality of conductive lines, the conductive lines penetrate the dielectric layer and are exposed at two opposite end faces of the integrated bundle. The interconnection between chips is achieved through the integrated bundle.

[0008] Furthermore, the conductive circuits are arranged uniformly in multiple layers of concentric circles. The conductive circuits arranged uniformly in multiple layers of concentric circles are arranged more closely under the condition of equal spacing, and have a higher integration density.

[0009] Furthermore, the conductive circuits of the outer layer are electrically led out toward the edge of the integrated bundle, so that more ports are reserved for the conductive circuits at the edge of the integrated bundle.

[0010] Furthermore, the diameter of the conductive line is 15-500 microns.

[0011] Furthermore, the distance between two adjacent conductive circuits is 2-1000 microns.

[0012] Furthermore, the dielectric layer is any one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.

[0013] Furthermore, the integrated bundle is cylindrical, truncated cone, cuboid or prism-shaped.

[0014] Furthermore, the conductive circuit is any one of copper, silver, gold and tin.

[0015] As can be seen from the above, the integrated bundle of the chip interconnection structure can be made separately from the chip, which is conducive to the detection of conductive line defects of the integrated bundle by measuring instruments. The chip packaging structure encapsulated with the integrated bundle has higher yield and reliability. The length of the integrated bundle is flexibly combined, with better adaptability, and can adapt to the interconnection of chips of different specifications and different processes. Compared with the TSV interconnection structure, the distance between the conductive lines of the integrated bundle is smaller, which reduces the length of the interconnection transmission channel, has a higher integration density, and provides a higher data transmission rate and bandwidth.

[0016] In the second aspect, the present application provides a high integration density chip packaging structure, including a flexible circuit board and the above-mentioned integrated bundle, the flexible circuit board including a connection area, and a plurality of patch areas of the same and / or different areas, the patch area is provided with a circuit layer, each of the patch areas is provided with one or more chips, heat sinks and passive devices, the chip is electrically connected to the circuit layer, at least one of the circuit layers is electrically led to the geometric center of the patch area, the edges of the plurality of patch areas form a cavity, an integrated bundle is provided in the cavity, at least one of the patch areas is electrically connected to the chips on the other patch areas through the integrated bundle.

[0017] Furthermore, the connection area is a plurality of connection lines.

[0018] As can be seen from the above, the chip packaging structure with high integration density interconnects the chips installed on multiple patch areas of the same area and different areas of the flexible circuit board by combining the integrated bundle with metal leads to form a chip packaging structure with high integration density. The patch area can mount chips of different quantities, specifications and processes, and has high flexibility and adaptability. The conductive circuits set in the integrated bundle have a high integration density, which greatly shortens the interconnection distance. The integrated bundle can be manufactured separately from the chip, which reduces the complexity of the packaging process and improves production efficiency.

[0019] In a third aspect, the present application provides a high integration density chip packaging method, including the above-mentioned integrated bundle, the packaging method comprising the following steps:

[0020] A flexible circuit board is provided, wherein the flexible circuit board comprises a connection area and a plurality of patch areas of the same or different areas, wherein the patch areas are provided with a circuit layer;

[0021] Cutting along the outer contours of the patch area and the connection area to form an unfolded structure;

[0022] Mounting one or more of a chip, a heat sink and a passive device on each of the patch areas, and the chip is disposed on at least two of the patch areas, and the chip is electrically connected to the circuit layer;

[0023] The circuit layer of at least one of the patch areas is electrically led out to its geometric center; the port of the circuit layer led out to its geometric center is electrically connected to one end of the integrated bundle, and the other end of the integrated bundle is electrically connected to the chip on the other patch area;

[0024] The unfolded structure is turned over and folded to make the edges of all the patch areas fit together, and the outer surface is plastic-sealed to obtain a chip packaging structure with high integration density.

[0025] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a cross-sectional view of the first embodiment of the chip interconnection structure of the present application.

[0027] Figure 2 This is a top view of the first embodiment of the chip interconnection structure of the present application.

[0028] Figure 3 This is a cross-sectional view of the second embodiment of the chip interconnection structure of the present application.

[0029] Figure 4 This is a top view of the second embodiment of the chip interconnection structure of the present application.

[0030] Figure 5 This is a cross-sectional view of the third embodiment of the chip interconnection structure of the present application.

[0031] Figure 6 This is a three-dimensional schematic diagram of one of the packaging structures of the present application.

[0032] Figure 7 This is a schematic plan view of one of the packaging structures of the present application.

[0033] Figure 8 This is a plan view of the second packaging structure of the present application.

[0034] Fig. 9 A plan view of the flexible circuit board of the present application is shown.

[0035] Fig.10 Shows Fig. 9 Revolved section view along line AA.

[0036] Fig.11 A schematic diagram showing the electrical lead-out of the circuit layer of the present application to the geometric center of the patch area is shown.

[0037] Fig.12 Another schematic diagram showing the electrical lead-out of the circuit layer of the present application to the geometric center of the patch area.

[0038] Fig.13 The planar expansion diagram of the chip packaging structure with high integration density of the present application before packaging is shown.

[0039] Fig.14 A flow chart showing the steps of a chip packaging method with high integration density of the present application is shown.

[0040] Description of reference numerals: 1. first chip module; 11. carrier board; 12. first chip; 13. second chip; 14. third chip; 15. fourth chip; 16. pad; 2. second chip module; 3. third chip module; 4. fourth chip module; 5. integrated bundle; 51. dielectric layer; 52. through hole; 53. conductive circuit; 6. flexible circuit board; 600. substrate; 601. first polyimide film layer; 601A. circuit layer; 602. 02, second polyimide film layer; 602A, hole position; 611, first patch area; 612, second patch area; 613, third patch area; 614, fourth patch area; 615, fifth patch area; 616, sixth patch area; 620, connecting line; 621, first connection area; 622, second connection area; 623, third connection area; 624, fourth connection area; 625, fifth connection area; 7, heat sink; 8, passive components. DETAILED DESCRIPTION

[0041] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0042] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0043] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0045] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0046] First embodiment

[0047] Figure 1 A cross-sectional view of the first embodiment of the chip interconnection structure of the present application is shown. Figure 2 The top view of the first embodiment of the chip interconnection structure of the present application is shown. The chip interconnection structure includes an integrated bundle 5. In the present embodiment, the integrated bundle 5 is a cylindrical bundle structure, and its length is determined according to the shortest straight-line distance of multiple chips that need to be packaged. The integrated bundle 5 includes a dielectric layer 51, and the dielectric layer 51 is provided with multiple axial through holes 52 along its length direction. A conductive circuit 53 is formed in each through hole 52. The conductive circuits 53 are evenly arranged in a multi-layer concentric circle. The conductive circuits 53 arranged in a concentric circle are called a layer of conductive circuits 53. In other words, the inner layer is close to the axis of the integrated bundle 5, and the outer layer is far away from the axis of the integrated bundle 5. The conductive circuit 53 of the outer layer is not limited to the outermost layer, but can also be two or more layers adjacent to the outermost layer. Multiple conductive circuits 53 are connected along the axial direction of the integrated bundle 5, and the dielectric layer 51 is coated on the outer surface of the multiple conductive circuits 53 to electrically isolate the conductive circuits 53. Among them, the upper and lower end surfaces of the cylindrical integrated bundle 5 are respectively the port lead-out planes of the conductive circuit 53, and the surfaces are respectively subjected to precision grinding treatment using a grinding disc, and the end surfaces of the integrated bundle 5 are chemically corroded by the addition of grinding liquid to obtain a bright and flat surface, so that the upper and lower ends of the conductive circuit 53 are fully exposed.

[0048] The material of the conductive line 53 can be any one of copper, silver, gold, and tin. Copper has good electrical conductivity, a high melting point, and good anti-electromigration performance, and is a common material for metal interconnection. In this embodiment, the electroplating process in electrochemical deposition is adopted. First, a blind hole is drilled or etched at a position corresponding to the through hole 52 on the integrated bundle 5 to be processed, and copper is used as an anode and the dielectric layer 51 is connected to a power supply as a cathode. A current is generated in a sulfate system solution to form an electric field. The copper at the anode reacts to form copper ions and electrons, and the copper ions and electrons at the cathode form copper that is plated on the blind hole surface of the dielectric layer 51. A layer of dense and evenly distributed copper with a diameter of 15-500 microns grows in the blind hole. Finally, the through hole 52 with the conductive line 53 is processed by the above-mentioned precision grinding process.

[0049] It should be noted that the material of the dielectric layer 51 can be one of ABF (Ajinomoto Build-up Film), Liquid Crystal Polyme (LCP), polyimide (PI), and high polymer polypropylene.

[0050] Second embodiment

[0051] Figure 3 A cross-sectional view of a second embodiment of the chip interconnection structure of the present application is shown. Figure 4 The top view of the second embodiment of the chip interconnection structure of the present application is shown. The difference from the integrated bundle 5 of the first embodiment is that the outermost conductive line 53 is led out from the axis of the integrated bundle 5 to the edge at the upper and lower ends of the integrated bundle 5. The purpose is that when the chip modules exceed two groups and are exactly six groups, they need to be packaged into a more complex cubic structure, as shown below. Figure 8 As shown, in addition to the upper and lower groups of chip modules (the first chip module 1 and the second chip module 2) that are relatively arranged to facilitate connection to the conductive line 53 port of the integrated bundle 5, since the planes where the pads 16 on the remaining four groups of chip modules (the third chip module 3, the fourth chip module 4 and the other two chip modules not shown in the figure) are located are perpendicular to the end faces of the integrated bundle 5, if the leads are further extended to the two end faces of the integrated bundle 5, the leads will be too long, increasing the transmission distance and reducing the transmission performance. It will also cause the metal leads to be locally too dense, affecting the welding efficiency.

[0052] To this end, the integrated bundle 5 can be formed by splicing multiple modules end to end, so that the number of ports leading out to the outer periphery of the integrated bundle 5 will be greatly increased, and the four groups of chip modules can be stretched to the outer periphery of the integrated bundle 5 with a shorter lead length to connect with the ports on the edge. If more chip modules located on the side of the integrated bundle 5 are connected to the integrated bundle 5, the integrated bundle 5 can also be appropriately deformed into a truncated cone, a rectangular parallelepiped or a prism shape, so that the conductive line 53 reserves more ports at the edge of the integrated bundle 5.

[0053] Third embodiment

[0054] Figure 5 The cross-sectional view of the chip interconnection structure in the third embodiment of the present application is shown. The shape of the integrated bundle 5 is a truncated cone, so that the conductive line 53 reserves more ports on the outer peripheral surface of the integrated bundle 5. Fig.13 In the packaging structure, the chip modules mounted on the first patch area 111, the third patch area 113 and the fourth patch area 114 on the side of the second patch area 112 provide more ports than the chip modules mounted on the sixth patch area 116. Therefore, when the integrated bundle 5 is truncated cone-shaped, the conductive circuits 53 on the outer layer of the integrated bundle 5 will be exposed on the outer peripheral surface of the integrated bundle 5, and more ports can be interconnected through the integrated bundle 5.

[0055] In some embodiments, the first embodiment of the chip interconnection structure is used to form a package structure. Figure 6 and Figure 7 The schematic diagram of the packaging structure is shown, including two first chip modules 1 and second chip modules 2 with the same shape and structure and arranged oppositely. The first chip module 1 includes a carrier 11, which can be a hard material such as a glass carrier, a plastic carrier, a stainless steel carrier, an alloy carrier, etc. The first chip 12, the second chip 13, the third chip 14 and the fourth chip 15 are all mounted on the carrier 11 in a face-up manner, that is, the metal pads 16 of the chips face upward, and the pads 16 are evenly distributed around the chips. The above four chips are arranged in a square array, with the geometric center of the square array as the axis, and the axis of the integrated bundle 5 is aligned with the geometric center of the square array, and temporarily fixed at a certain distance directly above the above four chips, and all the pads 16 of the above four chips are led out to the bottom of the integrated bundle 5 through metal leads.

[0056] Specifically, with the horizontal radial direction and the vertical radial direction of the integrated bundle 5 as channels, the pads 16 at the right end of the first chip 12, the pads 16 at the lower end of the first chip 12, the pads 16 at the right end of the fourth chip 15, the pads 16 at the upper end of the fourth chip 15, the pads 16 at the left end of the second chip 13, the pads 16 at the lower end of the second chip 13, the pads 16 at the left end of the third chip 14, and the leads bonded on the pads 16 at the upper end of the third chip 14 are stretched toward the horizontal radial channel space; similarly, the pads 16 at the left end of the first chip 12, the pads 16 at the upper end of the first chip 12 6. The bonding wires on the pads 16 at the left end of the fourth chip 15, the pads 16 at the bottom end of the fourth chip 15, the pads 16 at the right end of the second chip 13, the pads 16 at the top end of the second chip 13, the pads 16 at the right end of the third chip 14, and the pads 16 at the bottom end of the third chip 14 are stretched to the vertical radial channel space, so that all the ports of the above four chips correspond to the ports of the multi-layer concentrically arranged conductive circuits 53 one by one, and finally the metal leads are welded or otherwise formed into solder joints on the conductive circuits 53, so that the corresponding ports are electrically connected. Similarly, the chip mounted on the second chip module 2 is also led out to the top of the integrated bundle 5 in the same way and electrically connected to the port.

[0057] Two adjacent parallel lines will form wiring capacitance. Such capacitance can cause a current signal in another line when the voltage changes rapidly in one line. The large amount of coupling noise and crosstalk between channels in the conductive line 53 cause serious signal quality problems during signal transmission. The smaller the spacing of the conductive lines 53, the greater the coupling and the stronger the crosstalk. In order to improve the signal transmission quality inside the three-dimensional high-speed information system, by reasonably controlling the spacing of the conductive lines 53, the spacing between two adjacent conductive lines 53 is - microns, preferably microns, which is conducive to improving the problem of signal crosstalk affecting transmission performance due to electromagnetic coupling between adjacent conductive lines 53.

[0058] Since the integrated bundle 5 can be made separately from the chip, it is helpful to detect the defects of the conductive line 53 of the integrated bundle 5. The chip packaging structure encapsulated by the integrated bundle 5 has a higher yield and reliability, and its length can be flexibly combined, with better adaptability, and can adapt to the interconnection of chips of different specifications and different processes. Compared with the interconnection structure of TSV, the distance between the conductive lines 53 of the integrated bundle 5 is smaller, which reduces the length of the interconnection transmission channel, has a higher integration density, and provides a higher data transmission rate and bandwidth.

[0059] In some embodiments, the third embodiment of the chip interconnection structure is used to form a package structure. Fig. 9The planar development diagram of the flexible circuit board 6 of the present application is shown. The packaging structure includes a flexible circuit board 6, and the flexible circuit board 6 includes a connection area and a plurality of patch areas of the same and / or different areas. In the present embodiment, six patch areas are provided, namely, a first patch area 611, a second patch area 612, a third patch area 613, a fourth patch area 614, a fifth patch area 615 and a sixth patch area 616. The area relationship of the above patch areas is: the first patch area 611 = the second patch area 612> the third patch area 613 = the fourth patch area 614> the fifth patch area 615> the sixth patch area 616; there are five connection areas, namely, a first connection area 621, a second connection area 622, a third connection area 623, a fourth connection area 624 and a fifth connection area 625. The positional relationship between the patch area and the connection area is: with the second patch area 612 as the origin, the left side is connected in sequence with the first connection area 621 and the first patch area 611, the right side is connected in sequence with the second connection area 622, the fifth patch area 615, the fifth connection area 625 and the sixth patch area 616, the top is connected in sequence with the fourth connection area 624 and the fourth patch area 614, and the bottom is connected in sequence with the third connection area 623 and the third patch area 613.

[0060] It is worth mentioning that the above-mentioned patch areas are not limited to six, but can be any number above two; the shape of the patch area can be rectangular or irregular; the area of ​​the patch area is not limited to the area relationship shown above, and this embodiment only provides a typical structure for illustration.

[0061] Fig.10 Shows Fig. 9 Rotated cross-sectional view along line AA. All the above-mentioned patch areas are provided with a circuit layer 601A, and the chip is electrically connected to the circuit layer 601A. The function of the circuit layer 601A is to interconnect the chips in the same patch area to realize signal transmission between chips. One or more chips, heat sinks 7 or passive devices 8 are arranged on each patch area, and the number of chips can be one chip, two chips or multiple chips. The heat sink 7 has a plurality of protrusions and groove structures, which greatly increases the heat dissipation surface area. The heat generated by the chip is quickly transferred to the heat sink 7, and then the heat sink 7 dissipates the heat. The passive device 8 includes a peripheral circuit with radio frequency, filtering and other functions formed by coupling devices such as resistors, capacitors, and inductors.

[0062] In this embodiment, at least one circuit layer 601A is electrically led out to the geometric center of the patch area. For the patch area that needs to be electrically led out to the geometric center, the chip mounted thereon is mounted on the patch area in a face-down manner (the side with the pad 16 faces downward and contacts the patch area), while for the patch area that does not need to be electrically led out to the geometric center, the chip mounted thereon is mounted on the patch area in a face-up manner (the side with the pad 16 faces upward and does not contact the patch area), so as to facilitate the electrical connection between the integrated bundle 5 and the chip's pad 16 through metal leads.

[0063] Fig.11 A schematic diagram showing the electrical connection of the circuit layer 601A to the geometric center of the patch area is shown. Fig.12 Another schematic diagram of the electrical lead of the circuit layer 601A to the geometric center of the patch area is shown. The patch area in the figure is in the shape of a square, and the chip mounted thereon is mounted face-down on the patch area. Its geometric center is the intersection of the diagonal lines of the square. The total path from the intersection to the outer contour of the patch area is the smallest, which can provide the smallest transmission distance. A plurality of ports are arranged at the intersection, and the ports correspond one-to-one to the ports of the conductive circuit 53 of the integrated bundle 5 below. The dotted line is the pre-arranged line from the chip pad 16 to the above-mentioned port.

[0064] The connection area is rectangular in shape and has a large area. Although it can provide better bending resistance, it will limit the flip angle of the patch area in space. After the flip angle is limited, the flip amplitude of the patch area becomes smaller, and it is more difficult for the edges of the patch area to fit each other with appropriate curvature. In order to take into account the bending performance and spatial flip angle of the connection area, it is necessary to partially cut the connection area to form multiple connection lines 620, so that the space between two adjacent connection lines 620 in the connection area is hollowed out. In this embodiment, the connection line 620 is an arc connection line 620 to increase the bending performance of the connection area.

[0065] The edges of the plurality of patch areas form a cavity, in which an integrated bundle 5 is arranged, and at least one patch area is electrically connected to chips on other patch areas through the integrated bundle 5 .

[0066] The circuit layers 601A of the first patch area 611 to the fourth patch area 614 are all directed toward the geometric center of the patch area. The first patch area 611, the third patch area 613 and the fourth patch area 614 are respectively mounted with cylindrical integrated bundles 5 at their geometric centers. One end face of the cylindrical integrated bundle 5 coincides with the respective patch areas. The port of the integrated bundle 5 is connected to the port of the geometric center. The geometric center of the second patch area 612 is mounted with a truncated cone-shaped integrated bundle 5. The bottom surface of the truncated cone-shaped integrated bundle 5 coincides with the second patch area 612. After the integrated bundle 5 is installed, as shown in FIG. Fig.13 As shown, the first patch area 611, the third patch area 613, the fourth patch area 614 and the fifth patch area 615 are respectively folded toward the second patch area 612 ( Fig.13 The flexible circuit board 6 is formed into a three-dimensional structure (in the direction of the middle arrow). Since the flexible circuit board 6 is thin and has good bendability, it can be twisted and deformed into any curved surface. All edges of adjacent patch areas except the sixth patch area 616 are bonded to each other to form a semi-sealed structure with an open upper end. The ports of the other end faces of all cylindrical integrated bundles 5 are connected to the outer peripheral surface of the truncated cone-shaped integrated bundle 5 through metal leads, and then the ports of the chips in the sixth patch area 616 are connected to the ports on the upper bottom surface of the truncated cone-shaped integrated bundle 5 through metal leads. Finally, the edges of the sixth patch area 616 are bonded to the edges of other patch areas to form a completely sealed structure, and a layer of plastic sealing layer is covered on the outer surface to finally form a packaging structure with a high integration density.

[0067] In summary, the chip packaging structure with high integration density interconnects the chips of the same area and different area mounted on the flexible circuit board 6 by combining the integrated bundle 5 with metal leads, thereby forming a chip packaging structure with high integration density. The patch area can mount chips of different numbers, specifications and processes, and has high flexibility and adaptability. The conductive line 53 arranged in the integrated bundle 5 has a high integration density, which greatly shortens the interconnection distance. The integrated bundle 5 can be manufactured separately from the chip, which reduces the complexity of the packaging process and improves production efficiency.

[0068] Fig.14 The flowchart of the high integration density chip packaging method of the present application is shown. Specifically, the following steps are included:

[0069] Step 1: providing a flexible circuit board 6, wherein the flexible circuit board 6 comprises a connection area and a plurality of patch areas of different areas and / or the same area, wherein the patch area is provided with a circuit layer 601A;

[0070] Specifically, Fig.10 As shown, the flexible circuit board 6 includes a substrate 600, a first polyimide film layer 601, and a second polyimide film layer 602 from top to bottom. The manufacturing process of the flexible circuit board 6 specifically includes the following steps:

[0071] Providing a substrate 600, and forming a first polyimide film layer 601 on a surface of the substrate 600;

[0072] A circuit layer 601A is disposed on the first polyimide film layer 601, and the circuit layer 601A is electrically led out to the geometric center of the patch area where it is located;

[0073] A second polyimide film layer 602 is disposed on the circuit layer 601A, thereby obtaining a flexible circuit board 6 .

[0074] The second polyimide film layer 602 is subjected to a hole-opening process to form a hole 602A, and the hole 602A is used to expose the pad area of ​​the circuit layer 601A;

[0075] A chip, a heat sink 7 or a passive device 8 is disposed on the second polyimide film layer 602 , and the chip is electrically connected to the pad area of ​​the circuit layer 601A.

[0076] This application provides two methods for manufacturing the circuit layer 601A.

[0077] First method:

[0078] Providing a photosensitive dry film or photosensitive ink, and covering the photosensitive dry film or photosensitive ink on the first polyimide film layer 601;

[0079] Exposing and developing the photosensitive dry film or the photosensitive ink to form a first patterned through hole;

[0080] Electroplating copper in the first patterned through hole to form a preset circuit;

[0081] The photosensitive dry film or photosensitive ink is stripped, and a dielectric material layer is covered on the first polyimide film layer 601 to obtain a circuit layer 601A.

[0082] Second method:

[0083] Providing a copper foil, and pressing the copper foil onto the first polyimide film layer 601;

[0084] Etching the copper foil to form a preset circuit and forming a second patterned through hole;

[0085] A dielectric material layer is disposed in the second patterned through hole to obtain a circuit layer 601A.

[0086] Both of the above methods can set the circuit layer 601A on the first polyimide film layer 601, but preferably, the first method causes less damage to the first polyimide film layer 601. In practical applications, the material of the dielectric material layer can be one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.

[0087] Step 2: Cut along the outer contour of the patch area and the connection area to form an unfolded structure. The flexible circuit board 6 is placed flatly on the workbench of the laser cutting machine. After scanning by the scanning device, laser cutting is performed along the outer contour of the patch area and the connection area, and the edges after cutting are flat.

[0088] The connection area is partially cut to form a plurality of connection lines 620, so that the space between two adjacent connection lines 620 in the connection area is hollowed out. The connection lines are arc-shaped connection lines 620 to increase the bending performance of the connection area.

[0089] Step 3: Mount one or more of a chip, a heat sink 7 and a passive device 8 on each patch area, and at least two patch areas are provided with chips, and the chips are electrically connected to the circuit layer 601A.

[0090] Step 4: The circuit layer 601A of at least one patch area is electrically led out to its geometric center; the port of the circuit layer 601A led out to its geometric center is electrically connected to one end of the integrated bundle 5, and the other end of the integrated bundle 5 is electrically connected to the chips on other patch areas.

[0091] Step 5: Fold the unfolded structure over so that the edges of all patch areas fit together, and perform plastic sealing on the outer surface to obtain a packaging structure with high integration density.

[0092] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0093] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A chip interconnect structure with high integration density, It is characterized in that The integrated bundle (5) is in a bundle shape, and comprises a dielectric layer (51) and a plurality of conductive lines (53). The dielectric layer (51) is coated on the outer surfaces of the plurality of conductive lines (53), and the conductive lines (53) penetrate the dielectric layer (51) and are exposed at two opposite end surfaces of the integrated bundle (5); The conductive circuits (53) are evenly arranged in multiple layers of concentric circles; The conductive line (53) of the outer layer is electrically led out toward the edge of the integrated bundle (5); The diameter of the conductive circuit (53) is 15-500 microns, and the distance between two adjacent conductive circuits (53) is 2-1000 microns.

2. A chip interconnect structure with high integration density according to claim 1, It is characterized in that The dielectric layer (51) is any one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.

3. The chip interconnect structure with high integration density according to claim 1, It is characterized in that The integrated bundle (5) is cylindrical, truncated cone, rectangular parallelepiped or prism-shaped.

4. The chip interconnect structure with high integration density according to claim 1, It is characterized in that The conductive line (53) is made of any one of copper, silver, gold and tin.

5. A chip packaging structure with high integration density, comprising a flexible circuit board (6), It is characterized in that It also includes an integrated bundle as described in any one of claims 1 to 4, the flexible circuit board (6) includes a connection area, and a plurality of patch areas of the same and / or different areas, the patch area is provided with a circuit layer (601A), each of the patch areas is provided with one or more of a chip, a heat sink (7) and a passive device (8), the chip is electrically connected to the circuit layer (601A), at least one of the circuit layers (601A) is electrically led to the geometric center of the patch area, the edges of the plurality of patch areas form a cavity, an integrated bundle (5) is provided in the cavity, and at least one of the patch areas is electrically connected to the chips on the other patch areas through the integrated bundle (5).

6. The chip packaging structure with high integration density according to claim 5, It is characterized in that The connection area is a plurality of connection lines (620).

7. A high integration density chip packaging method, It is characterized in that Comprising the integrated bundle according to any one of claims 1 to 4, the packaging method comprises the following steps: A flexible circuit board (6) is provided, wherein the flexible circuit board (6) comprises a connection area and a plurality of patch areas of the same and / or different areas, wherein the patch areas are provided with a circuit layer (601A); Cutting along the outer contours of the patch area and the connection area to form an unfolded structure; Mounting one or more of a chip, a heat sink (7) and a passive device (8) on each of the patch areas, with the chip being arranged on at least two of the patch areas, and electrically connecting the chip to the circuit layer (601A); The circuit layer (601A) of at least one of the patch areas is electrically led out to its geometric center; the port of the circuit layer (601A) led out to its geometric center is electrically connected to one end of the integrated bundle (5), and the other end of the integrated bundle (5) is electrically connected to the chip on the other patch area; The unfolded structure is turned over and folded to make the edges of all the patch areas fit together, and the outer surface is plastic-sealed to obtain a chip packaging structure with high integration density.

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