Semiconductor Device and Method for Manufacturing the Same

Abstract

The present application provides a semiconductor device and a method for manufacturing the same. The second region of the semiconductor device has TGVs, and includes a substrate, and an epitaxial layer, a first dielectric layer, a first metal layer, a second dielectric layer, a protective layer, and a second metal layer that are sequentially stacked on the substrate; the first metal layer is located in the first region; the second dielectric layer has vias that penetrate through the second dielectric layer to connect the first metal layer and the protective layer, and the vias are filled with a connecting material to form connecting members; and the TGVs penetrate through the protective layer, the second dielectric layer, the first dielectric layer, the epitaxial layer to the substrate, and the second metal layer covers the inner walls of the protective layer and the TGVs and contacts the substrate. The protective layer in the semiconductor device can cover the connecting members, so that they are not affected during the TGV process, ensuring good conductive effects and thus not affecting the performance of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The wide-bandgap semiconductor GaN (gallium nitride) has the characteristics of high breakdown electric field, high electron mobility and high electron saturation drift velocity, and has broad application prospects in the fields of power electronics and radio frequency microwave. The piezoelectric polarization and spontaneous polarization generated by AlGaN (aluminum gallium nitride) / GaN will form a two-dimensional electron gas with a high concentration at the heterojunction interface, and its mobility and saturation velocity are much higher than those of silicon. The HEMT (high electron mobility transistor) made with the AlGaN / GaN heterojunction as the core has excellent performance and is very suitable for making power semiconductor devices, and is currently widely concerned in the industry.

[0003] In some semiconductor devices, in order to avoid damage to the device structure due to excessive stress during the packaging and cutting of the wafer, a TGV (through GaN vias) process needs to be added. This process is generally carried out after the last metal process. The TGV process needs to etch through both the dielectric layer and the epitaxial layer and stop on the substrate. At present, in order to meet the requirements of different packaging technologies, such as WLCSP (wafer level chip scale package) or ECP (embedded component package), the TGV process needs to be carried out before the last metal process, aiming to set metal in the TGV to facilitate the subsequent packaging wire connection and lead-out.

[0004] However, in the traditional manufacturing method, the morphology and quality of the tungsten plug are poor, and it is easy to leave photoresist and other substances during the implementation of the TGV process, resulting in an increase in the contact resistance of the via where the tungsten plug is located and affecting the overall performance of the device. Summary of the Invention

[0005] The present application provides a semiconductor device and a manufacturing method thereof, which can prevent the increase of the resistance in the via from affecting the device performance during the TGV process.

[0006] In a first aspect, the present application provides a semiconductor device, such as a HEMT, which has a TGV. Specifically, the semiconductor device has a first region and a second region, and the above TGV is disposed in the second region. The semiconductor device specifically includes a substrate and an epitaxial layer, a first dielectric layer, a first metal layer, a second dielectric layer, a protective layer, and a second metal layer that are sequentially stacked on the substrate. The first metal layer is located in the first region. The second dielectric layer has vias that penetrate the second dielectric layer to connect the first metal layer and the protective layer. The vias are filled with a bonding material to form a connection member, and the connection member can connect the first metal layer and the second metal layer to achieve device functions. The TGV penetrates the protective layer, the second dielectric layer, the first dielectric layer, the epitaxial layer to the substrate, and the substrate can be exposed from the bottom of the TGV. The second metal layer covers the inner walls of the protective layer and the TGV and contacts the substrate, so that the substrate can be led to the surface of the semiconductor device. Among them, the protective layer can cover the connection member so that it is not affected during the TGV process, ensuring a good conductive effect and thus not affecting the performance of the device.

[0007] Specifically, the protective layer can be selected as a single-layer structure or a multi-layer structure, and can be adaptively selected according to the application scenario in specific implementations. Among them, the material of the protective layer can be one or a combination of several of W, Ti, Ti / TiN, Al / Ti / TiN, and polysilicon doped conductive materials, and its thickness can be so as not to affect the electrical connection effect between the first metal layer and the second metal layer.

[0008] In addition, the material of the bonding material can be a combination of one or more of Ti, TiN, W, TiW, and Ni; the material of the substrate can be SiC, Si-based semiconductor material, or group III-V compound; the material of the first metal layer can be a laminated layer of one or a combination of several of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi, and their metal compounds; and / or, the material of the second metal layer can be a laminated layer of one or a combination of several of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi, and their metal compounds.

[0009] In some possible implementation manners, isolation structures such as grooves and notches are provided on the second metal layer, and the isolation structures are used to divide the second metal layer into different regions (such as a gate region, a source region, a drain region, etc.) to achieve different functions.

[0010] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device in the above technical solution, and includes the following steps:

[0011] An epitaxial layer, a first dielectric layer, a first metal layer, and a second dielectric layer are sequentially formed on a substrate; the substrate has a first region and a second region, and the first metal layer corresponds to the first region;

[0012] A via hole penetrating through the second dielectric layer to the first metal layer is formed on the second dielectric layer, and a connection material is filled in the via hole to form a connector;

[0013] A protective layer is formed on the side of the second dielectric layer facing away from the substrate;

[0014] The protective layer, the second dielectric layer, the first dielectric layer, and the epitaxial layer are etched to the substrate in the second region to form a TGV;

[0015] Metal is deposited on the side of the protective layer facing away from the substrate to form a second metal layer covering the protective layer. The second metal layer covers the inner wall of the TGV and contacts the substrate.

[0016] In some possible implementation manners, after forming the second metal layer, the following steps are further included:

[0017] The second metal layer is patterned to form different functional regions dividing the second metal layer. Description of the Drawings

[0018] Figure 1a It is a schematic structural diagram of a semiconductor device provided by the prior art;

[0019] Figures 1b to 1d It is a schematic diagram of the preparation process of a semiconductor device provided by the prior art;

[0020] Figure 2a And Figure 2b It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0021] Figure 3 It is a schematic structural diagram of a protective layer in a semiconductor device provided by an embodiment of the present application;

[0022] Figures 4a to 4c It is a schematic structural diagram of a protective layer in a semiconductor device provided by an embodiment of the present application;

[0023] Figure 5 It is a schematic diagram of the via hole resistance test effect of a semiconductor device provided by an embodiment of the present application;

[0024] Figure 6 It is a schematic flowchart of the preparation method of a semiconductor device provided by an embodiment of the present application;

[0025] Figures 7a to 7d It is a schematic diagram of the structural change of a semiconductor device during the preparation process provided by an embodiment of the present application;

[0026] Figure 8 Schematic diagram of a structure in the manufacturing process of a semiconductor device with a notch provided by an embodiment of the present application. Specific implementation manners

[0027] Generally, TGVs are made in current semiconductor devices to reduce structural damage caused by different thermal expansion coefficients between the epitaxial structure and the substrate structure during the manufacturing process. For example Figure 1a A semiconductor device of a commonly used HEMT device in the industry as shown, specifically including a substrate 1', an epitaxial layer 2', a first dielectric layer 3', and a second dielectric layer 4' sequentially provided on the substrate 1'. A first metal layer 5' is provided between the first dielectric layer 3' and the second dielectric layer 4'. The projected area of the first metal layer 5' on the first dielectric layer 3' corresponds to the functional area of the HEMT device; the HEMT device has a TGVA penetrating through the second dielectric layer 4', the first dielectric layer 3', the epitaxial layer 2' to the substrate 1'. A second metal layer 6' is provided on the surface of the second dielectric layer 4', and the second metal layer 6' also covers the TGVA. A tungsten plug 7' is provided on the second dielectric layer 4'. The tungsten plug 7' is conical and penetrates from the surface of the second dielectric layer 5' facing the second metal layer 6' to the surface of the second dielectric layer 5' facing the first metal layer 4' to realize electrical connection between the first metal layer 4' and the second metal layer 6'. During the manufacturing process of such a semiconductor device, first as Figure 1b shown, a via B is formed on the second dielectric layer 4' using photolithography and etching processes; then as Figure 1c shown, tungsten is deposited in the via B by CVD (chemical vapor deposition) and the tungsten outside the via B is etched back to form the tungsten plug 7', and the tungsten plug 7' abuts against the first metal layer 5'; then a TGV process is performed, specifically including processes such as coating with glue, exposure, development, etching, and removing glue to form Figure 1d the TGV A as shown; finally, a metal layer is sputter-deposited by PVD (physical vapor deposition) to form the second metal layer 6' (the structure can be referred to Figure 1a shown), and photolithography and etching are performed on the second metal layer 6' so that the metal in the TGV A can be led out to facilitate the connection of packaging wiring. For such an HEMT device, the tungsten filling morphology and quality at the middle position of the tungsten plug 7 are poor, the tungsten plug 7' is V-shaped, and it is easy to leave photoresist and other substances during the subsequent TGV process, ultimately resulting in an increase in the contact resistance of the via B and affecting the overall performance of the device.

[0028] Based on this, an embodiment of the present application provides a semiconductor device and a manufacturing method thereof to solve the above problems. To make the purpose, technical solution, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0029] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification and appended claims of this application, the singular forms "a", "an", "the", "above-mentioned", "said", and "this" are also intended to include expressions such as "one or more", unless the context clearly indicates otherwise.

[0030] Reference to "one embodiment" or "some embodiments" described in this specification means that a specific feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants mean "including but not limited to", unless otherwise specifically emphasized.

[0031] Please refer to Figure 2a , an embodiment of this application provides a semiconductor device, which includes a substrate 1, and an epitaxial layer 11, a first dielectric layer 2, a first metal layer 3, a second dielectric layer 4, a protective layer 5, and a second metal layer 6 that are sequentially stacked on the substrate 1 from bottom to top. According to the functional use division of the semiconductor device, the semiconductor device has a first region V1 and a second region V2. Among them, the first region V1 corresponds to the region where the functional devices in the semiconductor device are located, and the second region V2 is equivalent to other regions outside the region where the functional devices in the semiconductor device are located. The above-mentioned first metal layer 3 is correspondingly arranged in the first region V1, that is, the first metal layer 3 does not exist in the second region V2. In the second region V2, the first dielectric layer 2 and the second dielectric layer 4 are in direct contact. The second dielectric layer 4 has a via that penetrates through the second dielectric layer 4 to connect the first metal layer 3 and the protective layer 4. The via is filled with a connecting material to form a connecting member 7, and the connecting member 7 is equivalent to a conductor connecting the first metal layer 3 and the second metal layer 6. The shape of the connecting member 7 is adapted to the shape of the via, and is in the shape of a frustum of a cone with one end large and one end small. Its smaller end contacts the first metal layer 3, and its larger end contacts the second metal layer 6. In the second region V2, there is a TGV S that penetrates through the protective layer 5, the second dielectric layer 4, the first dielectric layer 2, the epitaxial layer 11 to the substrate 1, and the substrate 1 is exposed. The second metal layer 6 covers the protective layer 5 and the TGV S, and the metal of the substrate 1 exposed in the TGVS can be led out, which is convenient for subsequent packaging wiring. Among them, the epitaxial layer 11 can be grown on the substrate 1 during preparation.

[0032] The protective layer 5 covers the second dielectric layer 4 and the connecting member 7, such that the side of the structure facing the second metal layer 6 lies in the same horizontal plane, and protects the surface of the connecting member 7, preventing the connecting member 7 from being affected during subsequent preparation of the TGV S. The contact resistance of the connecting member 7 is maintained without being affected and reduced, and thus will not have an adverse effect on the performance of the semiconductor device having the same.

[0033] Please refer to Figure 2b , in some embodiments, the semiconductor device provided by the embodiments of the present application may further be provided with an isolation structure R penetrating the second metal layer 6 and the protective layer 5 to the second dielectric layer 4. Wherein, the isolation structure R corresponds to the first region V1, and may divide the second metal layer 6 into different regions, and different regions of the second metal layer 6 may be used to implement different functions. For example, the second metal layer 6 may be divided into a gate region, a source region, and a drain region. The isolation structure R may be a trench as shown in Figure 2b , and may also be other structures, which will not be elaborated herein.

[0034] Wherein, the material of the protective layer 5 may specifically be one or a combination of several of W, Ti, Ti / TiN, Al / Ti / TiN, and doped polysilicon conductive materials, and its thickness is selected to be The material of the connection material for forming the connecting member 7 may be one or a combination of several of Ti, TiN, W, TiW, and Ni. Among them, W is a relatively commonly used material. The material of the substrate 1 may be SiC, Si-based semiconductor material, or group III-V compound.

[0035] The material of the first metal layer 3 may be a laminate of one or a combination of several of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi, and their metal compounds; and / or, the material of the second metal layer 6 may be a laminate of one or a combination of several of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi, and their metal compounds.

[0036] Here, assuming that the content before "and / or" is solution a and the content after "and / or" is solution b, the above technical solution includes three implementation manners, namely, implementing solution a and solution b simultaneously, only implementing solution a, and only implementing solution b. In specific application scenarios, it can be adaptively selected according to the application scenario.

[0037] In some embodiments, the structure of the protective layer 5 may be a single-layer structure, specifically, it may be a single-layer structure of one material (not shown herein), or may be a structure in which at least one dopant 52 is doped in a matrix 51 as shown in Figure 3 .

[0038] In other embodiments, the structure of the protective layer 5 may be a multi-layer structure, specifically, it may be asFigure 4a It is shown that it is formed by stacking multiple single-layer structures of the same material, or it can be like Figure 4b shown, formed by stacking single-layer structures of at least two different materials; of course, in the protective layer 5 of the multi-layer structure, as Figure 4c shown, the single-layer structure of a certain layer can also be Figure 3 the structure in which the matrix 51 is doped with the dopant 52 as shown.

[0039] Batch testing and simulation of the contact resistance of different via processes can obtain Figure 5 the test results shown. The abscissa is different process states, and the ordinate is the resistance of the via. Among them, the structure of "via without protection" can refer to Figure 1a an existing semiconductor device shown. The resistance value range of the via B (the position where the connecting member 7' is located) is approximately between 3.5 - 3.9 Ω, and 3.63887 Ω is the median value of the resistance of the via B in this semiconductor device, that is, 50% of the resistance of the via B is greater than this resistance value. The structure of "via + protective layer" is the semiconductor device provided by the embodiment of the present application (which can refer to Figure 2a ), the resistance value range of its via M (the position where the connecting member 7 is located) is approximately between 1 - 1.2 Ω, and 1.05982 Ω is the median value of the resistance of the via B in this semiconductor device, that is, 50% of the resistance of the via M is greater than this resistance value. The resistance value range of the "without via" structure is approximately between 0.7 - 0.8 Ω, and 0.733745 Ω is the median value of the resistance between the two metal layers of this semiconductor device, that is, 50% of the resistance between the two metal layers is greater than this resistance value. It can be seen that compared with the semiconductor device without via protection ( Figure 1a the structure shown), due to the presence of the protective layer 5 in the semiconductor device provided by the embodiment of the present application, the resistance of the via M (the position where the connecting member 7 is located) between the first metal layer 3 and the second metal layer 6 can be significantly reduced, even less than one-third of the resistance at the position of the via B in the semiconductor device without via protection, and the resistance gap with the resistance between the two metal layers without via is not large, which can achieve a good current conduction effect and save energy consumption.

[0040] Based on this semiconductor device, the embodiment of the present application also provides a manufacturing method for manufacturing a semiconductor device, as Figure 6 shown, specifically including the following steps:

[0041] Step S1: Sequentially form an epitaxial layer 11, a first dielectric layer 2, a first metal layer 3, and a second dielectric layer 4 on the substrate 1; the substrate 1 has a first region V1 and a second region V2, and the first metal layer 3 corresponds to the first region V1; obtain Figure 7a the structure shown.

[0042] Step S2: Form a via M that penetrates through the second dielectric layer 4 to the first metal layer 3 on the second dielectric layer 4, and fill the via M with a connection material to form a connector 7; obtain Figure 7b the structure shown.

[0043] Specifically, apply glue on the second dielectric layer 4, and obtain the via M by exposure, development, and baking using the first template; then deposit a layer of connection material on the side of the second dielectric layer 4 facing away from the substrate 1 by chemical deposition, and etch back the other connection material outside the via to leave the connection material only in the via M to form the connector 7. The material of the connection material can be one or a combination of Ti, TiN, W, TiW, Ni.

[0044] Step S3: Form a protective layer 5 on the side of the second dielectric layer 4 facing away from the substrate 1; obtain Figure 7c the structure shown.

[0045] The material of the protective layer 5 can be selected from one or a combination of W, Ti, Ti / TiN, Al / Ti / TiN, polysilicon doped conductive materials, and its thickness is selected as

[0046] Step S4: Etch the protective layer 5, the second dielectric layer 4, the first dielectric layer 2, and the epitaxial layer 11 to the substrate 1 in the second region V2 to form TGV S;

[0047] Specifically, apply glue on the protective layer 5, expose, develop, and bake using the second template, and etch the protective layer 5, the second dielectric layer 4, the first dielectric layer 2, and the epitaxial layer 11 to the substrate 1 to obtain TGV S. The remaining photoresist and etching by-products can be removed by a process combining dry etching and wet etching, and obtain Figure 7d the structure shown.

[0048] Step S5: Deposit a metal on the side of the protective layer 5 facing away from the substrate 1 to form a second metal layer 6 covering the protective layer 5. The second metal layer 6 covers the inner wall of the TGV S and contacts the substrate 1;

[0049] Specifically, grow a metal on the side of the protective layer 5 facing away from the substrate 1 and inside the TGV S by physical vapor deposition to obtain the second metal layer 6. The material of the second metal layer 6 includes but is not limited to a combination of one or more of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi and their metal compounds in a stacked layer, and finally obtain Figure 2a the semiconductor device shown.

[0050] After implementing Step S5, in order to form a pattern on the second metal layer 6, glue can be applied on the second metal layer 6, exposed, developed, and baked using the third template, dry-etched the second metal layer 6, and finally remove the photoresist and etching by-products.

[0051] In some embodiments, if a semiconductor device formed with the isolation structure R shown in Figure 2b is to be obtained, after obtaining the structure shown in Figure 2a the semiconductor device shown in Figure 2b can be directly obtained by using a template to etch the second metal layer 6 and the protective layer 5; it is also possible to etch the protective layer 5 after obtaining the structure shown in Figure 7d to obtain the structure shown in Figure 8 and then deposit a metal on the side of the protective layer 5 facing away from the substrate 1 to obtain the second metal layer 6, and then etch the second metal layer 6 to obtain the semiconductor device shown in Figure 2b The isolation structure R can divide the second metal layer 6 into different functional regions (such as a gate region, a source region, and a drain region) to achieve different functions.

[0052] The semiconductor device provided by the embodiments of the present application has a TGV, which can alleviate the structural deformation caused by the different expansion coefficients of the epitaxial structure and the substrate structure. Since there is a protective layer 5 on the side of the second dielectric layer 4 facing away from the substrate 1, the protective layer 5 can weaken the influence of the TGV process on the via resistance, thereby ensuring the overall performance of the semiconductor device.

[0053] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a first region and a second region, the second region has a gallium nitride through hole TGV, and the semiconductor device includes: a substrate and an epitaxial layer, a first dielectric layer, a first metal layer, a second dielectric layer, a protective layer and a second metal layer stacked in sequence on the substrate; The first metal layer is located in the first area; the second dielectric layer has a via hole penetrating the second dielectric layer to connect the first metal layer and the protective layer, and the via hole is filled with a connecting material to form a connecting member; The TGV penetrates the protective layer, the second dielectric layer, the first dielectric layer, the epitaxial layer to the substrate, and the second metal layer covers the protective layer and the inner wall of the TGV and contacts the substrate; The material of the protective layer is one or a combination of W, Ti, Ti / TiN, Al / Ti / TiN, and polysilicon doped conductive materials.

2. The semiconductor device according to claim 1, wherein The thickness of the protective layer is 3. The semiconductor device according to claim 1, wherein The protective layer is a single-layer or multi-layer structure.

4. The semiconductor device according to claim 1, characterized in that, The material of the connecting material is one or more combinations of Ti, TiN, W, TiW and Ni.

5. The semiconductor device according to claim 1, wherein The substrate is made of SiC, Si-based semiconductor material or III-V group compound.

6. The semiconductor device according to claim 1, wherein, The material of the first metal layer is a composite layer of one or more selected from the group consisting of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi and metal compounds thereof; And / or, the material of the second metal layer is a combined stack of one or more of Al, AlCu, AlSiCu, TiN, W, Ni, Ta, TaN, Pd, WSi and metal compounds thereof.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The semiconductor device also has an isolation structure that penetrates the second metal layer and the protection layer to the second dielectric layer, so as to divide the second metal layer into different areas.

8. A method for manufacturing a semiconductor device, characterized in that, For preparing a semiconductor device according to any one of claims 1 to 7, the preparation method comprises the following steps: An epitaxial layer, a first dielectric layer, a first metal layer and a second dielectric layer are sequentially formed on a substrate; the substrate has a first region and a second region, and the first metal layer corresponds to the first region; forming a via hole on the second dielectric layer that penetrates the second dielectric layer to the first metal layer, and filling the via hole with a connecting material to form a connecting member; forming a protective layer on a side of the second dielectric layer facing away from the substrate; Etching the protective layer, the second dielectric layer, the first dielectric layer, and the epitaxial layer to the substrate in the second region to form the TGV; A metal is deposited on a side of the protection layer facing away from the substrate to form a second metal layer covering the protection layer, wherein the second metal layer covers an inner wall of the TGV and contacts the substrate.

9. The preparation method according to claim 8, wherein After forming the second metal layer, the method further comprises: The second metal layer is patterned to divide the second metal layer into different regions.

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