Vertical transistor array and method for forming a vertical transistor array

Abstract

The present application relates to a vertical transistor array and a method for forming a vertical transistor array. The vertical transistor array includes spaced-apart columns of individual vertical transistors, each of which includes an upper source / drain region, a lower source / drain region, and a channel region vertically located therebetween. The upper source / drain region includes a conductive oxide material in an individual of the columns. The channel region includes an oxide semiconductor material in an individual column. The lower source / drain region includes a first conductive oxide material in an individual column that is located on top of and directly abuts a second conductive oxide material in the individual column. Horizontally extended and spaced-apart conductor lines individually interconnect corresponding multiple vertical transistors in a column direction. The conductor lines individually include a second conductive oxide material located on top of and directly abuts a metal material. The first conductive oxide material, the second conductive oxide material, and the metal material include different components relative to each other.

Description

Technical Field

[0001] Embodiments disclosed herein relate to vertical transistor arrays and methods of forming vertical transistor arrays. Background Art

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be called bit lines, data lines, or sense lines) and access lines (which may also be called word lines). Digit lines conductively interconnect memory cells along the columns of the array, and access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time without power. Non-volatile memory is typically designated as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the states are considered to be either "0" or "1." In other systems, at least some individual memory cells can be configured to store information at more than two levels or states.

[0004] Field-effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one source / drain region to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The gate insulator may be programmable between at least two retained capacitive states, whereby the transistor is non-volatile. Alternatively, the gate insulator may not be programmable, whereby the transistor is volatile. In any case, field-effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate structure between the gate insulator and the conductive gate.

[0005] Capacitors are another type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, as an electric field, can be electrostatically stored within this material. Depending on the composition of the insulating material, the stored field will be either volatile or non-volatile. For example, a capacitor insulating material consisting solely of SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states and can thus comprise the programmable material of a capacitor and / or memory cell. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and remains (at least for a period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance than the other polarization state, and ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until it is desired to do so. Less undesirably, in certain memories having ferroelectric capacitors, the act of reading a memory state reverses the polarization. Thus, after the polarization state is determined, the memory cell is rewritten to place the memory cell in the pre-read state immediately after its determination. Regardless, due to the bistability of the ferroelectric material forming part of the capacitor, memory cells incorporating ferroelectric capacitors are ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0006] The capacitors and transistors may of course be used in integrated circuits other than memory circuitry and fabricated into arrays that may or may not be at least part of a memory array. Summary of the Invention

[0007] In one aspect, the present application provides a vertical transistor array comprising: spaced-apart pillars of individual vertical transistors; the spaced-apart pillars individually comprising an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region; the upper source / drain region comprising a conductive oxide material in individual ones of the pillars, the channel region comprising an oxide semiconductor material in the individual pillars, and the lower source / drain region comprising a first conductive oxide material in the individual pillars located on top of and directly abutting a second conductive oxide material in the individual pillars; horizontally elongated and spaced-apart conductor lines individually interconnecting a corresponding plurality of vertical transistors in the vertical transistors in a column direction, the conductor lines individually comprising the first conductive oxide material located on top of and directly abutting a metal material. two conductive oxide materials; the first conductive oxide material, the second conductive oxide material and the metal material include different components relative to each other; the second conductive oxide material of the conductor line is located below the second conductive oxide material of the lower source / drain region of the individual pillars of the corresponding multiple vertical transistors and directly abuts the second conductive oxide material; horizontally extended and spaced apart conductive gate lines, which are individually operatively located next to the oxide semiconductor material in the channel region of the individual pillars and individually interconnect the corresponding multiple vertical transistors in a row direction; and a conductive structure, which is laterally located between and spaced from adjacent spaced apart conductor lines in the spaced apart conductor lines in the row direction, the conductive structure individually including a top surface that is higher than the top surface of the metal material of the conductor line.

[0008] In another aspect, the present application provides a vertical transistor array comprising: spaced-apart pillars of individual vertical transistors; the spaced-apart pillars individually comprising an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region; the upper source / drain region comprising a conductive oxide material in individual ones of the pillars, the channel region comprising an oxide semiconductor material in the individual pillars, and the lower source / drain region comprising a first conductive oxide material in the individual pillars; horizontally elongated and spaced-apart conductor lines individually interconnecting a corresponding plurality of the vertical transistors in a column direction, the conductor lines individually comprising the second conductive oxide material located atop and directly against a metal material; the first conductive oxide material, the second conductive oxide material and the metal material include different components relative to each other; the second conductive oxide material of the conductor line is located below the first conductive oxide material of the lower source / drain region of the individual pillars of the corresponding multiple vertical transistors and directly abuts the first conductive oxide material; horizontally extended and spaced apart conductive gate lines, which are individually operatively located next to the oxide semiconductor material in the channel region of the individual pillars and individually interconnect the corresponding multiple vertical transistors in a row direction; and a conductive structure, which is laterally located between and spaced from adjacent spaced apart conductor lines in the spaced apart conductor lines in the row direction, the conductive structure individually including a top surface that is higher than the top surface of the metal material of the conductor line.

[0009] In another aspect, the present application provides a vertical transistor array comprising: spaced-apart pillars of individual vertical transistors; the spaced-apart pillars individually comprising an upper source / drain region above a channel region, the upper source / drain region comprising a conductive oxide material in individual ones of the pillars, the channel region comprising an oxide semiconductor material in the individual ones of the pillars; horizontally elongated and spaced-apart conductor lines individually interconnecting corresponding multiple vertical transistors in a column direction; the conductor lines individually comprising a first conductive oxide material, a second conductive oxide material, and a metal material; the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative to each other; the first conductive oxide material in the conductor line is located on top of and directly abuts the second conductive oxide material in the conductor line The present invention relates to a method for manufacturing a plurality of vertical transistors of the present invention to provide a plurality of conductive gate lines extending horizontally and spaced apart from each other, wherein the conductive gate lines are arranged in a horizontal direction and are ...

[0010] In another aspect, the present application provides a method for forming a vertical transistor array, comprising: forming laterally spaced and horizontally elongated line structures in a column direction; the line structures comprising an insulator material, a metal material above the insulator material, a transistor material above the metal material, and insulating material on lateral sides of the insulator material, the metal material, and the transistor material; the transistor material comprising an upper source / drain region above a channel region to be a part of an individual vertical transistor, the insulator material of the line structures being located above a conductive material; forming lateral electrodes in the line structures in the column direction; horizontally extending conductive lines between adjacent line structures and directly against the conductive material, the conductive lines individually including a top surface that is higher than the top surface of the metal material and located at or below the bottom of the channel region; after forming the conductive lines, cutting the transistor material to form spaced-apart pillars, the spaced-apart pillars individually including the upper source / drain regions and the channel regions of the individual vertical transistors; and forming horizontally extending conductive gate lines that are operatively located next to the channel regions of individual ones of the pillars, the horizontally extending conductive gate lines interconnecting the corresponding plurality of the vertical transistors in a row direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagrammatic cross-sectional view of a vertical transistor array according to an embodiment of the present invention and is a diagrammatic cross-sectional view through Figure 2 、 3 and intercepted by line 1-1 in 4.

[0012] Figure 2 It passes through Figure 1 and 4 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0013] Figure 3 It passes through Figure 1 、 2 and a diagrammatic cross-sectional view taken along line 3-3 in FIG. 4 .

[0014] Figure 4 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 4-4 in FIG.

[0015] Figure 5 yes Figure 4 Amplification of a part.

[0016] Figure 6 yes Figure 2 Amplification of a part.

[0017] Figure 7 is a diagrammatic cross-sectional view of a vertical transistor array according to an embodiment of the present invention.

[0018] Figure 8 is a diagrammatic cross-sectional view of a vertical transistor array according to an embodiment of the present invention.

[0019] Figures 9 to 12 is a diagrammatic cross-sectional view of a vertical transistor array according to an embodiment of the present invention.

[0020] Figures 13 to 16 is a diagrammatic cross-sectional view of a vertical transistor array according to an embodiment of the present invention.

[0021] Figures 17 to 35 According to some embodiments of the present invention, Figures 1 to 6 Illustrations of methods of construction are provided in sequential cross-sectional and / or enlarged views. DETAILED DESCRIPTION

[0022] Embodiments of the present invention include methods of forming a vertical transistor array, such as might be used in a memory or other integrated circuit.Embodiments of the present invention also include a vertical transistor array that is independent of the fabrication method.

[0023] refer to Figures 1 to 6 A portion of a first example array 10 of vertical transistors 25 is shown and described. This shows a construction 8 including a base substrate 11 that may include any one or more of conductive, semiconductive, and insulating (i.e., electrically insulating herein) materials. The various materials are located above the base substrate 11. The materials may be located Figures 1 to 6 11. For example, other partially fabricated or fully fabricated components of the integrated circuit may be located somewhere above, around, or within base substrate 11. Control and / or other peripheral circuitry for operating components within the transistor array may also be fabricated, and may or may not be entirely or partially within the array or sub-array. Additionally, multiple sub-arrays may be fabricated and operated independently of one another, sequentially, or in other ways. As used herein, a "sub-array" may also be considered an array.

[0024] Array 10 includes spaced-apart pillars 12 of individual vertical transistors 25. Pillars 12 individually include upper source / drain regions 14, lower source / drain regions 18, and channel regions 16 vertically therebetween. Upper source / drain regions 14 include conductive oxide material 20 ( Figure 5 and 6). Channel region 16 includes oxide semiconductor material 22 in each pillar 12. Lower source / drain region 18 includes first conductive oxide material 24 in each pillar 12, located atop and directly adjacent to second conductive oxide material 26 in each pillar 12. As used herein, each of the two-word phrases "conductor oxide" and "conductive oxide" encompasses oxides that are degenerate semiconductors as well as oxides that are more conductive than degenerate semiconductors. In one embodiment, first conductive oxide material 24 in each pillar 12 is thicker than second conductive oxide material 26 in each pillar 12.

[0025] Array 10 includes horizontally elongated and spaced apart conductor lines 32 (e.g., digit lines) that individually interconnect a corresponding plurality (e.g., a column) of vertical transistors 25 in a column direction 75. Conductor lines 32 each include a second conductive oxide material 26 located atop and directly abutting a metal material 34. The second conductive oxide material 26 of conductor line 32 is located below and directly abutting the second conductive oxide material 26 of the lower source / drain regions 18 of the respective pillars 12 of the corresponding plurality of vertical transistors 25. In one embodiment, the second conductive oxide material 26 of conductor line 32 and the second conductive oxide material 26 of the lower source / drain regions 18 of the respective pillars 12 have the same thickness relative to each other. In one embodiment, the metal material 34 in conductor line 32 is thicker than the second conductive oxide material 26 in conductor line 32. Regardless, the first conductive oxide material 24, the second conductive oxide material 26, and the metal material 34 comprise different compositions relative to each other. In one embodiment, the metal material 34 comprises at least one of an elemental metal, an alloy of an elemental metal, or a conductive metal nitride. In one embodiment, the metallic material 34 is free of any conductive oxide that is detectable (by any present or future developed means).

[0026] In one embodiment, the conductive oxide material 20 of the upper source / drain region 14 includes a first conductive oxide material 28 positioned above and directly adjacent to a second conductive oxide material 30, wherein the first and second conductive oxide materials comprise different compositions relative to one another. In one embodiment, the first conductive oxide material 28 and the second conductive oxide material 26 have the same composition relative to one another. In one embodiment, the second conductive oxide material 30 and the first conductive oxide material 24 have the same composition relative to one another.

[0027] Example conductive oxide materials and example conductor oxide materials are one or more of (stoichiometric or non-stoichiometric) indium tin oxide, indium oxide, tin oxide, zinc oxide, titanium oxide, and ruthenium oxide. Example oxide semiconductor materials 22 of the channel region 16 are one or more of: zinc tin oxide (ZnO), x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium oxide (In x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In x W y O, commonly referred to as "IWO"), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxide nitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x InyZnzO), aluminum oxide, tin indium zinc (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium oxide zinc tin (Zr x Zn y Sn z O) and other similar materials. A chemical formula containing at least one of "x", "y", "z" and "a" (e.g. Znx Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O、Al x Sn y In z Zn a In one embodiment, the channel material 22 is a composite material having an average ratio of "x" atoms of one element, "y" atoms of another element (if present), "z" atoms of an additional element (if present), and "a" atoms of yet another element (if present) for each atom of oxygen (O) in one or more regions thereof. Since the chemical formula represents relative atomic ratios and a loose chemical structure, the channel material 22 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x," "y," "z," and "a" may be integers or non-integers. As used herein, the term "non-stoichiometric" means and includes chemical compounds having an elemental composition that cannot be represented by a ratio of well-defined natural numbers and violates the law of definite proportions.

[0028] Horizontally elongated and spaced apart conductive gate lines 36 are individually operatively positioned adjacent to the oxide semiconductor material 20 of the channel region 16 of each pillar 12 and individually interconnect a corresponding plurality (e.g., a row) of vertical transistors 25 in a row direction 85. Gate lines 36 may individually extend along only one side of the channel region 16 (not shown), along both sides of the channel region 16 (as shown), or surround the gate channel region 16 (not shown). Example conductive materials for gate lines 36 include metallic materials (same as or different from metallic material 34) and / or conductively doped semiconductor materials. A gate insulator 38 is positioned between gate lines 36 and the oxide semiconductor material 22 of the channel region 16 of each pillar 12. This may include any existing or future developed gate insulator material, including, for example, reversibly programmable materials such as ferroelectrics. Insulating materials 58 and 60 (e.g., silicon nitride and / or silicon dioxide) are laterally positioned between pillars 12 and gate lines 36.

[0029] The conductive structures 40 are laterally located between and spaced apart from immediately adjacent spaced apart conductor lines 32 in the row direction 85. The conductive structures 40 individually include a top surface 42 that is higher than the top surface 35 of the metal material 34 of the conductor lines 32. In one embodiment and as shown, the conductive structures 40 are conductive lines 46 that extend horizontally along the immediately adjacent conductor lines 32 in the column direction 75. In one embodiment and as shown, the conductive structures 40 are directly electrically coupled to a common conductor 44 (e.g., a continuous blanket plate 44 within the array 10) spaced below the conductor lines 32. An insulator material 53 (e.g., silicon nitride and / or silicon dioxide) is vertically located between the conductor lines 32 and the common conductor 44. The insulator material 54 (e.g., silicon nitride and / or silicon dioxide) is laterally located between the conductor lines 32 and the conductive structures 40. In an ideal embodiment, in operation, the conductive structure 40 is connected to a suitable potential (eg, via the plate 44) to act as a parasitic capacitance buffer between immediately adjacent conductor lines 32, ideally canceling the parasitic capacitance therebetween.

[0030] Vertical transistor 25 may comprise an individual memory cell of a memory array. For example, additional programmable structures (not shown) may be provided as part of pillar 12 of vertical transistor 25. Alternatively and / or in addition, gate insulator 38 may be programmable to provide different set threshold voltage states of transistor 25 during operation, such as ferroelectric. Alternatively and / or in addition, and as shown, multiple memory elements 50 may be individually directly electrically coupled to individual upper source / drain regions 14 of individual pillars 12. Example memory elements 50 are schematically shown as being individually capacitors, which may be volatile or non-volatile, for example, between two capacitive states. Any alternative existing or future developed memory element may be used.

[0031] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0032] Figures 1 to 6 The depicted embodiment shows the conductive structure 40 as including (eg, being) a conductive line 46. Alternative configurations are contemplated, such as those described with reference to Figure 7 The configuration 8a shown and described (compared to Figure 3 ). Like reference numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "a" or by different reference numerals. Example conductive structure 40a includes conductive posts 57 spaced relative to one another along immediately adjacent conductor lines 32 in / along column direction 75. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used. Figures 1 to 6 Compared with the embodiment Figure 7The embodiment is preferred because Figures 1 to 6 The embodiment of is better at reducing the electric field and thus the parasitic capacitance between diagonally adjacent conductor lines 32 .

[0033] about Figure 8 The alternative embodiment in FIG. 8 shows an alternative example conductive structure 40b of the structure 8b (compared to Figure 3 and 7 ). The same reference numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "b" or by different reference numerals. Conductive structure 40b includes both conductive lines 46b and spaced-apart conductive posts 57b, where the spaced-apart conductive posts 57b protrude upwardly from the conductive material 55 of conductive lines 46b. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0034] refer to Figures 9 to 12 An alternative example embodiment construction 8c is shown and described. Like reference numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "c" or by different reference numerals. The example lower source / drain region 18 in an individual pillar 12c includes a first conductive oxide material 24, and the conductor line 32c includes a second conductive oxide material 26 located below and directly against the first conductive oxide material 24 of a corresponding plurality of vertical transistors (e.g., vertical transistors in a column along the column direction 75). In one embodiment, the second conductive oxide material 26 of the conductor line 32c is thicker than the first conductive oxide material 24 in the individual pillar 12c. In one embodiment, the metal material 34 of the conductor line 32c is thicker than the second conductive oxide material 26 of the conductor line 32c. In one embodiment, the top surface 42 of the conductive structure 40 is substantially aligned with the bottom surface 59 ( 50 ) of the first conductive oxide material 24 of the lower source / drain region 18c of the individual pillar 12c. Figure 10 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] Figures 13 to 16An alternative embodiment construction 8d is shown. Like reference numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "d" or by different reference numerals. Individual pillars 12d include an upper source / drain region 14 above the channel region 16. Conductor lines 32d individually include a first conductive oxide material 24 atop and directly against a second conductive oxide material 26, wherein the second conductive oxide material 26 in conductor line 32d is atop and directly against a metal material 34 in conductor line 32d. In one embodiment, the second conductive oxide material 26 in conductor line 32d is thicker than the first conductive oxide material 24 in conductor line 32d. In one embodiment, a top surface 42 of the conductive structure 40 is aligned with a bottom surface 61 ( 1 ) of the oxide semiconductor material 22 of the channel region 16 in an individual pillar 12. Figure 14 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] Embodiments of the present invention encompass methods for forming a vertical transistor array. Figures 17 to 35 Describe an example of this method to get Figures 1 to 6 The embodiment of the present invention has been constructed. The same reference numerals from the above embodiments have been used for predecessor structures, regions, and their similar / predecessor materials. Any attributes or aspects shown and / or described herein with respect to the structural embodiments may be used in the method embodiments. Similarly, any attributes or aspects shown and / or described herein with respect to the method embodiments may be used in the structural embodiments.

[0037] refer to Figures 17 to 19 , laterally spaced and horizontally elongated line structures 62 have been formed in the column direction 75. Line structures 62 include insulator material 53, metal material 34 thereover, and transistor material (e.g., 26 / 24 / 22 / 20) above metal material 34. The transistor material includes upper source / drain regions 14 above channel regions 16 of what will be individual vertical transistors (not shown). The transistor material includes at least materials 22 and 20 (whether or not 20 includes both 28 and 30) and may not include 26 and 24, e.g., depending on which of the fabrication configuration embodiments 10 / 10a / 10b, 10c, or 10d is used. The insulator material 53 of line structures 62 is located above the conductive material and, in one embodiment as shown, directly abuts the conductive material (e.g., the conductive material of common conductor / plate 44).

[0038] refer to Figure 20 , which is shown by Figure 19 Processing after the illustrated processing. Insulating material 54 has been formed (eg, as a conformal layer) as part of construction 8. Figure 21Subsequent processing is shown whereby insulator material 54 has been anisotropically etched (eg, in a maskless, spacer-like formation at least within array 10) to substantially remove insulator material 54 from above horizontal surfaces. Figure 20 and 21 Only one example method of forming insulator material 54 on the lateral sides of insulator material 53, metal material 34, and transistor material is shown. Any alternative existing or future developed technique may be used.

[0039] refer to Figure 22 , conductive material 55 has been formed in the spaces between and atop the wire formations 62 that are laterally between laterally adjacent insulator materials 54 . Figure 23 The conductive material 55 is shown etched back to form horizontally elongated conductive lines 46 directly against the conductive material 44 between laterally adjacent line structures 62 in the column direction 75. Conductive lines 46 individually include a top surface 42 that is above the top surface 35 of the metal material 34 and at or below the bottom 61 of the material 22 that will comprise the channel region. This is merely one example way to form conductive lines 46 that are individually self-aligned in the row direction 85 in one embodiment. Figures 24 to 26 The subsequent formation of insulating material 58 over conductive lines 46 is shown, followed by planarization of the insulating material 58 back to at least the top surface of line formation 62 .

[0040] refer to Figures 27 to 31 , and after forming conductive lines 46, example transistor material 28 / 30 / 22 / 24 / 26 has been cut (e.g., by etching using a photolithographic or other mask) to form spaced-apart pillars 12 that individually include upper source / drain regions 14 and channel regions 16 of individual vertical transistors. In one embodiment and as shown, such cutting has also formed pillars 12 that individually include lower source / drain regions 18. More than one etch chemistry may be used or required to etch example transistor material 28 / 30 / 22 / 24 / 26, may stop on conductive material 55, may etch into conductive material 55, and / or be performed as a timed etch in the final stage of such cutting to produce example configurations.

[0041] Figures 32 to 35Example subsequent processing is shown in which horizontally elongated conductive gate lines 36 have been operatively formed alongside the channel regions 16 of individual pillars 12 and interconnect a corresponding plurality (e.g., a row) of vertical transistors 25 in a row direction 85. Insulator material 60 can be deposited and etched back as shown to provide a surface against which gate insulator 38 and the conductive material of gate lines 36 can be deposited vertically self-aligned relative to the upper surface of material 60, followed ultimately by deposition of insulating material 58 atop and alongside material 60, as shown. Subsequent processing can be performed to produce the following as desired: Figures 1 to 6 , such as to form memory element 50 .

[0042] In one embodiment, conductive wires 46 / 46b remain in the finished configuration of the array, such as to produce configurations 8 or 8b as shown and described above. Alternatively, and by way of example only, conductive wires 46 may be cut so that they do not remain in the finished configuration of the array, such as to produce configuration 8a as shown and described above to form spaced apart conductive posts 57.

[0043] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0044] The above processing or construction can be viewed with respect to an array of components formed as or within a single stack or stack of such components, the stack or stack being above or as part of an underlying base substrate (although a single stack or stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the completed construction, and in some embodiments may be located below the array (e.g., below-array CMOS). Regardless, one or more additional such stacks or stacks may be provided or fabricated above and / or below the stacks or stacks shown in the figures or described above. Furthermore, the array of components in different stacks or stacks may be the same or different relative to each other, and different stacks or stacks may have the same thickness or different thickness relative to each other. Intervening structures may be disposed between vertically adjacent stacks or stacks (e.g., additional circuitry and / or dielectric layers). Furthermore, different stacks or stacks may be electrically coupled relative to each other. Multiple stacks or stacks may be fabricated separately and sequentially (e.g., one on top of another), or two or more stacks or stacks may be fabricated substantially simultaneously.

[0045] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0046] As used herein, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "above," "bottom," "above," "below," "down," "under," "upward," and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and relative to the substrate being processed during fabrication, and vertical is a direction generally perpendicular thereto. Reference to "exactly horizontal" is to a direction along the main substrate surface (i.e., not forming degrees with the main substrate surface) and relative to the substrate being processed during fabrication. Additionally, "vertical" and "horizontal," as used herein, are generally perpendicular directions relative to one another and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "vertically extending" refer to a direction that is tilted at least 45° from exactly horizontal. Additionally, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like with respect to a field effect transistor are references to the orientation of the transistor's channel length along which current flows between the source / drain regions during operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like are referenced to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within 10° of vertical.

[0047] Additionally, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Furthermore, use of "above" without preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outboard of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, use of "below" and "beneath" without preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inboard of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0048] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous on any overlying material. When one or more example components are provided for any material, the material may comprise, consist essentially of, or consist of such one or more components. Additionally, unless otherwise stated, each material may be formed using any suitable current or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0049] In addition, "thickness" alone (without a directional adjective in front) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of an adjacent material or region of different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If having a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such a material or region will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different components" only require that those parts of the two stated materials or regions that can directly abut each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions do not directly abut each other, then when such materials or regions are not uniform, "different components" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. Herein, a material, region or structure is "directly against" another material, region or structure when the stated materials, regions or structures are in at least some physical touching contact with each other. In contrast, “over,” “located on,” “adjacent to,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical touching contact with each other.

[0050] As used herein, regions, materials, and components are "electrically coupled" relative to one another if, during normal operation, electrical current can continuously flow from one region, material, and component to another region, material, and component, and flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be located between the region, material, and components and electrically coupled to the region, material, and component. In contrast, when the region, material, and components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region, material, and components.

[0051] Any use of "row" and "column" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. Additionally, rows and columns can intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0052] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductive-doped semiconductive / semiconductive / semiconductive materials. "Metallic material" refers to any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0053] As used herein, any use of "selective" with respect to etching, etching, removing, removal, depositing, forming, and / or forming refers to the action of one stated material at a rate of at least 2:1 by volume relative to another stated material being acted upon. Additionally, any use of selectively depositing, selectively growing, or selectively forming refers to the deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms at a rate of at least 2:1 by volume.

[0054] As used herein, "self-aligned" or "self-aligning" means a technique whereby at least one pair of opposing edges of a structure is formed by a pair of previously defined edges, thereby eliminating the need for subsequent photolithographic processing with respect to those opposing edges. As used herein, "vertically self-aligned" means a technique whereby the length and position of some or all of a vertically extending feature is formed by a previously defined underlying surface.

[0055] Unless otherwise indicated, the use of "or" herein includes either or both.

[0056] in conclusion

[0057] In some embodiments, a vertical transistor array includes spaced-apart pillars of individual vertical transistors, each of the spaced-apart pillars comprising an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region. The upper source / drain region comprises a conductive oxide material in individual ones of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source / drain region comprises a first conductive oxide material located atop and directly abutting a second conductive oxide material in the individual pillars. Horizontally extending and spaced-apart conductor lines individually interconnect corresponding ones of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material located atop and directly abutting a metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative to one another. The second conductive oxide material of the conductor line is located below and directly abuts the second conductive oxide material of the lower source / drain region of the individual pillars of the corresponding plurality of vertical transistors. Horizontally elongated and spaced-apart conductive gate lines are individually operatively located adjacent to the oxide semiconductor material of the channel region of the individual pillars and individually interconnect the corresponding plurality of vertical transistors in a row direction. A conductive structure is laterally located between and spaced apart from immediately adjacent ones of the spaced-apart conductor lines in the row direction. The conductive structure individually includes a top surface that is higher than a top surface of the metal material of the conductor line.

[0058] In some embodiments, a vertical transistor array includes individual, spaced-apart pillars, each of which includes an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region. The upper source / drain region includes a conductive oxide material in individual ones of the pillars. The channel region includes an oxide semiconductor material in the individual pillars. The lower source / drain region includes a first conductive oxide material in the individual pillars. Horizontally elongated, spaced-apart conductor lines individually interconnect corresponding ones of the vertical transistors in a column direction. The conductor lines individually include a second conductive oxide material located atop and directly abutting a metal material. The first conductive oxide material, the second conductive oxide material, and the metal material include different compositions relative to one another. The second conductive oxide material of the conductor lines is located below and directly abutting the first conductive oxide material in the lower source / drain region of the individual pillars of the corresponding plurality of vertical transistors. Horizontally elongated and spaced apart conductive gate lines are individually operatively positioned adjacent to the oxide semiconductor material of the channel regions of the respective pillars and individually interconnect the respective plurality of vertical transistors in a row direction. Conductive structures are laterally positioned between and spaced apart from immediately adjacent ones of the spaced apart conductor lines in the row direction. The conductive structures individually include a top surface that is higher than a top surface of the metal material of the conductor lines.

[0059] In some embodiments, a vertical transistor array includes spaced-apart pillars of individual vertical transistors, each of the spaced-apart pillars including an upper source / drain region above a channel region. The upper source / drain region includes a conductive oxide material in individual ones of the pillars. The channel region includes an oxide semiconductor material in the individual ones of the pillars. Horizontally elongated and spaced-apart conductor lines interconnect corresponding ones of the vertical transistors in a column direction. The conductor lines each include a first conductive oxide material, a second conductive oxide material, and a metal material. The first conductive oxide material, the second conductive oxide material, and the metal material include different compositions relative to one another. The first conductive oxide material in the conductor line is located atop and directly abuts the second conductive oxide material in the conductor line. The second conductive oxide material in the conductor line is located atop and directly abuts the metal material in the conductor line. The first conductive oxide material in the conductor line is located below and directly abuts the oxide semiconductor material in the channel region of the individual pillars of the corresponding plurality of vertical transistors. Horizontally elongated and spaced apart conductive gate lines are individually operatively positioned adjacent to the oxide semiconductor material of the channel regions of the respective pillars and individually interconnect the respective plurality of vertical transistors in a row direction. Conductive structures are laterally positioned between and spaced apart from immediately adjacent ones of the spaced apart conductor lines in the row direction. The conductive structures individually include a top surface that is higher than a top surface of the metal material of the conductor lines.

[0060] In some embodiments, a method for forming a vertical transistor array includes forming laterally spaced and horizontally extended line structures in a column direction. The line structures include an insulator material, a metal material above the insulator material, a transistor material above the metal material, and insulating material on the lateral sides of the insulator material, the metal material, and the transistor material. The transistor material includes an upper source / drain region above the channel region that will be the object of an individual vertical transistor. The insulator material of the line structure is located above a conductive material. Horizontally extended conductive lines are formed in the column direction, located between laterally adjacent line structures in the line structure and directly against the conductive material. The conductive lines individually include a top surface that is higher than the top surface of the metal material and located at or below the bottom of the channel region. After forming the conductive lines, the transistor material is cut to form spaced-apart pillars, each of which includes the upper source / drain region and the channel region of the individual vertical transistor. A horizontally elongated conductive gate line is formed operatively positioned beside the channel region of individual ones of the pillars, the horizontally elongated conductive gate line interconnecting a corresponding plurality of the vertical transistors in a row direction.

[0061] As specified, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A vertical transistor array comprising: spaced-apart columns of individual vertical transistors; The spaced-apart pillars individually include an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region; the upper source / drain region includes a conductive oxide material in individual ones of the pillars, the channel region includes an oxide semiconductor material in the individual pillars, and the lower source / drain region includes a first conductive oxide material in the individual pillar located atop and directly against a second conductive oxide material in the individual pillars; horizontally elongated and spaced apart conductor lines individually interconnecting corresponding ones of the vertical transistors in a column direction, the conductor lines individually comprising the second conductive oxide material atop and directly abutting a metal material; the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative to one another; the second conductive oxide material of the conductor lines being located below and directly abutting the second conductive oxide material of the lower source / drain regions of the respective pillars of the corresponding plurality of vertical transistors; horizontally elongated and spaced apart conductive gate lines, each operatively located adjacent to the oxide semiconductor material of the channel region of each pillar and interconnecting a corresponding plurality of the vertical transistors in a row direction; as well as Conductive structures are laterally located between and spaced apart from immediately adjacent ones of the spaced apart conductor lines in the row direction, the conductive structures individually comprising a top surface that is higher than a top surface of the metallic material of the conductor lines. 2 . The array of claim 1 , wherein the conductive structure in operation acts as a parasitic capacitance buffer between the immediately adjacent conductor lines.

3. The array of claim 1, wherein the conductive structures are electrically coupled directly to a common conductor spaced beneath the conductor lines.

4. The array of claim 1, wherein the first conductive oxide material in the individual pillars is thicker than the second conductive oxide material in the individual pillars.

5. The array of claim 1, wherein the second conductive oxide material of the conductor lines and the second conductive oxide material of the lower source / drain regions of the individual pillars have the same thickness relative to each other.

6. The array of claim 1, wherein the metal material in the conductor lines is thicker than the second conductive oxide material in the conductor lines.

7. The array of claim 1, wherein the metallic material comprises at least one of an elemental metal, an alloy of an elemental metal, or a conductive metal nitride.

8. The array of claim 1, wherein the metallic material is free of any detectable conductive oxide.

9. The array of claim 1, wherein the conductive structure is a conductive line extending horizontally along the immediately adjacent conductor lines in the column direction.

10. The array of claim 1, wherein the conductive structures are conductive pillars spaced relative to each other along the immediately adjacent conductor lines in the column direction.

11. The array of claim 1 , wherein the oxide semiconductor material comprises one or more of: Zn x Sn y O、In x Zn y O, Zn x O、In x Ga y Zn z O、In x Ga y Si z O a 、In x W y O、In x O, Sn x O、Ti x O, Zn x ON z Mg x Zn y O, Zr x In y Zn z O、Hf x In y Zn z O, Sn x In y Zn z O、Al x Sn y In z Zn a O、Si x In y Zn z O、Al x Zn y Sn z O.Ga x Zn y Sn z O, Zr x Zn y Sn z O and In x Ga y Si z O.

12. The array of claim 1, wherein the first conductive oxide material and the second conductive oxide material include at least one of indium tin oxide, indium oxide, tin oxide, zinc oxide, titanium oxide, and ruthenium oxide.

13. The array of claim 1 , wherein the conductive oxide material of the upper source / drain region comprises a first conductive oxide material positioned above and directly adjacent to a second conductive oxide material, the first conductive oxide material and the second conductive oxide material comprising different compositions relative to each other.

14. The array of claim 13, wherein the first conductive oxide material and the second conductive oxide material have the same composition relative to each other.

15. The array of claim 13, wherein the second conductor oxide material and the first conductive oxide material have the same composition relative to each other.

16. The array of claim 13, wherein The first conductive oxide material and the second conductive oxide material have the same composition relative to each other; and The second conductive oxide material and the first conductive oxide material have the same composition relative to each other.

17. The array of claim 13, wherein the first conductor oxide material and the second conductor oxide material comprise at least one of indium tin oxide, indium oxide, tin oxide, zinc oxide, titanium oxide, and ruthenium oxide.

18. The array of claim 1 wherein the vertical transistors comprise individual memory cells of a memory array.

19. The array of claim 1 comprising a plurality of memory elements individually electrically coupled directly to individual ones of the upper source / drain regions of the individual pillars.

20. A vertical transistor array comprising: spaced-apart columns of individual vertical transistors; The spaced-apart pillars individually include an upper source / drain region, a lower source / drain region, and a channel region vertically located between the upper source / drain region and the lower source / drain region; the upper source / drain region includes a conductive oxide material in individual ones of the pillars, the channel region includes an oxide semiconductor material in the individual pillars, and the lower source / drain region includes a first conductive oxide material in the individual pillars; horizontally elongated and spaced apart conductor lines individually interconnecting corresponding ones of the vertical transistors in a column direction, the conductor lines individually comprising a second conductive oxide material atop and directly abutting a metal material; the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative to one another; the second conductive oxide material of the conductor lines being below and directly abutting the first conductive oxide material of the lower source / drain regions of the respective pillars of the corresponding plurality of vertical transistors; horizontally elongated and spaced apart conductive gate lines, each operatively located adjacent to the oxide semiconductor material of the channel region of each pillar and interconnecting a corresponding plurality of the vertical transistors in a row direction; as well as Conductive structures are laterally located between and spaced apart from immediately adjacent ones of the spaced apart conductor lines in the row direction, the conductive structures individually comprising a top surface that is higher than a top surface of the metallic material of the conductor lines.

21. The array of claim 20, wherein the second conductive oxide material of the conductor lines is thicker than the first conductive oxide material in the individual pillars.

22. The array of claim 20, wherein the metal material of the conductor lines is thicker than the second conductive oxide material of the conductor lines.

23. The array of claim 20, wherein the top surface of the conductive structure vertically coincides with a bottom surface of the first conductive oxide material of the lower source / drain regions of the individual pillars.

24. A vertical transistor array comprising: spaced-apart columns of individual vertical transistors; The spaced-apart pillars individually include an upper source / drain region above a channel region, the upper source / drain region including a conductor oxide material in individual ones of the pillars, the channel region including an oxide semiconductor material in the individual ones of the pillars; horizontally elongated and spaced apart conductor lines that individually interconnect corresponding ones of the vertical transistors in a column direction; the conductor lines individually comprising a first conductive oxide material, a second conductive oxide material, and a metal material; the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative to one another; the first conductive oxide material in the conductor line being located atop and directly abutting the second conductive oxide material in the conductor line, the second conductive oxide material in the conductor line being located atop and directly abutting the metal material in the conductor line, and the first conductive oxide material in the conductor line being located below and directly abutting the oxide semiconductor material in the channel regions of the respective pillars of the corresponding plurality of vertical transistors; horizontally elongated and spaced apart conductive gate lines, each operatively located adjacent to the oxide semiconductor material of the channel region of each pillar and interconnecting a corresponding plurality of the vertical transistors in a row direction; as well as Conductive structures are laterally located between and spaced apart from immediately adjacent ones of the spaced apart conductor lines in the row direction, the conductive structures individually comprising a top surface that is higher than a top surface of the metallic material of the conductor lines.

25. The array of claim 24, wherein the second conductive oxide material in the conductor lines is thicker than the first conductive oxide material in the conductor lines.

26. The array of claim 24, wherein the top surface of the conductive structure vertically coincides with a bottom surface of the oxide semiconductor material of the channel region of the individual pillars.

27. A method for forming a vertical transistor array, comprising: forming laterally spaced-apart and horizontally elongated line structures in a column direction; the line structures comprising an insulator material, a metal material over the insulator material, a transistor material over the metal material, and insulating material on lateral sides of the insulator material, the metal material, and the transistor material; the transistor material including upper source / drain regions over channel regions that will be individual vertical transistors, the insulator material of the line structures being over a conductive material; forming horizontally elongated conductive lines between laterally adjacent ones of the line structures and directly against the conductive material in the column direction, the conductive lines individually including top surfaces that are higher than a top surface of the metal material and at or below a bottom of the channel region; After forming the conductive lines, cutting the transistor material to form spaced-apart pillars, the spaced-apart pillars individually comprising the upper source / drain regions and the channel regions of the individual vertical transistors; and A horizontally elongated conductive gate line is formed operatively positioned beside the channel region of individual ones of the pillars, the horizontally elongated conductive gate line interconnecting a corresponding plurality of the vertical transistors in a row direction.

28. The method of claim 27, wherein the conductive lines are individually formed to be self-aligned in the row direction.

29. The method of claim 27, wherein the conductive wires remain in the completed configuration of the array.

30. The method of claim 27, comprising cutting the conductive wires so that they do not remain in a completed configuration of the array.

31. The method of claim 27, comprising cutting the conductive line to form spaced apart conductive posts projecting upwardly from the conductive material.

32. The method of claim 27, comprising cutting the conductive line to form spaced apart conductive posts projecting upwardly from the conductive material of the conductive line.

33. The method of claim 27 including forming the upper source / drain region of the transistor material to include a conductor oxide material.

34. The method of claim 33, wherein the conductor oxide material of the upper source / drain region comprises a first conductor oxide material located above and directly adjacent to a second conductor oxide material, the first conductor oxide material and the second conductor oxide material comprising different compositions relative to each other.

35. The method of claim 27, comprising forming the transistor material to include a lower source / drain region below the channel region, the lower source / drain region comprising a first conductive oxide material.

36. The method of claim 35, wherein the transistor material of the lower source / drain region comprises a second conductive oxide material below and directly adjacent to the first conductive oxide material, the first conductive oxide material and the second conductive oxide material comprising different compositions relative to each other.

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