PWM Narrow Pulse Elimination Method and Single-Phase and Three-Phase PWM Narrow Pulse Elimination Devices

Abstract

The present application provides a PWM narrow pulse elimination method and single-phase and three-phase PWM narrow pulse elimination devices. The method includes: S11, obtaining carrier data; S12, processing the carrier data based on a triangular wave periodic signal and the dead time of the upper power transistor and the lower power transistor to obtain the PWM data of the upper power transistor and the lower power transistor; S13, respectively determining whether there are narrow pulses with a pulse width less than the minimum pulse width in the PWM data of the upper power transistor and / or the lower power transistor according to the PWM data of the upper power transistor and the lower power transistor; S14, if so, deleting the narrow pulses or compensating the pulse width of the narrow pulses according to the position of the narrow pulses in the current working clock period of the triangular wave periodic signal. Compensate for the influence brought by eliminating the narrow pulses, reduce the influence of eliminating the narrow pulses on the control performance, reduce the control error caused by eliminating the narrow pulses, and reduce the output ripple.

Description

Technical Field

[0001] This application relates to the technical field of wind power, and in particular, to a method for eliminating PWM narrow pulses and a single-phase and three-phase PWM narrow pulse elimination device. Background Art

[0002] In the converter of a wind turbine generator, the PWM drive of power devices is directly related to energy conversion and transmission. For example, narrow pulses in the PWM signal cannot fully turn on or turn off the power transistor IGBT (Insulated Gate Bipolar Transistor) of the converter, resulting in too high a peak voltage when the IGBT turns off, and at the same time, the switching loss will also increase, directly affecting the service life and loss of power devices.

[0003] By deleting narrow pulses with a pulse width less than a set value, the influence of incomplete conduction and turn-off on power devices can be well reduced. However, while deleting narrow pulses, the accuracy and smoothness of control will be affected. Summary of the Invention

[0004] This application provides a method for eliminating PWM narrow pulses and a single-phase and three-phase PWM narrow pulse elimination device.

[0005] Specifically, this application is implemented through the following technical solutions:

[0006] In the first aspect of the embodiments of this application, a method for eliminating PWM narrow pulses is provided, which is used to control an upper power transistor and a lower power transistor. The method includes: obtaining carrier data; processing the carrier data based on a triangular wave period signal and the dead time of the upper power transistor and the lower power transistor to obtain PWM data of the upper power transistor and the lower power transistor; according to the PWM data of the upper power transistor and the lower power transistor, respectively determining whether there are narrow pulses with a pulse width less than a minimum pulse width in the PWM data of the upper power transistor and / or the lower power transistor; if so, deleting the narrow pulses or compensating the pulse width of the narrow pulses according to the position of the narrow pulses in the current working clock period of the triangular wave period signal.

[0007] In the second aspect of the embodiments of this application, a single-phase PWM narrow pulse elimination device is provided, including one or more processors for implementing the PWM narrow pulse elimination method described in the first aspect.

[0008] In the third aspect of the embodiments of the present application, a three-phase PWM narrow pulse elimination device is provided, which is applied to a converter of a wind turbine generator. The converter includes an upper power transistor and a lower power transistor of phase A, an upper power transistor and a lower power transistor of phase B, and an upper power transistor and a lower power transistor of phase C. The three-phase PWM narrow pulse elimination device includes a PWM narrow pulse elimination device of phase A, a PWM narrow pulse elimination device of phase B, and a PWM narrow pulse elimination device of phase C. Among them, the PWM narrow pulse elimination device of phase A, the PWM narrow pulse elimination device of phase B, and the PWM narrow pulse elimination device of phase C include the single-phase PWM narrow pulse elimination device described in the second aspect.

[0009] According to the technical solution provided by the embodiments of the present application, in combination with the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated, so as to achieve the purpose of eliminating the narrow pulse, reduce the loss of the power transistor, extend the service life of the power transistor, and can well ensure the operation of the power transistor; at the same time, the influence brought by eliminating the narrow pulse is compensated, while ensuring the utilization rate of the DC bus voltage and the linear adjustment range, reducing the influence of eliminating the narrow pulse on the control performance, reducing the control error brought by eliminating the narrow pulse, and reducing the output ripple.

[0010] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0012] Figure 1 is a schematic flowchart of a PWM narrow pulse elimination method shown in an exemplary embodiment of the present application;

[0013] Figure 2 is a waveform schematic diagram of the PWM data of the upper power transistor and the lower power transistor generated in an exemplary embodiment of the present application;

[0014] Figure 3 is a waveform detail diagram of the PWM data of the upper power transistor and the lower power transistor generated in an exemplary embodiment of the present application;

[0015] Figure 4 is a PWM waveform diagram of the upper and lower power transistors in a situation without narrow pulses shown in an exemplary embodiment of the present application;

[0016] Figure 5A diagram showing a conduction narrow pulse and narrow pulse compensation in the first half cycle of the PWM data of an upper power transistor during the current working time period T2, as shown in an exemplary embodiment of the present application;

[0017] Figure 6 A diagram showing a conduction narrow pulse and narrow pulse compensation in the second half cycle of the PWM data of an upper power transistor during the current working time period T2, as shown in an exemplary embodiment of the present application;

[0018] Figure 7 A diagram showing a narrow pulse and narrow pulse deletion in the second half cycle of the PWM data of an upper power transistor during the current working time period T2, as shown in an exemplary embodiment of the present application;

[0019] Figure 8 A diagram showing a turn-off narrow pulse and narrow pulse deletion (narrow pulse following deletion of the lower power transistor) in the middle of the current working time period T2 of the PWM data of an upper power transistor, as shown in an exemplary embodiment of the present application;

[0020] Figure 9 A diagram showing a narrow pulse and narrow pulse compensation in the first half cycle of the PWM data of a lower power transistor during the current working time period T2, as shown in an exemplary embodiment of the present application;

[0021] Figure 10 A diagram showing a narrow pulse and narrow pulse deletion (narrow pulse following deletion of the upper power transistor) in the second half cycle of the PWM data of a lower power transistor during the current working time period T2, as shown in an exemplary embodiment of the present application;

[0022] Figure 11 A diagram showing a turn-off narrow pulse and narrow pulse deletion in the middle of the current working time period T2 of the PWM data of a lower power transistor, as shown in an exemplary embodiment of the present application;

[0023] Figure 12 A schematic structural diagram of a PWM narrow pulse elimination device, as shown in an exemplary embodiment of the present application. Detailed implementation manners

[0024] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0025] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0026] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".

[0027] The PWM narrow pulse elimination method of this application and the single-phase and three-phase PWM narrow pulse elimination devices will be described in detail below with reference to the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners may be combined with each other.

[0028] It should be noted that the PWM narrow pulse elimination method of the embodiments of this application can be used to control the upper power tube and the lower power tube, such as controlling the upper power tube and the lower power tube of the same bridge arm in the converter of a wind turbine generator.

[0029] Figure 1 is a schematic flowchart of a PWM narrow pulse elimination method shown in an exemplary embodiment of this application; as Figure 1 shown, the embodiments of this application provide a PWM narrow pulse elimination method that may include steps S11 to S16.

[0030] Among them, in S11, carrier data is acquired.

[0031] In S12, based on the triangular wave period signal and the dead time of the upper power tube and the lower power tube, the carrier data is processed to obtain the PWM data of the upper power tube and the lower power tube.

[0032] In this step, the carrier data can be modulated by the triangular wave period signal to generate the PWM data of the upper power tube and the lower power tube, and then the dead time is added to the PWM data to obtain the PWM data after adding the dead time, so as to ensure the normal dead time of the upper power tube and the lower power tube and prevent the upper power tube and the lower power tube of the same bridge arm from conducting simultaneously to form a short circuit.

[0033] A triangular wave signal can be generated based on a synchronization signal. The generation process of the triangular wave periodic signal can include: when the rising edge of the synchronization signal arrives, the counter is set to 1, and then the counter increments by 1 for each working clock. When the count reaches half of the period value of the working clock period, the counter starts to decrement until it reaches 1 and stops decrementing and waits for the synchronization signal to start the next cycle of counting. If the synchronization signal arrives before the counter decrements to 1, the counter is directly set to 1 and the next cycle of counting starts. Among them, the rising count of the counter is recorded as the first half cycle, and the falling count is recorded as the second half cycle, and high and low levels are used to represent them. For example, low level 0 represents the first half cycle, and high level 1 represents the second half cycle. A working clock period consists of the first half cycle and the second half cycle. The real-time count value of the triangular wave periodic signal increases in the first half cycle and decreases in the second half cycle. In the following text, the working clock period of the triangular wave periodic signal can be represented by MOD_PERIOD.

[0034] The clock frequency corresponding to the working clock period can be 50 MHZ, but it is not limited to 50 MHZ, and other clock frequencies can also be used.

[0035] In a feasible embodiment, the following registers are used to store and represent relevant data. sin_data_reg is used to represent carrier data, sin_data_calc_up is used to represent the comparison register value of the upper power transistor in the first half cycle (i.e., the PWM data of the upper power transistor in the first half cycle), sin_data_calc_down is used to represent the comparison register value of the lower power transistor in the first half cycle (i.e., the PWM data of the lower power transistor in the first half cycle), sin_data_calc_up_sec is used to represent the comparison register value of the upper power transistor in the second half cycle (i.e., the PWM data of the upper power transistor in the second half cycle), sin_data_calc_down_sec is used to represent the comparison register value of the lower power transistor in the second half cycle (i.e., the PWM data of the lower power transistor in the second half cycle), and IGBT_DT is used to represent the dead time (i.e., the dead zone width).

[0036] In this step, sin_data_calc_up = sin_data_reg;

[0037] sin_data_calc_down = sin_data_reg + IGBT_DT;

[0038] sin_data_calc_up_sec = sin_data_reg - IGBT_DT;

[0039] sin_data_calc_down_sec = sin_data_reg.

[0040] In a specific embodiment, the PWM data generation method may include the following steps:

[0041] (1) Receive an external synchronization signal.

[0042] (2) Based on the external synchronization signal in (1), output a synchronization signal according to the working clock cycle of the PWM signal generation.

[0043] (3) Generate a half-cycle signal of the triangular wave and a real-time count value tb_ctr_reg of the triangular wave based on the synchronization signal output in step (2).

[0044] (4) Process the carrier data based on the working clock cycle, the dead time of the upper power transistor and the lower power transistor, and the half-cycle signal output in (3) to obtain the processed carrier data, as Figure 2 shown.

[0045] Specifically, adjust the carrier data based on the working clock cycle and the dead time to obtain the adjusted carrier data; add the dead time to the adjusted carrier data to obtain the carrier data with dead time added; and update the carrier data with dead time added based on the half-cycle signal to obtain the updated carrier data. The above-mentioned processed carrier data includes the updated carrier data.

[0046] To prevent the upper power transistor and the lower power transistor of the same bridge arm from conducting simultaneously to form a short circuit, the dead time of the upper power transistor and the lower power transistor can be controlled, and an immediate turn-off and delayed turn-on control strategy can be adopted to control the turn-on time points of the upper power transistor and the lower power transistor.

[0047] In some embodiments, refer to Figure 3, adjust the carrier data based on the working clock cycle and the dead time to obtain the adjusted carrier data. Specifically, it can include: comparing the carrier data sin_data_reg with the difference between the half-cycle value MOD_PERIOD / 2 of the triangular wave and the dead time IGBT_DT, and the dead time IGBT_DT, where the half-cycle value MOD_PERIOD / 2 of the triangular wave is half of the working clock cycle; and adjusting the carrier data based on the comparison results of the carrier data sin_data_reg with the difference (MOD_PERIOD / 2 - IGBT_DT) and the dead time IGBT_DT. When the carrier data sin_data_reg is greater than the difference between the half-cycle value MOD_PERIOD / 2 of the triangular wave and the dead time IGBT_DT, that is, sin_data_reg > (MOD_PERIOD / 2 - IGBT_DT), the carrier data sin_data_reg is re-assigned to the difference MOD_PERIOD / 2 - IGBT_DT, that is, sin_data_reg1 = (MOD_PERIOD / 2 - IGBT_DT); when the carrier data sin_data_reg is less than the dead time IGBT_DT, the carrier data sin_data_reg is re-assigned to the dead time IGBT_DT, that is, sin_data_reg1 = IGBT_DT; otherwise, the carrier data sin_data_reg is not adjusted, that is, sin_data_reg1 = sin_data_reg. Thus, it can be used to ensure the normal dead time of the upper power transistor and the lower power transistor.

[0048] The dead time is added to the adjusted carrier data to obtain the carrier data after dead time addition, which specifically includes: calculating the edge time points of the upper and lower power transistors based on the dead time IGBT_DT and the adjusted carrier data sin_data_reg1 to obtain the carrier data after dead time addition. The carrier data after dead time addition includes the upper power transistor comparison register value sin_data_calc_up in the first half cycle, the lower power transistor comparison register value sin_data_calc_down in the first half cycle, the upper power transistor comparison register value sin_data_calc_up_sec in the second half cycle, and the lower power transistor comparison register value sin_data_calc_down_sec in the second half cycle. The upper power transistor comparison register value in the first half cycle is equal to the adjusted carrier data, i.e., sin_data_calc_up = sin_data_reg1; the lower power transistor comparison register value in the first half cycle is equal to the adjusted carrier data plus the dead time, i.e., sin_data_calc_down = sin_data_reg1 + IGBT_DT; the upper power transistor comparison register value in the second half cycle is equal to the adjusted carrier data minus the dead time, i.e., sin_data_calc_up_sec = sin_data_reg1 - IGBT_DT; and the lower power transistor comparison register value in the second half cycle is equal to the adjusted carrier data, i.e., sin_data_calc_down_sec = sin_data_reg1.

[0049] Updating the carrier data after adding the dead zone based on the half - cycle signal to obtain the updated carrier data may specifically include: respectively giving the upper power transistor comparison register value in the first half - cycle, the lower power transistor comparison register value in the first half - cycle, the upper power transistor comparison register value in the second half - cycle, and the lower power transistor comparison register value in the second half - cycle at the level switching positions of the half - cycle signal to obtain the updated carrier data. The updated carrier data includes the current value of the upper power transistor comparison register sin_data_calc_up_current and the current value of the lower power transistor comparison register sin_data_calc_down_current when the half - cycle signal switches from the first level to the second level, and the current value of the upper power transistor comparison register sin_data_calc_up_current and the current value of the lower power transistor comparison register sin_data_calc_down_current when the half - cycle signal switches from the second level to the first level. Among them, the current value of the upper power transistor comparison register sin_data_calc_up_current and the current value of the lower power transistor comparison register sin_data_calc_up_current when the half - cycle signal switches from the first level to the second level are respectively equal to the upper power transistor comparison register value sin_data_calc_up and the lower power transistor comparison register value sin_data_calc_down in the first half - cycle, and the current value of the upper power transistor comparison register sin_data_calc_up_current and the current value of the lower power transistor comparison register sin_data_calc_up_current when the half - cycle signal switches from the second level to the first level are respectively equal to the upper power transistor comparison register value sin_data_calc_up_sec and the lower power transistor comparison register value sin_data_calc_down_sec in the second half - cycle.

[0050] (5) In each working clock cycle, compare the processed carrier data in (4) with the real - time count value tb_ctr_reg of the triangular wave output in (3) to generate the upper power transistor PWM data and the lower power transistor PWM data.

[0051] Specifically, in each working clock cycle, the current value sin_data_calc_up_current of the upper power transistor comparison register and the current value sin_data_calc_down_current of the lower power transistor comparison register are respectively compared with the real-time triangular wave count value tb_ctr_reg; and based on the comparison results of the current value sin_data_calc_up_current of the upper power transistor comparison register and the current value sin_data_calc_down_current of the lower power transistor comparison register with the real-time triangular wave count value tb_ctr_reg, the PWM signals of the upper power transistor and the lower power transistor are generated. For example, if the current value sin_data_calc_up_current of the upper power transistor comparison register is less than the real-time triangular wave count value tb_ctr_reg, the upper power transistor outputs a low level; otherwise, the upper power transistor outputs a high level. If the current value sin_data_calc_down_current of the lower power transistor comparison register is greater than the real-time triangular wave count value tb_ct r_reg, the lower power transistor outputs a low level; otherwise, the lower power transistor outputs a high level.

[0052] In S13, according to the PWM data of the upper power transistor and the lower power transistor, it is determined whether there are narrow pulses with a pulse width less than the minimum pulse width in the PWM data of the upper power transistor and / or the lower power transistor respectively.

[0053] The counter calculation method can be used to determine the pulse width of each pulse in the current working clock cycle of the upper power transistor and the lower power transistor respectively. The minimum narrow pulse width can be represented by MIN_PULSE. In this step, if the pulse width is less than the minimum narrow pulse width MIN_PULSE, it indicates that the corresponding pulse is a narrow pulse.

[0054] In this embodiment, the pulses include two types: conduction pulses (controlling the corresponding power transistor to conduct) and turn-off pulses (controlling the corresponding power transistor to turn off).

[0055] In S14, if there are narrow pulses, according to the position of the narrow pulses in the current working clock cycle of the triangular wave periodic signal, the narrow pulses are deleted or the pulse width of the narrow pulses is compensated.

[0056] To determine the position of the narrow pulse in the current working clock cycle, it is necessary to determine whether the narrow pulse is located at the starting moment of the first half cycle of the current working clock cycle, or at the ending moment of the second half cycle of the current working clock cycle, or in the middle of the working clock cycle (i.e., the peak region of the triangular wave periodic signal).

[0057] In addition, if there are no narrow pulses with a pulse width less than the minimum pulse width in the upper power transistor and the lower power transistor during the current working clock cycle, there is no need to perform narrow pulse cancellation processing on the PWM data of the upper power transistor and the lower power transistor in the current working cycle. As Figure 4 shown, the pulse width D1 is greater than the minimum narrow pulse width MIN_PULSE, and the pulse width D2 is also greater than the minimum narrow pulse width MIN_PULSE. Therefore, there is no need to perform narrow pulse cancellation processing on the PWM data of the upper power transistor and the lower power transistor in the current working cycle.

[0058] Figure 4 In, T1 and T2 are both one working clock cycle of the triangular wave period information, and T1 = T2 = MOD_PERIOD.

[0059] In S14, the implementation method of deleting narrow pulses or compensating the pulse width of narrow pulses according to the position of narrow pulses in the current working clock cycle of the triangular wave period signal can include various types.

[0060] Next, the elimination of narrow pulses in the PWM data of the upper power transistor and the elimination of narrow pulses in the PWM data of the lower power transistor will be introduced respectively. It should be noted that Figures 4 to 11 in, the dotted line is the PWM data before eliminating the narrow pulses in the PWM data.

[0061] 1. Eliminate narrow pulses in the PWM data of the upper power transistor.

[0062] In some embodiments, when the narrow pulse is at the starting moment of the first half cycle of the current working clock cycle, the pulse width of the narrow pulse is compensated. Specifically, when there is a narrow pulse in the PWM data of the upper power transistor at the starting moment of the first half cycle of the current working clock cycle, and the narrow pulse is a conduction pulse, the falling edge of the narrow pulse is shifted backward until the pulse width of the narrow pulse is equal to the minimum pulse width; and the rising edge of the turn-off pulse corresponding to the narrow pulse in the PWM data of the lower power transistor is shifted backward accordingly.

[0063] As Figure 5 shown, the pulse width D3 is less than the minimum narrow pulse width MIN_PULSE. Therefore, the corresponding pulse ( Figure 5The pulse of the upper power transistor opposite to the D3 position in [the figure] is a narrow pulse, and the pulse width of this narrow pulse can be compensated. The magnitude of the compensation width value is the difference between the minimum narrow pulse width MIN_PULSE and the pulse width D3, that is, the compensation width value = (MIN_PULSE - D3). Moreover, the rising edge of the turn-off pulse corresponding to this narrow pulse in the PWM data of the lower power transistor is shifted backward by the magnitude of the compensation width value (MIN_PULSE - D3) to eliminate this narrow pulse. Compared with the method of directly deleting this narrow pulse, compensating the pulse width of this narrow pulse can reduce the impact of narrow pulse elimination on the control performance, reduce the control error caused by narrow pulse elimination, and reduce the output ripple. At the same time, the rising edge of the turn-off pulse corresponding to this narrow pulse in the PWM data of the lower power transistor follows and is shifted backward, ensuring the normal dead time between the upper power transistor and the lower power transistor. In this way, the comparison register values of the upper and lower power transistors after adjustment in the first half cycle are obtained:

[0064] sin_data_calc_up = MIN_PULSE - sin_data_calc_up_current;

[0065] sin_data_calc_down = MIN_PULSE - sin_data_calc_up_current + IGBT_DT.

[0066] In some other embodiments, when the narrow pulse is at the end moment of the second half cycle of the current working clock cycle, the narrow pulse is deleted or the pulse width of the narrow pulse is compensated according to the power transistor to which the narrow pulse belongs. For the upper power transistor, that is, when there is a narrow pulse in the PWM data of the upper power transistor at the end moment of the second half cycle of the current working clock cycle and the narrow pulse is a turn-on pulse, determine the turn-on time of the turn-on pulse at the start moment of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor; according to the turn-on time, delete the narrow pulse or compensate the pulse width of the narrow pulse.

[0067] Among them, when the difference between the turn-on time and the first difference is greater than or equal to the minimum pulse width and greater than or equal to the minimum pulse width, move the rising edge of the narrow pulse forward until the width of the pulse segment of the narrow pulse in the second half cycle is equal to half of the minimum pulse width; and according to the first difference, move the falling edge of the turn-on pulse at the start moment of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor forward. Among them, the first difference is the difference between half of the minimum pulse width and the width of the pulse segment of the narrow pulse in the second half cycle. As Figure 6 shown, the width D4 of the pulse segment is less than half of the minimum narrow pulse width MIN_PULSE, that is, D4 < MIN_PULSE / 2, so the corresponding pulse ( Figure 6The pulse of the upper power transistor opposite to the D4 position (in the middle) is a narrow pulse. It is necessary to further determine the magnitude of the difference t1 between the conduction time of the conduction pulse at the start time of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor and the first difference. Figure 6 As shown, t1 is greater than or equal to the minimum narrow pulse width MIN_PULSE. Therefore, the width of the pulse segment of this narrow pulse can be compensated. The magnitude of the compensation width value is the difference between half of the minimum narrow pulse width MIN_PULSE and the width D4 of the pulse segment of this narrow pulse, that is, compensation width value = (MIN_PULSE / 2 - D4). And, move the falling edge of the conduction pulse at the start time of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor forward by the magnitude of the compensation width value (MIN_PULSE / 2 - D4) to eliminate this narrow pulse. Compared with the method of directly deleting this narrow pulse, compensating the pulse width of this narrow pulse can reduce the impact of eliminating the narrow pulse on the control performance, reduce the control error caused by eliminating the narrow pulse, and reduce the output ripple. That is, for the narrow pulse at the end time of the second half cycle of the PWM data of the upper power transistor, if the conduction time of the conduction pulse at the start time of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor is long enough, then by reducing the conduction time of the conduction pulse at the start time of the first half cycle of the current working clock cycle and adding the reduced time to the second half cycle, while the conduction time of the entire working clock cycle remains unchanged, ensure that the conduction pulse at the end time of the second half cycle is equal to half of the minimum narrow pulse width MIN_PULSE / 2.

[0068] Furthermore, according to the first difference, move the falling edge of the turn-off pulse corresponding to the position of the narrow pulse in the PWM data of the lower power transistor forward; and according to the first difference, move the rising edge of the turn-off pulse corresponding to the position of the conduction pulse at the start time of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor in the PWM data of the lower power transistor forward. That is, the corresponding turn-off pulses of the PWM data of the lower power transistor follow the compensation to ensure the normal dead time of the upper power transistor and the lower power transistor. Also see Figure 6 Move the falling edge of the turn-off pulse corresponding to the position of the narrow pulse in the PWM data of the lower power transistor forward by the magnitude of (MIN_PULSE / 2 - D4), and move the rising edge of the turn-off pulse corresponding to the position of the conduction pulse at the start time of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor in the PWM data of the lower power transistor forward by the magnitude of (MIN_PULSE / 2 - D4). The comparison register values of the upper and lower power transistors after adjustment in the first and second half cycles are:

[0069] sin_data_calc_up = sin_data_calc_up - (MIN_PULSE / 2 - sin_data_calc_up_sec);

[0070] sin_data_calc_down = sin_data_calc_up - (MIN_PULSE / 2 - sin_data_calc_up_sec) + IGBT_DT;

[0071] sin_data_calc_up_sec = MIN_PULSE / 2;

[0072] sin_data_calc_down_sec = MIN_PULSE / 2 + IGBT_DT.

[0073] When the difference between the conduction time and the first difference is less than the minimum pulse width for conduction, the narrow pulse is deleted. As Figure 7 shown, the pulse width D5 is less than half of the minimum narrow pulse width MIN_PULSE, so the corresponding pulse ( Figure 7 the pulse of the upper power transistor directly opposite to the position of D5 in it) is a narrow pulse, Figure 7 the magnitude of the conduction time t2 of the conduction pulse at the start of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor is equal to the minimum narrow pulse width MIN_PULSE. Therefore, the difference between the conduction time t2 of the conduction pulse at the start of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor and the first difference is less than the minimum narrow pulse width MIN_PULSE. So, the narrow pulse is eliminated by deleting the pulse segment of the upper power transistor directly opposite to the position of D5. Additionally, since the width D6 of the turn-off pulse segment of the lower power transistor opposite to the position of D5 is greater than (MIN_PULSE - IGBT_DT) / 2, this turn-off pulse segment does not need to be processed. The adjusted register values of the upper and lower power transistors in the second half cycle are:

[0074] sin_data_calc_up_sec = 0;

[0075] sin_data_calc_down_sec = sin_data_calc_down_sec.

[0076] In some other embodiments, when there is a narrow pulse in the middle of the current working clock cycle of the upper power transistor, the narrow pulse is deleted. As Figure 8 shown, the pulse width D7 is less than the minimum narrow pulse width MIN_PULSE, so the corresponding pulse ( Figure 8 the pulse of the upper power transistor directly opposite to the position of D7 in it) is a narrow pulse, and this narrow pulse is in the middle of the current working clock cycle. Therefore, the narrow pulse can be eliminated by deleting this narrow pulse. The adjusted comparison register values of the upper and lower power transistors in the first and second half cycles are:

[0077] sin_data_calc_up = MOD_PERIOD / 2;

[0078] sin_data_calc_down = MOD_PERIOD / 2;

[0079] sin_data_calc_up_sec = MOD_PERIOD / 2;

[0080] sin_data_calc_down_sec = MOD_PERIOD / 2.

[0081] 2. Eliminate the narrow pulses in the PWM data of the lower power transistor.

[0082] In some embodiments, when there is a narrow pulse at the starting moment of the first half cycle of the current working clock cycle in the PWM data of the lower power transistor, and the narrow pulse is an off pulse, shift the rising edge of the off pulse of the narrow pulse until the pulse width of the narrow pulse is equal to the minimum pulse width. As Figure 9 shown, the pulse width D8 is less than the minimum narrow pulse width MIN_PULSE, so the corresponding pulse ( Figure 9 the pulse of the lower power transistor directly opposite to the position of D8 in ) is a narrow pulse, and the pulse width of this narrow pulse can be compensated. The size of the compensation width value is the difference between the minimum narrow pulse width MIN_PULSE and the pulse width D8 of this narrow pulse, that is, compensation width value = (MIN_PULSE - D8), to eliminate this narrow pulse. Compared with the method of directly deleting this narrow pulse, compensating the pulse width of this narrow pulse can reduce the impact of eliminating the narrow pulse on the control performance, reduce the control error caused by narrow pulse elimination, and reduce the output ripple. The comparison register values of the upper and lower power transistors after adjustment in the first half cycle are:

[0083] sin_data_calc_up = MIN_PULSE - sin_data_calc_down_current;

[0084] sin_data_calc_down = MIN_PULSE - sin_data_calc_down_current + IGBT_DT.

[0085] In some other embodiments, when there is a narrow pulse at the end moment of the second half cycle of the current working clock cycle in the PWM data of the lower power transistor, the narrow pulse is an off pulse and the width of the narrow pulse in the pulse segment of the second half cycle is less than half of the difference between the minimum pulse width and the dead time, delete the narrow pulse. As Figure 10As shown, D9 is less than half of the difference between the minimum narrow pulse width MIN_PULSE and the dead time IGBT_DT, that is, D9 < (MIN_PULSE - IGBT_DT) / 2. Therefore, the corresponding pulse ( Figure 10 the pulse of the lower power transistor directly opposite to the position of D9 in the figure) is a narrow pulse, and this narrow pulse needs to be deleted to eliminate it. The values of the upper and lower power transistor comparison registers after adjustment in the second half cycle are:

[0086] sin_data_calc_up_sec = 0;

[0087] sin_data_calc_down_sec = 0.

[0088] In some other embodiments, when there is a narrow pulse in the middle of the PWM data of the lower power transistor in the current working clock cycle, the narrow pulse is deleted. As Figure 11 shown, the pulse width D10 is less than the minimum narrow pulse width MIN_PULSE. Therefore, the corresponding pulse ( Figure 11 the pulse of the upper power transistor directly opposite to the position of D7 in the figure) is a narrow pulse, and this narrow pulse is in the middle of the current working clock cycle. Therefore, this narrow pulse can be eliminated by deleting it. The values of the lower power transistor comparison registers after adjustment in the first half and the second half cycles are:

[0089] sin_data_calc_down = MOD_PERIOD / 2;

[0090] sin_data_calc_down_sec = MOD_PERIOD / 2.

[0091] In the above embodiments, deleting the narrow pulse means deleting the edges of the narrow pulse.

[0092] In addition, it should be noted that the method for eliminating the narrow pulse in the PWM data of the upper power transistor and the method for eliminating the narrow pulse in the PWM data of the lower power transistor in the above embodiments can be combined, and different methods for eliminating the narrow pulse in the PWM data of different upper power transistors and different methods for eliminating the narrow pulse in the PWM data of different lower power transistors can also be combined.

[0093] The PWM narrow pulse elimination method of the embodiments of the present application may further include: when the deleted narrow pulse is at the end of the second half of the current working clock cycle, deleting the pulse segment of the narrow pulse in the next working clock cycle of the current working clock cycle, reducing the impact of eliminating the narrow pulse on the control performance, reducing the control error caused by eliminating the narrow pulse, and reducing the output ripple.

[0094] The PWM narrow pulse elimination method according to the embodiment of the present application combines the position of the narrow pulse in the current working clock cycle of the triangular wave periodic signal, deletes the narrow pulse or compensates the pulse width of the narrow pulse, so as to achieve the purpose of eliminating the narrow pulse, reduce the loss of the power tube, extend the service life of the power tube, and can well ensure the operation of the power tube. At the same time, it compensates for the influence brought by eliminating the narrow pulse, reduces the influence of eliminating the narrow pulse on the control performance, reduces the control error caused by eliminating the narrow pulse, and reduces the output ripple while ensuring the utilization rate of the DC bus voltage and the linear adjustment range. After the PWM generation is optimized, the control is closer to the actual switching point to be controlled. From the actual operation test of the product, the inventor can also measure that its harmonics become smaller.

[0095] The PWM narrow pulse elimination method according to the embodiment of the present application can be implemented by an FPGA (Field Programmable Gate Array), and the protection of the power device will be very fast. Once a fault occurs, fault protection can be achieved in nanoseconds, which is faster than the original DSP (Digital Signal Processing) solution.

[0096] See Figure 12 , the embodiment of the present application also provides a single-phase PWM narrow pulse elimination device, including one or more processors for implementing the PWM narrow pulse elimination method in the above embodiment.

[0097] The embodiment of the single-phase PWM narrow pulse elimination device can be applied to the converter of a wind turbine generator set. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. Taking software implementation as an example, as a logically meaningful device, it is formed by reading the corresponding computer program instructions in the non-volatile memory into the memory and running them through the processor of the converter of the wind turbine generator set where it is located. From the hardware level, as Figure 12 shown, it is a hardware structure diagram of the converter of the wind turbine generator set where the single-phase PWM narrow pulse elimination device of the present application is located. In addition to Figure 12 the shown processor, internal bus, memory, network interface, and non-volatile memory, the converter of the wind turbine generator set where the device is located in the embodiment usually includes other hardware according to the actual function of the wind turbine converter, which will not be elaborated here.

[0098] The embodiment of the present application also provides a computer-readable storage medium, on which a program is stored. When the program is executed by a processor, it implements the PWM narrow pulse elimination method in the above embodiment.

[0099] The computer-readable storage medium may be an internal storage unit of the converter of the wind turbine generator in any of the foregoing embodiments, such as a hard disk or a memory. The computer-readable storage medium may also be an external storage device of the wind turbine generator, such as a plug-in hard disk, a Smart Media Card (SMC), an SD card, a Flash Card, etc. equipped on the device. Further, the computer-readable storage medium may also include both an internal storage unit of the converter of the wind turbine generator and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the converter of the wind turbine generator, and may also be used to temporarily store the data that has been output or will be output.

[0100] An embodiment of the present application further provides a three-phase PWM narrow pulse elimination device, which is applied to the converter of a wind turbine generator. The converter includes an upper power transistor and a lower power transistor of phase A, an upper power transistor and a lower power transistor of phase B, and an upper power transistor and a lower power transistor of phase C. The three-phase PWM narrow pulse elimination device includes a PWM narrow pulse elimination device of phase A, a PWM narrow pulse elimination device of phase B, and a PWM narrow pulse elimination device of phase C. Among them, the PWM narrow pulse elimination device of phase A, the PWM narrow pulse elimination device of phase B, and the PWM narrow pulse elimination device of phase C all include the single-phase PWM narrow pulse elimination device in the above embodiment.

[0101] That is, the PWM narrow pulse elimination devices of phase A, phase B, and phase C eliminate PWM narrow pulses in the same way.

[0102] It should be noted that the PWM narrow pulse elimination device of phase A, the PWM narrow pulse elimination device of phase B, and the PWM narrow pulse elimination device of phase C are three independent modules.

[0103] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A PWM narrow pulse elimination method for controlling an upper power transistor and a lower power transistor, characterized in that, the method includes: obtaining carrier data; processing the carrier data based on a triangular wave period signal and the dead time of the upper power transistor and the lower power transistor to obtain PWM data of the upper power transistor and the lower power transistor; respectively determining whether there are narrow pulses with a pulse width less than a minimum pulse width in the PWM data of the upper power transistor and / or the lower power transistor according to the PWM data of the upper power transistor and the lower power transistor; if so, deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock period of the triangular wave period signal; wherein, the deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock period of the triangular wave period signal includes: when the difference between the conduction time and a first difference is less than the minimum pulse width, deleting the narrow pulse, where the first difference is the difference between half of the minimum pulse width and the width of the pulse segment of the narrow pulse in the second half period of the current working clock period; the conduction time is determined according to the conduction time of the conduction pulse at the start time of the first half period of the current working clock period in the PWM data of the upper power transistor when there is the narrow pulse in the PWM data of the upper power transistor and the narrow pulse is a conduction pulse.

2. The PWM narrow pulse elimination method according to claim 1, characterized in that, the deleting the narrow pulse or compensating the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock period of the triangular wave period signal includes: when the narrow pulse is at the start time of the first half period of the current working clock period, compensating the pulse width of the narrow pulse, where the real-time count value of the triangular wave period signal increases in the first half period.

3. The PWM narrow pulse elimination method according to claim 2, characterized in that, the compensating the pulse width of the narrow pulse includes: when there is the narrow pulse in the PWM data of the upper power transistor and the narrow pulse is a conduction pulse, shifting the falling edge of the narrow pulse backward until the pulse width of the narrow pulse is equal to the minimum pulse width; and shifting the rising edge of the turn-off pulse corresponding to the narrow pulse in the PWM data of the lower power transistor backward accordingly.

4. The PWM narrow pulse elimination method according to claim 2, characterized in that, the compensating the pulse width of the narrow pulse includes: when there is the narrow pulse in the PWM data of the lower power transistor and the narrow pulse is a turn-off pulse, shifting the rising edge of the turn-off pulse of the narrow pulse backward until the pulse width of the narrow pulse is equal to the minimum pulse width.

5. The PWM narrow pulse elimination method according to claim 1, characterized in that, Deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave period signal includes: When the narrow pulse is at the end moment of the second half cycle of the current working clock cycle, deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the power transistor to which the narrow pulse belongs, where the real-time count value of the triangular wave period signal decreases in the second half cycle.

6. The PWM narrow pulse elimination method according to claim 5, characterized in that deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the power transistor to which the narrow pulse belongs includes: When there is the narrow pulse in the PWM data of the upper power transistor and the narrow pulse is a conduction pulse, determining the conduction time of the conduction pulse located at the start moment of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor; Deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the conduction time.

7. The PWM narrow pulse elimination method according to claim 6, characterized in that deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the conduction time includes: When the difference between the conduction time and the first difference is greater than or equal to the minimum pulse width, moving the rising edge of the narrow pulse forward until the width of the pulse segment of the narrow pulse in the second half cycle is equal to half of the minimum pulse width; and Moving the falling edge of the conduction pulse located at the start moment of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor forward according to the first difference.

8. The PWM narrow pulse elimination method according to claim 7, characterized in that The method further includes: Moving the falling edge of the turn-off pulse corresponding to the position of the narrow pulse in the PWM data of the lower power transistor forward according to the first difference; and Moving the rising edge of the turn-off pulse corresponding to the position of the conduction pulse located at the start moment of the first half cycle of the current working clock cycle in the PWM data of the upper power transistor in the PWM data of the lower power transistor forward according to the first difference.

9. The PWM narrow pulse elimination method according to claim 5, characterized in that deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the power transistor to which the narrow pulse belongs includes: When there is the narrow pulse in the PWM data of the lower power transistor, the narrow pulse is a turn-off pulse and the width of the pulse segment of the narrow pulse in the second half cycle is less than half of the difference between the minimum pulse width and the dead time, deleting the narrow pulse.

10. The PWM narrow pulse elimination method according to claim 1, characterized in that deleting the narrow pulse or compensating for the pulse width of the narrow pulse according to the position of the narrow pulse in the current working clock cycle of the triangular wave period signal includes: When the narrow pulse is at the middle of the current working clock cycle, delete the narrow pulse, wherein the real-time count value of the triangular wave period signal increases in the first half cycle of the current working clock cycle and decreases in the second half cycle of the current working clock cycle.

11. The PWM narrow pulse elimination method according to claim 1, wherein, the method further includes: When the deleted narrow pulse is at the end moment of the second half cycle of the current working clock cycle, delete the pulse segment of the narrow pulse in the next working clock cycle of the current working clock cycle.

12. A single-phase PWM narrow pulse elimination device, wherein, comprises one or more processors for implementing the PWM narrow pulse elimination method according to any one of claims 1-11.

13. A three-phase PWM narrow pulse elimination device applied to the converter of a wind turbine generator, the converter comprising an upper power transistor and a lower power transistor of phase A, an upper power transistor and a lower power transistor of phase B, and an upper power transistor and a lower power transistor of phase C, wherein, the three-phase PWM narrow pulse elimination device includes a phase A PWM narrow pulse elimination device, a phase B PWM narrow pulse elimination device, and a phase C PWM narrow pulse elimination device, wherein the phase A PWM narrow pulse elimination device, the phase B PWM narrow pulse elimination device, and the phase C PWM narrow pulse elimination device include the single-phase PWM narrow pulse elimination device according to claim 12.

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