A chip and vehicle-mounted system with cyclic redundancy check function

Abstract

The embodiment of the present invention provides a chip and a vehicle-mounted system with a cyclic redundancy check function. The chip includes: a first register, a second register, a serial peripheral interface SPI, and a cyclic redundancy check CRC error reporting interface; the first register is used to store a first code, wherein the first code is used to implement a display function when executed; the second register is used to store a second code, wherein the second code is used to implement a CRC function when executed; the SPI is used to periodically receive the complete code of the first code sent by the host end; and drive the first register to use the complete code to overwrite the first code stored in the first register; the CRC error reporting interface is used to send an error message to the host end when the chip detects a data error through the CRC function. The chip can realize the auto reload function and the CRC function at the same time.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a chip with a cyclic redundancy check function. Background Art

[0002] Cyclic Redundancy Check (CRC) is a channel coding technology that generates a short fixed-bit check code based on data such as network packets or computer files. The CRC function can be used in the vehicle system to detect whether the displayed vehicle instrument is abnormal.

[0003] In the related art, codes for implementing the CRC function can be burned into the chip used to display the instrument data, so that the chip can implement the CRC function by executing these codes. In the related art, the implementation of the CRC function depends on the chip communicating with the host in real time through the Serial Peripheral Interface (SPI), so the CRC function will occupy the SPI of the chip.

[0004] The chip also has codes for display functions burned in it. The codes for display functions may be damaged by electrostatic discharge (ESD) or electrical over stress (EOS). Therefore, the host will periodically, such as every minute, resend the codes for display functions to the chip through SPI so that the chip can re-burn the codes into the registers. This function is called auto reload.

[0005] If the chip enables both the auto reload function and the CRC function, as analyzed above, the CRC function will occupy the SPI, resulting in the chip being unable to normally receive the code sent by the host during auto reload, which in turn causes the auto reload to fail. Therefore, in the related art, the chip cannot enable both the auto reload function and the CRC function at the same time. Summary of the invention

[0006] The purpose of the embodiment of the present invention is to provide a chip and a vehicle-mounted system with a cyclic redundancy check function, so as to provide a chip with both a CRC function and an auto reload function. The specific technical solution is as follows:

[0007] In a first aspect of an embodiment of the present invention, a chip with a cyclic redundancy check function is provided, the chip comprising:

[0008] First register, second register, serial peripheral interface SPI, cyclic redundancy check CRC error reporting interface;

[0009] The first register is used to store a first code, wherein the first code is used to implement a display function when executed;

[0010] The second register is used to store a second code, wherein the second code is used to implement a CRC function when executed;

[0011] The SPI is used to periodically receive the complete code of the first code sent by the host; and drive the first register to overwrite the first code stored in the first register with the complete code;

[0012] The CRC error reporting interface is used to send error reporting information to the host end when the chip detects a data error through the CRC function.

[0013] In a possible embodiment, the SPI is further used to receive a predicted CRC value sent by the host end, where the predicted CRC value is calculated by the host end according to a preset CRC algorithm based on the image to be displayed;

[0014] The CRC error interface is specifically used to send an error message to the host when the chip determines that the predicted CRC value is different from the calculated CRC value. The calculated CRC value is calculated by the chip according to the preset CRC algorithm based on the image to be displayed sent by the host.

[0015] In a possible embodiment, the second register is further used to set a preset flag bit in the second register when the chip determines that the predicted CRC value is different from the calculated CRC value;

[0016] The CRC error reporting interface is specifically used to read the preset identification bit; if the preset identification bit is set, an error reporting message is sent to the host end.

[0017] In a possible embodiment, the error information is a high level signal or a low level signal.

[0018] In a possible embodiment, the first register and the second register are located in the same page of the memory of the chip;

[0019] The SPI drives the first register to overwrite the first code stored in the first register with the complete code, including:

[0020] driving the first register to overwrite the first code stored in the first register with the complete code within a preset first time window;

[0021] The CRC error reporting interface reads the preset identification bit, including:

[0022] The preset identification bit is read within a preset second time window, wherein there is no intersection between the second time window and the first time window.

[0023] In a possible embodiment, the first register and the second register are located in different pages in the memory of the chip.

[0024] In a possible embodiment, the CRC error reporting interface is a probe.

[0025] In a second aspect of an embodiment of the present invention, a vehicle-mounted system is provided, the vehicle-mounted system comprising a host end and a chip;

[0026] The chip includes a first register, a second register, a serial peripheral interface SPI, and a cyclic redundancy check CRC error reporting interface;

[0027] The first register is used to store a first code, wherein the first code is used to implement a display function when executed;

[0028] The second register is used to store a second code, wherein the second code is used to implement a CRC function when executed;

[0029] The SPI is used to periodically receive the complete code of the first code sent by the host; and drive the first register to overwrite the first code stored in the first register with the complete code;

[0030] The CRC error reporting interface is used to send error reporting information to the host end when the chip detects a data error through the CRC function.

[0031] The host end is connected to the chip through the SPI and the CRC error reporting interface, and the host end is used to periodically send the complete code to the chip through the SPI.

[0032] In a possible embodiment, the host end is further used to send a predicted CRC value to the chip through the SPI, where the predicted CRC value is calculated by the host end according to a preset CRC algorithm based on the image to be displayed;

[0033] The CRC error interface is specifically used to send an error message to the host when the chip determines that the predicted CRC value is different from the calculated CRC value. The calculated CRC value is calculated by the chip according to the preset CRC algorithm based on the image to be displayed sent by the host.

[0034] In a possible embodiment, the second register is specifically used to set a preset flag bit in the second register when the chip determines that the predicted CRC value is different from the calculated CRC value;

[0035] The host end is also used to drive the CRC error reporting interface to read the preset identification bit, so that the CRC error reporting interface sends error information to the host end when the preset identification bit is set.

[0036] Beneficial effects of the embodiments of the present invention:

[0037] The chip with a redundant check function provided by an embodiment of the present invention can store a first code for realizing a display function and a second code for realizing a CRC function in a first register and a second register, respectively. Therefore, during the autoreload process, only the first register needs to use the complete code of the first code to overwrite the first code stored in the first register, and the second register is not involved. Therefore, the chip can normally realize the CRC function by reading and writing the second register. Moreover, when the chip detects a data error through the CRC function, it no longer reports an error to the host side through the SPI, but reports an error to the host side through the CRC error reporting interface. Therefore, it will not occupy the SPI, and will not affect the realization of the auto reload function. It can be seen that the selection of this embodiment can avoid the hardware conflict between the auto reload function and the CRC function, so that the chip can realize the auto reload function and the CRC function at the same time.

[0038] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0040] Figure 1 A schematic diagram of the structure of a chip with a cyclic redundancy check function provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a first time window and a second time window provided in an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of the layout of a memory in a chip with a cyclic redundancy check function provided by an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of the structure of a vehicle-mounted system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0045] See also Figure 1 , Figure 1 The chip with cyclic redundancy check function provided by an embodiment of the present invention includes:

[0046] A first register 101 , a second register 102 , an SPI 103 , and a CRC error reporting interface 104 .

[0047] The first register 101 is used to store a first code, wherein the first code is used to implement a display function when executed.

[0048] The second register 102 is used to store a second code, wherein the second code is used to implement a CRC function when executed.

[0049] The SPI 103 is used to periodically receive the complete code of the first code sent by the host, and drive the first register to overwrite the first code of the first register with the complete code.

[0050] The CRC error reporting interface 104 is used to send error reporting information to the host when the chip detects a data error through the CRC function.

[0051] By selecting this embodiment, the first code for realizing the display function and the second code for realizing the CRC function can be stored in the first register and the second register respectively. Therefore, during the auto reload process, only the first register needs to use the complete code of the first code to overwrite the first code stored in the first register, and the second register is not involved. Therefore, the chip can normally realize the CRC function by reading and writing the second register. In addition, when the chip detects a data error through the CRC function, it no longer reports an error to the host side through the SPI, but reports an error to the host side through the CRC error reporting interface. Therefore, it will not occupy the SPI, and will not affect the realization of the auto reload function. It can be seen that the selection of this embodiment can avoid the hardware conflict between the auto reload function and the CRC function, so that the chip can realize the auto reload function and the CRC function at the same time.

[0052] The first register 101, the second register 102, the SPI 103, and the CRC error reporting interface 104 will be described below respectively.

[0053] The number of the first register 101 and the second register 102 may be different according to different application scenarios. The first register 101 may be one register or multiple registers, and the second register 102 may be one register or multiple registers. Furthermore, the number of the first registers 101 is independent of the number of the second registers 102. In addition to the first register 101 and the second register 102, the chip may also be provided with other registers, and the information stored in the other registers may be different according to different application scenarios.

[0054] The display function implemented when the first code is executed refers to a function for displaying vehicle instruments, and the CRC function implemented when the second code is executed refers to a function for checking whether the displayed vehicle instruments are wrong. The CRC function can be implemented by any CRC method in the relevant technology, which will be explained exemplarily below and will not be repeated here.

[0055] The vehicle instrument displayed by the display function may be displayed in the form of an image, and the chip may receive an image for representing the vehicle instrument sent by the host end through a video interface, and display the received image through the display function, thereby realizing the display of the vehicle instrument.

[0056] The CRC error reporting interface 104 can be an interface of any form, and the CRC error reporting interface 104 should be able to directly or indirectly access the host end. Direct access to the host end means that the CRC error reporting interface can be connected to an interface in the host end, and indirect access to the host end means that the CRC error reporting interface can be connected to an interface in the host end through an adapter.

[0057] Exemplarily, assuming that the CRC error reporting interface 104 is a probe, in a possible embodiment, there is an interface in the host end that can be docked with the probe, which is recorded as the first interface, and the CRC error reporting interface 104 can be docked with the first interface, so that the CRC error reporting interface 104 is directly connected to the host end. In another possible embodiment, there is no interface in the host end that can be docked with the probe. It is assumed that there is an interface in the host end that is recorded as the second interface, and there is an adapter, and there are a third interface and a fourth interface on the adapter, wherein the third interface can be docked with the probe, and the fourth interface can be docked with the second interface, then the CRC error reporting interface can be docked with the third interface, and the fourth interface can be docked with the second interface, so that the CRC error reporting interface 104 is indirectly connected to the host end.

[0058] The following is an exemplary description of how the chip implements the CRC function. It can be understood that the following method of implementing the CRC function is only an example. In other possible embodiments, the chip can also implement the CRC function in other ways.

[0059] In this example, SPI 103 is also used to receive a predicted CRC value sent by the host. The predicted CRC value is calculated by the host according to the preset CRC algorithm based on the image to be displayed, wherein the image to be displayed is an image sent by the host to the chip so that the chip displays it through the display function, such as the image used to represent the vehicle instrument in the previous text. Exemplarily, assuming that the host sends a first image to the chip so that the chip displays the first image through the display function, the host can process the first image according to the preset CRC algorithm to obtain a predicted CRC value. In theory, there is a one-to-one correspondence between the CRC value and the image, that is, the CRC values ​​calculated from different images are theoretically different. If the CRC values ​​calculated from two images are the same, then the two images are theoretically the same image.

[0060] The CRC error interface 104 is specifically used to send an error message to the host when the chip determines that the predicted CRC value is different from the calculated CRC value stored locally in the chip, wherein the calculated CRC value is calculated by the chip according to a preset CRC algorithm based on the image to be displayed sent by the host.

[0061] It is understandable that errors may occur in the process of transmitting the image to be displayed from the host to the chip. Therefore, the image to be displayed received by the chip may be different from the image to be displayed sent by the host, resulting in inconsistency between the displayed image and the image to be displayed. As analyzed above, there is a one-to-one correspondence between the CRC value and the image, so the calculated CRC value may be different from the predicted CRC value. In addition, if the calculated CRC value is the same as the predicted CRC value, it can be considered that the image to be displayed received by the chip is the same as the image to be displayed sent by the host, that is, no error occurred in the transmission of the image to be displayed. On the contrary, if the calculated CRC value is different from the predicted CRC value, it can be considered that the image to be displayed received by the chip is different from the image to be displayed sent by the host, that is, an error occurred in the transmission of the image to be displayed.

[0062] Therefore, in this example, when the predicted CRC value is different from the calculated CRC value, the CRC error interface sends an error message to the host side.

[0063] The image to be displayed may be one or more images. If the image to be displayed is one image, the predicted CRC value is different from the calculated CRC value, which means that the predicted CRC value calculated based on the one image to be displayed is different from the calculated CRC value. If the image to be displayed is multiple images, the predicted CRC value is different from the calculated CRC value, which means that the predicted CRC value calculated based on each image to be displayed is different from the calculated CRC value, or the predicted CRC value calculated based on at least X images to be displayed is different from the calculated CRC value, where X is an arbitrary positive integer, or the predicted CRC value calculated based on at least X images to be displayed is different from the calculated CRC value, and the X images to be displayed are continuous in the time domain.

[0064] For example, taking X=32 as an example, and assuming that the image to be displayed is each image frame in the video to be displayed sent from the host to the chip, in this example, if the predicted CRC value and the calculated CRC value calculated based on 32 consecutive image frames in the video to be displayed are the same, the CRC error interface 104 sends an error message to the host.

[0065] In a possible embodiment, the second register 102 is also used to set a preset flag bit in the second register when the chip determines that the predicted CRC value is different from the calculated CRC value. The preset flag bit may be any bit in the second register that does not store a code, and the setting may be to set the flag bit to 1 or to set the preset flag bit to 0. For example, if the preset flag bit is 0 by default, the setting may be to set the preset flag bit to 1, and if the preset flag bit is 1 by default, the setting may be to set the preset flag bit to 0.

[0066] In this embodiment, the CRC error reporting interface 104 is specifically used to read the preset flag, and if the preset flag is set, send error information to the host. The CRC error reporting interface 104 can read the preset flag regularly, or read the preset flag under the drive of the host or chip.

[0067] By selecting this embodiment, the information that the predicted CRC value is different from the calculated CRC value can be transmitted to the CRC error reporting interface 104 through the preset identification bit to drive the CRC error reporting interface 104 to report an error to the host side, so that the host side can take countermeasures in time.

[0068] The error information may be any form of information, such as a message, a level signal, a current signal, etc. In a possible implementation, in order to simplify the error information, the error information may be a high level signal or a low level signal. Exemplarily, in a possible embodiment, the error information is a high level signal with a voltage of 3.3V. After receiving the high level signal sent by the CRC error interface 104, the host end may determine that the chip has detected a data error through the CRC function, that is, the image displayed by the display function is inconsistent with the image desired to be displayed, and the host then takes corresponding measures to make the image displayed by the display function consistent with the image desired to be displayed.

[0069] The first register 101 and the second register 102 may be located in the same page of the chip memory, or in different pages of the chip memory. The following will describe the cases where the first register 101 and the second register 102 are located in the same page and in different pages.

[0070] It is understandable that if the first register 101 and the second register 102 are located in the same page in the memory of the chip, then the reading and writing of the first register 101 and the reading and writing of the second register 102 are the reading and writing of the same page in the memory, which may cause a read-write conflict.

[0071] Based on this, in a possible embodiment, the SPI 103 drives the first register 101 to use the complete code to overwrite the first code stored in the first register 101, including:

[0072] The first register 101 is driven to use the complete code to overwrite the first code stored in the first register within a preset first time window.

[0073] And the aforementioned CRC error reporting interface 104 reads the preset identification bit, including:

[0074] The preset identification bit is read within a preset second time window, wherein there is no intersection between the second time window and the first time window.

[0075] By selecting this embodiment, the reading and writing of the first register and the reading and writing of the second register can be performed within two non-intersecting time windows, thereby avoiding possible reading and writing conflicts in the time domain.

[0076] The first time window and the second time window can be any two time windows that do not have an intersection. For example, Figure 2 As shown, the portion filled with slashes is the second time window, and the portion not filled with slashes is the first time window.

[0077] In the case where the first register 101 and the second register 102 are located in different pages of the memory of the chip, since the reading and writing of the first register 101 and the reading and writing of the second register 102 are reading and writing of different pages, there is no read-write conflict.

[0078] Assuming that there are a total of M pages in the memory, the first register 101 may be distributed in n pages specified therein, and the second register 102 may be distributed in y pages specified therein, and the n pages and the y pages do not have any intersection. Figure 3 As shown, the memory contains a total of 15 pages, which are recorded as pages 0-9 and pages AE respectively.

[0079] Among them, page 0 and page 1 are used to store codes related to the normal function, page 2 is used to store codes related to the positive analog gamma, page 3 is used to store codes related to the negative analog gamma, page 4 is used to store codes related to the gamma correction for red color, page 5 is used to store codes related to the gamma correction for green color, page 6 is used to store codes related to the gamma correction for blue color, page 7 is used to store codes related to the low voltage differential function (LVDS function), page 8 is used to store codes related to the temperature sensor function, page 9 is used to store codes related to the one time programmable function, page AD is used to store codes related to the CRC function, and page E is used to store the Vender ID.

[0080] That is, in this example, the second register is located in page AD and the first register is located in pages 0-9.

[0081] See also Figure 4 , Figure 4 The diagram shows a schematic diagram of the structure of a vehicle-mounted system provided by an embodiment of the present invention, which includes a host end 200 and a chip 100. The host end 200 can be any vehicle-mounted host.

[0082] The chip 100 includes: a first register 101 , a second register 102 , an SPI 103 and a CRC error reporting interface 104 .

[0083] The first register 101 is used to store a first code, wherein the first code is used to implement a display function when executed;

[0084] The second register 102 is used to store a second code, wherein the second code is used to implement a CRC function when executed;

[0085] The SPI 103 is used to periodically receive the complete code of the first code sent by the host end 200; and drive the first register to overwrite the first code stored in the first register with the complete code;

[0086] The CRC error reporting interface 104 is used to send error reporting information to the host end 200 when the chip 100 detects a data error through the CRC function.

[0087] The host end 200 is connected to the chip 100 through the SPI 103 and the CRC error reporting interface 104, and the host end 200 is used to periodically send the complete code to the chip through the SPI.

[0088] For the chip 100 and the first register 101, the second register 102, the SPI 103 and the CRC error reporting interface 104 in the chip, please refer to the above related descriptions, which will not be repeated here.

[0089] In a possible embodiment, the host end 200 is further used to send the predicted CRC value to the chip 100 through the SPI 103;

[0090] The CRC error interface 104 is specifically used to send error information to the host end when the chip 100 determines that the predicted CRC value is different from the calculated CRC value.

[0091] For the prediction and calculation of CRC values, please refer to the above related instructions, which will not be repeated here.

[0092] In a possible embodiment, the second register 102 is specifically used to set a preset flag bit in the second register 102 when the chip 100 determines that the predicted CRC value is different from the calculated CRC value;

[0093] The host end 200 is also used to drive the CRC error reporting interface 104 to read the preset identification bit, so that the CRC error reporting interface 104 sends error information to the host end 200 when the preset identification bit is set.

[0094] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0095] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0096] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A chip with a cyclic redundancy check function, characterized in that: The chip comprises: First register, second register, serial peripheral interface SPI, cyclic redundancy check CRC error reporting interface; The first register is used to store a first code, wherein the first code is used to implement a display function when executed; The second register is used to store a second code, wherein the second code is used to implement a CRC function when executed; The SPI is used to periodically receive the complete code of the first code sent by the host; and drive the first register to overwrite the first code stored in the first register with the complete code; The CRC error reporting interface is used to send error reporting information to the host end when the chip detects a data error through the CRC function.

2. The chip according to claim 1, characterized in that: The SPI is further used to receive a predicted CRC value sent by the host end, where the predicted CRC value is calculated by the host end according to a preset CRC algorithm based on the image to be displayed; The CRC error interface is specifically used to send an error message to the host when the chip determines that the predicted CRC value is different from the calculated CRC value. The calculated CRC value is calculated by the chip according to the preset CRC algorithm based on the image to be displayed sent by the host.

3. The chip according to claim 2, characterized in that: The second register is further used to set a preset flag bit in the second register when the chip determines that the predicted CRC value is different from the calculated CRC value; The CRC error reporting interface is specifically used to read the preset identification bit; if the preset identification bit is set, an error reporting message is sent to the host end.

4. According to the chip described in any one of claims 1-3, the error information is a high-level signal or a low-level signal.

5. The chip according to claim 3, characterized in that: The first register and the second register are located in the same page of the memory of the chip; The SPI drives the first register to overwrite the first code stored in the first register with the complete code, including: driving the first register to overwrite the first code stored in the first register with the complete code within a preset first time window; The CRC error reporting interface reads the preset identification bit, including: The preset identification bit is read within a preset second time window, wherein there is no intersection between the second time window and the first time window.

6. The chip according to claim 1, characterized in that: The first register and the second register are located in different pages of the memory of the chip.

7. The chip according to claim 1, characterized in that: The CRC error reporting interface is a probe.

8. A vehicle-mounted system, characterized in that: The vehicle-mounted system comprises a host end and a chip as described in any one of claims 1 to 7; The chip includes a first register, a second register, a serial peripheral interface SPI, and a cyclic redundancy check CRC error reporting interface; The first register is used to store a first code, wherein the first code is used to implement a display function when executed; The second register is used to store a second code, wherein the second code is used to implement a CRC function when executed; The SPI is used to periodically receive the complete code of the first code sent by the host; and drive the first register to overwrite the first code stored in the first register with the complete code; The CRC error reporting interface is used to send error reporting information to the host end when the chip detects a data error through the CRC function; The host end is connected to the chip through the SPI and the CRC error reporting interface, and the host end is used to periodically send the complete code to the chip through the SPI.

9. The system according to claim 8, characterized in that The host end is further used to send a predicted CRC value to the chip through the SPI, where the predicted CRC value is calculated by the host end according to a preset CRC algorithm based on the image to be displayed; The CRC error interface is specifically used to send an error message to the host when the chip determines that the predicted CRC value is different from the calculated CRC value. The calculated CRC value is calculated by the chip according to the preset CRC algorithm based on the image to be displayed sent by the host.

10. The system according to claim 9, characterized in that The second register is specifically used to set a preset flag bit in the second register when the chip determines that the predicted CRC value is different from the calculated CRC value; The host end is also used to drive the CRC error reporting interface to read the preset identification bit, so that the CRC error reporting interface sends error information to the host end when the preset identification bit is set.

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