Memory access method based on network card, memory access method, device and system

Abstract

The embodiments of the present application provide a memory access method, a memory access method, a device and a system based on a network card. In the embodiments of the present application, the memory attribute information of the memory to be accessed can be determined according to the access request; and the memory to be accessed can be accessed according to the access path adapted by the memory attribute information, thereby realizing the separation of the access paths of the volatile memory and the persistent memory. Among them, the access path adapted by the volatile memory passes through the processor cache, and the low latency performance of the processor cache can be utilized to reduce the access latency of the volatile memory; on the other hand, the access path of the persistent memory does not pass through the processor cache, which reduces the intermediate links of accessing the persistent memory, and helps to improve the access efficiency of the persistent memory. In summary, the embodiments of the present application help to improve the efficiency of memory access.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory access method based on a network card, a memory access method, a device and a system. Background Art

[0002] With the development of non-volatile memory and Remote Direct Memory Access (RDMA) technology, data centers with high storage performance and low-latency network access have become a trend. Persistent memory has characteristics such as low latency, which is consistent with the high-performance network's high bandwidth and low latency characteristics. Therefore, persistent memory is widely used in data storage in data centers.

[0003] In the prior art, when writing to persistent memory, the persistent memory can be written through the processor cache. However, when the bandwidth load is high, there is competition between the software (running on the processor) writing to the persistent memory and the peripherals writing to the persistent memory in the processor cache, which ultimately leads to a decline in the overall external performance of the software system and the inability to fully exert the device performance of the persistent memory. Alternatively, the processor cache can be directly turned off so that the peripherals write to the persistent memory directly without going through the processor cache. However, directly turning off the processor cache will result in all memory accesses not being accelerated by the processor cache, and the overall external service capability of the system will be reduced. Summary of the invention

[0004] Multiple aspects of the present application provide a network card-based memory access method, a memory access method, a device, and a system for separating the access paths of volatile memory and persistent memory, thereby helping to improve memory access efficiency.

[0005] The present application provides a memory access method, including:

[0006] Get the first access request;

[0007] Determining memory attribute information of the memory to be accessed according to the first access request;

[0008] Accessing the memory to be accessed according to the access path adapted by the memory attribute information and the first access request;

[0009] Among them, the access path adapted by volatile memory includes processor cache; the access path adapted by persistent memory does not include processor cache.

[0010] The embodiment of the present application also provides a memory access method based on a network card, including:

[0011] The network card obtains a first access request; determines memory attribute information of a memory to be accessed according to the first access request; performs protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with a communication protocol between the network card and the processor; and provides the second access request to the processor;

[0012] The processor accesses the memory to be accessed according to the access path adapted by the memory attribute information carried by the second access request;

[0013] Among them, the access path adapted by volatile memory includes processor cache; the access path adapted by persistent memory does not include processor cache.

[0014] The present application also provides a memory access method, including:

[0015] Obtain memory attribute information of the memory to be accessed;

[0016] Generate an access request according to the memory attribute information;

[0017] The access request is provided to other computer devices, so that the other computer devices can access the memory to be accessed according to the access path adapted by the memory attribute information.

[0018] The embodiment of the present application also provides a data processing system, including: a client device and a server device;

[0019] Wherein, the client device is used to: obtain memory attribute information of the memory to be accessed; generate an access request according to the memory attribute information; and provide the access request to the server device;

[0020] The server device is used to: determine the memory attribute information of the memory to be accessed according to the access request; access the memory to be accessed according to the access path adapted by the memory attribute information and the access request; wherein the access path adapted by the volatile memory includes the processor cache; and the access path adapted by the persistent memory does not include the processor cache.

[0021] The embodiment of the present application also provides a computer device, including: a processor, a network card, a volatile memory and a persistent memory;

[0022] The processor is coupled to the network card, the volatile memory and the persistent memory, and is used to: obtain a first access request through the network card; determine memory attribute information of the memory to be accessed according to the first access request; access the memory to be accessed according to an access path adapted to the memory attribute information and the first access request; wherein the access path adapted to the volatile memory includes a processor cache; and the access path adapted to the persistent memory does not include a processor cache.

[0023] An embodiment of the present application further provides a computer device, including: a memory, a processor, and a network card;

[0024] Wherein, the memory is used to store a computer program;

[0025] The processor is coupled to the memory and the network card, and is used to execute the computer program to: obtain memory attribute information of a memory to be accessed; generate an access request according to the memory attribute information; and provide the access request to other computer devices through the network card, so that the other computer devices access the memory to be accessed according to an access path adapted to the memory attribute information.

[0026] In the embodiment of the present application, the memory attribute information of the memory to be accessed can be determined according to the access request; and the memory to be accessed can be accessed according to an access path adapted to the memory attribute information, realizing the separation of the access paths of volatile memory and persistent memory. Among them, the access path adapted to volatile memory passes through the processor cache, and the low latency performance of the processor cache can be utilized to reduce the access latency of volatile memory; on the other hand, the access path of persistent memory does not pass through the processor cache, reducing the intermediate links for accessing persistent memory, which helps to improve the access efficiency of persistent memory. In summary, the embodiment of the present application helps to improve the memory access efficiency. Description of the Drawings

[0027] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0028] Figure 1 is a schematic structural diagram of a data processing system provided by an embodiment of the present application;

[0029] Figure 2 is a schematic access path diagram provided by an embodiment of the present application;

[0030] Figure 3 and Figure 4a is a schematic flow diagram of a memory access method provided by an embodiment of the present application;

[0031] Figure 4b is a schematic flow diagram of a memory access method based on a network card provided by an embodiment of the present application;

[0032] Figure 5 and Figure 6 is a schematic structural diagram of a computer device provided by an embodiment of the present application. Detailed Embodiments

[0033] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0034] In order to improve memory access efficiency, a scheme for separating the access paths of volatile memory and persistent memory is proposed, wherein the access path adapted for volatile memory includes processor cache; and the access path adapted for persistent memory does not include processor cache. In an embodiment of the present application, the memory attribute information of the memory to be accessed can be determined according to the access request; and the memory to be accessed can be accessed according to the access path adapted for the memory attribute information, thereby realizing the separation of the access paths of volatile memory and persistent memory. Among them, the access path adapted for volatile memory passes through the processor cache, and the low latency performance of the processor cache can be utilized to reduce the access latency of volatile memory; on the other hand, the access path of persistent memory does not pass through the processor cache, which reduces the intermediate links for accessing persistent memory, and helps to improve the access efficiency of persistent memory. In summary, the embodiments of the present application help to improve memory access efficiency.

[0035] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0036] It should be noted that the same reference numerals denote the same objects in the following drawings and embodiments, and therefore, once an object is defined in one drawing or embodiment, it does not need to be further discussed in the subsequent drawings and embodiments.

[0037] Figure 1 This is a schematic diagram of the structure of the data processing system provided in the embodiment of the present application. Figure 1 As shown, the data processing system includes: a client device 10 and a server device 20.

[0038] Among them, the client device 10 and the server device 20 can be connected wirelessly or by wire. Optionally, the server device 20 can be connected to the client device 10 through a mobile network. Accordingly, the network standard of the mobile network can be any one of 2G (GSM), 2.5G (GPRS), 3G (WCDMA, TD-SCDMA, CDMA2000, UTMS), 4G (LTE), 4G+ (LTE+), 5G, WiMax, etc. Optionally, the client device 10 can also be connected to the server device 20 through Bluetooth, WiFi, infrared, etc. Of course, the client device 10 and the server device 20 can also be connected through a high-speed virtual private network (VPN) communication connection, etc.

[0039] In this embodiment, the client device 10 and the server device 20 are logical clients and servers. The client device 10 may be a single server device with client functions in a data center, or a cloud server array, or a virtual machine (VM) running in a cloud server array.

[0040] In this embodiment, the server device 20 refers to a computer device that can perform data management, respond to the service request of the client device 10, and provide the user with services corresponding to the service request, and generally has the ability to undertake and guarantee services. The server device 20 can be a single server device, or a cloud server array, or a virtual machine (VM) running in a cloud server array. In addition, the server device 20 can also refer to other computing devices with corresponding service capabilities, such as computers and other terminal devices (running service programs), etc.

[0041] In the embodiments of the present application, Figure 1 As shown, the client device 10 may include a memory 101 and a processor 102. The memory 101 may be implemented as any form of storage medium, such as a memory, etc. The memory may include: a volatile memory, such as a random access memory (RAM); of course, the memory may also include a persistent memory, etc.

[0042] In this embodiment, the client device 10 can access the memory of the server device 20. Optionally, the client device 10 can access the memory of the server device 20 through RDMA technology. Accordingly, the client device 10 can be configured with a network card 103. The network card 103 can be an RDMA network card.

[0043] In the embodiments of the present application, Figure 1As shown, the server device 20 may include: a network card 201, a processor 202, a volatile memory 203, and a persistent memory 204. Among them, the network card 201, the volatile memory 203, and the persistent memory 204 are respectively connected to the processor 202 for communication. Optionally, the network card 201, the volatile memory 203, and the persistent memory 204 may be respectively connected to the processor 202 for communication through a PCIe interface. The network card 201 may be a Remote Direct Memory Access (RDMA) network card.

[0044] In the embodiment of the present application, volatile memory is one of the important components of the computer, also known as internal memory and main memory, which is used to temporarily store the calculation data in the processor and the data exchanged with the external memory such as the hard disk. It is a bridge for the external storage medium to communicate with the processor (such as the central processing unit CPU). The operation of all programs in the computer device is carried out in the memory, and the strength of the memory performance affects the overall performance of the computer. When the computer device starts running, the software will transfer the data to be calculated from the memory to the processor for calculation. When the calculation is completed, the processor transmits the result. After the computer device loses power, the data in the volatile memory will be lost.

[0045] After the computer device loses power, the data written to the persistent memory will not be lost, and the data can be read again after the computer device is restarted.

[0046] The processor can be the central processing unit (CPU) of a computer device, which is the computing and control core of the computer device and the final execution unit for information processing and program running. The software runs on the processor, and the software can access volatile memory and persistent memory through the processor. Figure 2 As shown, the processor 202 has a cache area, referred to as the processor cache. Compared with volatile memory and persistent memory, the processor cache has a lower access latency. Therefore, caching data in the processor cache can reduce access latency and improve access efficiency. In particular, the direct data input and output (DDIO) module in the last level cache (LLC) of the processor cache can accelerate the access of peripherals to memory data. The network card can access memory data through DDIO. If the processor cache hits, there is no need to access the memory again, which helps to improve the data access speed. Among them, peripherals refer to other external facilities other than memory, such as network cards, hard disks or processors.

[0047] In this embodiment, the network card has information forwarding and logic processing capabilities. The network card may include a processing unit. In the embodiment of the present application, the implementation form of the processing unit of the network card is not limited. In some embodiments, the processing unit of the network card may be an ASIC chip, FPGA, etc., but is not limited thereto.

[0048] Generally speaking, the access latency of the processor cache is about 10ns; the access latency of volatile memory is about 80ns to 100ns; and the access latency of persistent memory is about 350ns. Accordingly, the access latency of volatile memory is about 8-10 times that of the processor cache; and the access latency of persistent memory is about 35-40 times that of the processor cache. Since the processor cache is also a volatile storage medium, in the case of writing data to volatile memory, writing data to the processor cache can be considered as writing to volatile memory.

[0049] However, in the scenario of writing to persistent memory, software (running on the processor) writing to persistent memory will compete with external facilities writing to persistent memory for processor cache, ultimately resulting in a decrease in the overall external performance of the software system and failure to fully utilize the device performance of persistent memory.

[0050] In other solutions, the processor cache can be directly turned off, so that all peripherals writing to persistent memory do not go through the processor cache. This method of directly turning off the processor cache will result in no processor cache acceleration for access to all peripherals in the slot corresponding to the processor, resulting in an overall decrease in the device's external service capabilities. On the other hand, it will also result in the inability to use processor cache acceleration for access to volatile memory, resulting in low access efficiency.

[0051] On the other hand, since the minimum unit of the processor cache is 64 bytes and the minimum unit of persistent memory is 256 bytes, in the process of the processor cache persisting small blocks of data, volatile memory data may be written to the processor cache, causing part of the persistent data in the processor cache to be updated to volatile memory data, and ultimately causing the data written to the persistent memory to be lost due to the update of the memory data in the processor cache; therefore, the data newly written to the persistent memory needs to be re-read into the processor cache; then modified in the processor cache; and then the modified data is flushed back to the persistent memory, which increases the write latency of the persistent memory.

[0052] In an embodiment of the present application, in order to improve memory access efficiency, a scheme for separating the access paths of volatile memory and persistent memory is proposed, wherein the access path adapted for volatile memory includes the processor cache; the access path adapted for persistent memory does not include the processor cache. In this way, in the case where the memory to be accessed is volatile memory, the volatile memory can be accessed through the processor cache. In the case where the memory to be accessed is persistent memory, the persistent memory can be accessed directly. Since the access path adapted for volatile memory passes through the processor cache, the low latency performance of the processor cache can be used to reduce the access latency of the volatile memory; on the other hand, the access path of the persistent memory does not pass through the processor cache, which reduces the intermediate links for accessing the persistent memory, and helps to improve the access efficiency of the persistent memory. In summary, the embodiments of the present application help to improve memory access efficiency. The following is an exemplary description of the memory access method provided in the embodiments of the present application.

[0053] In this embodiment, when the client device 10 accesses the memory of the server device 20, it can obtain the memory attribute information of the memory to be accessed. Among them, the memory attribute information refers to the characteristics of the memory storage data, which may include: volatile memory and persistent memory. The above-mentioned memory to be accessed is the memory of the server device 20, which may be volatile memory 203 or persistent memory 204. The specific type of memory is determined by the processor 102 of the client device 10.

[0054] In the embodiment of the present application, in order to separate the access paths of volatile memory and persistent memory, a queue pair (QP) memory attribute is added to the RDMA communication library to identify memory attribute information, that is, to identify whether the memory is volatile memory or persistent memory. Based on this, the client device 10 can generate an access request according to the memory attribute information.

[0055] Optionally, the processor 102 may generate a first access request that complies with the communication protocol between the processor 102 and the network card 103 based on the memory attribute information; and provide the first access request to the network card 103. In some embodiments, the network card 103 is an RDMA network card, and the PCIe protocol is followed between the network card 103 and the processor 102. Based on this, the processor 102 may generate a first access request that complies with the PCIe protocol based on the memory attribute information of the memory to be accessed. Specifically, the processor 102 may encapsulate the memory attribute information of the memory to be accessed into the header field of the PCIe transaction layer packet (Transaction Layer Packet, TLP), and encapsulate the access content into the data part of the PCIe TLP to obtain the PCIe TLP, i.e., the first access request. Further, the processor 102 may provide the first access request to the network card 103.

[0056] For the network card 103, the memory attribute information of the memory to be accessed can be parsed from the first access request; further, the network card 103 can perform protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the network protocol. Specifically, the network card 103 can parse the message body of the first access request from the first access request; use the memory attribute information of the memory to be accessed as the message header field, and encapsulate the message body of the first access request according to the network protocol to obtain a second access request that complies with the network protocol.

[0057] Furthermore, the client device 10 may provide the access request to the server device 20. Specifically, the client device 10 may provide the second access request to the server device 20 through the network card 103.

[0058] For RDMA network cards, RDMA is a host-based direct memory access (Direct Memory Access) capability. It uses direct memory access technology during multi-host communication to provide remote access from the requesting host to the responding host memory function. Network cards with RDMA function are responsible for managing reliable connections between the source and the target. The message service is based on the channel-input and output (Channel-IO) connection created between the local and remote applications of the communicating parties. When an application needs to communicate, a channel connection is created, and the head and tail endpoints of each channel are two pairs of QPs. Each pair of QPs consists of a send queue (SQ) and a receive queue (RQ), which manage various types of messages. The QP will be mapped to the virtual address space of the application, allowing the application to access the network card directly through it.

[0059] Based on the above analysis, in the embodiment of the present application, for the RDMA network card, the client device 10 and the server device 20 can pre-establish different QP links to transmit access requests for different memory attribute information. In the embodiment of the present application, the QP link corresponding to the volatile memory and the QP link corresponding to the persistent memory can be pre-established between the client device 10 and the server device 20. Based on the QP link, the client device 10 can provide the above second access request to the server device 20 through the QP link corresponding to the memory attribute information of the memory to be accessed.

[0060] Accordingly, the server device 20 may receive the second access request and determine the memory attribute information of the memory to be accessed according to the second access request. Optionally, the server device 20 may parse the memory attribute information of the memory to be accessed from the second access request. Further, the server device 20 may access the memory to be accessed according to the access path adapted by the memory attribute information and the second access request. Figure 1As shown, the access path adapted by the volatile memory includes the processor cache; the access path adapted by the persistent memory does not include the processor cache. In this way, if the memory to be accessed is a volatile memory, the server device 20 can access the volatile content 203 through the processor cache according to the second access request. If the memory to be accessed is a persistent memory, the server device 20 can directly access the persistent memory according to the second access request.

[0061] In the embodiments of the present application, the specific implementation form of the access request is not limited. In some embodiments, the access request is a read memory request, and the server device 20 can read the data requested by the first access request from the memory to be accessed according to the access path adapted to the memory attribute information of the memory to be accessed. Of course, the access request can be a write memory request, and the server device 20 can write the data to be written contained in the second access request to the memory to be accessed according to the access path adapted to the memory attribute information of the memory to be accessed.

[0062] In the case where the access request is a memory write request, for the server device 20, the network card 201 may receive a second access request provided by the client device 10; and parse the memory attribute information of the memory to be accessed from the second access request; and then, according to the memory attribute information of the memory to be accessed, the second access request may be protocol converted to obtain a third access request that complies with the communication protocol between the network card 201 and the processor 202. In the embodiment of the present application, the specific implementation of the communication protocol between the network card 201 and the processor 202 is not limited. In some embodiments, the communication protocol between the network card 201 and the processor 202 is the PCIe protocol, then the network card 201 may perform protocol conversion on the second access request according to the PCIe protocol standard according to the memory attribute information of the memory to be accessed to obtain a PCIe TLP, etc.

[0063] Specifically, the network card 201 can also parse the data to be written contained in the second access request from the second access request; then, using the memory attribute information as the message header field, the data to be written is encapsulated according to the communication protocol between the network card 201 and the processor 202 to obtain a third access request.

[0064] Afterwards, the network card 201 may provide the third access request to the processor 202. Optionally, the network card 201 may provide the third access request to the processor 202 through a connection channel (such as a PCIe high-speed channel) between the network card 201 and the processor 202.

[0065] Accordingly, the processor 202 may parse the data to be written and the memory attribute information from the third access request; and then, may write the data to be written into the memory to be accessed according to the access path adapted by the memory attribute information.

[0066] Specifically, Figure 2As shown, in the case where the memory attribute information of the memory to be accessed is a volatile memory, the processor 202 can write the data to be written into the volatile memory 203 through the direct input and output (DDIO) module. Specifically, the processor 202 can write the data to be written into the DDIO module. Since both the volatile memory and the DDIO module are volatile storage media, writing the data to be written into the DDIO module can be considered to be successful. Since the access latency of DDIO is low, the writing efficiency of volatile data can be improved compared to the write memory operation that is not accelerated by the DDIO module. Further, the processor 202 can control the DDIO module to write the data to be written into the volatile memory 203.

[0067] If the memory attribute information of the memory to be accessed is a persistent memory, the processor 202 may directly write the data to be written into the persistent memory 204. Figure 2 As shown, the processor 202 can write the to-be-accessed data directly to the persistent memory 204 through the integrated memory controller (IMC). The to-be-written data is directly written to the persistent memory 204 without passing through the processor cache (such as the DDIO module), which reduces the intermediate links of accessing the persistent memory and helps to improve the access efficiency of the persistent memory.

[0068] On the other hand, since the access latency of the persistent memory 204 is much higher than that of the DDIO module, which is about 35-40 times of the access latency of the DDIO module, if data is written to the persistent memory 204 through the DDIO module, the data to be written will be retained in the DDIO module for a long time, causing competition for processor cache resources, thereby affecting the performance of the volatile memory. In this embodiment, the access paths of the volatile memory and the persistent memory are separated, and the access path of the persistent memory does not pass through the processor cache, so there is no competition with the volatile memory for processor cache resources, which helps to improve the performance of the volatile memory.

[0069] In the embodiment of the present application, since the access path of the volatile memory passes through the processor cache, if a power failure event occurs in the server device 20, if the data in the processor cache is not specifically stored, data loss will occur. In order to solve this problem, in the embodiment of the present application, an energy storage device, such as a capacitor battery energy storage, can be added to the mainboard of the server device 20, so that when the server device 20 loses power, the energy storage device corresponding to the mainboard can continue to power the mainboard, and while the energy storage device continues to power the mainboard, the data in the processor cache is stored in the persistent memory 204. Based on this, the processor 202 can write the data in the processor cache to the persistent memory 204 in response to the power failure event. Specifically, in some embodiments, the processor 202 can use the asynchronous memory refresh (Asynchronous DRAM Refresh, ADR) technology to write the data in the write waiting queue (Write Pending Queue, WPQ) in the IMC of the processor to the persistent memory 204. In other embodiments, the processor 202 may use enhanced ADR (Enhanced ADR, eADR) technology to write the data in the processor cache (CPUCache) to the persistent memory 204. The entire process can be completed within 100 μs. Therefore, when the server device 20 loses power, the embodiment of the present application writes the data in the processor cache to the persistent memory 204, which can prevent the data in the processor cache from being lost due to the power failure of the server device 20, and help improve data security.

[0070] It is worth noting that the above data processing system only takes the client device and the server device as examples to illustrate the memory access process. Among them, the data processing logic of the client device can be adapted to any request sending end; the data processing logic of the server device can be adapted to any request receiving end. In the embodiment of the present application, the request receiving end includes: volatile memory and persistent memory.

[0071] In addition to the above-mentioned data processing system embodiment, the embodiment of the present application also provides a memory access method. The memory access method provided by the embodiment of the present application is exemplarily described below from the perspectives of the request sending end and the receiving end, respectively, in combination with specific embodiments.

[0072] Figure 3 The flowchart of the memory access method provided in the embodiment of the present application is shown in FIG. The memory access method is applicable to the request sending end. Figure 3 As shown, the method includes:

[0073] 301. Obtain memory attribute information of the memory to be accessed.

[0074] 302. Generate an access request according to the memory attribute information.

[0075] 303. Provide an access request to other computer devices, so that the other computer devices can access the memory to be accessed according to the access path adapted by the memory attribute information.

[0076] In this embodiment, the request sending end can be implemented as any form of computer device, such as a terminal device or a server device. In this embodiment, the request sending end can access the memory of other computer devices. Optionally, the memory of other computer devices can be accessed through RDMA technology. Accordingly, the request sending end can be configured with a network card. The network card can be an RDMA network card.

[0077] In this embodiment, when the request sender accesses the memory of other computer devices, it can obtain the memory attribute information of the memory to be accessed in step 301. The memory attribute information refers to the characteristics of the memory storage data, which may include: volatile memory and persistent memory.

[0078] In the embodiment of the present application, in order to separate the access paths of volatile memory and persistent memory, a QP memory attribute is added to the RDMA communication library to identify memory attribute information, that is, to identify whether the memory is volatile memory or persistent memory. Based on this, in step 302, an access request can be generated according to the memory attribute information.

[0079] Optionally, for the request sending end, the processor may generate a first access request that complies with the communication protocol between the processor and the network card based on the memory attribute information; and provide the first access request to the network card. In some embodiments, the network card is an RDMA network card, and the PCIe protocol is followed between the network card and the processor. Based on this, the processor may generate a first access request that complies with the PCIe protocol based on the memory attribute information of the memory to be accessed. Specifically, the processor may encapsulate the memory attribute information of the memory to be accessed into the header field of the PCIe TLP, and encapsulate the access content into the data part of the PCIe TLP to obtain the PCIe TLP, i.e., the first access request. Further, the processor may provide the first access request to the network card.

[0080] For the network card, the memory attribute information of the memory to be accessed can be parsed from the first access request; further, the network card can perform protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the network protocol. Specifically, the network card can parse the message body of the first access request from the first access request; use the memory attribute information of the memory to be accessed as the message header field, encapsulate the message body of the first access request according to the network protocol, and obtain a second access request that complies with the network protocol.

[0081] Furthermore, in step 303, the access request may be provided to other computer devices. Specifically, the second access request may be provided to other computer devices via a network card.

[0082] For the request receiving end, the memory can be accessed according to the access path adapted to the memory attribute information carried in the received access request. The memory access logic of the request receiving end is exemplarily described below.

[0083] Figure 4a A flowchart of another memory access method provided in an embodiment of the present application. The method is applicable to a request receiving end. The method includes:

[0084] 401. Get the second access request.

[0085] 402. Determine memory attribute information of the memory to be accessed according to the second access request.

[0086] 403. Access the memory to be accessed according to the access path adapted by the memory attribute information and the second access request; wherein the access path adapted by the volatile memory includes the processor cache; and the access path adapted by the persistent memory does not include the processor cache.

[0087] In an embodiment of the present application, the request receiving end may also be implemented as a computer device of any form, such as a terminal device or a server device. Accordingly, in step 401, a second access request may be received; and in step 402, the memory attribute information of the memory to be accessed may be determined according to the second access request. Optionally, the memory attribute information of the memory to be accessed may be parsed from the second access request. Further, in step 403, the memory to be accessed may be accessed according to the access path adapted to the memory attribute information and the second access request. Among them, the access path adapted to the volatile memory includes the processor cache; the access path adapted to the persistent memory does not include the processor cache. In this way, in the case where the memory to be accessed is a volatile memory, the volatile content may be accessed through the processor cache according to the second access request. In the case where the memory to be accessed is a persistent memory, the persistent memory may be directly accessed according to the second access request.

[0088] In this embodiment, if the memory to be accessed is volatile memory, the volatile memory can be accessed through the processor cache. If the memory to be accessed is persistent memory, the persistent memory can be accessed directly. For the access path adapted for volatile memory, which passes through the processor cache, the low latency performance of the processor cache can be used to reduce the access latency of the volatile memory; on the other hand, the access path of the persistent memory does not pass through the processor cache, which reduces the intermediate links for accessing the persistent memory, and helps to improve the access efficiency of the persistent memory.

[0089] In the embodiments of the present application, the specific implementation form of the access request is not limited. In some embodiments, the access request is a read memory request, and the data requested by the first access request can be read from the memory to be accessed according to the access path adapted to the memory attribute information of the memory to be accessed. Of course, the access request can be a write memory request, and the data to be written contained in the second access request can be written to the memory to be accessed according to the access path adapted to the memory attribute information of the memory to be accessed.

[0090] In the case where the access request is a memory write request, for the request receiving end, the network card can receive a second access request; and parse the memory attribute information of the memory to be accessed from the second access request; thereafter, the second access request can be protocol converted according to the memory attribute information of the memory to be accessed to obtain a third access request that complies with the communication protocol between the network card and the processor.

[0091] Specifically, the network card can also parse the data to be written contained in the second access request from the second access request; then, using the memory attribute information as the message header field, the data to be written is encapsulated according to the communication protocol between the network card and the processor to obtain a third access request.

[0092] Afterwards, the network card may provide the third access request to the processor at the request receiving end. Optionally, the network card may provide the third access request to the processor via a connection channel (such as a PCIe high-speed channel) between the network card and the processor.

[0093] Accordingly, the processor may parse the data to be written and the memory attribute information from the third access request; and then, may write the data to be written into the memory to be accessed according to the access path adapted by the memory attribute information.

[0094] Specifically, in the case where the memory attribute information of the memory to be accessed is a volatile memory, the processor can write the data to be written into the volatile memory through the direct input and output (DDIO) module. Specifically, the processor can write the data to be written into the DDIO module. Since both the volatile memory and the DDIO module are volatile storage media, once the data to be written is written into the DDIO module, it can be considered that the data to be written is written successfully. Since the access latency of DDIO is low, the writing efficiency of volatile data can be improved compared to the write memory operation that is not accelerated by the DDIO module. Furthermore, the processor can control the DDIO module to write the data to be written into the volatile memory.

[0095] In the case where the memory attribute information of the memory to be accessed is persistent memory, the processor can write the data to be written directly to the persistent memory. Optionally, the processor can write the data to be accessed directly to the persistent memory through an integrated memory controller (IMC). Among them, writing the data to be written directly to the persistent memory without passing through the processor cache (such as the DDIO module) reduces the intermediate links for accessing the persistent memory, which helps to improve the access efficiency of the persistent memory.

[0096] On the other hand, since the access latency of the persistent memory is much higher than that of the DDIO module, which is about 35-40 times of the access latency of the DDIO module, if data is written to the persistent memory through the DDIO module, the data to be written will be retained in the DDIO module for a long time, causing competition for processor cache resources, thereby affecting the performance of the volatile memory. In this embodiment, the access paths of the volatile memory and the persistent memory are separated, and the access path of the persistent memory does not pass through the processor cache. Therefore, there is no competition with the volatile memory for processor cache resources, which helps to improve the performance of the volatile memory.

[0097] In an embodiment of the present application, since the access path of the volatile memory passes through the processor cache, if a power outage occurs at the request receiving end, if the data in the processor cache is not specifically stored, data loss will occur. In order to solve this problem, in an embodiment of the present application, an energy storage device, such as a capacitor battery energy storage, can be added to the mainboard of the request receiving end. In this way, when the request receiving end loses power, the energy storage device corresponding to the mainboard can continue to power the mainboard, and while the energy storage device continues to power the mainboard, the data in the processor cache is stored in the persistent memory. Therefore, when the device loses power, the embodiment of the present application writes the data in the processor cache to the persistent memory, which can prevent the data in the processor cache from being lost due to power failure at the request receiving end, and helps to improve data security. Regarding the specific implementation method of writing the data in the processor cache to the persistent memory in response to a power outage, please refer to the relevant content of the above embodiment, which will not be repeated here.

[0098] The memory access method provided in the above embodiment is implemented based on a network card, and in particular, the memory access method is implemented based on an RDMA network card, which will be described below in conjunction with specific embodiments.

[0099] Figure 4b The flowchart of the memory access method based on the network card provided in the embodiment of the present application is as follows. Figure 4b As shown, the method includes:

[0100] S1. The network card obtains a second access request.

[0101] S2. Determine memory attribute information of the memory to be accessed according to the second access request.

[0102] S3. Perform protocol conversion on the second access request according to the memory attribute information to obtain a third access request that complies with the communication protocol between the network card and the processor.

[0103] S4. Provide the third access request to the processor.

[0104] S5. The processor accesses the memory to be accessed according to the access path adapted by the memory attribute information carried in the third access request; wherein the access path adapted by the volatile memory includes the processor cache; and the access path adapted by the persistent memory does not include the processor cache.

[0105] The network card-based memory access method provided in this embodiment is applicable to the request receiving end. The network card and the processor may be the network card and the processor of the request receiving end. In step S1, the network card may receive a second access request; and in step S2, according to the second access request, the memory attribute information of the memory to be accessed is determined. Optionally, the memory attribute information of the memory to be accessed may be parsed from the second access request.

[0106] Afterwards, in step S3, the network card can perform protocol conversion on the second access request according to the memory attribute information of the memory to be accessed, so as to obtain a third access request that complies with the communication protocol between the network card and the processor. For the specific implementation of step S3, please refer to the relevant content of the above embodiment, which will not be repeated here.

[0107] Then, in step S4, the network card may provide the third access request to the processor at the request receiving end. Optionally, the network card may provide the third access request to the processor via a connection channel (such as a PCIe high-speed channel) between the network card and the processor.

[0108] Accordingly, in step S5, the memory to be accessed is accessed according to the access path adapted to the memory attribute information carried in the third access request. For the specific implementation of step S5, please refer to the relevant contents of the above embodiment, which will not be described in detail here.

[0109] In this embodiment, if the memory to be accessed is volatile memory, the volatile memory can be accessed through the processor cache. If the memory to be accessed is persistent memory, the persistent memory can be accessed directly. For the access path adapted for volatile memory, which passes through the processor cache, the low latency performance of the processor cache can be used to reduce the access latency of the volatile memory; on the other hand, the access path of the persistent memory does not pass through the processor cache, which reduces the intermediate links for accessing the persistent memory, and helps to improve the access efficiency of the persistent memory.

[0110] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 401 and 402 can be device A; for another example, the execution subject of step 401 can be device A, and the execution subject of step 402 can be device B; and so on.

[0111] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations appearing in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel, and the sequence numbers of the operations, such as 401, 402, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel.

[0112] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 5 As shown, the computer device includes: a memory 50a, a processor 50b and a network card 50c. In this embodiment, the computer device can be implemented as a request sending end. Optionally, the network card 50c can be an RDMA network card, etc.

[0113] The memory 50a is used to store computer programs.

[0114] The processor 50b is coupled to the memory 50a and the network card 50c, and is used to execute a computer program for: obtaining memory attribute information of the memory to be accessed; generating an access request based on the memory attribute information; and providing the access request to other computer devices through the network card 50c, so that the other computer devices can access the memory to be accessed according to the access path adapted by the memory attribute information.

[0115] In some embodiments, when generating an access request, the processor 50b is specifically used to: generate a first access request that complies with the communication protocol between the processor 50b and the network card 50c according to the memory attribute information; and provide the first access request to the network card 50c.

[0116] Accordingly, the network card 50c is used to parse the memory attribute information of the memory to be accessed from the first access request; perform protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the network protocol; and provide the second access request to other computer devices.

[0117] In some optional embodiments, such as Figure 5 As shown, the computer device may also include: other components besides the network card 50c, such as a communication component 50d and a power supply component 50e. Figure 5The components are shown only schematically, and do not mean that the computer equipment must include Figure 5 The components shown do not necessarily mean that the computer equipment can only include Figure 5 Components shown.

[0118] The computer device provided in this embodiment can identify access requests to volatile memory and persistent memory, so that other computer devices that subsequently receive the access request can access the memory to be accessed through different access paths based on the attribute information of the memory to be accessed, thereby realizing the separation of the access paths of volatile memory and persistent memory. Among them, the access path adapted to the volatile memory passes through the processor cache, and the low latency performance of the processor cache can be used to reduce the access latency of the volatile memory; on the other hand, the access path to the persistent memory does not pass through the processor cache, which reduces the intermediate links in accessing the persistent memory, and helps to improve the access efficiency of the persistent memory. In summary, the embodiments of the present application help to improve memory access efficiency.

[0119] Figure 6 This is a schematic diagram of the structure of another computer device provided in an embodiment of the present application. Figure 6 As shown, the computer device includes: a processor 60a, a network card 60b, a volatile memory 60c and a persistent memory 60d. The processor 60a and the network card 60b are in communication connection. The network card 60b can be an RDMA network card.

[0120] In this embodiment, the processor 60a is coupled to the network card 60b, the volatile memory 60c and the persistent memory 60d, and is used to: obtain a first access request through the network card 60b; determine the memory attribute information of the memory to be accessed according to the first access request; access the memory to be accessed according to the access path adapted by the memory attribute information and the first access request; wherein, the access path adapted by the volatile memory 60c includes the processor cache; and the access path adapted by the persistent memory 60d does not include the processor cache.

[0121] Optionally, correspondingly, when the processor 60a accesses the memory to be accessed, it is specifically configured to: write the data to be written included in the first access request into the memory to be accessed according to the access path adapted by the memory attribute information.

[0122] Optionally, the memory attribute information is volatile memory. Accordingly, when the processor 60a writes the to-be-written data included in the first access request into the to-be-accessed memory, it is specifically configured to: write the to-be-accessed data into the volatile memory 60c through the direct input / output module of the processor 60a.

[0123] Optionally, the memory attribute information is persistent memory. Accordingly, when the processor 60a writes the to-be-written data included in the first access request into the to-be-accessed memory, it is specifically configured to: directly write the to-be-written data into the persistent memory 60d.

[0124] In this embodiment, the network card 60b performs protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the communication protocol between the network card and the processor; and provides the second access request to the processor 60a.

[0125] Accordingly, when writing the data to be written into the memory to be accessed, the processor 60a is specifically used to: parse the data to be written and the memory attribute information from the second access request; and write the data to be written into the memory to be accessed according to the access path adapted by the memory attribute information.

[0126] Among them, when the network card 60b performs protocol conversion on the first access request, it is specifically used to: parse out the data to be written contained in the first access request from the first access request; use the memory attribute information as the message header field, and encapsulate the data to be written according to the communication protocol between the network card and the processor to obtain the second access request.

[0127] In some embodiments of the present application, the computer device further includes: a motherboard 60e. The processor 60a may be disposed on the motherboard 60e. Optionally, the motherboard 60e is further provided with an energy storage device 60f. The energy storage device 60f may supply power to the motherboard 60e when the computer device loses power. Optionally, the energy storage device 60f may include: a capacitor battery.

[0128] Accordingly, the processor 60a is further configured to: in response to a power-off event, write the data in the processor cache into the persistent memory 60d.

[0129] In some optional embodiments, such as Figure 6 As shown, the computer device may also include optional components such as a power supply component 60g. Figure 6 The components are shown only schematically, and do not mean that the computer equipment must include Figure 6 The components shown do not necessarily mean that the computer equipment can only include Figure 6 Components shown.

[0130] The computer device provided in this embodiment can determine the memory attribute information of the memory to be accessed according to the access request; and access the memory to be accessed according to the access path adapted by the memory attribute information, thereby realizing the separation of the access paths of volatile memory and persistent memory. Among them, the access path adapted by the volatile memory passes through the processor cache, and the low latency performance of the processor cache can be used to reduce the access latency of the volatile memory; on the other hand, the access path of the persistent memory does not pass through the processor cache, which reduces the intermediate links of accessing the persistent memory, and helps to improve the access efficiency of the persistent memory. In summary, the embodiments of the present application help to improve memory access efficiency.

[0131] In an embodiment of the present application, the memory is used to store a computer program and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0132] In the embodiment of the present application, the processor can be any hardware processing device that can execute the logic of the above method. Optionally, the processor can be a central processing unit (CPU), a graphics processing unit (GPU) or a microcontroller unit (MCU); it can also be a field programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), a complex programmable logic device (CPLD) and other programmable devices; or an advanced reduced instruction set (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (System on Chip, SoC), etc., but not limited to this.

[0133] In an embodiment of the present application, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G, 5G or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component can also be implemented based on near field communication (NFC) technology, radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology or other technologies.

[0134] In an embodiment of the present application, a power supply component is configured to provide power to various components of the device in which it is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located.

[0135] It should be noted that the descriptions such as “first” and “second” in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit “first” and “second” to different types.

[0136] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0137] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0138] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0139] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0140] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0141] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0142] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0143] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0144] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A memory access method based on a network card, It is characterized in that include: The network card obtains the first access request; Determining memory attribute information of the memory to be accessed according to the first access request; Performing protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the communication protocol between the network card and the processor; providing the second access request to the processor; The processor accesses the memory to be accessed according to the access path adapted by the memory attribute information carried by the second access request; Among them, the access path adapted by the volatile memory includes the processor cache; The access path adapted for persistent memory does not include the processor cache.

2. A memory access method, It is characterized in that include: Get the first access request; Determining memory attribute information of the memory to be accessed according to the first access request; Accessing the memory to be accessed according to the access path adapted by the memory attribute information and the first access request; Among them, the access path adapted by the volatile memory includes the processor cache; The access path adapted for persistent memory does not include the processor cache.

3. The method according to claim 2, It is characterized in that The step of accessing the memory to be accessed according to the access path adapted according to the memory attribute information and the first access request includes: The data to be written contained in the first access request is written into the memory to be accessed according to the access path adapted by the memory attribute information.

4. The method according to claim 3, It is characterized in that The memory attribute information is a volatile memory, and the step of writing the to-be-written data contained in the first access request into the to-be-accessed memory according to the access path adapted by the memory attribute information includes: The data to be accessed is written into the volatile memory through a direct input-output module of the processor.

5. The method according to claim 3, It is characterized in that The memory attribute information is a persistent memory, and writing the to-be-written data contained in the first access request into the to-be-accessed memory according to the access path adapted by the memory attribute information includes: The data to be written is directly written into the persistent memory.

6. The method according to any one of claims 3 to 5, It is characterized in that Before writing the data to be written into the memory to be accessed according to the access path adapted by the memory attribute information, the method further includes: The network card performs protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the communication protocol between the network card and the processor; and provides the second access request to the processor; The step of writing the data to be written into the memory to be accessed according to the access path adapted by the memory attribute information comprises: The processor parses the to-be-written data and the memory attribute information from the second access request; The data to be written is written into the memory to be accessed according to the access path adapted by the memory attribute information.

7. The method according to claim 6, It is characterized in that The network card performs protocol conversion on the first access request according to the memory attribute information, including: Parsing the to-be-written data contained in the first access request from the first access request; The memory attribute information is used as a message header field, and the data to be written is encapsulated according to the communication protocol between the network card and the processor to obtain the second access request.

8. The method according to any one of claims 2 to 5, It is characterized in that Also includes: In response to a power-off event, writing data in the processor cache to the persistent memory.

9. A memory access method, It is characterized in that include: Obtain memory attribute information of the memory to be accessed; Generate an access request according to the memory attribute information; Providing the access request to other computer devices, so that the other computer devices can access the memory to be accessed according to the access path adapted by the memory attribute information; Among them, the access path adapted by the volatile memory includes the processor cache; The access path adapted for persistent memory does not include the processor cache.

10. The method according to claim 9, It is characterized in that The step of generating an access request according to the memory attribute information includes: The processor generates a first access request that complies with a communication protocol between the processor and the network card according to the memory attribute information; and provides the first access request to the network card; The network card parses the first access request to obtain memory attribute information of the memory to be accessed; and performs protocol conversion on the first access request according to the memory attribute information to obtain a second access request that complies with the network protocol.

11. A data processing system, It is characterized in that include: Client devices and server devices; Wherein, the client device is used to: obtain memory attribute information of the memory to be accessed; generate an access request according to the memory attribute information; and provide the access request to the server device; The server device is used to: determine the memory attribute information of the memory to be accessed according to the access request; access the memory to be accessed according to the access path adapted by the memory attribute information and the access request; wherein the access path adapted by the volatile memory includes the processor cache; and the access path adapted by the persistent memory does not include the processor cache.

12. A computer device, It is characterized in that include: Processor, network card, volatile memory and persistent memory; The processor is coupled to the network card, the volatile memory and the persistent memory, and is used to: obtain a first access request through the network card; Determining memory attribute information of the memory to be accessed according to the first access request; Accessing the memory to be accessed according to the access path adapted by the memory attribute information and the first access request; wherein the access path adapted by the volatile memory includes a processor cache; The access path adapted for persistent memory does not include the processor cache.

13. A computer device, It is characterized in that include: Memory, processor and network card; Wherein, the memory is used to store computer programs; The processor is coupled to the memory and the network card, and is used to execute the computer program for: obtaining memory attribute information of the memory to be accessed; generating an access request based on the memory attribute information; providing the access request to other computer devices through the network card, so that the other computer devices can access the memory to be accessed according to the access path adapted by the memory attribute information; wherein the access path adapted by the volatile memory includes the processor cache; and the access path adapted by the persistent memory does not include the processor cache.

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