Nonvolatile memory device, operating method, controller, and storage apparatus

Abstract

A non-volatile memory device includes an array of memory cells including a plurality of memory blocks each including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one memory block among the plurality of memory blocks based on an address, a voltage generator configured to apply word line voltages corresponding to a selected word line and unselected word lines among the plurality of word lines, a page buffer connected to the plurality of bit lines and configured to read data from memory cells connected to a word line among the selected word lines of the selected memory block among the plurality of memory blocks, and control logic configured to control the row decoder, the voltage generator, and the page buffer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0090763, filed on July 22, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to non-volatile storage devices. Background Technology

[0004] Typically, storage devices use error correction code (ECC) circuitry to generate error correction codes during write operations, and then refer to these codes during read operations to correct errors in the data. However, due to the potentially severe degradation of storage cells, there are situations where ECC circuitry cannot correct errors. In such cases, a read retry operation using sensing technology, distinct from normal read operations, can be performed. Summary of the Invention

[0005] One aspect of the present invention is to provide a non-volatile storage device for improving data reliability, a method of operating the device, a controller for controlling the device, and a storage device having the device.

[0006] One aspect of the present invention is to provide a non-volatile storage device for determining cell states, a method of operating the device, a controller for controlling the device, and a storage device having the device.

[0007] One aspect of the present invention is to provide a non-volatile storage device for acquiring cell state information without degrading system performance, a method for operating the device, a controller for controlling the device, and a storage device having the device.

[0008] According to one aspect of the present invention, a non-volatile storage device includes: a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The non-volatile storage device further includes: a row decoder configured to select one memory block among the plurality of memory blocks based on an address; a voltage generator configured to apply word line voltages corresponding to selected and unselected word lines among the plurality of word lines; a page buffer connected to the plurality of bit lines and configured to read data from a memory cell connected to one of the word lines of the selected memory block among the plurality of memory blocks; and control logic configured to control the row decoder, the voltage generator, and the page buffer. The control logic includes a heterogeneous multi-sensor circuit configured to: perform a plurality of sensing operations for at least two threshold voltage distributions under different sensing conditions based on a health check command; and output cell status information corresponding to the performed plurality of sensing operations to an external device.

[0009] According to one aspect of the present invention, a non-volatile memory device includes: a memory cell region having a first metal pad; and a peripheral circuit region having a second metal pad, and connected in a vertical direction to the memory cell region via the first metal pad and the second metal pad. The non-volatile memory device further includes: a memory cell array disposed in the memory cell region, and comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The non-volatile memory device further includes: a row decoder disposed in the peripheral circuit region and configured to select one word line among the plurality of word lines; a page buffer circuit disposed in the peripheral circuit region and including a plurality of page buffers connected to the plurality of bit lines; and control logic disposed in the peripheral circuit region and configured to: receive a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a data strobe (DQS) signal via a control pin; and latch a command or address at the edge of the received WE signal based on the received CLE signal and the received ALE signal to perform heterogeneous multi-sensor operation. The heterogeneous multi-sensor operation includes: a plurality of sensing operations performed for at least two threshold voltage distributions under different sensing conditions.

[0010] According to one aspect of the present invention, a method for operating a non-volatile storage device includes: receiving a health check command; performing heterogeneous multi-sensor operation under different sensing conditions based on the received health check command; and outputting cell status information corresponding to the performed heterogeneous multi-sensor operation to an external device. The heterogeneous multi-sensor operation includes: a plurality of sensing operations performed under the different sensing conditions, and page buffer groups corresponding to the plurality of sensing operations are configured respectively.

[0011] According to one aspect of the present invention, a controller includes: a control pin configured to provide a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a data strobe (DQS) control signal to at least one non-volatile memory device. The controller further includes an error correction circuit configured to receive data from the at least one non-volatile memory device for a first read operation and correct at least one error within the received data. The controller also includes at least one processor configured to: issue a health check command based on the fact that the at least one error in the received data cannot be corrected; send the issued health check command to the at least one non-volatile memory device; receive cell status information corresponding to the sent health check command from the at least one non-volatile memory device; change the read level based on the received cell status information; and perform a second read operation in the at least one non-volatile memory device based on the changed read level.

[0012] According to one aspect of the present invention, a storage device includes at least one non-volatile memory device and a controller. The controller includes control pins configured to provide the at least one non-volatile memory device with a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a data strobe (DQS) signal via the control pins. The controller is also configured to read data from the at least one non-volatile memory device. The at least one non-volatile memory device is configured to: latch a health check command at the edge of a provided WE signal based on the provided CLE and ALE signals to perform a heterogeneous multi-sensor operation, and output cell state information corresponding to the performed heterogeneous multi-sensor operation to the controller. The heterogeneous multi-sensor operation includes multiple sensing operations performed under different sensing conditions for at least two threshold voltage distributions. Attached Figure Description

[0013] The above and other aspects, features and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 This is a diagram illustrating a storage device 10 according to an embodiment of the concept of the present invention.

[0015] Figure 2 It is shown Figure 1 A diagram of the non-volatile storage device 100 is shown.

[0016] Figure 3 It is shown Figure 1 The diagram shows the circuit diagram of one of the memory blocks, BLK1.

[0017] Figure 4 This is a diagram illustrating read levels for identifying threshold voltage distributions in a non-volatile memory device 100, according to an embodiment of the present invention.

[0018] Figure 5A and Figure 5B This is a diagram illustrating heterogeneous multi-sensing operation according to an embodiment of the concept of the present invention.

[0019] Figure 6A , Figure 6B and Figure 6C This diagram illustrates heterogeneous multisensor operation performed on the same word line WLk in the same BLK2 under different read levels RD1 and RD2 or different development times DevT1 and DevT2.

[0020] Figure 7A , Figure 7B and Figure 7C This diagram illustrates heterogeneous multisensor operations performed on different word lines WLk and WLi in the same BLK2 under different read levels RD1 and RD2 or different generation times DevT1 and DevT2.

[0021] Figure 8A , Figure 8B and Figure 8C This diagram illustrates heterogeneous multisensor operations performed on different word lines WLk and WLi in the same BLK2 block under the same read level RD1 or the same generation time DevT1.

[0022] Figure 9A , Figure 9B and Figure 9CThis is a diagram illustrating heterogeneous multisensor operations performed on different word lines WLk and WLi in different blocks BLK1 and BLK2 under different read levels RD1 and RD2 or different generation times DevT1 and DevT2.

[0023] Figure 10 This is a flowchart illustrating heterogeneous multi-sensor operation of a non-volatile storage device 100 according to an embodiment of the present invention.

[0024] Figure 11 This is a diagram illustrating read levels for identifying threshold voltage distributions in a non-volatile memory device 100, according to another embodiment of the concept of the present invention.

[0025] Figure 12A and Figure 12B This is a diagram illustrating a heterogeneous multisensor operation consisting of four sensing operations.

[0026] Figure 13A and Figure 13B This is a diagram illustrating an example of using cell status information to correct the read level.

[0027] Figure 14 This is a diagram illustrating an example of using the distribution characteristics of memory cells connected to adjacent word lines WLi-1 to determine whether reclamation can be performed, according to an embodiment of the present invention.

[0028] Figure 15 This is a diagram illustrating an example of determining whether an adjacent word line WLi+1 is disconnected using the distribution characteristics of memory cells connected to adjacent word lines WLi+1, according to an embodiment of the present invention.

[0029] Figure 16A This is a flowchart illustrating a method of operating a non-volatile storage device 100 according to an embodiment of the present invention.

[0030] Figure 16B This is a flowchart illustrating a method of operating a non-volatile storage device 100 according to another embodiment of the concept of the present invention.

[0031] Figure 17 This is a flowchart illustrating a method for reading from a storage device 10 according to an embodiment of the present invention.

[0032] Figure 18 This is a ladder diagram illustrating the process of optimizing the read level in a compensated storage device 10 according to an embodiment of the present invention.

[0033] Figure 19 This is a diagram illustrating a storage device 20 according to another embodiment of the concept of the present invention.

[0034] Figure 20This is a diagram illustrating a non-volatile storage device 1000 implemented as a C2C structure according to an embodiment of the present invention.

[0035] Figure 21 This is a diagram illustrating a data center employing a storage device according to an embodiment of the concept of the present invention. Detailed Implementation

[0036] Hereinafter, the contents of the present invention will be described clearly and in detail to the extent that those skilled in the art can readily implement it using the accompanying drawings.

[0037] According to embodiments of the present invention, a non-volatile memory device, a controller for controlling the non-volatile memory device, a storage device including the non-volatile memory device, and an operating method for the non-volatile memory device can, in response to a health check command, sample cell state information for at least two threshold voltage distributions, and can use the sampled cell state information to check the health status of the memory cells. In this case, the at least two threshold voltage distributions may correspond to the same word line in the same block, different word lines in the same block, or different word lines in different blocks.

[0038] Figure 1 This is a diagram illustrating a storage device 10 according to an embodiment of the concept of the present invention. (Refer to...) Figure 1 The storage device 10 may include at least one non-volatile storage device NVM 100 and a controller CNTL 200.

[0039] At least one non-volatile memory device 100 can be implemented to store data. The non-volatile memory device 100 can be NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. Furthermore, the non-volatile memory device 100 can be implemented with a three-dimensional array structure. This invention concept can be applied to flash memory devices where the charge storage layer is formed by a conductive floating gate and charge-trapping flash memory (CTF) devices where the charge storage layer is formed by an insulating film. In the following description, for ease of description, the non-volatile memory device 100 will be referred to as a vertical NAND (VNAND) flash memory device.

[0040] Additionally, the non-volatile storage device 100 can be implemented as including multiple storage blocks BLK1 to BLKz (where z is an integer greater than or equal to 2) and control logic 150.

[0041] Each of the multiple storage blocks BLK1 to BLKz can include multiple pages Page 1 to Page m, where m is an integer greater than or equal to 2. Each of the multiple pages Page 1 to Page m can include multiple storage units. Each of the multiple storage units can store at least one bit.

[0042] Control logic 150 can receive commands CMD and addresses ADD from controller CNTL 200, and can be implemented to execute operations (programming operations, read operations, erase operations, etc.) corresponding to the received commands CMD in the memory cell corresponding to address ADD.

[0043] Additionally, the control logic 150 may include a heterogeneous multi-sensor circuit 155. The heterogeneous multi-sensor circuit 155 can be implemented to sample unit state information for at least two threshold voltage distributions by performing sensing operations under different sensing conditions. For example, the heterogeneous multi-sensor circuit 155 may perform a first sensing operation corresponding to a first threshold voltage distribution under a first sensing condition to obtain a first sampled data, and may perform a second sensing operation corresponding to a second threshold voltage distribution under a second sensing condition to obtain a second sampled data. In embodiments, the first sensing condition and the second sensing condition may be different from each other. In embodiments, both the first sensing condition and the second sensing condition may include voltage information (read level, etc.), time information (pre-charge time, generation time, recovery time, etc.), and location information (physical location or the like) for the sensing operation.

[0044] The controller CNTL 200 can be connected to at least one non-volatile memory device 100 via multiple control pins that transmit control signals (e.g., command latch enable (CLE), address latch enable (ALE), chip enable (CE), write enable (WE), read enable (RE), etc.). Furthermore, the controller CNTL 200 can be implemented to control the non-volatile memory device 100 using control signals (CLE, ALE, CE, WE, RE, etc.). For example, the non-volatile memory device 100 can latch a command (CMD) or address (ADD) at the edge of the WE signal based on the CLE and ALE signals to perform heterogeneous multi-sensor operation.

[0045] Additionally, the controller 200 may include a health check module 211. The health check module 211 may be implemented in hardware, software, or firmware. The health check module 211 may be executed by at least one processor in the controller 200.

[0046] Typically, storage devices can use cell state information about the threshold voltage distribution in non-volatile storage devices to improve the reliability of storage cells. Techniques for using such cell state information to improve the reliability of storage cells are available as IP applications filed by Samsung Electronics and described in US 9,437,310, US 9,977,711, US 10,424,388, US2020 / 0151539, US 2020 / 0152279, US10,229,749, US10,381,090, and US10,607,708, which are incorporated herein by reference.

[0047] Typically, to identify the threshold voltage distribution used to set the optimized read level, the storage device can determine on / off cells through a first read operation at a first read level, and then determine on / off cells among those determined to be off cells through a second read operation at a second read level, to output cell count data. As mentioned above, because the method for setting the read level performs two read operations, its performance may be worse than that of the method using a conventional predefined table (PDT).

[0048] The storage device 10 according to an embodiment of the present invention can output cell state information about at least two threshold voltage distributions under different sensing conditions in a single read operation, thereby improving latency performance compared to conventional storage devices.

[0049] Figure 2 It is shown Figure 1 A diagram of the non-volatile storage device 100 is shown. (Refer to...) Figure 2 The non-volatile storage device 100 may include a storage cell array 110, a row decoder 120, a page buffer circuit 130, an input / output (I / O) buffer circuit 140, control logic 150, a voltage generator 160, and a cell counter 170.

[0050] The memory cell array 110 can be connected to the row decoder 120 via word lines WLs or select lines SSL and GSL. The memory cell array 110 can be connected to the page buffer circuit 130 via bit lines BLs. The memory cell array 110 may include multiple cell strings. Each channel of a cell string can be formed in a vertical or horizontal direction. Each cell string may include multiple memory cells. In this case, multiple memory cells can be programmed, erased, or read by providing voltage to the bit lines BLs or word lines WLs. Typically, programming operations can be performed on a page-by-page basis, and erasing operations can be performed on a block-by-block basis.

[0051] Row decoder 120 can be implemented to select any memory block BLK1 to BLK2 of memory cell array 110 in response to address ADD. Row decoder 120 can select any word line of the selected memory block in response to address ADD. Row decoder 120 can transmit the word line voltage VWL corresponding to the operating mode to the word line of the selected memory block. During programming operation, row decoder 120 can apply programming voltage and verification voltage to the selected word line, and can apply a pass voltage to the unselected word line. During read operation, row decoder 120 can apply a read voltage to the selected word line, and can apply a read pass voltage to the unselected word line.

[0052] Page buffer circuit 130 can be implemented as a write driver or a sense amplifier. During a programming operation, page buffer circuit 130 can apply a bit line voltage corresponding to the data to be programmed to the bit lines of memory cell array 110. During a read operation or a verified read operation, page buffer circuit 130 can sense the data stored in a selected memory cell via bit line BL. Multiple page buffers PB1 to PBn (where n is an integer greater than or equal to 2) included in page buffer circuit 130 can each be connected to at least one bit line.

[0053] Multiple page buffers PB1 to PBn can all be implemented to perform sensing and latching for OVS operations. For example, multiple page buffers PB1 to PBn can each perform multiple sensing operations under the control of control logic 150 to identify a state stored in a selected memory cell. Furthermore, after multiple page buffers PB1 to PBn have stored data sensed through multiple sensing operations, data can be selected under the control of control logic 150. For example, multiple page buffers PB1 to PBn can each perform multiple sensing operations to identify a state. Additionally, multiple page buffers PB1 to PBn can each select or output optimized data from the multiple data sensed according to the control of control logic 150.

[0054] The input / output buffer circuit 140 can provide externally supplied data to the page buffer circuit 130. The input / output buffer circuit 140 can provide externally supplied commands (CMD) to the control logic 150. The input / output buffer circuit 140 can provide externally supplied addresses (ADD) to the control logic 150 or the row decoder 120. Additionally, the input / output buffer circuit 140 can output data sensed and latched by the page buffer circuit 130 to the outside.

[0055] Control logic 150 can be implemented to control line decoder 120 and page buffer circuit 130 in response to command CMD sent from an external source.

[0056] Control logic 150 may include heterogeneous multi-sensor circuitry 155, which is used in response to a health check command (HCCMD, see below) Figure 1 This is used to obtain cell state information about at least two threshold voltage distributions.

[0057] The heterogeneous multi-sensor circuit 155 can be implemented to control the page buffer circuit 130 and the voltage generator 160 to perform heterogeneous multi-sensor operation. In this case, the heterogeneous multi-sensor operation can include sensing operations for at least two threshold voltage distributions under different sensing conditions. Additionally, the heterogeneous multi-sensor circuit 155 can control multiple page buffers PB1 to PBn to store sensing data corresponding to each result of the multiple sensing operations in multiple latch sets disposed in each of the multiple page buffers PB1 to PBn.

[0058] For example, the heterogeneous multi-sensor circuit 155 can, in response to a health check command HCCMD, perform a first sensing operation at a first read level for a first threshold voltage distribution for a first memory cell corresponding to a first page buffer group (e.g., an odd-numbered page buffer), and can, in response to the health check command HCCMD, perform a second sensing operation at a second read level for a second threshold voltage distribution for a second memory cell corresponding to a second page buffer group (e.g., an even-numbered page buffer). The heterogeneous multi-sensor circuit 155 can send data to the controller 200 (see [link to controller 200]). Figure 1 The output is the on / off unit information stored in the first page buffer group according to the first sensing operation and the on / off unit information stored in the second page buffer group according to the second sensing operation, as the unit status information corresponding to the health check command HCCMD.

[0059] Control logic 150 can be implemented to perform processing for selecting optimized data from multiple sensing data. To select optimized data, control logic 150 can refer to the counting result nC provided from unit counter 170.

[0060] Voltage generator 160 can be implemented, under the control of control logic 150, to generate various types of word line voltages to be applied to word lines and well voltages to be supplied to the bulk (e.g., well region) forming the memory cell. The word line voltages applied to the word lines may include programming voltage, pass voltage, read voltage, read pass voltage, etc.

[0061] Cell counter 170 can be implemented to count the number of memory cells corresponding to a threshold voltage range based on data sensed by page buffer circuit 130. For example, cell counter 170 can process data sensed in multiple page buffers PB1 to PBn respectively to count the number of memory cells having a threshold voltage within the threshold voltage range.

[0062] According to an embodiment of the present invention, the non-volatile storage device 100 can perform heterogeneous multi-sensor operation in response to a health check command HCCMD to output cell state information about the threshold voltage distribution in a single read operation.

[0063] Figure 3 It is shown Figure 1 The diagram shows the circuit diagram of memory block BLK1, one of the memory blocks shown. (Refer to...) Figure 3 The diagram illustrates a first storage block BLK1 with a three-dimensional structure. The first storage block BLK1 may include multiple cell strings CS11, CS12, CS21, and CS22. These cell strings can be arranged along both row and column directions to form rows and columns.

[0064] In this embodiment, unit strings CS11 and CS12 can be connected to string select lines SSL1a and SSL1b to form a first row. Unit strings CS21 and CS22 can be connected to string select lines SSL2a and SSL2b to form a second row. For example, unit strings CS11 and CS21 can be connected to the first bit line BL1 to form a first column. Unit strings CS12 and CS22 can be connected to the second bit line BL2 to form a second column.

[0065] Multiple cell strings CS11, CS12, CS21, and CS22 may each include multiple cell transistors. For example, multiple cell strings CS11, CS12, CS21, and CS22 may each include string select transistors SSTa and SSTb, multiple memory cells MC1 to MC8, ground select transistors GSTA and GSTb, and dummy memory cells DMC1 and DMC2. For example, the multiple cell transistors included in multiple cell strings CS11, CS12, CS21, and CS22 may each be charge-trapped flash memory (CTF) cells.

[0066] Multiple memory cells MC1 to MC8 can be connected in series and stacked in a height direction perpendicular to the plane formed by the row and column directions. Serial select transistors SSTa and SSTb can be connected in series, and the series-connected serial select transistors SSTa and SSTb can be positioned between the multiple memory cells MC1 to MC8 and the bit line BLs. Ground select transistors GSTA and GSTb can be connected in series, and the series-connected ground select transistors GSTA and GSTb can be positioned between the multiple memory cells MC1 to MC8 and the common source line CSL.

[0067] In an embodiment, the first dummy memory cell DMC1 can be disposed between the plurality of memory cells MC1 to MC8 and the ground selection transistors GSTA and GSTb. For example, the second dummy memory cell DMC2 can be disposed between the plurality of memory cells MC1 to MC8 and the string selection transistors SSTa and SSTb.

[0068] The ground selection transistors GSTA and GSTb of cell strings CS11, CS12, CS21, and CS22 can be connected together to the ground selection line GSL. For example, ground selection transistors in the same row can be connected to the same ground selection line, while ground selection transistors in different rows can be connected to different ground selection lines. For example, the first ground selection transistor GSTA of cell strings CS11 and CS12 in the first row can be connected to the first ground selection line. Similarly, among the second string selection transistors SSTb of the same height, string selection transistors in the same row can be connected to the same string selection line, while string selection transistors in different rows can be connected to different string selection lines. For example, the second string selection transistors SSTb of cell strings CS11 and CS12 in the first row can be connected together to the string selection line SSL1b, and the second string selection transistors SSTb of cell strings CS21 and CS22 in the second row can be connected together to the string selection line SSL2b.

[0069] The string select transistors of the same row of cells can be connected to the same string select line. For example, the first string select transistor SSTa and the second string select transistor SSTb of cells CS11 and CS12 in the first row can be connected to the same string select line. Similarly, the first string select transistor SSTa and the second string select transistor SSTb of cells CS21 and CS22 in the second row can be connected to the same string select line.

[0070] In this embodiment, dummy memory cells with the same height can be connected to the same dummy word line, while dummy memory cells with different heights can be connected to different dummy word lines. For example, the first dummy memory cell DMC1 can be connected to the first dummy word line DWL1, and the second dummy memory cell DMC2 can be connected to the second dummy word line DWL2.

[0071] In the first memory block BLK1, erase operations can be performed on a block-by-block or sub-block basis. When an erase operation is performed on a block-by-block basis, all memory cells MC of the first memory block BLK1 can be erased simultaneously according to a single erase request. When performed on a sub-block basis, a portion of the memory cells MC of the first memory block BLK1 can be erased simultaneously according to a single erase request, and erase operations on other memory cells within it can be disabled. A low voltage (e.g., ground voltage) can be supplied to the word lines connected to the erased memory cells, and word lines connected to memory cells that are disabled from being erased can be floated.

[0072] Figure 3 The first memory block BLK1 shown is illustrative. According to the present invention, the lines GSL, WL, DWL, SSL, etc. connected to the cell transistors are not limited by the number of cell strings, rows, columns, or the number of cell transistors (GST, MC, DMC, SST, etc.).

[0073] Figure 4 This is a diagram illustrating read levels for identifying threshold voltage distributions in a non-volatile memory device 100, according to an embodiment of the present invention. (Refer to...) Figure 4 Eight (8) states E and P1 to P7 are shown. In order to identify the threshold voltage distribution of the memory cells of the non-volatile memory device 100, it may be necessary to have first cell state information corresponding to the erase state E and second cell state information corresponding to the highest programming state P7.

[0074] In this embodiment, the first unit state information may include conduction unit information (or first multiple sampled data) of a first sensing operation based on a first read level. In this case, the first read level may be the read level RD1 corresponding to the erase state E.

[0075] In this embodiment, the second unit state information may include shutdown unit information (or second multiple sampled data) based on a second sensing operation according to a second read level. In this case, the second read level may be the read level RD2 corresponding to the highest programming state P7.

[0076] Understandably, in Figure 4 In this paper, the erase state E and programming state P7 selected for identifying the threshold voltage distribution are merely illustrative. In the present invention, at least two states can be selected in various ways to identify the threshold voltage distribution.

[0077] The non-volatile storage device 100 according to an embodiment of the present invention can output multiple sampled data for identifying cell distribution through heterogeneous multi-sensor operation. In this case, in heterogeneous multi-sensor operation, data sensed under various conditions can be sampled in a single page. For this purpose, the page buffer circuit 130 (see...) Figure 1 The data can be divided into two or more page buffer groups. Each page buffer group can store multiple sampled data points sensed under different conditions. The non-volatile storage device 100 can output multiple sampled data points from each page buffer group for direct memory access (DMA) with a single page size.

[0078] Figure 5A and Figure 5B This is a diagram illustrating heterogeneous multi-sensor operation according to an embodiment of the concept of the present invention.

[0079] Reference Figure 5A A word line that needs to read data from a single word line at two read levels can be set to the first read level, and then the word line can be sensed by the first page buffer in the page buffer, and the sensed first multiple sample data can be stored in a latch.

[0080] Afterwards, the word line can be set to the second read level, and then the word line can be sensed through the second page buffer in the page buffer, and the sensed second multiple sample data can be stored in the latch.

[0081] In an embodiment, when outputting read data, the first multiple sampled data read by the first sensing operation at the first read level can be output first through the data output line, and the second multiple sampled data read by the second sensing operation at the second read level can be output continuously.

[0082] In one embodiment, the size of the data stored in the page buffer can be 16KB. The size of the page buffer in this invention is not limited to this. In another embodiment, the size of the first and second plurality of sampled data can be 8KB. The size of the plurality of sampled data in this invention is not limited to this.

[0083] like Figure 5A As shown, after performing the page buffer initialization operation (PBInit) for the first sensing operation, the first sensing operation with the first read level can be performed (1). st After performing a latching operation on the first plurality of sampled data according to the first sensing operation, a recovery operation (Rcy) can be performed. In this case, the latching operation may include sending data from the sensing latch to the data latch. Then, a second sensing operation (2) can be performed according to the second read level.nd The page buffer initialization operation (sensing) is performed. Afterwards, a recovery operation can be performed after latching the second plurality of sampled data according to the second sensing operation.

[0084] In an embodiment, after the latching operation is completed, the Ready & Busy (RnB, also known as "Ready & Busy") signal RnB (e.g., RnBx) can return from low to high. In an embodiment, after the recovery operation, the RnB signal RnB (e.g., RnBi) can internally return from low to high.

[0085] In this embodiment, after the RnB signal returns from low to high, the first multiple sampled data of the first page buffer group can be output as the first read level data, and then the second multiple sampled data of the second page buffer group can be output as the second read level data.

[0086] Figure 5A This demonstrates heterogeneous multi-sensor operation achieved using two single-level cell (SLC) readouts. The inventive concept can also be realized using multi-level cell readouts.

[0087] Figure 5B This illustrates heterogeneous multi-sensor operation to be implemented using a single triple-level cell (TLC) readout. (See reference...) Figure 5B ,and Figure 5A In contrast, heterogeneous multisensor operation implemented via TLC reading may not include latching operation based on the first sensing operation, recovery operation based on the first sensing operation, and page buffer initialization operation for the second sensing operation.

[0088] Typically, as NAND flash memory generations advance and cell sizes shrink, cells may become more prone to degradation, potentially leading to decreased performance and reliability. To compensate for this, read levels can be appropriately corrected as needed. A defensive code technique that uses machine learning to analyze cell distribution and determine read levels based on the shape of the analyzed distribution can be disclosed. Therefore, numerous additional read operations may be required to identify the cell distribution. Figure 1 The non-volatile memory devices in the embodiments can use heterogeneous multi-sensor technology to analyze cell distribution more quickly.

[0089] Typically, defense coding techniques can be a method of selecting an optimized read level table for the current cell distribution from multiple predefined tables (PDTs). Conventional AI defense coding techniques identify the cell distribution by performing two SLC read operations, and then select an optimized read level. This can result in longer latency compared to using a PDT based on two SLC read operations. The present invention aims to improve this latency by performing a single read operation based on heterogeneous multi-sensor operations, quickly providing optimized read levels in a single product without burdening the system.

[0090] The non-volatile memory device 100 according to an embodiment of the present invention can sample data at two or more read levels within a single ready & busy signal and can output the sampled data. For example, when data read at two read levels is required to identify a threshold voltage distribution, the controller 200 can perform heterogeneous multi-sensing operation in the non-volatile memory device 100, thereby performing sensing operation in a first output unit (e.g., 8K), and can retrieve a first plurality of sampled data (DMA1) from a first page buffer group. st Data), can be extracted from the second page buffer group of the second DMA to retrieve the second multiple sampled data (DMA2). nd Data).

[0091] exist Figure 5A and Figure 5B The heterogeneous multi-sensing operation shown may include two sensing operations on a single word line. It is understood that the heterogeneous multi-sensing operation of the present invention is not limited thereto. The heterogeneous multi-sensing operation of the present invention can store cell state information sampled in multiple page buffer groups in a single page buffer circuit 130 according to various combinations of at least one read level, at least one generation time, at least one word line, and at least one block. For example, each page buffer group of page buffer circuit 130 can store multiple sampled data according to various combinations through the heterogeneous multi-sensing operation and can output them separately. The non-volatile memory device 100 according to embodiments of the present invention can output multiple sampled data corresponding to different sensing conditions in a single ready & busy and a single page DMA, instead of a single user data.

[0092] The heterogeneous multisensor operation performed under various conditions will be described below.

[0093] Figure 6A , Figure 6B and Figure 6C This diagram illustrates heterogeneous multisensor operation performed on the same word line WLk in the same BLK2 under different read levels RD1 and RD2 or different generation times DevT1 and DevT2.

[0094] like Figure 6A As shown, the first sensing operation can be performed at the first read level RD1 or within the first generation time DevT1 in the bit lines BL1, BL3, BL5 and BL7 connected to the odd-numbered page buffers PB1, PB3, PB5 and PB7, and in the memory cells connected to the word line WLk in the second block BLK2.

[0095] like Figure 6B As shown, the second sensing operation can be performed at the second read level RD2 or within the second generation time DevT2 in the bit lines BL2, BL4, BL6 and BL8 connected to the even-numbered page buffers PB2, PB4, PB6 and PB8, and in the memory cells connected to the word line WLk in the second block BLK2.

[0096] like Figure 6C As shown, after the heterogeneous multi-sensor operation, the first multi-sample data 1 st R-Data can be stored in the first page buffer group PB1, PB3, PB5, and PB7, and the second multiple sampled data 2 nd R-Data can be stored in the second page buffer groups PB2, PB4, PB6, and PB8.

[0097] Figure 7A , Figure 7B and Figure 7C This diagram illustrates heterogeneous multisensor operations performed on different word lines WLk and WLi in the same BLK2 under different read levels RD1 and RD2 or different generation times DevT1 and DevT2.

[0098] Reference Figure 7A , Figure 7B and Figure 7C In heterogeneous multi-sensor operation, with Figure 6A , Figure 6B and Figure 6C The difference, as shown, is that the second sensing operation can be performed using memory cells in the same BLK2 connected to different word lines WLi.

[0099] Figure 8A , Figure 8B and Figure 8C This diagram illustrates heterogeneous multisensor operations performed on different word lines WLk and WLi in the same BLK2 block under the conditions of the same read level RD1 or the same generation time DevT1.

[0100] Reference Figure 8A , Figure 8B and Figure 8C In heterogeneous multi-sensor operation, with Figure 7A, Figure 7B and Figure 7C The difference, as shown, is that the second sensing operation can be performed at the same read level RD1 or at the same generation time.

[0101] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating heterogeneous multisensor operations performed on different word lines WLk and WLi in different blocks BLK1 and BLK2 under different read levels RD1 and RD2 or different generation times DevT1 and DevT2.

[0102] Reference Figure 9A , Figure 9B and Figure 9C In heterogeneous multi-sensor operation, with Figure 7A , Figure 7B and Figure 7C The difference, as shown, is that a second sensing operation can be performed on memory cells in the first block BLK1 that are connected to different word lines WLi corresponding to word lines WLk of a block BLK2.

[0103] Understandable Figures 6A to 9C The heterogeneous multi-sensor operation described herein is merely illustrative. In the heterogeneous multi-sensor operation of this invention, multiple sensing operations can be performed in a single read operation (single command) under various sensing conditions.

[0104] Figure 10 This is a flowchart illustrating heterogeneous multi-sensor operation of a non-volatile memory device 100 according to an embodiment of the present invention. (Refer to...) Figures 1 to 10 The heterogeneous multi-sensor operation of the non-volatile storage device 100 can be performed as follows.

[0105] From controller 200 (see Figure 1 ) Receives health check commands for heterogeneous multi-sensor operation (HCCMD, see Figure 1 (S110). In this case, the health check command HCCMD may include location information for performing heterogeneous multi-sensor operations. In one embodiment, the location information for the first sensing operation may be the same as the location information for the second sensing operation. In another embodiment, the location information for the first sensing operation may be different from the location information for the second sensing operation. The page buffer may be initialized in response to the health check command HCCMD (S111).

[0106] Next, a first sensing condition for the first sensing operation can be set (S112). A first sensing operation corresponding to the first page buffer group can be executed based on the first sensing condition (S113). Next, a second sensing condition for the second sensing operation can be set (S114). A second sensing operation corresponding to the second page buffer group can be executed based on the second sensing condition (S115). Then, a recovery operation can be performed (S116). After the recovery operation, the RnB signal can be returned to the controller 200 (S117).

[0107] Then, a first plurality of sampled data based on the first sensing condition can be output from the first page buffer group (S118), and a second plurality of sampled data based on the second sensing condition can be output from the second page buffer group (S119).

[0108] According to embodiments of the present invention, non-volatile storage devices can output three or more sampled data in heterogeneous multi-sensor operation.

[0109] Figure 11 This is a diagram illustrating read levels for identifying threshold voltage distributions in a non-volatile memory device 100, according to another embodiment of the concept of the present invention.

[0110] Reference Figure 11 To identify the threshold voltage distribution, a first read level RD1 and a second read level RD2 corresponding to the erase state E can be used, and a third read level RD3 and a fourth read level RD4 corresponding to the highest state P7 can be used.

[0111] Figure 12A and Figure 12B This is a diagram illustrating a heterogeneous multisensor operation consisting of four sensing operations.

[0112] Reference Figure 12A In response to a health check command, HCCMD can perform four (4) sensing operations (1) based on different sensing conditions. st Sensing up to 4 th (Sensing), and can output multiple sampled data (R-Data1 to R-Data4) based on the sensing operation.

[0113] Reference Figure 12BIt can perform four (4) sensing operations based on different sensing conditions in response to the health check command HCCMD, and can store calculated values ​​for multiple sampled data in the four (4) sensing operations. In an embodiment, the result value based on the first sensing operation and the second sensing operation can be calculated and stored in a first page buffer group, and the result value based on the third sensing operation and the fourth sensing operation can be calculated and stored in a second page buffer group.

[0114] Then, the computed data stored in the first page buffer group and the computed data stored in the second page buffer group can be output as cell status information with a single page size corresponding to the health check command HCCMD.

[0115] The storage device 10 according to an embodiment of the present invention can use cell state information to optimize read levels.

[0116] Figure 13A and Figure 13B This diagram illustrates an example of using cell status information to correct read levels. (Example) Figure 13A As shown, the heterogeneous multi-sensor operation of the non-volatile memory device 100 can output cell state information below the first read level in the erase state E and cell state information above the second read level in the highest programming state P7. In an embodiment, the cell state information may include count information corresponding to the threshold voltage distribution.

[0117] Controller 200 (reference) Figure 1 The cell status information received from the non-volatile storage device 100 can be used to identify the distributed degradation characteristics of the storage cells and change the existing read level to an optimized read level.

[0118] According to an embodiment of the present invention, the storage device 10 can perform recycling using cell status information of the storage cell connected to the word line WLi-1 adjacent to the selected word line WLi.

[0119] Figure 14 This is a diagram illustrating an example of using the distribution characteristics of memory cells connected to adjacent word lines WLi-1 to determine whether to perform a reclamation, according to an embodiment of the present invention. Figure 14 As shown, when the first read level E under The following is an example of a first unit count value NC1 being lower than a first reference value, or a second read level P7. upper When the second cell count value NC2 is lower than the second reference value, it can be determined that the degradation is severe. In this case, the data in the memory cell connected to the selected word line WLi can be recycled to the memory cell connected to another word line.

[0120] According to an embodiment of the present invention, the storage device 10 can use the cell status information of the storage cell connected to the word line WLi+1 adjacent to the selected word line WLi to determine whether the adjacent word line is disconnected.

[0121] Figure 15 This diagram illustrates an example of determining whether adjacent word lines WLi+1 are disconnected using the distribution characteristics of memory cells connected to adjacent word lines WLi+1, according to an embodiment of the present invention. Figure 15 As shown, when the read level P7 corresponds to the highest programming state P7 upper When the cell count value NC2 of a higher read level is zero (0), the adjacent word line WLi+1 can be identified as a disconnected word line.

[0122] Figure 16A This is a flowchart illustrating a method of operating a non-volatile storage device 100 according to an embodiment of the present invention. (Refer to...) Figures 1 to 16A The operation of the non-volatile storage device 100 can be performed as follows.

[0123] Storage device 10 can perform operations to improve data reliability in response to external or internal requests. To this end, storage device 10 can first identify the state of the threshold voltage distribution of the storage cells. Controller 200 can issue a health check command HCCMD and send it to non-volatile storage device 100. Non-volatile storage device 100 can periodically or irregularly receive the health check command HCCMD from controller 200 (S210).

[0124] The non-volatile storage device 100 can perform heterogeneous multi-sensor operation (S220) in response to the health check command HCCMD. In this case, multiple sampled data corresponding to the threshold voltage distribution according to the heterogeneous multi-sensor operation can be stored in each page buffer group.

[0125] Then, multiple sampled data stored in each page buffer group can be output to the controller 200 (S230) as unit status information corresponding to the health check command HCCMD.

[0126] It can also calculate and output multiple sampling data of heterogeneous multi-sensor operation according to an embodiment of the present invention.

[0127] Figure 16B This is a flowchart illustrating a method of operating a non-volatile storage device 100 according to another embodiment of the concept of the present invention. (Refer to...) Figures 1 to 16B ,and Figure 16ACompared to the operation of a non-volatile memory device, the operation of the non-volatile memory device 100 may further include calculating the sensing result value (S225). The calculated result value may be stored in a page buffer group, and the data stored in the page buffer group may be output to the controller 200 as cell status information.

[0128] Figure 17 This is a flowchart illustrating a method for reading from a storage device 10 according to an embodiment of the present invention. (Refer to...) Figures 1 to 17 The read operation of storage device 10 can be performed as follows.

[0129] In response to controller 200 (see Figure 1 The read command sent by the non-volatile storage device 100 ( Figure 1 The first read operation can be performed using the default read voltage level (S310). In this case, information corresponding to the default read voltage level can be sent from the controller 200 along with the read command.

[0130] As a result of the first read operation, the controller 200 can determine whether an uncorrectable error correction code (UECC) has occurred (S320). If no UECC has occurred, the read operation can be completed. If a UECC has occurred, the non-volatile storage device 100 can perform a heterogeneous multi-sensor operation in response to a health check command HCCMD sent from the controller 200 (S330). The controller 200 can receive cell status information from the non-volatile storage device 100 according to the heterogeneous multi-sensor operation (S340). The controller 200 can use the received cell status information to adjust the default read level to an optimized default read level (S350). Then, the controller 200 can send a read command to the non-volatile storage device 100 using the optimized default read level. Afterwards, the non-volatile storage device 100 can use the optimized default read level to perform a second read operation (S360).

[0131] In an embodiment, the non-volatile memory device 100 can output multiple sampled data corresponding to word line positions or bit line positions to a controller based on multiple sensing operations for at least two threshold voltage distributions.

[0132] In an embodiment, the non-volatile storage device 100 can sample data corresponding to at least two threshold voltage distributions at at least two read levels within a single ready & busy signal, and can output the sampled data.

[0133] In one embodiment, the controller 200 may use machine learning to issue health check commands and may output the issued health check commands to the non-volatile storage device 100.

[0134] Figure 18 This is a ladder diagram illustrating the process of compensating for and optimizing read levels in a storage device 10 according to an embodiment of the present invention. (Refer to...) Figures 1 to 18 The read operation of storage device 10 can be performed as follows.

[0135] A read request for storage device 10 can be received from the host (S30). The controller CNTL can issue a normal or historical read command corresponding to the read request, and can send the normal or historical read command to the non-volatile storage device NVM (S31). In this case, the normal or historical read command may include a default read level. In an embodiment, during a historical read operation, the default read voltage level can be determined using the read voltage level offset information of the historical read table.

[0136] Subsequently, the non-volatile storage device NVM can perform a read operation using the default read level in response to a normal / historical read command. The read data based on the read operation can be output to the controller CNTL (S32).

[0137] Subsequently, the controller CNTL can determine whether the read data received from the non-volatile memory device NVM has passed the error correction circuit ECC (S33). If it has passed the error correction circuit ECC, the read data can be sent to the host to complete the read operation (S34-1). If it has not passed the error correction circuit ECC, the controller CNTL can issue a read retry command to the non-volatile memory device NVM and can send a read retry command to the non-volatile memory device NVM (S34-2). The non-volatile memory device NVM can perform the read operation in a predetermined manner (e.g., on-chip valley search method) in response to the read retry command. Afterwards, the read data corresponding to the read retry command can be output to the controller CNTL (S35).

[0138] Afterwards, the controller CNTL can again determine whether the read data received from the non-volatile storage device NVM has passed through the error correction circuit ECC (S36). When there is no error or error correction is possible, the read data can be output to the host (S37), and the read operation can be completed.

[0139] If the error correction circuit ECC fails again, the controller CNTL can issue a health check command HCCMD and send the issued health check command HCCMD to the non-volatile storage device NVM (S38). The non-volatile storage device NVM can perform heterogeneous multi-sensor operation in response to the health check command HCCMD and can output the cell status information corresponding to the execution result to the controller CNTL (S39).

[0140] The controller CNTL can use cell status information to update the historical read table (S40). For example, the controller CNTL can use cell status information to optimize and correct the default read level.

[0141] Subsequently, the controller CNTL can issue a history read command at the corrected history read level and can send the issued history read command to the non-volatile storage device NVM (S41).

[0142] Subsequently, the non-volatile storage device (NVM) can perform a read operation using the corrected default read level in response to a historical read command. The read data obtained from this read operation can then be output to the controller CNTL (S42). Afterward, the read data can be output to the host (S43).

[0143] Subsequently, when a new read request for the same location is received from the host (S44), a history read command with the changed default read level can be sent to the non-volatile storage device NVM (S45). Afterwards, the read operation of the non-volatile storage device NVM will be performed as described above.

[0144] The health check operation for non-volatile storage devices according to embodiments of the present invention can be performed by a separate processor for artificial intelligence.

[0145] Figure 19 This is a diagram illustrating a storage device 20 according to another embodiment of the concept of the present invention. (Refer to...) Figure 19 The storage device 20 may include at least one non-volatile storage device 100 and a controller 200a for controlling the non-volatile storage device.

[0146] The controller CNTL 200a can be connected to at least one non-volatile memory device 100 via multiple control pins that transmit control signals (e.g., CLE, ALE, CE, WE, RE, etc.). Furthermore, the control signals (e.g., CLE, ALE, CE, WE, RE, etc.) can be implemented to control the non-volatile memory device 100. For example, the non-volatile memory device 100 can latch a command or address at the edge of the write enable (WE) signal based on the command latch enable (CLE) signal and the address latch enable (ALE) signal to perform heterogeneous multi-sensor operation.

[0147] The controller 200a can be implemented to control the overall operation of the storage device 20. The controller 200a can perform various management operations such as: cache / buffer management, firmware management, garbage collection management, wear leveling management, data replication and removal management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read voltage level management, erase / programming management, hot / cold data management, power failure protection management, dynamic thermal management, initialization management, and redundant array of independent disks (RAID) management, etc.

[0148] Additionally, controller 200a may include an artificial intelligence processor 212 and error correction circuitry 230. The artificial intelligence processor 212 may be implemented to perform operations using artificial intelligence. Figures 1 to 18 The health check procedure described in the document is used to perform optimization procedures based on the results.

[0149] ECC circuit 230 can be implemented to generate error correction codes during programming operations and use the error correction codes to recover data DATA during read operations. For example, ECC circuit 230 can generate error correction codes (ECC) to correct fault bits or error bits in data DATA received from non-volatile storage device 100. ECC circuit 230 can perform error correction coding on data provided to non-volatile storage device 100 to form data DATA with parity bits added. Parity bits can be stored in non-volatile storage device 100. Additionally, ECC circuit 230 can perform error correction decoding on data DATA output from non-volatile storage device 100. ECC circuit 230 can use parity bits to correct errors. ECC circuit 230 can use coding modulation such as low-density parity-check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., to correct errors.

[0150] The non-volatile memory device according to embodiments of the present invention can be implemented having a chip-to-chip (C2C) structure.

[0151] Figure 20 A non-volatile storage device 1000 implemented in a C2C architecture according to an example embodiment is shown.

[0152] A C2C structure can refer to: fabricating an upper chip including cell regions (CELLs) on a first wafer and fabricating a lower chip including peripheral circuit regions (PERIs) on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process can be a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip to bonding metals formed on the topmost metal layer of the lower chip. In an example embodiment, when the bonding metal includes copper (Cu), copper-copper bonding is used. However, in an example embodiment, this is not a limitation. For example, the bonding metal can be formed of aluminum (Al) or tungsten (W).

[0153] The peripheral circuit region PERI and cell region CELL of the non-volatile memory device 1000 can each include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0154] The Peripheral Circuit Region (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c disposed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c disposed on the first metal layers 1230a, 1230b, and 1230c. In an example embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten (W) having relatively high resistance. In an example embodiment, the second metal layers 1240a, 1240b, and 1240c may be formed of copper (Cu) having relatively low resistance.

[0155] exist Figure 20 The diagram shows first metal layers 1230a, 1230b, and 1230c and second metal layers 1240a, 1240b, and 1240c, but this disclosure is not limited thereto. One or more additional metal layers may also be provided on metal layers 1240a, 1240b, and 1240c. At least some of the one or more additional metal layers provided on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum (Al) or similar materials with a resistance lower than that of copper (Cu) forming the second metal layers 1240a, 1240b, and 1240c.

[0156] In an example embodiment, an interlayer insulating layer 1215 may be disposed on a first substrate 1210 to cover a plurality of circuit elements 1220a, 1220b, and 1220c, first metal layers 1230a, 1230b, and 1230c, and second metal layers 1240a, 1240b, and 1240c. In an example embodiment, the interlayer insulating layer 1215 may include an insulating material such as silicon oxide or silicon nitride.

[0157] Lower bonding metals 1271b and 1272b can be disposed on the second metal layer 1240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 1271b and 1272b of the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 1371b and 1372b of the cell area (CELL) using a bonding method. In an example embodiment, the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum (Al), copper (Cu), tungsten (W), etc. Furthermore, the upper bonding metals 1371b and 1372b in the cell area (CELL) can be referred to as first metal pads, while the lower bonding metals 1271b and 1272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0158] A cell region (CELL) may include at least one memory block. In an example embodiment, the cell region (CELL) may include a second substrate 1310 and a common source line 1320. Multiple word lines 1331 to 1338 (collectively referred to as 1330) may be stacked on the second substrate 1310 in a direction perpendicular to the upper surface of the second substrate 1310 (Z-axis direction). In an example embodiment, a serial select line and a ground select line may be disposed above and below the word line 1330, respectively. In an example embodiment, multiple word lines 1330 may be disposed between the serial select line and the ground select line.

[0159] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 1310 (Z-axis direction) to penetrate the word line 1330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc. The channel layer can be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact, and the second metal layer 1360c can be a bit line. In an example embodiment, the bit line 1360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 1310.

[0160] like Figure 20As shown, the region where the channel structure CH and bit line 1360c are provided can be defined as the bit line bonding region BLBA. In the example embodiment, in the bit line bonding region BLBA, bit line 1360c can be electrically connected to circuit element 1220c that provides page buffer 1393 in peripheral circuit region PERI. Bit line 1360c can be connected to upper bonding metals 1371c and 1372c in cell region CELL. Upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c that are connected to circuit element 1220c of page buffer 1393.

[0161] In the word line bonding area (WLBA), word lines 1330 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 1310 and perpendicular to the first direction. In an example embodiment, word lines 1330 may be connected to a plurality of cell contact plugs 1341 to 1347 (collectively referred to as 1340). For example, word lines 1330 and cell contact plugs 1340 may be connected to each other on pads, wherein at least some word lines 1330 are configured to extend at different lengths in the second direction. In an example embodiment, a first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portion of the cell contact plugs 1340 connected to the word lines 1330. In an example embodiment, in the word line bonding area (WLBA), cell contact plugs 1340 may be connected to the peripheral circuitry area (PERI) via upper bonding metals 1371b and 1372b in the cell region (CELL) and lower bonding metals 1271b and 1272b in the peripheral circuitry area (PERI).

[0162] In an example embodiment, cell contact plug 1340 may be electrically connected to circuit element 1220b forming row decoder 1394 in peripheral circuit region PERI. In an example embodiment, the operating voltage of circuit element 1220b forming row decoder 1394 may differ from the operating voltage of circuit element 1220c forming page buffer 1393. For example, the operating voltage of circuit element 1220c forming page buffer 1393 may be higher than the operating voltage of circuit element 1220b forming row decoder 1394.

[0163] A common source line contact plug 1380 may be disposed in the external pad bonding region PA. In an example embodiment, the common source line contact plug 1380 may be formed of a conductive material such as a metal, a metal compound, or polysilicon. The common source line contact plug 1380 may be electrically connected to a common source line 1320. A first metal layer 1350a and a second metal layer 1360a may be sequentially stacked on the common source line contact plug 1380. For example, the region in which the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed may be defined as the external pad bonding region PA.

[0164] Input / output pads 1205 and 1305 can be set in the external pad bonding area PA. (See reference...) Figure 20 A lower insulating layer 1201 may be disposed below the first substrate 1210 to cover the lower surface of the first substrate 1210. A first input / output pad 1205 may be disposed on the lower insulating layer 1201. In an example embodiment, the first input / output pad 1205 may be connected via a first input / output contact plug 1203 to any one or any combination of a plurality of circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI. In an example embodiment, the first input / output pad 1205 may be separated from the first substrate 1210 by the lower insulating layer 1201. Additionally, a side insulating layer may be disposed between the first input / output contact plug 1203 and the first substrate 1210 to electrically separate the first input / output contact plug 1203 from the first substrate 1210. In an example embodiment, a second input-output pad 1305 is electrically connected to circuit element 1220a.

[0165] Reference Figure 20 An upper insulating layer 1301 may be disposed on the second substrate 1310 to cover the upper surface of the second substrate 1310. A second input / output pad 1305 may be disposed on the upper insulating layer 1301. In an example embodiment, the second input / output pad 1305 may be connected via a second input / output contact plug 1303 to any one or any combination of a plurality of circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI. For example, the second input / output pad 1305 may be electrically connected to circuit element 1220a via the second input / output contact plug 1303 through metal patterns 1272a and 1271a.

[0166] In the example embodiment, the second substrate 1310, common source line 1320, etc., may not be located in the area where the second input / output contact plug 1303 is disposed. The second input / output pad 1305 may not overlap with the word line 1330 in the third direction (Z-axis direction). (Refer to...) Figure 20The second input / output contact plug 1303 may be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310. Furthermore, the second input / output contact plug 1303 may be connected to the second input / output pad 1305 through the interlayer insulating layer 1315 in the cell region.

[0167] In an example embodiment, the first input / output pad 1205 and the second input / output pad 1305 can be selectively provided. For example, the non-volatile memory device 1000 may include only the first input / output pad 1205 disposed on the first substrate 1210, or only the second input / output pad 1305 disposed on the second substrate 1310. In another example embodiment, the non-volatile memory device 1000 may include both the first input / output pad 1205 and the second input / output pad 1305.

[0168] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern set on the top metal layer may exist as a dummy pattern or may not exist.

[0169] In the external pad bonding area PA, the non-volatile memory device 1000 according to the example embodiment may include a lower metal pattern 1273a disposed on the uppermost metal layer in the peripheral circuit area PERI, corresponding to an upper metal pattern 1372a disposed on the uppermost metal layer in the cell area CELL. The lower metal pattern 1273a and the upper metal pattern 1372a in the cell area CELL have the same cross-sectional shape and are connected to each other. The lower metal pattern 1273a disposed on the uppermost metal layer in the peripheral circuit area PERI may not be connected to additional contacts in the peripheral circuit area PERI. The upper metal pattern 1372a may be connected to the second metal layer 1360a via contact 1371a. Similarly, in the external pad bonding area PA, the non-volatile memory device 1000 may include an upper metal pattern 1372a disposed on the uppermost metal layer in the cell area CELL, corresponding to a lower metal pattern 1273a disposed on the uppermost metal layer in the peripheral circuit area PERI, the upper metal pattern 1372a and the lower metal pattern 1273a in the peripheral circuit area PERI having the same shape.

[0170] Lower bonding metals 1271b and 1272b may be disposed on the second metal layer 1240b in the word line bonding region WLBA. In an example embodiment, in the word line bonding region WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 1371b and 1372b in the cell region CELL via Cu-Cu bonding.

[0171] Furthermore, in the bit line bonding area (BLBA), the non-volatile memory device 1000 may include an upper metal pattern 1392 disposed on the uppermost metal layer in the cell region (CELL) to correspond to a lower metal pattern 1252 disposed on the uppermost metal layer in the peripheral circuit region (PERI). The upper metal pattern 1392 and the lower metal pattern 1252 in the PERI have the same cross-sectional shape. No contact may be formed on the upper metal pattern 1392 disposed on the uppermost metal layer in the cell region (CELL). The lower metal pattern 1252 may have a contact 1251 for connection to the second metal layer 1240c.

[0172] In an example embodiment, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other region (CELL). No contact may be formed on the reinforcing metal pattern.

[0173] The concept of this invention can be applied to data server systems.

[0174] Figure 21 This is a diagram illustrating a data center employing a storage device according to an embodiment of the concept of the present invention. (Refer to...) Figure 21 Data center 7000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 7000 can be a system for operating search engines and databases, and can be a computing system used by companies such as banks or government agencies. Data center 7000 can include application servers 7100 to 7100n and storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can be selected differently depending on the embodiment, and the number of application servers 7100 to 7100n can be different from the number of storage servers 7200 to 7200m.

[0175] Application server 7100 and storage server 7200 may each include any one or any combination of processors 7110 and 7210 and memories 7120 and 7220. When described using storage server 7200 as an example, processor 7210 can control the overall operation of storage server 7200 and can access memory 7220 to execute commands or data loaded in memory 7220. Memory 7220 may be Double Data Rate Synchronous DRAM (DDR SDRAM), High Bandwidth Memory (HBM), Heterogeneous Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, or Non-Volatile DIMM (NVMDIMM). Depending on the embodiment, the number of processors 7210 and the number of memories 7220 included in storage server 7200 may be selected differently.

[0176] In an embodiment, processor 7210 and memory 7220 may provide a processor-memory pair. In an embodiment, the number of processors 7210 may differ from the number of memories 7220. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to an embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one storage device 7250. Storage device 7250 may be implemented according to... Figures 1 to 20 The health check command shown is used to perform heterogeneous multi-sensor operations. This heterogeneous multi-sensor operation can be performed using machine learning (ML). For example, storage device 7250 can be implemented to operate machine learning-based defense code. According to embodiments, the number of storage devices 7250 included in storage server 7200 can be selected differently.

[0177] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC can be the medium for relatively high-speed data transmission, and optical switches providing high performance / high availability can be used. Depending on the access method of network 7300, storage servers 7200 to 7200m can be configured as file storage, block storage, or object storage.

[0178] In this embodiment, network 7300 may be a storage-only network such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to SCSI over TCP / IP or Internet SCSI (iSCSI) protocols. In another embodiment, network 7300 may be a general-purpose network such as a TCP / IP network. For example, network 7300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or NVMe over Fabrics (NVMe-oF).

[0179] The following description will focus on application server 7100 and storage server 7200. The description of application server 7100 can be applied to other application servers 7100n, and the description of storage server 7200 can be applied to other storage servers 7200m.

[0180] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Additionally, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server, a database management system (DBMS), etc.

[0181] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or it can access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n or storage servers 7200 to 7200m. For example, application server 7100 can execute commands for moving or copying data between application servers 7100 to 7100n or storage servers 7200 to 7200m. In this scenario, data can be moved from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7120 to 7120n of application servers 7100 to 7100n via storage devices 7220 to 7220m of storage servers 7200 to 7200m, or directly from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7120 to 7120n of application servers 7100 to 7100n. Data moved via network 7300 can be encrypted data for security or privacy purposes.

[0182] Referring to storage server 7200 as an example, interface 7254 can provide physical connections between processor 7210 and controller 7251, as well as physical connections between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using a Direct Attach Storage (DAS) method, in which storage device 7250 is directly connected via a dedicated cable. Alternatively, interface 7254 can be implemented using various interface methods such as: Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, Fast PCI (PCIe) interface, Fast NVM (NVMe) interface, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Memory (UFS) interface, Embedded Universal Flash Memory (eUFS) interface, Compact Flash Memory (CF) card interface, etc.

[0183] The storage server 7200 may also include a switch 7230 and a NIC 7240. The switch 7230 can selectively connect the processor 7210 and the storage device 7250 according to the control of the processor 7210, or selectively connect the NIC 7240 and the storage device 7250.

[0184] In this embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 may connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and may connect to processor 7210, switch 7230, etc., via the host bus interface. The host bus interface may be implemented as one of the examples of interface 7254 described above. In this embodiment, NIC 7240 may be integrated with any one or any combination of processor 7210, switch 7230, and storage device 7250.

[0185] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send commands to storage devices 7150 to 7150n and 7250 to 7250m or memories 7120 to 7120n and 7220 to 7220m to program or read data. In this case, the data can be data that has already been corrected by an error-correcting code (ECC) engine. The data can be data that has been processed by data bus inversion (DBI) or data masking (DM) and can include cyclic redundancy check (CRC) information. The data can be encrypted data for security or privacy purposes.

[0186] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, the read enable (RE) signal can be input as a data output control signal and can be used to output data to the DQ bus. The RE signal can be used to generate a data strobe (DQS) signal. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0187] Controller 7251 can fully control the operation of storage device 7250. In embodiments, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory device 7252 in response to a write command, or can read data from NAND flash memory device 7252 in response to a read command. For example, write or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 may temporarily store (buffer) data to be written to NAND flash memory device 7252, or may temporarily store (buffer) data read from NAND flash memory device 7252. In addition, DRAM 7253 may store metadata. In this case, metadata may be user data, or it may be data generated by controller 7251 for managing NAND flash memory device 7252. Storage device 7250 may include a security element (SE) for security or privacy.

[0188] According to embodiments of the present invention, a non-volatile storage device can divide heterogeneous data read by sampling at two or more read levels within a single ready & busy signal into output data (Dout Data) and can output it.

[0189] In an embodiment, the non-volatile storage device can sample data from a NAND flash memory with 16K-byte (Kbyte) pages in 8K units and can output data read at two read levels within a single page-sized Dout data. In an embodiment, the first 8K Dout Data can be a first read-level data, and the second 8K Dout Data can be a second read-level data.

[0190] In this embodiment, the non-volatile storage device can sample data from a NAND flash memory with a 16KB page in 4KB units and can output data read at four read levels within a single page-sized Dout data. In this embodiment, the first / second / third / fourth 4K DoutData can be the first / second / third / fourth read level data, respectively.

[0191] In embodiments of the present invention, a non-volatile storage device can sample two or more different WLs within a single ready & busy signal, divide the read heterogeneous data into Dout Data, and output it.

[0192] A non-volatile storage device according to an embodiment of the present invention can partition heterogeneous data read by sampling two or more different blocks within a single ready & busy signal into Dout Data, and can output this Dout Data. In an embodiment, the controller can use the sampled and output Dout Data to adjust the read level and read the data again. In an embodiment, the controller can use the sampled and output Dout Data to adjust the recycling time point.

[0193] The above-described inventive concept is merely an example for implementing the inventive concept. The inventive concept includes not only specific and practically usable devices themselves, but also technical concepts that can be abstract and used as conceptual concepts for future technologies.

[0194] According to embodiments of the present invention, a non-volatile storage device, its operation method, a controller for controlling it, and a storage device having it can perform heterogeneous multi-sensor operation according to a health check command to output cell status information more quickly.

[0195] The non-volatile storage device, its operation method, controller for controlling it, and storage device having the present invention can output cell status information without degrading system performance.

[0196] Although embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: A memory cell array, the memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; A row decoder configured to select one memory block among the plurality of memory blocks based on an address; A voltage generator configured to apply word line voltages corresponding to selected and unselected word lines among the plurality of word lines; A page buffer, connected to the plurality of bit lines, and configured to read data from a memory cell connected to a selected word line of a selected memory block among the plurality of memory blocks; as well as Control logic, configured to control the line decoder, the voltage generator, and the page buffer. The control logic includes a heterogeneous multi-sensor circuit, which is configured to perform heterogeneous multi-sensor operations on different word lines in the same block or different word lines in different blocks. The heterogeneous multi-sensor operations include: Based on a health check command, under different sensing conditions, multiple sensing operations are performed for at least two threshold voltage distributions, wherein the at least two threshold voltage distributions correspond to different word lines in the same block or different word lines in different blocks; and It outputs unit status information corresponding to the multiple sensing operations performed to external devices.

2. The non-volatile storage device according to claim 1, wherein, The multiple sensing operations include multiple single-level unit readout operations. The multiple single-level unit read operations include: The first single-stage unit sensing operation performed under the first sensing condition; and The second single-order unit sensing operation is performed under the second sensing condition, and The first sensing condition and the second sensing condition have different read levels or different generation times.

3. The non-volatile storage device according to claim 2, wherein, The heterogeneous multi-sensor circuit is further configured to perform a recovery operation after each of the first single-level unit sensing operation and the second single-level unit sensing operation.

4. The non-volatile storage device according to claim 1, wherein, The multiple sensing operations include multiple third-order unit readout operations.

5. The non-volatile storage device according to claim 4, wherein, The multiple third-order unit read operations include: The first sensing operation performed under the first sensing condition; and A second sensing operation is performed after the first sensing operation, under second sensing conditions different from the first sensing conditions.

6. The non-volatile storage device according to claim 5, wherein, The heterogeneous multi-sensor circuit is further configured to: A latching operation is performed after the second sensing operation; and A recovery operation is performed after the latching operation.

7. The non-volatile storage device according to claim 6, wherein, The heterogeneous multi-sensor circuit is further configured to: Following the latching operation, based on direct memory access, the first read data corresponding to the first sensing operation is output to the outside from the first page buffer among a plurality of page buffers; as well as After outputting the first read data, based on direct memory access, the second read data corresponding to the second sensing operation is output to the outside from the second page buffer among the plurality of page buffers.

8. The non-volatile storage device according to claim 1, wherein, The plurality of sensing operations include: A first sensing operation is performed under a first sensing condition corresponding to the erasure state; A second sensing operation performed under second sensing conditions different from the first sensing conditions; The third sensing operation performed under the third sensing condition corresponding to the highest programming state in the programming state; and A fourth sensing operation performed under a fourth sensing condition different from the third sensing condition.

9. The non-volatile storage device according to claim 8, wherein, The heterogeneous multi-sensor circuit is further configured to: Perform a first calculation on the sensing data based on the first sensing operation and the sensing data based on the second sensing operation; The first calculated data is stored in the first page buffer group within the page buffer; Output the data stored in the first page buffer group to the external device; A second calculation is performed on the sensing data based on the third sensing operation and the sensing data based on the fourth sensing operation; The data calculated in the second calculation is stored in the second page buffer group within the page buffer; as well as The data stored in the second page buffer group is output to the external device.

10. The non-volatile storage device according to claim 1, further comprising: A storage cell region, the storage cell region including the storage cell array; as well as The peripheral circuit region includes any one or any combination of the row decoder, the page buffer, and the control logic. The storage cell region is electrically connected to the peripheral circuit region via pads formed in the vertical direction.

11. A non-volatile storage device, comprising: A storage cell region having a first metal pad; as well as The peripheral circuit region has a second metal pad and is vertically connected to the memory cell region via the first and second metal pads. The non-volatile storage device includes: A memory cell array is disposed in the memory cell region and includes multiple memory blocks, each memory block including multiple memory cells connected to multiple word lines and multiple bit lines; A line decoder, disposed in the peripheral circuit region and configured to select one word line among the plurality of word lines; A page buffer circuit, disposed in the peripheral circuit region, and comprising a plurality of page buffers connected to the plurality of bit lines; and Control logic, which is located in the peripheral circuit area and configured to: The system receives command latch enable signal, address latch enable signal, chip enable signal, write enable signal, read enable signal, and data strobe signal via control pins; and Based on the received command latch enable signal and the received address latch enable signal, the command or address is latched at the edge of the received write enable signal to perform heterogeneous multi-sensor operation on different word lines in the same block or different word lines in different blocks. The heterogeneous multi-sensor operation includes: multiple sensing operations performed for at least two threshold voltage distributions under different sensing conditions, wherein the at least two threshold voltage distributions correspond to different word lines in the same block or different word lines in different blocks.

12. The non-volatile storage device according to claim 11, wherein, The heterogeneous multi-sensor operation includes: A first sensing operation on a first memory cell connected to a word line in one of the plurality of memory blocks; and A second sensing operation on a second memory cell connected to another word line in the said memory block.

13. The non-volatile storage device according to claim 11, wherein, The heterogeneous multi-sensor operation includes: A first sensing operation on a first memory cell connected to a word line in one of the plurality of memory blocks; and A second sensing operation on a second memory cell connected to a word line in another memory block of the plurality of memory blocks.

14. The non-volatile storage device according to claim 11, wherein, The different sensing conditions have different read levels or different generation times.

15. A method of operating a non-volatile storage device, comprising: Receive health check order; Based on the received health check command, heterogeneous multi-sensor operation is performed on different word lines in the same block or different word lines in different blocks; as well as Output the unit status information corresponding to the heterogeneous multi-sensor operation performed to external devices; The heterogeneous multi-sensor operation includes: multiple sensing operations performed under different sensing conditions for at least two threshold voltage distributions, wherein the at least two threshold voltage distributions correspond to different word lines in the same block or different word lines in different blocks. Among them, page buffer groups corresponding to the plurality of sensing operations are set.

16. The method according to claim 15, wherein, The execution of heterogeneous multi-sensor operation includes: Initialize the first page buffer group in the page buffer group; Perform the first sensing operation in the initialized first page buffer group; Based on the first sensing operation performed, a first latching operation is performed on the first sensing data; Restore any one or any combination of word lines and bit lines corresponding to the first page buffer group; Initialize the second page buffer group in the page buffer group; Perform a second sensing operation in the initialized second page buffer group; Based on the executed second sensing operation, a second latching operation is performed on the second sensing data; and Restore any one or any combination of word lines and bit lines corresponding to the second page buffer group.

17. The method according to claim 15, wherein, The execution of heterogeneous multi-sensor operation includes: Initialize the page buffer group; The first sensing operation is performed in the first page buffer group of the initialized page buffer group; The second sensing operation is performed in the second page buffer group of the initialized page buffer group; Perform latching operations on first sensing data based on the first sensing operation performed and second sensing data based on the second sensing operation performed; and Restore any one or any combination of word lines and bit lines corresponding to the page buffer group.

18. The method of claim 17, further comprising: After the recovery, Return to ready and busy signal; Output the data stored in the first page buffer group; as well as Output the data stored in the second page buffer group.

19. The method of claim 17, further comprising: Calculate the first sensing data and the second sensing data.

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