Wafer structure for bonding and method of manufacturing the same

Abstract

The present invention provides a bonding wafer structure and a manufacturing method thereof, wherein the bonding wafer structure comprises a support substrate, a bonding layer, and a silicon carbide layer. The bonding layer is formed on the surface of the support substrate, and the silicon carbide layer is bonded to the bonding layer, wherein the carbon surface of the silicon carbide layer is in direct contact with the bonding layer. The basal plane dislocation (BPD) of the silicon carbide layer is 1000 ea / cm 2 ~20000ea / cm 2 The total thickness variation (TTV) of the silicon carbide layer is greater than the total thickness variation of the support substrate, and the diameter of the silicon carbide layer is equal to or smaller than the diameter of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

Description

Technical Field

[0001] The present invention relates to a semiconductor bonding technology, and in particular to a bonding wafer structure and a manufacturing method thereof. Background Art

[0002] Epitaxy is the process of growing new crystals on a wafer to form a semiconductor layer. Due to the advantages of high purity and well-controlled thickness, epitaxy has become widely used in the manufacture of RF and power devices.

[0003] However, epitaxially grown wafers or ingots are typically discarded because the epitaxial structures adjacent to the seed crystals have many defects and high stress. Only the epitaxial structures with better quality are retained, resulting in increased waste costs. Summary of the Invention

[0004] The present invention is directed to a bonding wafer structure that can reduce costs and convert poor-quality silicon carbide wafers into bonding substrates.

[0005] The present invention is also directed to a method for manufacturing a bonding wafer structure, which can be used to produce a bonding wafer structure for use in epitaxial growth processes of radio frequency devices or power devices.

[0006] According to an embodiment of the present invention, a bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide layer. The bonding layer is formed on the surface of the support substrate, and the silicon carbide layer is bonded to the bonding layer, wherein the carbon surface of the silicon carbide layer is in direct contact with the bonding layer. The basal plane dislocation (BPD) of the silicon carbide layer is 1000 ea / cm 2 ~20000ea / cm 2 The total thickness variation (TTV) of the silicon carbide layer is greater than the total thickness variation of the supporting substrate, and the diameter of the silicon carbide layer is equal to or smaller than the diameter of the supporting substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

[0007] In the bonding wafer structure according to an embodiment of the present invention, the bonding layer has a softening point between 50° C. and 200° C., a thickness less than 100 μm, and a uniformity less than 10%.

[0008] In the bonding wafer structure according to an embodiment of the present invention, the total thickness variation of the support substrate is less than 3 μm, the curvature is less than 20 μm, the warp is less than 40 μm, and the Young's modulus is greater than 160 GPa.

[0009] In the bonding wafer structure according to an embodiment of the present invention, the support substrate includes a single-layer or multi-layer structure, and the bonding layer includes a single-layer or multi-layer structure.

[0010] In the bonding wafer structure according to the embodiment of the present invention, the concentricity between the silicon carbide layer and the support substrate is less than 1 mm.

[0011] In the bonding wafer structure according to an embodiment of the present invention, the bonding wafer structure may further include an epitaxial silicon carbide substrate bonded to the silicon surface of the silicon carbide layer, wherein the basal plane dislocation of the epitaxial silicon carbide substrate is smaller than the basal plane dislocation of the silicon carbide layer, and the stress of the epitaxial silicon carbide substrate is smaller than the stress of the silicon carbide layer.

[0012] In the bonding wafer structure according to an embodiment of the present invention, the bonding wafer structure may further include an ion implantation region formed in the epitaxial silicon carbide substrate, wherein the ion implantation region is within about 1 μm from the bonding surface between the epitaxial silicon carbide substrate and the silicon carbide layer.

[0013] In the bonding wafer structure according to the embodiment of the present invention, the thickness of the silicon carbide layer is less than 500 μm, and the thickness of the bonding wafer structure is less than 2000 μm.

[0014] According to another embodiment of the present invention, a method for manufacturing a bonding wafer structure includes coating a surface of a support substrate to form a bonding layer, bonding a carbon surface of a silicon carbide layer to the bonding layer, wherein the total thickness variation (TTV) of the silicon carbide layer is greater than the total thickness variation of the support substrate, the diameter of the silicon carbide layer is equal to or less than the diameter of the support substrate, and the basal plane dislocation (BPD) of the silicon carbide layer is less than 1000 ea / cm 2 ~20000ea / cm 2 The silicon carbide layer has a bow greater than 75 μm and a warp greater than 150 μm before bonding. The silicon surface of the silicon carbide layer is then ground to reduce the thickness of the silicon carbide layer. The ground silicon surface of the silicon carbide layer is then polished to obtain a bonding wafer structure having a total thickness variation of less than 10 μm, a bow less than 30 μm, and a warp less than 60 μm.

[0015] In a manufacturing method according to another embodiment of the present invention, a method of bonding the carbon surface of the silicon carbide layer to the bonding layer includes: aligning a flat edge of the support substrate with a flat edge of the silicon carbide layer.

[0016] In a manufacturing method according to another embodiment of the present invention, a load on the carbon surface of the silicon carbide layer bonded to the bonding layer is 8 kgf to 10 kgf.

[0017] In a manufacturing method according to another embodiment of the present invention, after bonding the carbon surface of the silicon carbide layer to the bonding layer, the method may further include removing residual bonding layer material and cleaning the support substrate.

[0018] In a manufacturing method according to another embodiment of the present invention, the thickness of the silicon carbide layer removed by grinding is between 5 μm and 12 μm.

[0019] In a manufacturing method according to another embodiment of the present invention, a change in curvature (ΔBow) between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 80 μm, and a change in warpage (ΔWarp) between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 160 μm.

[0020] In a manufacturing method according to another embodiment of the present invention, the method of forming the bonding layer by coating includes: spin coating wax onto the surface of the supporting substrate at a temperature of 110° C. to 130° C.

[0021] In a manufacturing method according to another embodiment of the present invention, before grinding the silicon surface of the silicon carbide layer, the method may further include measuring the total thickness variation of the supporting substrate, bonding layer and silicon carbide layer bonded together. If the total thickness variation is less than 10 μm, subsequent steps are performed; otherwise, if it is above 10 μm, the method includes: removing the bonding layer and the silicon carbide layer, and then re-performing the step of coating the surface of the supporting substrate to form a bonding layer.

[0022] In a manufacturing method according to another embodiment of the present invention, the polishing includes rough polishing and fine polishing.

[0023] Based on the above, the bonding wafer structure of the present invention is essentially composed of three layers, including a low-quality (high-stress) silicon carbide layer that replaces a portion of the original support substrate. This silicon carbide layer is waste material removed after epitaxial growth. Reusing it in the bonding structure not only reduces the material and waste costs of the support substrate, but also allows direct bonding with the epitaxial silicon carbide substrate, improving wafer bonding yield. The bonding wafer structure of the present invention is suitable for applications in power device or radio frequency (RF) device processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic cross-sectional view of a bonding wafer structure according to a first embodiment of the present invention;

[0025] Figure 2 is a cross-sectional schematic diagram of another bonding wafer structure according to the first embodiment of the present invention;

[0026] Figure 3 is a flowchart of a manufacturing process of a bonding wafer structure according to a second embodiment of the present invention;

[0027] Figure 4 FIG. 4 is a perspective schematic diagram of step S302 of the second embodiment.

[0028] Description of Reference Numerals

[0029] 100, 200: Wafer structure for bonding

[0030] 102: Support substrate

[0031] 104: Bonding layer

[0032] 106: Silicon carbide layer

[0033] 106a: Carbon surface

[0034] 106b: Silicon surface

[0035] 106c, 102a: flat edge

[0036] 202: Silicon carbide substrate for epitaxy

[0037] 204: Ion implantation area

[0038] 206: Joint surface

[0039] s: distance

[0040] S300, S302, S304, S306, S308, S310, S312, S314: Steps DETAILED DESCRIPTION

[0041] The following will fully describe exemplary embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. For clarity, the sizes and thicknesses of various regions, parts, and layers may not be drawn to scale. For ease of understanding, identical components will be represented by the same reference numerals throughout the following description.

[0042] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a bonding wafer structure according to the first embodiment of the present invention.

[0043] Please refer to Figure 1The bonding wafer structure 100 of the first embodiment basically includes a supporting substrate 102, a bonding layer 104, and a silicon carbide layer 106. The supporting substrate 102 is a substrate made of a strong material with high rigidity and not easily deformed / warped / damaged during processing, such as a material with a Young's modulus greater than 160 GPa, preferably a material with a Young's modulus greater than 180 GPa. In one embodiment, the total thickness variation (TTV) of the supporting substrate 102 is, for example, less than 3 μm, preferably less than 1 μm; the bow of the supporting substrate 102 is, for example, less than 20 μm, preferably less than 15 μm; the warp of the supporting substrate 102 is, for example, less than 40 μm, preferably less than 30 μm. For example, the supporting substrate 102 is a silicon substrate, a sapphire substrate, a ceramic substrate, or a combination thereof. In other words, the supporting substrate 102 can be a single-layer or multi-layer structure. The bonding layer 104 is formed on the surface of the supporting substrate 102, wherein the softening point of the bonding layer 104 is, for example, between 50°C and 200°C, preferably between 80°C and 150°C. If the softening point of the bonding layer 104 is set within the above range, it will be beneficial to use high temperature to separate the supporting substrate 102 and the silicon carbide layer 106 when they are subsequently separated. The thickness of the bonding layer 104 is, for example, less than 100μm, preferably between 10μm and 20μm; the uniformity of the bonding layer 104 is, for example, less than 10%, preferably less than 5%. For example, the material of the bonding layer 104 can be wax or a fixing glue. Considering that the support substrate 102 and the silicon carbide layer 106 need to be adjusted in alignment during bonding, it is preferable to use wax with greater fluidity as the material of the bonding layer 104. However, the present invention is not limited thereto; if the support substrate 102 and the silicon carbide layer 106 are accurately aligned, a fixing adhesive such as UV adhesive may also be used as the material of the bonding layer 104. Furthermore, the bonding layer 104 may also be a single layer or multi-layer structure.

[0044] Please continue to refer to Figure 1 The silicon carbide layer 106 is bonded to the bonding layer 104, that is, the silicon carbide layer 106 is fixed to the support substrate 102 through the bonding layer 104. The carbon surface 106a of the silicon carbide layer 106 is in direct contact with the bonding layer 104, and the silicon surface 106b of the silicon carbide layer 106 is exposed and can be used for subsequent bonding with other epitaxial substrates (not shown). The basal plane dislocation (BPD) of the silicon carbide layer 106 is 1000 ea / cm 2 ~20000ea / cm 2 between, for example, 4000ea / cm 2 ~10000ea / cm 2The total thickness variation (TTV) of the silicon carbide layer 106 is greater than the total thickness variation of the supporting substrate 102, and the diameter of the silicon carbide layer 106 is equal to or less than the diameter of the supporting substrate 102. For example, the TTV of the silicon carbide layer 106 before bonding is, for example, less than 10μm, preferably less than 5μm; but the Bow is, for example, greater than 75μm or greater than 100μm, and the Warp is, for example, greater than 150μm or greater than 200μm. This is because the silicon carbide layer 106 before bonding is a high-stress silicon carbide wafer using adjacent seed crystals, so the Bow and Warp are relatively large. However, after bonding, the TTV of the bonding wafer structure 100 is less than 10μm, the Bow is less than 30μm, and the Warp is less than 60μm, so it can be applied to the epitaxial process of power devices or radio frequency (RF) devices. In one embodiment, the bonding wafer structure 100 can have a TTV of less than 3 μm, a Bow of less than 20 μm, and a Warp of less than 40 μm. In this embodiment, the thickness of the silicon carbide layer 106 is, for example, less than 500 μm, preferably less than 400 μm; the thickness of the bonding wafer structure 100 is, for example, less than 2000 μm, preferably less than 1000 μm. Furthermore, the concentricity between the silicon carbide layer 106 and the support substrate 102 is, for example, less than 1 mm, preferably less than 0.5 mm.

[0045] Figure 2 is a cross-sectional view of another bonding wafer structure according to the first embodiment of the present invention, wherein Figure 1 The same device symbols are used to represent the same or similar components, and the same or similar components can also refer to Figure 1 The relevant instructions will not be repeated here.

[0046] exist Figure 2 In the embodiment, the bonding wafer structure 200 may include an epitaxial silicon carbide substrate 202 bonded to the silicon surface 106b of the silicon carbide layer 106, wherein the basal plane dislocation (BPD) of the epitaxial silicon carbide substrate 202 is smaller than the basal plane dislocation of the silicon carbide layer 106, and the stress of the epitaxial silicon carbide substrate 202 is smaller than the stress of the silicon carbide layer 106. Furthermore, an ion implantation region 204 (i.e., the region indicated by the dotted line) may be formed within the epitaxial silicon carbide substrate 202 . The ion implantation region 204 is located close to the interface 206 between the epitaxial silicon carbide substrate 202 and the silicon carbide layer 106 . In one embodiment, the distance s between the ion implantation region 204 and the interface 206 is, for example, less than 1 μm. Since the ion implantation region 204 creates a relatively fragile structure within the epitaxial silicon carbide substrate 202 , the epitaxial silicon carbide substrate 202 and the silicon carbide layer 106 can be easily separated from the ion implantation region 204 .

[0047] Figure 3FIG. 1 is a flowchart of a manufacturing process of a bonding wafer structure according to a second embodiment of the present invention.

[0048] Please refer to Figure 3 , first perform step S300, and form a bonding layer on the surface of the supporting substrate, wherein the softening point of the bonding layer is, for example, between 50°C and 200°C, preferably between 80°C and 150°C. If wax is used as the material of the bonding layer, liquid wax can be spin-coated onto the surface of the supporting substrate at a temperature of 110°C to 130°C. The Young's modulus of the supporting substrate is, for example, greater than 160GPa, preferably greater than 180GPa; the TTV is, for example, less than 3μm, preferably less than 1μm; the Bow is, for example, less than 20μm, preferably less than 15μm; and the Warp is, for example, less than 40μm, preferably less than 30μm. The supporting substrate is, for example, a silicon substrate, a sapphire substrate, a ceramic substrate, or a combination thereof, and the supporting substrate can be a single-layer or multi-layer structure. As for the thickness of the bonding layer, for example, it is less than 100μm, preferably between 10μm and 20μm; the uniformity is, for example, less than 10%, preferably less than 5%.

[0049] Then, step S302 is performed to bond the carbon surface of the silicon carbide layer to the bonding layer, wherein the TTV of the silicon carbide layer is greater than the TTV of the support substrate, the diameter of the silicon carbide layer is equal to or smaller than the diameter of the support substrate, and the BPD of the silicon carbide layer is 1000 ea / cm 2 ~20000ea / cm 2 between, for example, 4000ea / cm 2 ~10000ea / cm 2 The thickness of the silicon carbide layer is, for example, less than 500 μm, preferably less than 400 μm. The TTV of the silicon carbide layer before bonding is, for example, less than 10 μm, preferably less than 5 μm; however, the Bow is greater than 75 μm, for example, greater than 100 μm, and the Warp is greater than 150 μm, for example, greater than 200 μm. In this embodiment, the method of bonding the silicon carbide layer is, for example, Figure 4 As shown, the flat edge 102a of the support substrate 102 is aligned with the flat edge 106c of the silicon carbide layer 106 to reduce the risk of edge chipping or collapse during post-processing. Figure 4 The bonding layer is omitted. The bonding load is, for example, >8 kgf, preferably 8 kgf to 10 kgf. After step S302, the concentricity between the silicon carbide layer and the support substrate is, for example, less than 1 mm, preferably less than 0.5 mm.

[0050] Then, step S304 is performed to grind the silicon surface of the silicon carbide layer to reduce the thickness of the silicon carbide layer. The thickness of the silicon carbide layer removed by grinding is, for example, between 5 μm and 12 μm, preferably between 8 μm and 12 μm, so that the TTV of the silicon surface is less than 5 μm, preferably less than 1 μm. After grinding, the overall chip is flatter and has a better geometry.

[0051] Then, step S306 is performed to polish the silicon surface of the ground silicon carbide layer to obtain a bonding wafer structure. The polishing includes rough polishing and fine polishing to reduce the geometric TTV of the silicon surface to less than 2 μm, preferably less than 1 μm. In one embodiment, the roughness Ra after rough polishing and after fine polishing is as follows:

[0052] 1. Rough polishing haze = 4.67, Ra about 0.1nm ~ 0.19nm.

[0053] 2. Fine polishing haze = 4.16 ~ 4.19, Ra average about 0.13nm ~ 0.062nm.

[0054] After step S306, the bonding wafer structure has a TTV of less than 10 μm (e.g., less than 3 μm), a Bow of less than 30 μm (e.g., less than 20 μm), and a Warp of less than 60 μm (e.g., less than 40 μm). In other words, the difference in bow (ΔBow) between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 45 μm, preferably greater than 80 μm, and the difference in warp (ΔWarp) between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 90 μm, preferably greater than 160 μm. The thickness of the bonding wafer structure is, for example, less than 2000 μm, preferably less than 1000 μm.

[0055] In addition, after step S302 , step S308 may be performed first to remove the remaining bonding layer material and clean the support substrate.

[0056] Considering the yield of the subsequent epitaxial growth process, step S310 can be performed before step S304 to measure the TTV of the bonded support substrate, bonding layer, and silicon carbide layer. If the TTV is less than 10 μm in step S312, step S304 can be performed. Otherwise, if the TTV is greater than 10 μm, step S314 can be performed to remove the bonding layer and silicon carbide layer, and then step S300 can be returned to form a new bonding layer on the original support substrate. Step S310 can be performed after step S302 or step S308.

[0057] Several experiments are listed below to verify the effects of the present invention, but the present invention is not limited to the following contents.

[0058] Analysis method

[0059] 1. Thickness: Wafer thickness is measured using a non-contact instrument (MX-203 / FRT / ADE7000).

[0060] 2.TTV, Warp, Bow: measured using non-contact instruments.

[0061] 3.BPD: Use automatic optical inspection (AOI) and calculate its density.

[0062] <Experimental Example 1>

[0063] Step 1) Spin-coat wax onto the surface of the silicon carbide and silicon substrate at room temperature (the thickness is not limited and is selected in conjunction with the current process fixture), place it on a 120°C hot plate, and heat for 60 seconds.

[0064] Step 2) Bond the silicon carbide layer to the silicon substrate, aligning the flat edge of the silicon substrate with the flat edge of the silicon carbide layer, and applying a load of >8 kgf and letting it stand for 60 seconds. The basal plane dislocation (BPD) of the silicon carbide layer is approximately 4048 ea / cm 2 .

[0065] Step 3), grinding the silicon surface of the silicon carbide layer by about 5 μm.

[0066] Step 4) polishing the silicon surface of the ground silicon carbide layer at a temperature of 35°C to 60°C. This temperature range can prevent wafer edge peeling and ensure sufficient removal. The polishing removal amount is about 1 μm to obtain a wafer structure for bonding.

[0067] The planarity characteristics of the silicon substrate and the silicon carbide layer alone (before bonding) were measured and reported in Table 1. The planarity characteristics of the entire structure were also measured after steps 2), 3), and 4) and reported in Table 1.

[0068] <Experimental Example 2>

[0069] The bonding wafer structure was prepared in the same manner as in Experimental Example 1, except that the BPD of the silicon carbide layer was about 4002 ea / cm 2 The flatness characteristics of the structures at each stage were then measured and recorded in Table 1 below.

[0070] <Experimental Example 3>

[0071] The bonding wafer structure was prepared in the same manner as in Experimental Example 1, except that the BPD of the silicon carbide layer was about 3957 ea / cm 2 The flatness characteristics of the structures at each stage were then measured and recorded in Table 1 below.

[0072] Table 1

[0073]

[0074] As can be seen from the table above, both the Bow and Warp values of the individual SiC layers prior to bonding are relatively high (greater than 100 / greater than 200, respectively). However, in Experiments 1-3, after bonding in step 2), the Bow and Warp values have been significantly reduced (approximately less than 20 / 40, respectively), enabling their application in epitaxial growth processes for power or RF devices.

[0075] In summary, the bonding wafer structure of the present invention utilizes a low-quality (high-stress) silicon carbide layer to replace a portion of the original support substrate, directly bonding it to the epitaxial silicon carbide substrate. Furthermore, after completing the aforementioned bonding process, the bonding wafer structure can be separated from the support substrate and the low-quality silicon carbide layer at high temperature, allowing the support substrate to be reused. This not only reduces the material consumption of the support substrate but also the cost of discarding low-quality SiC epitaxial wafers. Furthermore, the bonding wafer structure of the present invention, with its high flatness, facilitates the customer's bonding process, improves wafer bonding yield, and is suitable for use in epitaxial processes for power / RF devices.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer structure for bonding, characterized in that: include: a supporting substrate; a bonding layer formed on a surface of the supporting substrate; as well as A silicon carbide layer is bonded to the bonding layer, wherein the carbon surface of the silicon carbide layer is in direct contact with the bonding layer, and the basal plane dislocation of the silicon carbide layer is 1000 ea / cm 2 ~20000ea / cm 2 The total thickness variation of the silicon carbide layer is greater than the total thickness variation of the support substrate, the diameter of the silicon carbide layer is equal to or smaller than the diameter of the support substrate, and The bonding wafer structure has a total thickness variation of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

2. The bonding wafer structure according to claim 1, wherein: The thickness of the silicon carbide layer is less than 500 μm, and the thickness of the bonding wafer structure is less than 2000 μm.

3. The bonding wafer structure according to claim 1, wherein: The bonding layer has a softening point between 50° C. and 200° C., a thickness less than 100 μm, and a uniformity less than 10%.

4. The bonding wafer structure according to claim 1, wherein: The support substrate has a total thickness variation of less than 3 μm, a curvature of less than 20 μm, a warpage of less than 40 μm, and a Young's modulus of greater than 160 GPa.

5. The bonding wafer structure according to claim 1, wherein: The supporting substrate includes a single layer or a multi-layer structure, and the bonding layer includes a single layer or a multi-layer structure.

6. The bonding wafer structure according to claim 1, wherein: The concentricity between the silicon carbide layer and the support substrate is less than 1 mm.

7. The bonding wafer structure according to claim 1, wherein: It also includes an epitaxial silicon carbide substrate bonded to the silicon surface of the silicon carbide layer, the basal plane dislocation of the epitaxial silicon carbide substrate is smaller than the basal plane dislocation of the silicon carbide layer, and the stress of the epitaxial silicon carbide substrate is smaller than the stress of the silicon carbide layer.

8. The bonding wafer structure according to claim 7, wherein: The method further includes an ion implantation region formed in the epitaxial silicon carbide substrate, wherein the ion implantation region is within 1 μm from a bonding surface between the epitaxial silicon carbide substrate and the silicon carbide layer.

9. A method for manufacturing a wafer structure for bonding, characterized in that: include: Forming a bonding layer by coating a surface of a supporting substrate; The carbon surface of the silicon carbide layer is bonded to the bonding layer, wherein the total thickness variation of the silicon carbide layer is greater than the total thickness variation of the supporting substrate, the diameter of the silicon carbide layer is equal to or less than the diameter of the supporting substrate, and the basal plane dislocation of the silicon carbide layer is 1000 ea / cm 2 ~20000ea / cm 2 The curvature of the silicon carbide layer before bonding is greater than 75 μm and the warpage is greater than 150 μm; Grinding the silicon surface of the silicon carbide layer to reduce the thickness of the silicon carbide layer; as well as The ground silicon surface of the silicon carbide layer is polished to obtain a bonding wafer structure, wherein the bonding wafer structure has a total thickness variation of less than 10 μm, a curvature of less than 30 μm, and a warpage of less than 60 μm.

10. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The method of bonding the carbon surface of the silicon carbide layer to the bonding layer includes aligning a flat edge of the support substrate with a flat edge of the silicon carbide layer.

11. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The load on the carbon surface of the silicon carbide layer bonded to the bonding layer is 8 kgf to 10 kgf.

12. The method for manufacturing a bonding wafer structure according to claim 9, wherein: After bonding the carbon surface of the silicon carbide layer to the bonding layer, the method further includes removing residual bonding layer material and cleaning the support substrate.

13. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The thickness of the silicon carbide layer removed by grinding is between 5 μm and 12 μm.

14. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The change in curvature between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 80 μm, and the change in warpage between the silicon carbide layer before bonding and the bonding wafer structure after polishing is greater than 160 μm.

15. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The method of forming the bonding layer by coating includes: spin coating wax onto the surface of the support substrate at a temperature of 110° C. to 130° C.

16. The method for manufacturing a bonding wafer structure according to claim 9, wherein: Before grinding the silicon surface of the silicon carbide layer, the method further comprises: measuring a total thickness variation of the support substrate, the bonding layer, and the silicon carbide layer bonded together; and If the measured total thickness variation is less than 10 μm, the subsequent steps are performed. If it is greater than 10 μm, the subsequent steps include: removing the bonding layer and the silicon carbide layer, and then re-performing the step of coating the surface of the support substrate to form a bonding layer.

17. The method for manufacturing a bonding wafer structure according to claim 9, wherein: The polishing includes rough polishing and fine polishing.

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