Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region; forming a first gate structure on the first region, forming first source / drain doped regions in the substrate on both sides of the first gate structure, forming a dielectric structure on the substrate, the dielectric structure being located on the sidewall surface and top surface of the first gate structure; forming a first opening in the dielectric structure on the first region, the first opening exposing the surface of the first source / drain doped regions; forming a mask layer on the dielectric structure, the mask layer exposing the first region; using the mask layer as a mask, performing a first ion implantation on the first source / drain doped regions exposed by the first opening; after performing the first ion implantation, removing the mask layer; after removing the mask layer, forming a first isolation layer on the sidewall surface of the first opening. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different layers of metal lines to achieve signal transmission and control. Therefore, the formation of metal interconnect structures has a significant impact on the performance and manufacturing cost of semiconductor devices during semiconductor manufacturing. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between these semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Generally, in the back-end interconnect process of semiconductor device manufacturing, the first metal layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first metal layer, it is usually necessary to pre-form the local interconnect structure of the semiconductor device. The local interconnect structure includes: a zeroth metal layer (M0) electrically connected to the underlying source / drain regions, and a zeroth gate metal layer (M0G) electrically connected to the gate structure.

[0004] However, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of a semiconductor structure with local interconnect structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region; forming a first gate structure on the first region, forming first source / drain doped regions in the substrate on both sides of the first gate structure, forming a dielectric structure on the substrate, the dielectric structure being located on the sidewall surface and top surface of the first gate structure; forming a first opening in the dielectric structure on the first region, the first opening exposing the surface of the first source / drain doped regions; forming a mask layer on the dielectric structure, the mask layer exposing the first region; using the mask layer as a mask, performing a first ion implantation on the first source / drain doped regions exposed by the first opening; after performing the first ion implantation, removing the mask layer; after removing the mask layer, forming a first isolation layer on the sidewall surface of the first opening.

[0007] Optionally, the substrate further includes a second region; the formation method further includes: forming a second gate structure on the second region, forming second source / drain doped regions in the substrate on both sides of the second gate structure, and the dielectric structure being located on the sidewall surface and top surface of the second gate structure.

[0008] Optionally, it further includes: forming a second opening within a dielectric structure on the second region, the second opening exposing the surface of the second source / drain doped region; the mask layer is also located within the second opening.

[0009] Optionally, the method for forming the mask layer includes: forming an initial mask layer on a substrate; removing the initial mask layer on the first region to form the mask layer.

[0010] Optionally, the material of the mask layer includes photoresist.

[0011] Optionally, the process for removing the mask layer includes an ashing process, wherein the gas used in the ashing process includes oxygen or an oxygen-containing gas.

[0012] Optionally, after removing the mask layer and before forming the first isolation layer, the method further includes performing a second ion implantation on the first source / drain doped region exposed by the first opening and the second source / drain doped region exposed by the second opening.

[0013] Optionally, the second ion implanted in the second ion includes IVA ions or inert gas ions.

[0014] Optionally, after performing the second ion implantation, the method further includes forming a second isolation layer on the surface of the second opening sidewall.

[0015] Optionally, the method for forming the first isolation layer and the second isolation layer includes: forming an isolation material layer on the first opening sidewall surface and bottom surface, the second opening sidewall surface and bottom surface, and the dielectric structure; and etching back the isolation material layer until the first source / drain doped region surface and the second source / drain doped region surface are exposed to form the first isolation layer and the second isolation layer.

[0016] Optionally, after forming the first isolation layer and the second isolation layer, the method further includes: forming a first conductive structure in the first opening, the first conductive structure being electrically connected to the first source / drain doped region; and forming a second conductive structure in the second opening, the second conductive structure being electrically connected to the second source / drain doped region.

[0017] Optionally, the material of the first source / drain doped region includes silicon and germanium.

[0018] Optionally, the first ion implanted in the first ion includes a P-type ion, which includes boron ions, boron-fluorine ions, or indium ions.

[0019] Optionally, the material of the first isolation layer includes a dielectric material, wherein the dielectric material includes silicon nitride; the material of the second isolation layer includes a dielectric material, wherein the dielectric material includes silicon nitride.

[0020] Optionally, the method for forming the first gate structure, the second gate structure, the first source / drain doped region, the second source / drain doped region, and the dielectric structure includes: forming a first dummy gate structure on a first region of a substrate, and forming a second dummy gate structure on a second region of a substrate; forming a first source / drain doped region in the substrate on both sides of the first dummy gate structure, and forming a second source / drain doped region in the substrate on both sides of the second dummy gate structure; forming an initial dielectric structure on the substrate, the initial dielectric structure being located on the sidewalls of the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening, and forming a second gate structure in the second gate opening; after forming the first gate structure and the second gate structure, forming the dielectric structure, the dielectric structure being located on the sidewall surface and the top surface of the first gate structure, and the dielectric structure being located on the sidewall surface and the top surface of the second gate structure.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] The semiconductor structure formation method in the technical solution of the present invention first performs a first ion implantation process on the first source / drain doped region exposed by the first opening, and then forms a first isolation layer on the sidewall surface of the first opening. This makes the first isolation layer less susceptible to modification during the processes of forming the mask layer, first ion implantation, and removing the mask layer, thereby reducing the possibility of the first isolation layer becoming larger after modification. As a result, it is easier to fill the conductive structure material in the first opening, and the contact effect between the formed conductive structure and the first source / drain doped region is better. Attached Figure Description

[0023] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process in one embodiment;

[0024] Figures 4 to 10 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, the performance of existing back-end metal interconnect processes and the resulting semiconductor structures still needs improvement. This will now be analyzed and explained with reference to specific embodiments.

[0026] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process in one embodiment.

[0027] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first region I and a second region II; a first gate structure 101 is formed on the first region I, and a second gate structure 102 is formed on the second region II; a first source / drain doped region 103 is formed in the substrate on both sides of the first gate structure 101; a second source / drain doped region 104 is formed in the substrate on both sides of the second gate structure 102; a dielectric structure 105 is formed on the substrate, the dielectric structure 105 being located on the sidewalls of the first gate structure 101 and the second gate structure 102; a first opening 106 is formed in the dielectric structure 105 on the first region I, the first opening 106 exposing the surface of the first source / drain doped region 103; a second opening 107 is formed in the dielectric structure 105 on the second region II, the second opening 107 exposing the surface of the second source / drain doped region 104.

[0028] Please refer to Figure 2 A first isolation layer 108 is formed on the sidewall of the first opening 106; a second isolation layer 109 is formed on the sidewall of the second opening 107.

[0029] Please refer to Figure 3 A mask layer 110 is formed on the substrate, the mask layer 110 exposing the first region I; ion implantation is performed on the first source / drain doped region 103 using the mask layer 110 as a mask.

[0030] In the method for forming the semiconductor structure, the first region I is used to form a PMOS device, the second region II is used to form an NMOS device, and the first isolation layer 108 is used to increase the electrical isolation between the conductive structure subsequently formed in the first opening 106 and the first gate structure 101. The material of the first isolation layer 108 includes a dielectric material, which is typically silicon nitride. After ion implantation, the ion concentration on the surface of the first source / drain doped region 103 is high. When a conductive structure electrically connected to the first source / drain doped region 103 is subsequently formed in the first opening 106, the contact resistance between the conductive structure and the first source / drain doped region 103 becomes smaller.

[0031] However, when forming the mask layer 110 that exposes the first region I, exposure, development and etching steps are required. After ion implantation of the first source-drain doped region 103, the mask layer 110 also needs to be removed. As a result, after the above exposure, development, etching, removal and ion implantation processes, the first isolation layer 108 is easily oxidized into a modified isolation layer 111, which increases the volume of the modified isolation layer 111. This makes the size of the first opening 106 in the modified isolation layer 111 smaller. When metal material is subsequently deposited in the first opening 106 to form a conductive structure, it is difficult for the metal material to fill the first opening 106.

[0032] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This method involves first performing a first ion implantation process on the first source / drain doped region exposed by the first opening, and then forming a first isolation layer on the sidewall surface of the first opening. This makes the first isolation layer less susceptible to modification during the mask layer formation, first ion implantation, and mask layer removal processes, thereby reducing the likelihood of the first isolation layer increasing in volume after modification. Consequently, it facilitates the subsequent filling of the conductive structure material within the first opening, resulting in better contact between the formed conductive structure and the first source / drain doped region.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 10 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0035] Please refer to Figure 4 A substrate 200 is provided, the substrate 200 including a first region I.

[0036] In this embodiment, the substrate 200 further includes a second region II.

[0037] The first region I is used for the subsequent formation of PMOS devices, and the second region II is used for the subsequent formation of NMOS devices.

[0038] In this embodiment, the substrate 200 is made of silicon.

[0039] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0040] Please refer to Figure 5 A first gate structure 201 is formed on the first region I, and a first source / drain doped region 203 is formed in the substrate 200 on both sides of the first gate structure 201. A dielectric structure 205 is formed on the substrate 200, and the dielectric structure 205 is located on the sidewall surface and the top surface of the first gate structure 201.

[0041] In this embodiment, a second gate structure 202 is formed on the second region II, and a second source / drain doped region 204 is formed in the substrate 200 on both sides of the second gate structure 202. The dielectric structure 205 is located on the sidewall surface and the top surface of the second gate structure 202.

[0042] In this embodiment, the material of the first source / drain doped region 203 includes silicon-germanium; the material of the second source / drain doped region 204 includes silicon-carbon.

[0043] The method for forming the first gate structure 201, the second gate structure 202, the first source / drain doped region 203, the second source / drain doped region 204, and the dielectric structure 205 includes: forming a first dummy gate structure (not shown) on a first region I of a substrate 200, and forming a second dummy gate structure (not shown) on a second region II of the substrate 200; forming the first source / drain doped region 203 in the substrate 200 on both sides of the first dummy gate structure, and forming the second source / drain doped region 204 in the substrate 200 on both sides of the second dummy gate structure; and forming an initial dielectric structure (not shown) on the substrate 200, wherein the initial dielectric structure is located on the sidewall of the first dummy gate structure and the sidewall of the second dummy gate structure. The first and second pseudo-gate structures are removed, and a first gate opening (not shown) is formed in the initial dielectric structure on the first region I, and a second gate opening (not shown) is formed in the initial dielectric structure on the second region II; a first gate structure 201 is formed in the first gate opening, and a second gate structure 202 is formed in the second gate opening; after forming the first gate structure 201 and the second gate structure 202, the dielectric structure 205 is formed, the dielectric structure 205 is located on the sidewall surface and the top surface of the first gate structure 201, and the dielectric structure 205 is located on the sidewall surface and the top surface of the second gate structure 202.

[0044] The first gate structure 201 includes a first gate dielectric layer (not shown) and a first gate layer (not shown) located on the first gate dielectric layer. In this embodiment, the first gate structure 201 further includes a first work function layer (not shown), which is located between the first gate dielectric layer and the first gate layer.

[0045] The material of the first gate dielectric layer includes a high dielectric constant material, wherein the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the first gate layer includes a metal, wherein the metal includes tungsten; the material of the first work function layer includes a P-type work function material, wherein the P-type work function material includes titanium nitride or tantalum nitride.

[0046] The second gate structure 202 includes a second gate dielectric layer (not shown) and a second gate layer (not shown) located on the second gate dielectric layer. In this embodiment, the second gate structure 202 further includes a second work function layer (not shown), which is located between the second gate dielectric layer and the second gate layer.

[0047] The material of the second gate dielectric layer includes a high dielectric constant material with a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the second gate layer includes a metal, and the metal includes tungsten; the material of the second work function layer includes an N-type work function material, and the N-type work function material includes titanium aluminum.

[0048] The dielectric structure 205 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the dielectric structure 205 is made of silicon oxide.

[0049] Please refer to Figure 6 A first opening 206 is formed in the dielectric structure 205 on the first region I, and the first opening 206 exposes the surface of the first source / drain doped region 203.

[0050] In this embodiment, while forming the first opening 206, a second opening 207 is also formed in the dielectric structure 205 on the second region II, and the second opening 207 exposes the surface of the second source / drain doped region 204.

[0051] The method for forming the first opening 206 and the second opening 207 includes: forming a patterned layer (not shown) on a dielectric structure 205, the patterned layer exposing the dielectric structure 205 on the surface of the first source / drain doped region 203 and the dielectric structure 205 on the surface of the second source / drain doped region 204; using the patterned layer as a mask, etching the dielectric structure 205 until the surfaces of the first source / drain doped region 203 and the second source / drain doped region 204 are exposed, forming the first opening 206 in the dielectric structure 205 in the first region I and the second opening 207 in the dielectric structure 205 in the second region II.

[0052] In this embodiment, the etching process of the dielectric structure 205 includes a dry etching process, which can obtain a first opening 206 and a second opening 207 with good sidewall morphology and high dimensional accuracy.

[0053] Please refer to Figure 7 A mask layer 208 is formed on the dielectric structure 205, the mask layer 208 exposing the first region I.

[0054] In this embodiment, the mask layer 208 is also located within the second opening 207.

[0055] The method for forming the mask layer 208 includes: forming an initial mask layer (not shown) on a substrate 200; removing the initial mask layer on the first region I to form the mask layer 208.

[0056] In this embodiment, the material of the mask layer 208 includes photoresist; the process of forming the mask layer 208 includes an exposure process and a development process.

[0057] Please continue to refer to this. Figure 7 Using the mask layer 208 as a mask, the first source / drain doped region 203 exposed by the first opening 206 is subjected to first ion implantation.

[0058] The first ion implantation process increases the ion concentration on the surface of the first source / drain doped region 203, thereby reducing the Schottky barrier between the subsequently formed first conductive structure and the first source / drain doped region 203, thus reducing the contact resistance between the first conductive structure and the first source / drain doped region 203 and improving the performance of the semiconductor structure.

[0059] In this embodiment, the first ion implanted by the first ion includes a P-type ion, which includes boron ions, boron-fluorine ions, or indium ions.

[0060] The first ion in the first ion implantation process includes P-type ions, which can increase the number of holes in the first source / drain doped region 203, thereby increasing the hole mobility of the channel and improving the performance of the device in the first region I.

[0061] Please refer to Figure 8 After the first ion implantation, the mask layer 208 is removed.

[0062] In this embodiment, the process of removing the mask layer 208 includes an ashing process, wherein the gas used in the ashing process includes oxygen or an oxygen-containing gas.

[0063] First, the first source / drain doped region 203 exposed by the first opening 206 is implanted with ions using a first ion implantation process. Then, a first isolation layer is formed on the sidewall surface of the first opening 206. This makes the first isolation layer less susceptible to oxidation during the processes of forming the mask layer 208, first ion implantation, and removing the mask layer 208, thereby reducing the possibility of the first isolation layer becoming larger after modification.

[0064] Please continue to refer to this. Figure 8 After removing the mask layer 208, a second ion implantation is performed on the first source / drain doped region 203 exposed by the first opening 206 and the second source / drain doped region 204 exposed by the second opening 207.

[0065] The second ion implantation process is used to amorphize the materials of the first source / drain doped region 203 and the second source / drain doped region 204, making it easier to form metal silicides between the first conductive structure and the first source / drain doped region 203, and between the second conductive structure and the second source / drain doped region 204. At the same time, the quality of the formed metal silicides is better, thereby reducing the contact resistance between the first conductive structure and the first source / drain doped region 203, and reducing the contact resistance between the second conductive structure and the second source / drain doped region 204, thus improving the conductivity.

[0066] The second ion in the second ion implantation process includes the IVA ion or an inert gas ion.

[0067] In this embodiment, the second ion in the second ion implantation process includes germanium ions.

[0068] Please refer to Figure 9 After the second ion implantation, a first isolation layer 209 is formed on the sidewall surface of the first opening 206.

[0069] In this embodiment, while forming the first isolation layer 209, a second isolation layer 210 is also formed on the sidewall surface of the second opening 207.

[0070] The first isolation layer 209 is used to increase the electrical isolation between the first conductive structure and the first gate structure 201 subsequently formed in the first opening 206, and the second isolation layer 210 is used to increase the electrical isolation between the second conductive structure and the second gate structure 202 subsequently formed in the second opening 207.

[0071] The method for forming the first isolation layer 209 and the second isolation layer 210 includes: forming an isolation material layer (not shown) on the sidewall surface and bottom surface of the first opening 206, the sidewall surface and bottom surface of the second opening 207, and the dielectric structure 205; and etching back the isolation material layer until the surface of the first source / drain doped region 203 and the surface of the second source / drain doped region 204 are exposed, thereby forming the first isolation layer 209 and the second isolation layer 210.

[0072] The first insulating layer 209 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. The second insulating layer 210 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0073] In this embodiment, the material of the first isolation layer 209 includes silicon nitride; the material of the second isolation layer 210 includes silicon nitride.

[0074] The process for forming the isolation material layer includes atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, the process for forming the isolation material layer includes ALD, which can form a dense and thin isolation material layer.

[0075] Because the first ion implantation process is first used to implant the first source / drain doped region 203 exposed by the first opening 206, and then the first isolation layer 209 is formed on the sidewall surface of the first opening 206, the first isolation layer 209 is less likely to be modified in the process of forming the mask layer 208, the first ion implantation, and the removal of the mask layer 208. This reduces the possibility of the first isolation layer 209 becoming larger after modification. As a result, it is easier to fill the first opening 206 with conductive material, and the contact effect between the formed first conductive structure and the first source / drain doped region 203 is better.

[0076] Please refer to Figure 10 After forming the first isolation layer 209 and the second isolation layer 210, the method further includes: forming a first conductive structure 211 in the first opening 206, the first conductive structure 211 being electrically connected to the first source / drain doped region 203; and forming a second conductive structure 212 in the second opening 207, the second conductive structure 212 being electrically connected to the second source / drain doped region 204.

[0077] The method for forming the first conductive structure 211 and the second conductive structure 212 includes: forming a conductive material layer (not shown) in the first opening 206, the second opening 207 and on the dielectric structure 205; planarizing the conductive material layer until the surface of the dielectric structure 205 is exposed; forming the first conductive structure 211 in the first opening 206 and forming the second conductive structure 212 in the second opening 207.

[0078] The process for forming the conductive material layer includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the process for forming the conductive material layer includes chemical vapor deposition.

[0079] Because the first ion implantation process is first used to implant the first source / drain doped region 203 exposed by the first opening 206, and then the first isolation layer 209 is formed on the sidewall surface of the first opening 206, the first isolation layer 209 is less likely to be modified in the process of forming the mask layer 208, the first ion implantation, and the removal of the mask layer 208. This reduces the possibility of the first isolation layer 209 becoming larger after being modified. As a result, when the conductive structure material is filled into the first opening 206, it is easier to fill, and the contact effect between the formed first conductive structure 211 and the first source / drain doped region 203 is better.

[0080] After forming the first conductive structure 211 and the second conductive structure 212, the process further includes: annealing the first conductive structure 211 and the second conductive structure 212 to form metal silicides (not shown) between the first conductive structure 211 and the first source / drain doped region 203 and between the second conductive structure 212 and the second source / drain doped region 204. The process for forming the metal silicides is a common technique in the art and will not be described in detail here.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first gate structure is formed on a first region, and first source / drain doped regions are formed in the substrates on both sides of the first gate structure. A second gate structure is formed on a second region, and second source / drain doped regions are formed in the substrates on both sides of the second gate structure. A dielectric structure is formed on the substrate, wherein the dielectric structure is located on the sidewall surface and top surface of the first gate structure and on the sidewall surface and top surface of the second gate structure. A first opening is formed within a dielectric structure in a first region, the first opening exposing the surface of the first source / drain doped region; a second opening is formed within a dielectric structure in a second region, the second opening exposing the surface of the second source / drain doped region. A mask layer is formed on the dielectric structure, the mask layer is also located within the second opening, and the mask layer exposes the first region; Using the mask layer as a mask, the first source / drain doped region exposed by the first opening is subjected to first ion implantation; After the first ion implantation, the mask layer is removed; A second ion implantation is performed on the first source / drain doped region exposed by the first opening and the second source / drain doped region exposed by the second opening; After removing the mask layer, a first isolation layer is formed on the surface of the first opening sidewall.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the mask layer includes: forming an initial mask layer on a substrate; removing the initial mask layer on the first region to form the mask layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the mask layer includes photoresist.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The process for removing the mask layer includes an ashing process, wherein the gas used in the ashing process includes oxygen or an oxygen-containing gas.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second ion implanted in the second ion includes IVA ions or inert gas ions.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the second ion implantation, the method further includes forming a second isolation layer on the surface of the second opening sidewall.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the first isolation layer and the second isolation layer includes: forming an isolation material layer on the first opening sidewall surface and bottom surface, the second opening sidewall surface and bottom surface, and a dielectric structure; and etching back the isolation material layer until the first source / drain doped region surface and the second source / drain doped region surface are exposed, thereby forming the first isolation layer and the second isolation layer.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the first isolation layer and the second isolation layer, the method further includes: forming a first conductive structure in the first opening, the first conductive structure being electrically connected to the first source / drain doped region; and forming a second conductive structure in the second opening, the second conductive structure being electrically connected to the second source / drain doped region.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first source / drain doped region includes silicon and germanium.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first ion implanted in the first ion includes a P-type ion, which includes boron ions, boron-fluorine ions, or indium ions.

11. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first isolation layer is made of a dielectric material, which includes silicon nitride; the second isolation layer is made of a dielectric material, which includes silicon nitride.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first gate structure, the second gate structure, the first source / drain doped region, the second source / drain doped region, and the dielectric structure includes: forming a first dummy gate structure on a first region of a substrate, and forming a second dummy gate structure on a second region of a substrate; forming a first source / drain doped region in the substrate on both sides of the first dummy gate structure, and forming a second source / drain doped region in the substrate on both sides of the second dummy gate structure; forming an initial dielectric structure on the substrate, the initial dielectric structure being located on the sidewalls of the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, forming a first gate opening in the initial dielectric structure on the first region, and forming a second gate opening in the initial dielectric structure on the second region; forming a first gate structure in the first gate opening, and forming a second gate structure in the second gate opening; after forming the first gate structure and the second gate structure, forming the dielectric structure, the dielectric structure being located on the sidewall surface and the top surface of the first gate structure, and the dielectric structure being located on the sidewall surface and the top surface of the second gate structure.

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