Circuits and methods of forming circuits

Abstract

A circuit is provided. The circuit may include: a power stage including a first transistor and a second transistor; an encapsulation including an encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape relative to each other along their long axes; and passive electronic components disposed on or at least partially embedded in the encapsulation, which, in a top view, are located within a rectangular region defined by the L-shaped configuration and further adjacent to the first transistor and the second transistor.

Description

Technical Field

[0001] Several different embodiments generally relate to a circuit and a method of forming the circuit. Background Technology

[0002] like Figure 1A The multi-die power stage and half-bridge package shown can be configured with V IN -GND capacitor, used to provide a current loop during transistor switching.

[0003] A key characteristic of a loop is its parasitic stray loop inductance, which is crucial for the safe operation of the power stage. High loop inductance can cause significant drain-source voltage spikes during transistor switching, potentially leading to undesirable avalanche phenomena.

[0004] Typically, capacitors are mounted next to their packages on a printed circuit board (PCB). Figure 1B The image shows an example of such a circuit 101, comprising a package 100 with two transistors Q1 and Q2 and a capacitor 102 mounted on a PCB 104. Due to the need for a stable potential and the large distance between the capacitor leads, the impedance and inductance of these connections can be high. Furthermore, the assembly spacing between each pair of multiple power stages or half-bridges can be quite large because the capacitors are located between the power stages. Summary of the Invention

[0005] A circuit is provided. The circuit may include: a power stage including a first transistor and a second transistor; an encapsulation including an encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape relative to each other along their long axes; and passive electronic components disposed on or at least partially embedded in the encapsulation, which, in a top view, are located within a rectangular region defined by the L-shaped configuration and further adjacent to the first transistor and the second transistor. Attached Figure Description

[0006] In the accompanying drawings, the same reference numerals generally refer to the same parts in different views. The drawings are not necessarily drawn to scale, but the emphasis is generally on illustrating the principles of the invention. In the following description, several different embodiments of the invention are described with reference to the following drawings, wherein:

[0007] Figure 1A and Figure 1B Each of the diagrams schematically illustrates a circuit, in which, Figure 1B A circuit is shown that includes passive electronic components in an unoptimized location;

[0008] Figure 2A-2C Each of the diagrams schematically illustrates elements of a circuit according to several different embodiments;

[0009] Figure 3A and 3B Each of the above schematically illustrates a circuit according to several different embodiments;

[0010] Figures 4A-4C Each of the above schematically illustrates a circuit according to several different embodiments;

[0011] Figure 5A A circuit with an alternative configuration is schematically shown;

[0012] Figure 5B Will Figure 5A Visualization of current density in the circuit;

[0013] Figure 5C The circuits according to several different embodiments are illustrated schematically;

[0014] Figure 5D Will Figure 5C Visualization of current density in the circuit;

[0015] Figure 5E The circuits according to several different embodiments are illustrated schematically;

[0016] Figure 5F Will Figure 5E Visualization of current density in the circuit;

[0017] Figure 5G The circuits according to several different embodiments are illustrated schematically;

[0018] Figure 5H Will Figure 5G Visualization of current density in the circuit;

[0019] Figure 6A and 6B Circuits according to several different embodiments are schematically shown in top view and cross-sectional view, respectively.

[0020] Figure 7 A flowchart illustrating a method for forming a circuit according to several different embodiments is shown; and

[0021] Figure 8 A flowchart illustrating a method for forming a circuit according to several different embodiments is shown. Detailed Implementation

[0022] The following detailed description refers to the accompanying drawings, which illustrate by way of illustration specific details and embodiments in which the invention may be practiced.

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily considered superior to or better than other embodiments or designs.

[0024] The term "above" as used herein to describe the formation of deposited material "on" a side or surface may be used to indicate that the deposited material can be formed "directly" on the side or surface, for example, in direct contact with the side or surface. The term "above" as used herein to describe the formation of deposited material "on" a side or surface may also be used to indicate that the deposited material can be formed "indirectly" on the side or surface with one or more additional layers disposed between the side or surface and the deposited material.

[0025] Several different aspects of this disclosure are provided for apparatuses, and several different aspects of this disclosure are provided for methods. It should be understood that the basic characteristics of the apparatus also apply to these methods, and vice versa. Therefore, for the sake of brevity, repeated descriptions of such characteristics may have been omitted.

[0026] Minimizing loop inductance may be directly related to the location and orientation of capacitors in a circuit that may include, for example, multi-die power stages and / or half-bridge packages that can be arranged on a printed circuit board (PCB).

[0027] In several different embodiments, a circuit is provided having a parasitic loop inductance value equal to or lower than that of a conventional component adjacent to a package on a PCB. External capacitors on the PCB can be removed. Therefore, a circuit with reduced size is provided.

[0028] In several different embodiments, for example, a circuit comprising multiple die power stages or a half-bridge package or a circuit consisting of multiple die power stages or a half-bridge package is provided with an encapsulation (thereby forming a semiconductor package) and one or more capacitors may be integrated on top of or embedded within the encapsulation.

[0029] In several different embodiments, the power stage may include two transistors that can be arranged in an L-shape, passive electronic components, such as V having the functions described above. IN The GND capacitor can be arranged in an L-shape within or on an encapsulation. Guidelines for optimizing the location and orientation of passive electronic components are provided in several different embodiments.

[0030] In several different embodiments, the closed-loop region formed in the circuit by multiple die half-bridges (high-voltage side and low-voltage side dies) and capacitors that can be connected to pads on the two dies to stabilize the voltage between those pads can be minimized. The closed-loop region 550 is... Figure 5C and 5E It is marked in, and is still Figure 5A An alternative configuration is shown in the figure.

[0031] Figure 2A-2C , Figure 3A , Figure 3B , Figures 4A-4C , Figure 5C , Figure 5E , Figure 5G , Figure 6A and Figure 6B Each of the above schematically illustrates a circuit 200 or an element thereof according to a plurality of different embodiments, and Figure 5A An alternative configuration is shown.

[0032] Circuit 200 may include a power stage (which may operate in common-emitter, CE, or common-source mode) comprising a first transistor Q1 and a second transistor Q2. The power stage may, for example, include a half-bridge circuit, wherein the first transistor Q1 may be the high-side transistor of the half-bridge circuit, and the second transistor Q2 may be the low-side transistor of the half-bridge circuit. The first transistor Q1 and the second transistor Q2 may be arranged in an L-shape relative to each other along their long axes. This can be seen in all figures showing circuit 200 from the top and labelling the first transistor Q1 and the second transistor Q2. Figure 2A-2C This indicates how the dimensions and positions of the components in circuit 200 are defined. The first transistor Q1 can be a high-side transistor of the power stage, and the second transistor Q2 can be a low-side transistor of the power stage.

[0033] Circuit 200 may further include encapsulation 660, which includes encapsulation material for encapsulating a power stage. Encapsulation 660 is only used in... Figure 6B The sectional view shown is illustrated and has been omitted in other figures to avoid confusion.

[0034] Circuit 200 may also include passive electronic components 102, which may be disposed on or embedded within encapsulation 660. Passive electronic components 102 may be, for example, capacitors, such as V... IN -GND capacitor. In some diagrams, for example in Figure 2A-2C , Figures 4A-4C , Figures 6A-6B In this figure, the passive electronic component 102 is represented as a single element, while in other figures, such as in [the figure], it is shown as a single element. Figure 3A and 3B , Figure 5A-5G In this drawing, the passive electronic component 102 is represented as a two-part element. The difference lies in that, in one case, the passive electronic component 102 itself is represented as a single element, while in the other case, only its two contact pads are shown. Both representations are indicated by the reference numeral 102.

[0035] Although most of the accompanying drawings show many elements of circuit 200, such as redistribution layers, vias, etc., only relevant elements and aspects are discussed herein, particularly the relative positioning of the first transistor Q1, the second transistor Q2, and the passive electronic component 102. Apart from this, circuit 200 can be formed substantially as is known in the art, for example, by chip embedding techniques.

[0036] The passive electronic component 102 may be at least partially arranged within a rectangular region B1 (also referred to as rectangle B1), which, in a top view, is defined by an L-shaped configuration of the first transistor Q1 and the second transistor Q2. The rectangular region B1 may also be adjacent to both the first transistor Q1 and the second transistor Q2. In other words, the rectangular region B1 may be an "inner" rectangular region of an L-shape and may be directly adjacent to each of the first transistor Q1 and the second transistor Q2.

[0037] The (larger) rectangular region B1 can be defined as follows (see...) Figure 2A In the first direction a, the rectangular region B1 can be adjacent to the inner edge of the first transistor Q1 and can have a length Bl. a The length Bl a Corresponding to the difference between the length X2 of the major axis of the second transistor Q2 and the length X1 of the minor axis of the first transistor Q1, and in a second direction b that can be orthogonal to the first direction a, rectangle B1 can be adjacent to the inner edge of the second transistor Q2 and can have a length B1. b The length B1 b This corresponds to the sum of the interval d between the first transistor Q1 and the second transistor Q2 and the length h of the major axis of the first transistor Q1.

[0038] In the accompanying drawings illustrating various embodiments, passive electronic components 102, such as V, are positioned. IN Various options for the GND capacitor are shown.

[0039] It is easy to see that positioning the passive electronic component 102, such as a capacitor, anywhere within the rectangular region B1 creates a more efficient and effective electronic configuration than... Figure 1B The existing technology configuration is more compact. In other words, compared to any embodiment where passive electronic components 102, such as capacitors, are embedded in or arranged on the encapsulation 660 within the rectangular region B1, Figure 1B Existing technology configurations all require more PCB space. The loop inductance value can be improved relative to at least some existing technology configurations.

[0040] In several different embodiments, the location of the passive electronic component 102 may be further confined within a rectangular region B1, for example, within a triangular region B2 (also referred to as triangle B2) or a (smaller) rectangular region B3 (also referred to as (smaller) rectangle B3), both of which can be completely contained within the (larger) rectangular region B1. This reduces the loop inductance value, which can improve the performance of circuit 200.

[0041] In several different embodiments, the triangular region B2 can be defined as follows (see...) Figure 2B In the first direction a, the triangular region B2 can be adjacent to the inner edge of the first transistor Q1 and can have a length B2. a Length B2 a This corresponds to the difference between the major axis length X2 of the second transistor Q2 and the minor axis length X1 of the first transistor Q1 (in other words, it is the same as the length of the rectangular region B1).

[0042] In a second direction b that can be orthogonal to the first direction a, triangle B2 can be adjacent to the inner edge of the second transistor Q2 and can have a length B2. b Length B2 b The interval d between the first transistor Q1 and the second transistor Q2 is the sum of the length h of the major axis of the first transistor Q1 (in other words, the same as the length of the rectangular region B1). The hypotenuse of the triangular region B2 can be defined by connecting the open endpoints of the sides of triangle B2 in the first direction with the open endpoints of the sides of triangle B2 in the second direction.

[0043] In other words, the triangular region B2 can be defined by an L-shaped configuration and a line connecting the inner edge of the first transistor Q1 to the end furthest from the second transistor Q2 and the inner edge of the second transistor Q2 to the end furthest from the first transistor Q1.

[0044] In several different embodiments, the orientation of the passive electronic component 102 of circuit 400 (which may additionally include or be composed of components similar to or identical to those of circuit 200) can be limited to a range of orientation angle α. The orientation angle α can be measured between the minor axis of the passive electronic component 102 (wherein the major axis of the passive electronic component 102 extends through the center of the two contact pads of the passive electronic component 102, and the minor axis is perpendicular to the major axis) and the line connecting the geometric center of the first transistor Q1 and the geometric center of the second transistor Q2. In other words, the orientation angle α is the angle between a line of symmetry along the short edge of the passive electronic component 102 and the connecting line passing through the top-view center of the first transistor Q1 and the top-view center of the second transistor Q2. In several different embodiments, the orientation angle α can range from about 45° to about 135°. This can reduce the loop inductance value, which can improve the performance of circuit 200.

[0045] In several different embodiments, the passive electronic component 102 can be arranged within a rectangular region B1, a triangular region B2, or a smaller rectangular region B3 at an orientation angle α ranging from approximately 45° to approximately 135°. This allows for the combination of the positive effects of the position and orientation of the passive electronic component 102 on the loop inductance value. If the passive electronic component 102 is arranged at an angle α between 45° and 135° in the smaller rectangular region B3, the loop inductance is likely to be minimized.

[0046] Some configurations of loop inductance values ​​are shown in some diagrams, for example in... Figure 3A , 3B 5A / 5B, 5C / 5D, 5E / 5F, and 5G / 5H are indicated, and their range extends from where most of the passive electronic components 102 are arranged in a smaller rectangular region B3 with an angle α = 65°. Figure 5E The configuration of 0.19nH ( / 5F) includes passive electronic components 102 partially arranged within a smaller rectangular region B3, but partially arranged outside a triangular region B2 with an angle α of approximately 25°. Figure 3A To avoid crowding, Figure 3A The angle α is not marked, but it is related to... Figure 5A The configuration (roughly the same as in the previous example) is 0.88nH. The main reason for such a large difference in loop inductance values ​​is likely due to different current paths and different loop regions.

[0047] The effects of the loop region can be visualized by the distribution of AC current density in circuits 200 and 400 during switching. This visualization is shown in... Figure 5B , 5D In 5F and 5H, Figure 5B and 5E Shown as perspective top and bottom views. The comparison of the distributions shows that the embodiment with a high loop inductance value covers a larger area with an even higher value.

[0048] In several different embodiments, the (smaller) rectangular region B3 can be defined as follows (see...) Figure 2C In the first direction a, the rectangular region B3 may be adjacent to the inner edge of the first transistor Q1 and may have a length B3 that is one-third of the major axis of the second transistor Q2. a Furthermore, in a second direction b that can be orthogonal to the first direction a, the rectangular region B3 can be adjacent to the inner edge of the second transistor Q2 and can have a length B3 that is the sum of the interval d between the first transistor Q1 and the second transistor Q2 and one-third of the major axis of the second transistor Q2 or half of the major axis of the first transistor Q1. b The larger one shall prevail (in other words, B3). b=max[h / 2;X / 3]+d.

[0049] Figure 7 A flowchart 700 showing a method for forming a circuit according to several different embodiments is shown.

[0050] The method may include: forming a power stage, including arranging a first transistor and a second transistor in an L-shape relative to each other along their long axes (in step 710); encapsulating the power stage with an encapsulation material (in step 720); and arranging passive electronic components on the encapsulation material or embedding passive electronic components at least partially within the encapsulation material such that the passive electronic components are located in a rectangular region defined by the L-shaped arrangement and further adjacent to the first transistor and the second transistor in a top view (in step 730).

[0051] Figure 8 A flowchart 800 showing a method for forming a circuit according to several different embodiments is shown.

[0052] The method may include: forming a power stage, including arranging a first transistor and a second transistor in an L-shape relative to each other along their long axes (in step 810); encapsulating the power stage with an encapsulation material (in step 820); and arranging passive electronic components on the encapsulation material or embedding passive electronic components at least partially within the encapsulation material such that the passive electronic components are arranged with an orientation angle in the range of about 45° to about 135°, wherein the orientation angle is the angle between a line of symmetry along the short edge of the passive electronic component and a line connecting the top view centers of the first transistor and the second transistor (in step 830).

[0053] The following will illustrate various examples:

[0054] Example 1 is a circuit comprising: a power stage including a first transistor and a second transistor; an encapsulation comprising an encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape relative to each other along their long axes; and passive electronic components disposed on or at least partially embedded in the encapsulation, wherein, in a top view, the passive electronic components are within a rectangular region defined by the L-shaped configuration and further adjacent to the first transistor and the second transistor.

[0055] In Example 2, the subject matter of Example 1 may optionally include: passive electronic components arranged at an orientation angle ranging from about 45° to about 135°, wherein the orientation angle is the angle between a line of symmetry along the short edge of the passive electronic component and a connecting line passing through the top view center of the first transistor and the top view center of the second transistor.

[0056] In Example 3, the subject of Example 1 or 2 may optionally include: passive electronic components arranged entirely within a rectangular area.

[0057] Example 4 is a circuit comprising: a power stage including a first transistor and a second transistor; an encapsulation comprising an encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape relative to each other along their long axes; and a passive electronic component arranged on or embedded in the encapsulation at an orientation angle ranging from about 45° to about 135°, wherein the orientation angle is the angle between a line of symmetry along a short edge of the passive electronic component and a connecting line passing through the top view center of the first transistor and the top view center of the second transistor.

[0058] In Example 5, the subject of Example 4 may optionally include: in a top view, passive electronic components are arranged within a rectangular area defined by an L-shaped configuration and further adjacent to the first and second transistors.

[0059] In Example 6, the subject of Example 5 may optionally include: a rectangular region defined as follows: in a first direction, the rectangle is adjacent to the inner edge of the first transistor and has a length of one-third of the major axis of the second transistor; and in a second direction orthogonal to the first direction, the rectangle is adjacent to the inner edge of the second transistor and has a length that is the sum of the larger of the interval between the first and second transistors and one-third of the major axis of the second transistor and half of the major axis of the first transistor.

[0060] In Example 7, the subject matter of any one of Examples 1-6 may optionally include: the passive electronic component is arranged at least partially in a triangular region defined by an L-shaped configuration and a line connecting the inner edge of the first transistor to the end furthest from the second transistor and the inner edge of the second transistor to the end furthest from the first transistor.

[0061] In Example 8, the subject matter of Example 7 may optionally include: the passive electronic components are arranged entirely within a triangular region.

[0062] In Example 9, the subject matter of any of Examples 1-8 may optionally include: the passive electronic component is a capacitor.

[0063] In Example 10, the subject matter of any one of Examples 1-9 may optionally include: the power stage includes a half-bridge circuit, wherein the first transistor is a high-side transistor of the half-bridge circuit and the second transistor is a low-side transistor of the half-bridge circuit.

[0064] In Example 11, the subject matter of Example 10 may optionally include: the passive electronic component is electrically connected between the drain of the high-voltage side transistor and the source of the low-voltage side transistor.

[0065] In Example 12, the subject matter of any one of Examples 1-11 may optionally include: the first transistor and the second transistor are arranged via chip embedding technology.

[0066] In Example 13, the subject matter of any of Examples 1-12 may optionally further include a driver circuit, wherein the passive electronic component is arranged laterally between the second transistor and the driver circuit in a top view.

[0067] In Example 14, the subject matter of any one of Examples 1-13 may optionally include: the first transistor region covered by the first transistor is smaller than the second transistor region covered by the second transistor.

[0068] Example 15 is a method of forming a circuit. The method may include: forming a power stage, including arranging a first transistor and a second transistor in an L-shape relative to each other along their long axes; encapsulating the power stage with an encapsulation material; and arranging passive electronic components on the encapsulation material or embedding passive electronic components at least partially within the encapsulation material such that the passive electronic components are located in a rectangular region defined by the L-shaped arrangement and further adjacent to the first transistor and the second transistor in a top view.

[0069] In Example 16, the subject matter of Example 15 may optionally include: the passive electronic component is arranged with an orientation angle in the range of about 45° to about 135°, wherein the orientation angle is the angle between a line of symmetry along the short edge of the passive electronic component and a line connecting the top view center of the first transistor and the top view center of the second transistor.

[0070] In Example 17, the subject matter of Example 15 or 16 may optionally include: the passive electronic components are arranged entirely within a rectangular area.

[0071] Example 18 is a method of forming a circuit. The method may include: forming a power stage, including arranging a first transistor and a second transistor in an L-shape relative to each other along their long axes; encapsulating the power stage with an encapsulation material; and arranging passive electronic components on or at least partially embedding passive electronic components within the encapsulation material such that the passive electronic components are arranged at an orientation angle ranging from about 45° to about 135°, wherein the orientation angle is the angle between a line of symmetry along a short edge of the passive electronic component and a connecting line passing through the top view center of the first transistor and the top view center of the second transistor.

[0072] In Example 19, the subject matter of Example 18 may optionally include: in a top view, passive electronic components are arranged within a rectangular region defined by an L-shaped configuration and further adjacent to the first and second transistors.

[0073] In Example 20, the subject of Example 19 may optionally include: a rectangular region defined as follows: in a first direction, the rectangle is adjacent to the inner edge of the first transistor and has a length of one-third of the major axis of the second transistor; and in a second direction orthogonal to the first direction, the rectangle is adjacent to the inner edge of the second transistor and has a length that is the sum of the larger of the interval between the first and second transistors and one-third of the major axis of the second transistor and half of the major axis of the first transistor.

[0074] In Example 21, the subject matter of any one of Examples 15-20 may optionally include: the passive electronic component is arranged at least partially in a triangular region defined by an L-shaped configuration and a line connecting the inner edge of the first transistor to the end furthest from the second transistor and the inner edge of the second transistor to the end furthest from the first transistor.

[0075] In Example 22, the subject matter of Example 21 may optionally include: the passive electronic components are arranged entirely within a triangular region.

[0076] In Example 23, the subject matter of any of Examples 15-22 may optionally include: the passive electronic component is a capacitor.

[0077] In Example 24, the subject matter of any one of Examples 15-23 may optionally include: the power stage includes a half-bridge circuit, wherein the first transistor is a high-side transistor of the half-bridge circuit and the second transistor is a low-side transistor of the half-bridge circuit.

[0078] In Example 25, the subject matter of Example 24 may optionally include: the passive electronic component is electrically connected between the drain of the high-voltage side transistor and the source of the low-voltage side transistor.

[0079] In Example 26, the subject matter of any of Examples 15-25 may optionally include: forming a power stage including embedding a first transistor and a second transistor.

[0080] In Example 27, the subject matter of any of Examples 15-26 may optionally include: arranging the driver circuit in such a way that passive electronic components are arranged between the second transistor and the driver circuit.

[0081] In Example 28, the subject matter of any one of Examples 15-27 may optionally include: the first transistor region covered by the first transistor is smaller than the second transistor region covered by the second transistor.

[0082] While the invention has been specifically shown and described with reference to particular embodiments, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the scope of the invention is indicated by the appended claims and is thus intended to include all changes falling within the meaning and scope of equivalent substitutions that fall within the claims.

Claims

1. A circuit comprising: The power stage includes a first transistor (Q1) and a second transistor (Q2); Encapsulation materials, including encapsulation materials for encapsulating power stages; The first transistor (Q1) and the second transistor (Q2) are arranged in an L-shape relative to each other along their long axes; and A capacitor disposed on or at least partially embedded within an encapsulation, which, in a top view, lies within a rectangular region defined by an L-shaped configuration and is further adjacent to a first transistor (Q1) and a second transistor (Q2), the rectangular region being defined as follows: in a first direction, the rectangular region is adjacent to the inner edge of the first transistor (Q1) and its length corresponds to the difference between the length of the major axis of the second transistor (Q2) and the length of the minor axis of the first transistor (Q1); and in a second direction orthogonal to the first direction, the rectangular region is adjacent to the inner edge of the second transistor (Q2) and its length corresponds to the sum of the spacing between the first transistor (Q1) and the second transistor (Q2) and the length of the major axis of the first transistor (Q1). The capacitors are arranged entirely within a rectangular area.

2. The circuit according to claim 1, in, The capacitors are arranged with an orientation angle ranging from 45° to 135°, wherein the orientation angle is the angle between a line of symmetry along the short edge of the capacitor and a line connecting the top view center of the first transistor (Q1) and the top view center of the second transistor (Q2).

3. The circuit according to claim 2, in, The capacitor is arranged at least partially within a rectangular region as defined below: In the first direction, the rectangle is adjacent to the inner edge of the first transistor (Q1) and its length is one-third of the major axis of the second transistor; and In a second direction orthogonal to the first direction, the rectangle is adjacent to the inner edge of the second transistor (Q2) and its length is the sum of the larger of the interval between the first and second transistors and one-third of the major axis of the second transistor and half of the major axis of the first transistor.

4. The circuit according to any one of claims 1-3, in, The capacitor is at least partially arranged in a triangular region defined by an L-shaped configuration and a line connecting the inner edge of the first transistor (Q1) to the end furthest from the second transistor (Q2) and the inner edge of the second transistor (Q2) to the end furthest from the first transistor (Q1).

5. The circuit according to claim 4, in, The capacitors are arranged entirely within the triangular region.

6. The circuit according to any one of claims 1-3 and 5, in, The power stage includes a half-bridge circuit; Wherein, the first transistor (Q1) is the high-voltage side transistor of the half-bridge circuit; and The second transistor (Q2) is the low-voltage side transistor of the half-bridge circuit.

7. The circuit according to claim 6, in, The capacitor is electrically connected between the drain of the high-voltage side transistor and the source of the low-voltage side transistor.

8. The circuit according to any one of claims 1-3, 5, and 7, in, The first transistor and the second transistor are arranged using chip embedding technology.

9. The circuit according to any one of claims 1-3, 5, and 7, further comprising: Driver circuit, In the top view, the capacitor is arranged laterally between the second transistor and the driver circuit.

10. The circuit according to any one of claims 1-3, 5, and 7, in, The area of ​​the first transistor covered by the first transistor is smaller than the area of ​​the second transistor covered by the second transistor.

11. A method of forming a circuit, the method comprising: Forming a power stage includes arranging a first transistor and a second transistor in an L-shape relative to each other along their long axes; Encapsulate the power stage with encapsulating material; as well as The capacitor is arranged on or at least partially embedded in the encapsulation material such that, in a top view, the capacitor is located within a rectangular region defined by an L-shaped arrangement and further adjacent to a first transistor and a second transistor. This rectangular region is defined as follows: in a first direction, the rectangular region is adjacent to the inner edge of the first transistor and its length corresponds to the difference between the length of the major axis of the second transistor and the length of the minor axis of the first transistor; and in a second direction orthogonal to the first direction, the rectangular region is adjacent to the inner edge of the second transistor and its length corresponds to the sum of the spacing between the first and second transistors and the length of the major axis of the first transistor. The capacitors are arranged entirely within a rectangular area.

12. The method according to claim 11, in, The capacitor is arranged with an orientation angle ranging from 45° to 135°, wherein the orientation angle is the angle between a line of symmetry along the short edge of the capacitor and a line connecting the top view center of the first transistor and the top view center of the second transistor.

13. The method according to claim 12, in, The capacitor is arranged at least partially within a rectangular region as defined below: In the first direction, the rectangle is adjacent to the inner edge of the first transistor and its length is one-third of the major axis of the second transistor; and In a second direction orthogonal to the first direction, the rectangle is adjacent to the inner edge of the second transistor and its length is the sum of the larger of the interval between the first and second transistors and one-third of the major axis of the second transistor and half of the major axis of the first transistor.

14. The method according to any one of claims 11-13, in, The capacitor is at least partially arranged in a triangular region defined by an L-shaped configuration and a line connecting the inner edge of the first transistor (Q1) to the end furthest from the second transistor (Q2) and the inner edge of the second transistor (Q2) to the end furthest from the first transistor (Q1).

15. The method according to claim 14, in, The capacitors are arranged entirely within the triangular region.

16. The method according to any one of claims 11-13, 15, in, The power stage includes a half-bridge circuit; Wherein, the first transistor (Q1) is the high-voltage side transistor of the half-bridge circuit; and The second transistor (Q2) is the low-voltage side transistor of the half-bridge circuit.

17. The method according to claim 16, in, The capacitor is electrically connected between the drain of the high-voltage side transistor and the source of the low-voltage side transistor.

18. The method according to any one of claims 11-13, 15, and 17, in, Forming a power stage includes embedding a first transistor and a second transistor.

19. The method according to any one of claims 11-13, 15, and 17, further comprising: The driver circuit is arranged such that the capacitor is placed between the second transistor and the driver circuit.

20. The method according to any one of claims 11-13, 15, and 17, in, The area of ​​the first transistor covered by the first transistor is smaller than the area of ​​the second transistor covered by the second transistor.

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