Semiconductor package

Abstract

A semiconductor package includes a semiconductor chip having normal connection electrodes and measurement connection electrodes formed on a first surface, and a substrate having normal substrate pads connected to the normal connection electrodes and measurement substrate pads connected to the measurement connection electrodes. The normal substrate pads and the measurement substrate pads are formed on a surface facing the first surface. The measurement connection electrodes include first and second edge measurement connection electrodes and first and second central measurement connection electrodes. The measurement substrate pads include a central measurement substrate pad, first and second edge measurement substrate pads. The first edge measurement connection electrode and the first central measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second central measurement connection electrode are electrically connected to each other.

Description

Technical Field

[0001] This patent document relates to semiconductor packages, and more specifically, to semiconductor packages in which semiconductor chips are mounted on a substrate. Background Technology

[0002] Semiconductor chips can be mounted on a substrate in various ways. As an example, a method can be used to attach the connection electrodes of the semiconductor chip to pads formed on the surface of the substrate, such as a flip-chip bonding method.

[0003] In flip chip bonding processes, various methods can be used to check whether the connection electrodes of a semiconductor chip are correctly bonded to the substrate pads. Summary of the Invention

[0004] In one embodiment, a semiconductor package may include: a semiconductor chip including normal connection electrodes and measurement connection electrodes formed on a first surface; and a substrate including normal substrate pads connected to the normal connection electrodes and measurement substrate pads connected to the measurement connection electrodes, the normal substrate pads and measurement substrate pads being formed on a surface facing the first surface, wherein the measurement connection electrodes include first edge measurement connection electrodes and second edge measurement connection electrodes respectively formed in two side edge regions of the semiconductor chip, and first central measurement connection electrodes and second central measurement connection electrodes arranged spaced apart from each other in a central region of the semiconductor chip, the side edge regions extending along a first direction, and the central region having two electrodes arranged in the first direction. Between the side edge regions, wherein the measurement substrate pads include: a central measurement substrate pad having a long side in the arrangement direction of a first central measurement connection electrode and a second central measurement connection electrode to simultaneously connect the first central measurement connection electrode and the second central measurement connection electrode; a first edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad to simultaneously connect the first edge measurement connection electrode; and a second edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad to simultaneously connect the second edge measurement connection electrode, wherein the first edge measurement connection electrode and the first central measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second central measurement connection electrode are electrically connected to each other. Attached Figure Description

[0005] Figure 1A This is a plan view of a semiconductor chip illustrating a semiconductor package according to an embodiment of the present disclosure.

[0006] Figure 1B It is along Figure 1A The cross-sectional view taken by line AA′.

[0007] Figure 2This is a plan view illustrating a substrate of a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 3A This is an example in Figure 1A and Figure 1B Semiconductor chips are installed in Figure 2 A plan view of a semiconductor package in its state on a substrate.

[0009] Figure 3B It is along Figure 3A The cross-sectional view taken from line BB′.

[0010] Figures 4A to 4E This is a diagram illustrating the alignment between the semiconductor chip 100 and the substrate 200.

[0011] Figure 5A This is a plan view of a semiconductor chip illustrating a semiconductor package according to another embodiment of the present disclosure.

[0012] Figure 5B It is along Figure 5A The cross-sectional view taken by line CC′.

[0013] Figure 6 This is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure.

[0014] Figure 7 A block diagram illustrating an electronic system employing a memory card including a semiconductor package, according to an embodiment, is shown.

[0015] Figure 8 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0016] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] The accompanying drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly show some features of the described example or implementation. When a particular example in the drawings or description is presented with two or more layers of a multilayer structure, the relative positioning of these layers or the order in which these layers are arranged reflects the specific implementation of the described or illustrated example, and different relative positioning or order in which layers are arranged may be possible. In addition, the described or illustrated example of a multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between the two layers shown). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also indicate a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0018] In the following description of the implementation, when a parameter is referred to as “predetermined,” it can be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during a period of execution of the process or algorithm.

[0019] It will be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0020] Furthermore, it will be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0021] In the following text, reference will be made to Figures 1A to 3B A semiconductor package according to embodiments of the present disclosure is described.

[0022] Figure 1A This is a plan view of a semiconductor chip illustrating a semiconductor package according to an embodiment of the present disclosure, and Figure 1B It is along Figure 1A The cross-sectional view taken by line AA′. Figure 2 This is a plan view illustrating a substrate of a semiconductor package according to an embodiment of the present disclosure. Figure 3A This is an example in Figure 1A and Figure 1B Semiconductor chips installed Figure 2 A plan view of a semiconductor package in its state on a substrate, and Figure 3B It is along Figure 3A The cross-sectional view taken from line BB′.

[0023] First, refer to Figure 1A and Figure 1B A semiconductor chip 100 according to this embodiment can be provided. The semiconductor chip 100 may include a main body 110 and a plurality of connection electrodes 120 and 130 attached to a first surface 111 of the main body 110 and electrically connected to the semiconductor chip 100.

[0024] The main body 110 may include a first surface 111, a second surface 112 facing the first surface 111, and a side surface connecting the first surface 111 and the second surface 112. Figure 1B In this configuration, the semiconductor chip 100 can be configured such that the first surface 111 faces upward and the second surface 112 faces downward. However, the relative positions of the first surface 111 and the second surface 112 can be changed. For example, when the semiconductor chip 100 is mounted on a substrate described later (see reference...). Figures 2 to 3B When “200” is mentioned, the semiconductor chip 100 can be mounted with the first surface 111 facing down. Figure 1A This is a plan view illustrating the first surface 111.

[0025] The main body 110 may include a multilayer wiring structure that performs the required functions of the semiconductor chip 100. In this embodiment, for ease of description, only the wiring layer L1 of the multilayer wiring structure is illustrated. The wiring layer L1 may have a surface at the same level as the first surface 111 and may contact the connecting electrodes 120 and 130. When the semiconductor chip 100 is configured with the first surface 111 facing upwards, as shown... Figure 1B As shown, wiring layer L1 can be the topmost wiring layer in a multi-layer wiring structure. Wiring layer L1 can include multiple conductive patterns of various shapes (see...). Figure 1A and Figure 1B (Referring to 113, 114, and 115 in the diagram). These conductive patterns will be described later, along with the description of connecting electrodes 120 and 130.

[0026] An insulating layer 140 may be formed on the first surface 111 of the main body 110. The insulating layer 140 may have openings that expose portions of the wiring layer L1 while covering the first surface 111 of the main body 110. Connection electrodes 120 and 130 may be connected to the wiring layer L1 through these openings. The portions of the wiring layer L1 exposed through the openings of the insulating layer 140 may be referred to as pads. These pads will be described later along with the connection electrodes 120 and 130.

[0027] The connecting electrodes 120 and 130 may include a normal connecting electrode 120 and a measurement connecting electrode 130.

[0028] Normal connection electrodes 120 can be connection electrodes to which signals or electricity required for the operation of semiconductor chip 100 are applied. In this embodiment, a plurality of normal connection electrodes 120 may be arranged along a first column R1 and a second column R2 in a plan view. That is, each column of the first column R1 and the second column R2 may include a plurality of normal connection electrodes 120 arranged in a row along a first direction. The first column R1 and the second column R2 may be arranged to be spaced apart from each other in a second direction, which is a direction intersecting the first direction. The number of normal connection electrodes 120 included in the first column R1 may be different from the number of normal connection electrodes 120 included in the second column R2. The first column R1 and the second column R2 may be located in the central region of semiconductor chip 100 in the second direction. For reference, the central region may refer to the region in the second direction excluding the two edge regions. The two edge regions may correspond to regions in the second direction whose distance from the two side surfaces of semiconductor chip 100 is less than half the width of semiconductor chip 100 in the second direction. However, this disclosure is not limited thereto, and the number, position, and arrangement of normal connection electrodes 120 may vary in various ways.

[0029] The conductive pattern of the wiring layer L1 connected to the normal connection electrode 120 is referred to as the normal conductive pattern 113. Furthermore, the portion of the normal conductive pattern 113 exposed through openings formed in the insulating layer 140 is referred to as the normal pad 113P. The normal connection electrode 120 can be electrically connected to the normal conductive pattern 113 by directly or indirectly contacting the normal pad 113P. The normal conductive pattern 113 can be part of the multilayer wiring structure of the main body 110 and can transmit signals or provide power to the normal connection electrode 120. Figure 1A In the planar view, the normal conductive pattern 113 and normal pad 113P are omitted. However, the normal conductive pattern 113 can have various planar shapes for signal and power transmission. The normal pad 113P can overlap with each normal connection electrode 120 and can have a planar shape slightly larger than each normal connection electrode 120. Similar to the normal connection electrodes 120, the normal pad 113P can also be disposed in the central region of the semiconductor chip 100. Therefore, the semiconductor chip 100 can be referred to as a central pad type semiconductor chip.

[0030] The measuring connection electrode 130 can be a connection electrode used to detect whether the connection between the normal substrate pad 220 and the normal connection electrode 120, which will be described in more detail later, is made normal. Here, the measuring connection electrode 130 can be positioned adjacent to the normal connection electrode 120, and can be positioned by considering the area of ​​the semiconductor chip 100. More specifically, it is as follows.

[0031] As described above, a plurality of normal connection electrodes 120 can be arranged in a first column R1 and a second column R2 along a first direction. In this case, in the first direction, the two edge regions of the area where the plurality of normal connection electrodes 120 are arranged will be referred to as the first edge region ER1 and the second edge region ER2, respectively, and the region between the first edge region ER1 and the second edge region ER2 will be referred to as the central region CR. The first edge region ER1 can be a region in which the distance from the normal connection electrode 120 closest to one side surface of the semiconductor chip 100 in the first direction is less than half the width of the area where the plurality of normal connection electrodes 120 are arranged in the first direction. The second edge region ER2 can be a region in which the distance from the normal connection electrode 120 closest to the other side surface of the semiconductor chip 100 in the first direction is less than half the width of the area where the plurality of normal connection electrodes 120 are arranged in the first direction.

[0032] In this configuration, the measurement connection electrode 130 may include a first edge measurement connection electrode 130E1 disposed in the first edge region ER1, a first central measurement connection electrode 130C1 and a second central measurement connection electrode 130C2 disposed in the central region CR, and a second edge measurement connection electrode 130E2 disposed in the second edge region ER2. The first edge measurement connection electrode 130E1 and the second edge measurement connection electrode 130E2 may be disposed on opposite sides of the first column R1 and the second column R2 in the second direction, respectively. Figure 1A In the plan view, the first edge measurement connection electrode 130E1 can be disposed on the right side of the second column R2, and the second edge measurement connection electrode 130E2 can be disposed on the left side of the first column R1. However, this disclosure is not limited thereto. In another embodiment, the first edge measurement connection electrode 130E1 can be disposed on the left side of the first column R1, and the second edge measurement connection electrode 130E2 can be disposed on the right side of the second column R2. The first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be disposed between the first column R1 and the second column R2 in a second direction. The first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be arranged at a predetermined interval along a first direction.

[0033] The conductive pattern of wiring layer L1 connecting the first edge measurement connection electrode 130E1 and the first central measurement connection electrode 130C1 to connect them will be referred to as the first measurement conductive pattern 114. The first measurement conductive pattern 114 may have a line shape extending between the first edge measurement connection electrode 130E1 and the first central measurement connection electrode 130C1. The two ends of the first measurement conductive pattern 114 may be exposed through openings formed in the insulating layer 140, and these exposed portions will be referred to as the first measurement pads 114P. Among the first measurement pads 114P, the pad connected to the first edge measurement connection electrode 130E1 will be referred to as the first edge measurement pad 114PE, and the pad connected to the first central measurement connection electrode 130C1 will be referred to as the first central measurement pad 114PC.

[0034] Additionally, the conductive pattern of wiring layer L1 connecting the second edge measurement connection electrode 130E2 and the second central measurement connection electrode 130C2 to connect them will be referred to as the second measurement conductive pattern 115. The second measurement conductive pattern 115 may have a line shape extending between the second edge measurement connection electrode 130E2 and the second central measurement connection electrode 130C2. Further reference... Figure 3B The two ends of the second measurement conductive pattern 115 can be exposed through openings formed in the insulating layer 140, and these exposed portions will be referred to as the second measurement pads 115P. Among the second measurement pads 115P, the pad connected to the second edge measurement connection electrode 130E2 will be referred to as the second edge measurement pad 115PE, and the pad connected to the second central measurement connection electrode 130C2 will be referred to as the second central measurement pad 115PC.

[0035] Normal conductive pattern 113, first measuring conductive pattern 114, and second measuring conductive pattern 115 can be used Figure 1B They are located at the same level in the vertical direction (i.e., in the direction of measuring the thickness of the semiconductor chip 100). Furthermore, the normal conductive pattern 113, the first measuring conductive pattern 114, and the second measuring conductive pattern 115 can be physically and electrically separated from each other. Although in Figure 1A There is no example of the shape of the normal conductive pattern 113 in the plan view; however, the first measuring conductive pattern 114 and the second measuring conductive pattern 115 can bypass the normal conductive pattern 113 to be electrically isolated from it. For this purpose, the first measuring conductive pattern 114 and the second measuring conductive pattern 115 can have a line shape that is curved in various directions.

[0036] In this embodiment, the normal connection electrode 120 and the measurement connection electrode 130 can be conductive bumps. Additionally, in this embodiment, the normal connection electrode 120 and the measurement connection electrode 130 can have a square shape in a plan view. For ease of description, the thickness of the lines in the square shape is shown to be different. However, this disclosure is not limited to this, and the normal connection electrode 120 and the measurement connection electrode 130 can be conductors with various shapes. As an example, the normal connection electrode 120 and the measurement connection electrode 130 can be solder bumps or metal pillar bumps on which a solder layer is formed.

[0037] Next, refer to Figure 2 The substrate 200 of this embodiment can be provided. The substrate 200 can be a substrate for a semiconductor package, having wiring structures and / or circuits for providing power or transmitting signals. For example, the substrate 200 can be a printed circuit board (PCB).

[0038] Refer to together Figure 1A , Figure 1B and Figure 2 The substrate 200 may have a first surface 201 facing the first surface 111 of the semiconductor chip 100. Substrate pads 220 and 230, electrically connecting the connection electrodes 120 and 130 of the semiconductor chip 100 to the substrate 200, may be formed on the first surface 201 of the substrate 200. For reference, a substrate pad may represent a conductive element or conductive terminal exposed through the first surface 201 of the substrate 200 for connecting the substrate 200 to other components. Further reference... Figure 3B In this embodiment, substrate pads 220 and 230 may be buried in substrate 200, and one surface of each of substrate pads 220 and 230 may be at the same level as the first surface 201 for exposure. However, this disclosure is not limited thereto. In another embodiment, some or all of substrate pads 220 and 230 may protrude from the first surface 201 of substrate 200.

[0039] The substrate pads 220 and 230 may include normal substrate pads 220 connected to normal connection electrodes 120 of semiconductor chip 100 and measurement substrate pads 230 connected to measurement connection electrodes 130 of semiconductor chip 100.

[0040] Normal substrate pads 220 may be part of the circuitry and / or wiring structure of substrate 200. As an example, normal substrate pads 220 may be bonding pads for flip-chip bonding. Multiple normal substrate pads 220 may be connected one-to-one to multiple normal connection electrodes 120. Therefore, normal substrate pads 220 may be arranged in the same manner as normal connection electrodes 120. For example, normal substrate pads 220 may be arranged in two columns along a first direction at the center of the second substrate 200 in a second direction. In this embodiment, in a plan view, normal substrate pads 220 may have a strip shape having a short side in the first direction and a long side in the second direction. However, this disclosure is not limited thereto. The planar shape of normal substrate pads 220 may be varied in various ways to facilitate connection with normal connection electrodes 120. Although not shown, one or both ends of normal substrate pads 220 may be connected to the circuitry and / or wiring structure of substrate 200 to provide a path for transmitting signals or providing power.

[0041] The measurement substrate pad 230 can be formed separately from the normal substrate pad 220 and the circuitry and / or wiring structure of the substrate 200 having the normal substrate pad 220. That is, the measurement substrate pad 230 can be electrically isolated from the circuitry and / or wiring structure of the substrate 200 while being spaced apart from it. Furthermore, the measurement substrate pad 230 can be formed from a different material than the normal substrate pad 220, or it can be formed to have a different thickness than the normal substrate pad 220. As an example, the measurement substrate pad 230 can be a lead.

[0042] The measurement substrate pad 230 may include: a first edge measurement substrate pad 230E1 connected to a first edge measurement connection electrode 130E1, a central measurement substrate pad 230C connected to a first central measurement connection electrode 130C1 and a second central measurement connection electrode 130C2, and a second edge measurement substrate pad 230E2 connected to a second edge measurement connection electrode 130E2.

[0043] The central measurement substrate pad 230C may have a shape that overlaps with and connects to the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2. As described above, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 may be arranged to be spaced apart from each other in a first direction. Therefore, the central measurement substrate pad 230C may have a strip shape having a long side in the first direction and a short side in the second direction.

[0044] The first edge measurement substrate pad 230E1 may have a strip shape with its long side in the second direction, and overlap with the first edge measurement connection electrode 130E1. That is, the long side of the first edge measurement substrate pad 230E1 may be orthogonal to the long side of the central measurement substrate pad 230C. The second edge measurement substrate pad 230E2 may have a strip shape with its long side in the second direction, and overlap with the second edge measurement connection electrode 130E2. That is, the long side of the second edge measurement substrate pad 230E2 may also be orthogonal to the long side of the central measurement substrate pad 230C. The reason for making the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2 orthogonal to the central measurement substrate pad 230C may be to detect misalignment between the semiconductor chip 100 and the substrate 200 and to detect the resulting connection failure between the semiconductor chip and the substrate 200. (See below for further details.) Figures 4A to 4E This will be described.

[0045] Furthermore, the first measurement terminal 231 and the second measurement terminal 232 can be connected to the ends of the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2, respectively. The first measurement terminal 231 and the second measurement terminal 232 can have a flat plate shape with dimensions relatively larger than the substrate pads to facilitate contact with probes or the like used for current detection. In this case, the first measurement terminal 231 and the second measurement terminal 232 can be spaced apart from the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2. This is because the positions of the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2 are determined based on the positions of the first edge measurement connection electrode 130E1 and the second edge measurement connection electrode 130E2 of the semiconductor chip 100, while the first measurement terminal 231 and the second measurement terminal 232 are formed in areas that do not overlap with the semiconductor chip 100 to facilitate contact with probes or the like. In this configuration, a first extension 235 extending from the first edge measurement substrate pad 230E1 to the first measurement terminal 231 and a second extension 236 extending from the second edge measurement substrate pad 230E2 to the second measurement terminal 232 can also be formed. Regardless of the orientation of the long sides of the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2, the first extension 235 and the second extension 236 can extend toward the first measurement terminal 231 and the second measurement terminal 232. In this embodiment, the first extension 235 and the second extension 236 can extend in a first direction. The first extension 235 and the second extension 236 can be leads integrally formed with the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2.

[0046] Next, refer to Figure 3A and Figure 3B, Figure 1A and Figure 1B Semiconductor chip 100 can be installed Figure 2 On substrate 200. Because semiconductor chip 100 is mounted on substrate 200 and first surface 111 faces substrate 200, the positions of normal connection electrode 120 and measurement connection electrode 130 in the second direction can be aligned with... Figure 1A The related components are reversed. That is, the left and right positions of the normal connection electrode 120 and the measurement connection electrode 130 can be reversed.

[0047] The normal connection electrode 120 of the semiconductor chip 100 can be connected to the corresponding normal substrate pad 220 of the substrate 200. The measurement connection electrode 130 of the semiconductor chip 100 can be connected to the corresponding measurement substrate pad 230 of the substrate 200. More specifically, the first edge measurement connection electrode 130E1 can be connected to the first edge measurement substrate pad 230E1, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be simultaneously connected to the central measurement substrate pad 230C, and the second edge measurement connection electrode 130E2 can be connected to the second edge measurement substrate pad 230E2.

[0048] Here, the first edge measurement connection electrode 130E1 and the first central measurement connection electrode 130C1 can be connected to each other through the first measurement conductive pattern 114, and the second edge measurement connection electrode 130E2 and the second central measurement connection electrode 130C2 can be connected to each other through the second measurement conductive pattern 115. As a result, a daisy-chain connection structure can be formed, comprising the first measurement terminal 231, the first extension 235, the first edge measurement substrate pad 230E1, the first edge measurement connection electrode 130E1, the first measurement conductive pattern 114, the first central measurement connection electrode 130C1, the central measurement substrate pad 230C, the second central measurement connection electrode 130C2, the second measurement conductive pattern 115, the second edge measurement connection electrode 130E2, the second edge measurement substrate pad 230E2, the second extension 236, and the second measurement terminal 232. Whether or not this connection structure is formed can be determined (see reference). Figure 3B The current (the dashed arrow in the diagram) indicates the connection between the semiconductor chip 100 and the substrate 200 (more specifically, the connection between the normal connection electrode 120 and the normal substrate pad 220). Conversely, if no current is generated, it indicates that the connection between the semiconductor chip 100 and the substrate 200 is not functioning correctly.

[0049] Based on the above embodiments, connection faults between the semiconductor chip 100 and the substrate 200 can be detected when the connection electrodes 120 and 130 of the semiconductor chip 100 are connected to the substrate pads 220 and 230 of the substrate 200. Therefore, this facilitates fault detection and minimizes fault detection costs. Furthermore, when multiple semiconductor chips 100 are present, faults in all of the multiple semiconductor chips 100 can be detected as an alternative to detecting faults through sampling.

[0050] Furthermore, in this embodiment, the first edge measuring substrate pad 230E1 and the second edge measuring substrate pad 230E of the substrate 200 may have a long side in the second direction, while the central measuring substrate pad 230C has a long side in the first direction. In this case, even if misalignment occurs in any direction between the semiconductor chip 100 and the substrate 200, all connection failures between the semiconductor chip 100 and the substrate 200 caused by such misalignment can be detected. (Refer to...) Figures 4A to 4E This will be described.

[0051] Figures 4A to 4E These figures illustrate the alignment between the semiconductor chip 100 and the substrate 200. For ease of description, the figures show the outline of the semiconductor chip 100, the outline of the substrate 200, the measurement connection electrodes 130E1, 130C1, 130C2 and 130E2, and the measurement substrate pads 230E1, 230C and 230E2.

[0052] Figure 4A An example is shown where the semiconductor chip 100 and the substrate 200 are normally aligned. In this case, the first edge measurement connection electrode 130E1 can be connected to the first edge measurement substrate pad 230E1, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be simultaneously connected to the central measurement substrate pad 230C, and the second edge measurement connection electrode 130E2 can be connected to the second edge measurement substrate pad 230E2.

[0053] Figure 4BAn example is illustrated where the semiconductor chip 100 moves to one side (e.g., to the left) in a second direction and is not aligned with the substrate 200. In this case, the first edge measurement connection electrode 130E1 can be connected to the first edge measurement substrate pad 230E1, and the second edge measurement connection electrode 130E2 can be connected to the second edge measurement substrate pad 230E2. This is because the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2 have long sides in the second direction. Even if the first edge measurement connection electrode 130E1 and the second edge measurement connection electrode 130E2 move to a predetermined degree in the second direction, the connection between the first edge measurement connection electrode 130E1 and the first edge measurement substrate pad 230E1, and the connection between the second edge measurement connection electrode 130E2 and the second edge measurement substrate pad 230E2, can be maintained.

[0054] On the other hand, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 may not be able to connect to the central measurement substrate pad 230C. This is because the central measurement substrate pad 230C has a short side in the second direction.

[0055] In this situation, because the daisy-chain connection structure described above is cut off at the center, no current can be generated through the connection structure. As a result, misalignment and connection faults between the semiconductor chip 100 and the substrate 200 can be detected.

[0056] Figure 4C An example is illustrated where the semiconductor chip 100 moves to one side (e.g., upward) in a first direction and is not aligned with the substrate 200. In this case, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be connected to the central measurement substrate pad 230C. This is because the central measurement substrate pad 230C has a long side in the first direction. Even if the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 move to a predetermined degree in the first direction, the connection between the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 and the central measurement substrate pad 230C can be maintained.

[0057] On the other hand, the first edge measurement connection electrode 130E1 and the first edge measurement substrate pad 230E1 may not be connected, and the second edge measurement connection electrode 130E2 and the second edge measurement substrate pad 230E2 may not be connected. This is because the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2 have short sides in the first direction.

[0058] In this situation, because the daisy-chain connection structure described above is cut off at the edge, no current can be generated through the connection structure. As a result, misalignment and connection faults between the semiconductor chip 100 and the substrate 200 can be detected.

[0059] Figure 4D An example is illustrated where the semiconductor chip 100 is moved diagonally relative to the first and second directions (e.g., in the direction toward the upper right) and is not aligned with the substrate 200. In this case, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 may not be able to connect to the central measurement substrate pad 230C, the first edge measurement connection electrode 130E1 may not be able to connect to the first edge measurement substrate pad 230E1, and the second edge measurement connection electrode 130E2 may not be able to connect to the second edge measurement substrate pad 230E2.

[0060] In this situation, because the daisy-chain connection structure described above is cut off at the center and edges, no current can be generated through the connection structure. As a result, misalignment and connection faults between the semiconductor chip 100 and the substrate 200 can be detected.

[0061] Figure 4E An example is illustrated where the semiconductor chip 100 is rotated by a predetermined angle and is not aligned with the substrate 200. In this case, at least one of the following connections may be impossible: the connection between the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 and the central measurement substrate pad 230C; the connection between the first edge measurement connection electrode 130E1 and the first edge measurement substrate pad 230E1; and the connection between the second edge measurement connection electrode 130E2 and the second edge measurement substrate pad 230E2.

[0062] In this situation, because the described daisy-chain connection structure is broken at the unconnected portions, no current can be generated through the connection structure. As a result, misalignment and connection faults between the semiconductor chip 100 and the substrate 200 can be detected. Furthermore, the type of misalignment occurring between the semiconductor chip 100 and the substrate 200 can be determined.

[0063] In addition, Figures 1A to 3B The wiring layer L1 described in the embodiments can be formed during the packaging process in a fab-out state where the wafer with the circuit pattern has been fabricated. Alternatively, the wiring layer L1 can be formed together with the circuit pattern in a front-end process where the circuit pattern is formed in the wafer. Hereinafter, the case of forming the wiring layer L1 in the front-end process will be described exemplarily.

[0064] Figure 5AThis is a plan view of a semiconductor chip illustrating a semiconductor package according to another embodiment of the present disclosure, and Figure 5B It is along Figure 5A The cross-sectional view taken by line CC′.

[0065] Reference Figure 5A and Figure 5B The semiconductor chip 300 of this embodiment may include a lower structure US, redistribution conductive layers 313, 314, and 315 formed above the lower structure US, and a protective layer 340 covering the lower structure US and the redistribution conductive layers 313, 314, and 315 while exposing portions of the redistribution conductive layers 313, 314, and 315. Here, the redistribution conductive layers 313, 314, and 315 may correspond to the wiring layer L1 of the above embodiment, and the protective layer 340 may correspond to the insulating layer 140 of the above embodiment.

[0066] The lower structure US may include a semiconductor substrate S having a semiconductor material such as silicon, a multilayer conductive pattern ML formed on one surface of the semiconductor substrate S to form an integrated circuit, and an interlayer insulating layer ILD that buries the multilayer conductive pattern ML. Although not shown, the interlayer insulating layer ILD may also have a multilayer structure.

[0067] A multilayer conductive pattern ML may include multiple conductors arranged in multiple layers and having various shapes in a direction perpendicular to the upper surface of the semiconductor substrate S. For example, the multilayer conductive pattern ML may include a combination of contact plugs C and pads P. The multilayer conductive pattern ML may be connected to a portion of the semiconductor substrate S, such as a junction of a transistor.

[0068] The materials used to form the multilayer conductive pattern ML and the interlayer insulating layer ILD can be appropriately selected to meet the desired characteristics of the semiconductor chip. As an example, at least a portion of the multilayer conductive pattern ML may include a metal with low resistance, such as copper (Cu). Furthermore, as an example, at least a portion of the interlayer insulating layer ILD may include a material with a low dielectric constant, such as a low-k material with a dielectric constant of 2.7 or less.

[0069] However, if a semiconductor chip in which multiple conductive patterns ML and interlayer insulating layers ILD are formed is covered with a protective layer and then fabricated (fab-out) for packaging, moisture can penetrate through the relatively hygroscopic low-k material. Moisture can cause electrical movement of metal ions (especially copper ions), and thus may result in the loss of the multiple conductive patterns ML or an electrical short circuit with another adjacent conductor. Therefore, in the semiconductor chip 300 of this embodiment, moisture penetration can be prevented by forming a thick insulating layer 302 on the interlayer insulating layer ILD.

[0070] Insulating layer 302 may comprise an insulating material having a higher dielectric constant and / or lower hygroscopicity than low-k materials, such as silicon oxide, silicon nitride, or combinations thereof. Additionally, insulating layer 302 may have a single-layer or multi-layer structure. Insulating layer 302 may be formed relatively thick to prevent moisture penetration. Insulating layer 302 may be thicker than any layer of an interlayer insulating layer (ILD) with a multi-layer structure. For example, insulating layer 302 may have tens of thousands of layers. The thickness.

[0071] However, since it is necessary to connect the multilayer conductive pattern ML to external components, a contact plug 304 that penetrates the insulating layer 302 and is connected to the multilayer conductive pattern ML, and a redistributed conductive layer 313 that is formed above the insulating layer 302 and connected to the contact plug 304 can be further formed.

[0072] The redistribution conductive layers 313, 314, and 315 may comprise various conductive materials such as metallic aluminum (Al) and may have a single-layer or multi-layer structure. Furthermore, the redistribution conductive layers 313, 314, and 315 may be formed to be relatively thick to achieve smooth signal transmission and balance with the insulating layer 302. The redistribution conductive layers 313, 314, and 315 may have the same or similar thickness as the insulating layer 302. For example, the redistribution conductive layers 313, 314, and 315 may have tens of thousands of [thickness values ​​missing]. The thickness.

[0073] A protective layer 340 may be disposed above redistribution conductive layers 313, 314, and 315. The protective layer 340 may define redistribution pads 313P, 314PC, 314PE, 315PC, and 315PE by exposing portions of the redistribution conductive layers 313, 314, and 315 while protecting the semiconductor chip 300. The protective layer 340 may have a single-layer or multi-layer structure with various insulating materials (such as insulating polymers). Specifically, the protective layer 340 may include a polyimide material, such as polyimide isoindolequinazolinidone (PIQ).

[0074] The processes for forming the lower structure US, the redistribution conductive layers 313, 314, and 315, and the protective layer 340 can all be performed before fabrication is complete (fab-out) (i.e., in the front-end processes). As an example, the lower structure US and the redistribution conductive layers 313, 314, and 315 can be formed by repeating a deposition process of conductive or insulating materials, along with masking and etching processes. The protective layer 340 can be formed by a coating method.

[0075] The redistribution conductive layers 313, 314, and 315 may include a normal redistribution conductive layer 313, a first measurement redistribution conductive layer 314, and a second measurement redistribution conductive layer 315. The normal redistribution conductive layer 313, the first measurement redistribution conductive layer 314, and the second measurement redistribution conductive layer 315 may correspond to the normal conductive pattern 113, the first measurement conductive pattern 114, and the second measurement conductive pattern 115 of the above embodiments, respectively.

[0076] The normal redistribution conductive layer 313 can be formed above the entire surface of the underlying structure US and can have various planar shapes based on patterning. The normal redistribution conductive layer 313 can be electrically connected to the multilayer conductive pattern ML. The portion of the normal redistribution conductive layer 313 exposed through the opening in the protective layer 340 will be referred to as the normal redistribution pad 313P. As an example, the normal redistribution pad 313P can be disposed in the central region of the semiconductor chip 300 in the second direction. Furthermore, a plurality of normal redistribution pads 313P can be arranged in two columns along the first direction.

[0077] A normal redistribution conductive layer 313 can be used to connect normal redistribution pads 313P that are applied with the same power to each other. This is to efficiently supply the power required during the operation of the semiconductor chip 300. For this purpose, the normal redistribution conductive layer 313 may include: an overlapping portion that overlaps with each of two or more normal redistribution pads 313P applied with the same power; and a flat plate portion that connects the overlapping portions to each other to form a flat plate. A normal redistribution conductive layer 313 connected to one column of two columns of normal redistribution pads 313P (e.g., the left column of normal column redistribution pads 313P) may include a flat plate extending to the left region of the semiconductor chip 300. Additionally, a normal redistribution conductive layer 313 connected to the other column of two columns of normal redistribution pads 313P (e.g., the right column of normal redistribution pads 313P) may include a flat plate extending to the right region of the semiconductor chip 300. These normal redistribution conductive layers 313 may extend to both side edges of the semiconductor chip 300 in a second direction.

[0078] The first measurement redistribution conductive layer 314 and the second measurement redistribution conductive layer 315 may not be connected to the multilayer conductive pattern ML. In other words, there may be no conductive elements connected to them beneath the first measurement redistribution conductive layer 314 and the second measurement redistribution conductive layer 315. The portions of the first measurement redistribution conductive layer 314 exposed through the protective layer 340 will be referred to as the first measurement redistribution pads 314PC and 314PE, and the portions of the second measurement redistribution conductive layer 315 exposed through the protective layer 340 will be referred to as the second measurement redistribution pads 315PC and 315PE. The first measurement redistribution pads 314PC and 314PE may include a first edge measurement redistribution pad 314PE and a first central measurement redistribution pad 314PC. The second measurement redistribution pads 315PC and 315PE may include a second edge measurement redistribution pad 315PE and a second central measurement redistribution pad 315PC. The first edge measurement redistribution pad 314PE can be disposed in the first edge region ER1 in the first direction, and can be disposed to the left of the left column of the normal redistribution pad 313P in the second direction. The first central measurement redistribution pad 314PC and the second central measurement redistribution pad 315PC can be disposed in the central region CR in the first direction, and can be disposed between the left and right columns of the normal redistribution pad 313P in the second direction. The second edge measurement redistribution pad 315PE can be disposed in the second edge region ER2 in the first direction, and can be disposed to the right of the right column of the normal redistribution pad 313P in the second direction.

[0079] The first measurement redistribution conductive layer 314 may have a line shape connecting the first edge measurement redistribution pad 314PE and the first central measurement redistribution pad 314PC. In this case, because the normal redistribution conductive layer 313 comprises a plate covering the left region of the semiconductor chip 300, the first measurement redistribution conductive layer 314 may be spaced apart from the normal redistribution conductive layer 313 and may bypass the normal redistribution conductive layer 313. For example, the first measurement redistribution conductive layer 314 may pass through the left edge of the semiconductor chip 300 in a second direction while simultaneously surrounding the normal redistribution conductive layer 313 from the first central measurement redistribution pad 314PC to the first edge measurement redistribution pad 314PE.

[0080] Additionally, the second measurement redistribution conductive layer 315 may have a line shape connecting the second edge measurement redistribution pad 315PE and the second central measurement redistribution pad 315PC. In this case, because the normal redistribution conductive layer 313 includes a plate covering the right region of the semiconductor chip 300, the second measurement redistribution conductive layer 315 may be spaced apart from and bypass the normal redistribution conductive layer 313. For example, the second measurement redistribution conductive layer 315 may pass through the right edge of the semiconductor chip 300 in a second direction while simultaneously surrounding the normal redistribution conductive layer 313 from the second central measurement redistribution pad 315PC to the second edge measurement redistribution pad 315PE.

[0081] Based on this embodiment, in addition to the advantages of the above-described embodiments, the following advantages may also be present.

[0082] Because the relatively thick insulating layer 302 is formed on the multilayer conductive pattern ML and the interlayer insulating layer ILD, moisture penetration into the semiconductor chip 300 is prevented, even if the multilayer conductive pattern ML and the interlayer insulating layer ILD include hygroscopic low-k materials and metals such as copper that are ionized and easily moved due to moisture. As a result, the reliability of the semiconductor chip 300 can be ensured.

[0083] Furthermore, by using a normal redistribution conductive layer 313 to connect the normal redistribution pads 313P to which the same power is applied, an efficient power supply can be achieved. As a result, the operating characteristics of the semiconductor chip 300 can be improved.

[0084] Furthermore, in the above description Figures 1A to 3B In this embodiment, since the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 are arranged in the first direction, the long side of the central measurement substrate pad 230C connected thereto is also arranged in the first direction. Furthermore, the long sides of the first edge measurement substrate pad 230E1 and the second edge measurement substrate pad 230E2 are arranged in the second direction so as to be orthogonal to the central measurement substrate pad 230C. However, this disclosure is not limited to this, and various embodiments are possible, as long as the central measurement substrate pad is connected to the two central measurement connection electrodes disposed in the central region and intersects the first edge measurement substrate pad and the second edge measurement substrate pad at a predetermined angle.

[0085] Figure 6 This is a plan view illustrating a semiconductor package according to another embodiment of the present disclosure. The focus will be on... Figures 1A to 3B The differences in the implementation methods will be described.

[0086] Reference Figure 6 Semiconductor chip 400 can be mounted on substrate 500.

[0087] The semiconductor chip 400 may include a main body 410 and a measurement connection electrode 430 and a normal connection electrode 420 formed on a surface of the main body 410.

[0088] In the plan view, multiple normal connection electrodes 420 can be arranged in the first column R1 and the second column R2. In the first direction, the two edge regions of the area where the multiple normal connection electrodes 420 are arranged will be referred to as the first edge region ER1 and the second edge region ER2, respectively, and the region between the first edge region ER1 and the second edge region ER2 will be referred to as the central region CR.

[0089] The measurement connection electrode 430 can be configured to be adjacent to the normal connection electrode 420, and can be configured by considering the area of ​​the first semiconductor chip 400. For example, the measurement connection electrode 430 may include: a first edge measurement connection electrode 430E1 disposed in the first edge region ER1, a first central measurement connection electrode 430C1 and a second central measurement connection electrode 430C2 disposed in the central region CR, and a second edge region ER2 disposed in the second edge region ER2. In this case, unlike the above embodiment, the first central measurement connection electrode 130C1 and the second central measurement connection electrode 130C2 can be arranged at a predetermined interval along the second direction.

[0090] The first edge measurement connection electrode 430E1 and the first central measurement connection electrode 430C1 can be connected via the first measurement conductive pattern 414. The second edge measurement connection electrode 430E2 and the second central measurement connection electrode 430C2 can be connected via the second measurement conductive pattern 415.

[0091] The substrate 500 may have a first surface 501 facing the normal connection electrode 420 and the measurement connection electrode 430 of the semiconductor chip 400. On the first surface 501 of the substrate 500, normal substrate pads 520 and measurement substrate pads 530 respectively connected to the normal connection electrode 420 and the measurement connection electrode 430 of the semiconductor chip 400 may be formed.

[0092] Normal substrate pads 520 can be connected to normal connection electrodes 420 one by one.

[0093] The measurement substrate pad 530 may include: a first edge measurement substrate pad 530E1 connected to a first edge measurement connection electrode 430E1, a central measurement substrate pad 530C connected to a first central measurement connection electrode 430C1 and a second central measurement connection electrode 430C2, and a second edge measurement substrate pad 530E2 connected to a second edge measurement connection electrode 430E2.

[0094] The central measurement substrate pad 530C may have a shape that overlaps with and connects to the first central measurement connection electrode 430C1 and the second central measurement connection electrode 430C2. As described above, the first central measurement connection electrode 430C1 and the second central measurement connection electrode 430C2 may be arranged to be spaced apart from each other in a second direction. Therefore, the central measurement substrate pad 530C may have a strip shape, which has a long side in the second direction and a short side in the first direction.

[0095] The first edge measurement substrate pad 530E1 may have a strip shape with its long side in the first direction, and overlap with the first edge measurement connection electrode 430E1. That is, the long side of the first edge measurement substrate pad 530E1 may be orthogonal to the long side of the central measurement substrate pad 530C. The second edge measurement substrate pad 530E2 may have a strip shape with its long side in the first direction, and overlap with the second edge measurement connection electrode 430E2. That is, the long side of the second edge measurement substrate pad 530E2 may also be orthogonal to the long side of the central measurement substrate pad 530C.

[0096] The first measurement terminal 531 and the second measurement terminal 532 can be connected to the ends of the first edge measurement substrate pad 530E1 and the second edge measurement substrate pad 530E2, respectively. Furthermore, a first extension 535 extending from the first edge measurement substrate pad 530E1 to the first measurement terminal 531 and a second extension 536 extending from the second edge measurement substrate pad 530E2 to the second measurement terminal 532 can be further formed.

[0097] Based on the embodiments of this disclosure, connection faults between semiconductor chips and substrates can be easily and accurately detected.

[0098] Figure 7 A block diagram illustrating an electronic system is shown, including a memory card 7800 employing at least one semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and memory controller 7820 may include at least one semiconductor package according to the described embodiment.

[0099] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 to read or store data in response to a read / write request from the host 7830.

[0100] Figure 8 A block diagram of an exemplary electronic system 8710 is shown, which includes at least one semiconductor package according to a described embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0101] In embodiments, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypads, keyboards, display devices, touchscreens, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands to be executed by controller 8711.

[0102] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory can be installed in information processing systems such as mobile terminals or desktop computers. Flash memory can form a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0103] The electronic system 8710 may further include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0104] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a cordless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0105] If electronic system 8710 represents equipment capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0106] Although various embodiments have been described for exemplary purposes, it will be apparent to those skilled in the art that various variations and modifications may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0107] Cross-reference to related applications

[0108] This application claims priority to Korean Patent Application No. 10-2020-0084078, filed on July 8, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package comprising: A semiconductor chip, the semiconductor chip including a normal connection electrode and a measurement connection electrode formed on a first surface; as well as The substrate includes normal substrate pads connected to the normal connection electrode and measurement substrate pads connected to the measurement connection electrode, the normal substrate pads and the measurement substrate pads being formed on a surface facing the first surface. The measurement connection electrodes include a first edge measurement connection electrode and a second edge measurement connection electrode formed on two side edge regions of the semiconductor chip, and a first central measurement connection electrode and a second central measurement connection electrode arranged spaced apart from each other in the central region of the semiconductor chip. The side edge regions extend along a first direction, and the central region is disposed between the two side edge regions in the first direction. The measurement substrate pads include: a central measurement substrate pad having a long side in the arrangement direction of the first central measurement connection electrode and the second central measurement connection electrode to simultaneously connect the first central measurement connection electrode and the second central measurement connection electrode; a first edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad and simultaneously connected to the first edge measurement connection electrode; and a second edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad and simultaneously connected to the second edge measurement connection electrode. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other. The substrate further includes: A first measurement terminal, the first measurement terminal being electrically connected to the first edge measurement substrate pad; and The second measurement terminal is electrically connected to the second edge measurement substrate pad, and The electrical path is formed to pass through the first measurement terminal, the first edge measurement substrate pad, the first edge measurement connection electrode, the first central measurement connection electrode, the central measurement substrate pad, the second central measurement connection electrode, the second edge measurement connection electrode, the second edge measurement substrate pad, and the second measurement terminal.

2. The semiconductor package according to claim 1, wherein, When the first edge measurement substrate pad and the first measurement terminal are spaced apart from each other, the substrate further includes a first connection portion that connects the first edge measurement substrate pad to the first measurement terminal.

3. The semiconductor package according to claim 1, wherein, When the second edge measurement substrate pads and the second measurement terminal are spaced apart from each other, the substrate further includes a second connection portion that connects the second edge measurement substrate pads to the second measurement terminal.

4. The semiconductor package according to claim 1, wherein, The semiconductor chip further includes: a first measurement conductive pattern that connects the first edge measurement connection electrode to the first central measurement connection electrode; and a second measurement conductive pattern that connects the second edge measurement connection electrode to the second central measurement connection electrode.

5. The semiconductor package according to claim 4, wherein, The semiconductor chip includes multiple wiring layers arranged in a third-direction orientation, where the third-direction orientation is the thickness direction of the semiconductor chip. The normal connection electrode is connected to a normal conductive pattern, which is the portion of the plurality of wiring layers closest to the first surface of the semiconductor chip.

6. The semiconductor package according to claim 5, wherein, The first and second measuring conductive patterns are at the same level as the normal conductive pattern in the third direction.

7. The semiconductor package according to claim 6, wherein, The first and second measuring conductive patterns are physically and electrically separated from the normal conductive pattern.

8. The semiconductor package according to claim 1, wherein, The normal connection electrodes include: a first column of normal connection electrodes arranged in a row along the first direction; and a second column of normal connection electrodes arranged in a row along the first direction, wherein the first column of normal connection electrodes is spaced apart from the second column of normal connection electrodes in a second direction orthogonal to the first direction. Wherein, the first edge measurement connection electrode and the second edge measurement connection electrode are respectively disposed on both sides of the first column of normal connection electrodes and the second column of normal connection electrodes in the second direction, and The first central measurement connection electrode and the second central measurement connection electrode are disposed in the second direction between the first column of normal connection electrodes and the second column of normal connection electrodes.

9. The semiconductor package according to claim 8, wherein, The first column of normal connection electrodes and the second column of normal connection electrodes are disposed in the central region of the semiconductor chip in the second direction.

10. The semiconductor package according to claim 1, wherein, The semiconductor chip includes a lower structure having multiple conductive patterns and a redistributed conductive layer disposed above the lower structure, and The redistribution conductive layer includes a normal redistribution conductive layer connected to the normal connection electrode and a measurement redistribution conductive layer connected to the measurement connection electrode.

11. The semiconductor package of claim 10, wherein, The normal redistribution conductive layer is electrically connected to the multilayer conductive pattern, and The measurement redistribution conductive layer is electrically insulated from the multilayer conductive pattern.

12. The semiconductor package of claim 10, wherein, The measurement redistribution conductive layer includes: a first measurement redistribution conductive layer, wherein the first measurement redistribution conductive layer connects the first edge measurement connection electrode to the first central measurement connection electrode; and a second measurement redistribution conductive layer, wherein the second measurement redistribution conductive layer connects the second edge measurement connection electrode to the second central measurement connection electrode.

13. The semiconductor package of claim 10, wherein, The normal redistribution conductive layer includes: overlapping portions, each overlapping with a normal connection electrode to which the same power is applied; and plate portions, each plate portion connecting to the overlapping portions.

14. The semiconductor package of claim 13, wherein, The measurement redistribution conductive layer is shaped to surround the plate portion while being spaced apart from the normal redistribution conductive layer.

15. The semiconductor package according to claim 1, wherein, The normal connection electrode and the measurement connection electrode include conductive bumps.

16. The semiconductor package according to claim 1, wherein, The first central measurement connection electrode and the second central measurement connection electrode are arranged in the first direction, and Each of the first edge measurement substrate pad and the second edge measurement substrate pad has a long side extending in a second direction, which is orthogonal to the first direction.

17. The semiconductor package according to claim 1, wherein, The first central measurement connection electrode and the second central measurement connection electrode are arranged in a second direction, which is orthogonal to the first direction, and Each of the first edge measurement substrate pad and the second edge measurement substrate pad has a long side extending in the first direction.

18. A semiconductor package comprising: A semiconductor chip, the semiconductor chip including a normal connection electrode and a measurement connection electrode formed on a first surface; as well as The substrate includes normal substrate pads connected to the normal connection electrode and measurement substrate pads connected to the measurement connection electrode, the normal substrate pads and the measurement substrate pads being formed on a surface facing the first surface. The measurement connection electrodes include a first edge measurement connection electrode and a second edge measurement connection electrode formed on two side edge regions of the semiconductor chip, and a first central measurement connection electrode and a second central measurement connection electrode arranged spaced apart from each other in the central region of the semiconductor chip. The side edge regions extend along a first direction, and the central region is disposed between the two side edge regions in the first direction. The measurement substrate pads include: a central measurement substrate pad having a long side in the arrangement direction of the first central measurement connection electrode and the second central measurement connection electrode to simultaneously connect the first central measurement connection electrode and the second central measurement connection electrode; a first edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad and simultaneously connected to the first edge measurement connection electrode; and a second edge measurement substrate pad having a long side intersecting the long side of the central measurement substrate pad and simultaneously connected to the second edge measurement connection electrode. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other. The substrate further includes: A first measurement terminal, the first measurement terminal being electrically connected to the first edge measurement substrate pad; and The second measurement terminal is electrically connected to the second edge measurement substrate pad, and Specifically, the normal connection electrode of the semiconductor chip is determined to be connected to the normal substrate pad of the substrate based on whether a current path is formed including the first measurement terminal, the first edge measurement substrate pad, the first edge measurement connection electrode, the first central measurement connection electrode, the central measurement substrate pad, the second central measurement connection electrode, the second edge measurement connection electrode, the second edge measurement substrate pad, and the second measurement terminal.

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