Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a substrate, the substrate comprising a first region; a first polarization layer located on the first region, the material of the first polarization layer being a semiconductor compound material having first polarization atoms; and a first gate structure located on the first polarization layer. Through the first polarization layer located on the first region, the material of the first polarization layer being a semiconductor compound material having first polarization atoms. Since the first polarization atoms in the first polarization layer directly form corresponding salt compounds with semiconductor materials, the first polarization layer can have a higher threshold voltage, and thus in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, reducing the problem of the same threshold voltage of different gates, and effectively improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] MOS (Metal-Oxide-Semiconductor) transistor is one of the most important components in modern integrated circuits. The basic structure of MOS transistor includes: semiconductor substrate; gate structure located on the surface of semiconductor substrate, the gate structure includes: gate dielectric layer located on the surface of semiconductor substrate and gate electrode layer located on the surface of gate dielectric layer; source and drain doping regions in the semiconductor substrate on both sides of the gate structure. MOS includes PMOS transistor and NMOS transistor.

[0003] In order to meet the switching speed requirements of different transistors in integrated circuit design, it is necessary to form a plurality of transistors with different threshold voltages.

[0004] In order to reduce and adjust the threshold voltage of the PMOS transistor and the NMOS transistor, a corresponding work function layer is formed on the surface of the gate dielectric layer of the PMOS transistor and the NMOS transistor. Among them, the work function layer of the PMOS transistor needs to have a higher work function, while the work function layer of the NMOS transistor needs to have a lower work function. In the PMOS transistor and the NMOS transistor, the materials of the work function layer are different to meet the needs of their respective work function adjustments.

[0005] However, the performance of the multi-threshold voltage FinFET formed in the prior art still needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of a multi-threshold voltage fin field effect transistor.

[0007] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region; a first polarization layer located on the first region, the material of the first polarization layer is a semiconductor compound material having first polarization atoms; and a first gate structure located on the first polarization layer.

[0008] Optionally, the first polarized atoms include: La, Ce, Nb, Mg, Sc or Al.

[0009] Optionally, the material of the first polarization layer includes: x Si y O z 、M x Ge y O z or M x Si yGe z O w , where M is the first polarizable atom, and x, y, z, and w are positive integers.

[0010] Optionally, the substrate also includes: a second region and a third region; the semiconductor structure also includes: a second polarization layer located on the second region, the material of the second polarization layer having the first polarization atoms; a second gate structure located on the second polarization layer; a first gate oxide layer located on the third region; and a third gate structure located on the first gate oxide layer.

[0011] Optionally, it also includes: a dielectric layer located on the substrate, the dielectric layer having a first opening, a second opening and a third opening, the first opening being located on the first region, the second opening being located on the second region, and the third opening being located on the third region; the first polarization layer and the first gate structure being located in the first opening; the second polarization layer and the second gate structure being located in the second opening; and the first gate oxide layer and the third gate structure being located in the third opening.

[0012] Optionally, the first gate structure includes: a first gate dielectric layer located on the first polarization layer; and a first gate layer located on the first gate dielectric layer.

[0013] Optionally, the first gate structure further includes: a first work function layer, wherein the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer.

[0014] Optionally, the second gate structure includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer located on the second gate dielectric layer.

[0015] Optionally, the second gate structure further includes: a second work function layer, wherein the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer.

[0016] Optionally, the third gate structure includes: a third gate dielectric layer located on the first gate oxide layer; and a third gate layer located on the third gate dielectric layer.

[0017] Optionally, the third gate structure further includes: a third work function layer, wherein the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer.

[0018] Optionally, a material of the first gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0019] Optionally, the material of the second gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0020] Optionally, the material of the third gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0021] Optionally, the content of the first polarization atoms in the first polarization layer is 2% to 30%.

[0022] Optionally, the content of the first polarization atoms in the second polarization layer is less than 1%.

[0023] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming a first polarization layer on the first region, the material of the first polarization layer being a semiconductor compound material having first polarization atoms; and forming a first gate structure on the first polarization layer.

[0024] Optionally, the first polarized atoms include: La, Ce, Nb, Mg, Sc or Al.

[0025] Optionally, the material of the first polarization layer includes: x Si y O z 、M x Ge y O z or M x Si y Ge z O w , where M is the first polarizable atom, and x, y, z, and w are positive integers.

[0026] Optionally, the substrate also includes: a second region and a third region; the semiconductor structure also includes: a second polarization layer located on the second region, the material of the second polarization layer having the first polarization atoms; a second gate structure located on the second polarization layer; a first gate oxide layer located on the third region; and a third gate structure located on the first gate oxide layer.

[0027] Optionally, it also includes: forming a dielectric layer on the substrate, the dielectric layer having a first opening, a second opening and a third opening, the first opening being located on the first region, the second opening being located on the second region, and the third opening being located on the third region; forming the first polarization layer and the first gate structure in the first opening; forming the second polarization layer and the second gate structure in the second opening; and forming the first gate oxide layer and the third gate structure in the third opening.

[0028] Optionally, the method for forming the first polarization layer and the second polarization layer includes: forming a first diffusion layer on the first region; forming a second gate oxide layer in the second region; forming a second diffusion layer on the second gate oxide layer; annealing the first diffusion layer and the second diffusion layer to modify the second gate oxide layer into the second polarization layer and modify the first diffusion layer into the first polarization layer.

[0029] Optionally, the material of the first diffusion layer includes: lanthanum oxide or cerium oxide; the material of the second diffusion layer includes: lanthanum oxide or cerium oxide

[0030] Optionally, the first gate structure includes: a first gate dielectric layer located on the first polarization layer; and a first gate layer located on the first gate dielectric layer.

[0031] Optionally, the first gate structure further includes: a first work function layer, wherein the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer.

[0032] Optionally, the second gate structure includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer located on the second gate dielectric layer.

[0033] Optionally, the second gate structure further includes: a second work function layer, wherein the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer.

[0034] Optionally, the third gate structure includes: a third gate dielectric layer located on the first gate oxide layer; a third gate layer located on the third gate dielectric layer;

[0035] Optionally, the third gate structure further includes: a third work function layer, wherein the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer.

[0036] Optionally, the content of the first polarization atoms in the first polarization layer is 2% to 30%.

[0037] Optionally, the content of the first polarization atoms in the second polarization layer is less than 1%.

[0038] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0039] In the structure of the technical solution of the present invention, the first polarization layer located on the first region is made of a semiconductor compound material having first polarization atoms. The first polarization atoms in the first polarization layer directly form corresponding salt compounds with semiconductor materials, so that the first polarization layer can have a higher threshold voltage, and then in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, the problem of the same threshold voltage of different gates is reduced, and the performance of the semiconductor structure finally formed is effectively improved.

[0040] In the formation method of the technical solution of the present invention, a first polarization layer is formed on the first region, and the material of the first polarization layer is a semiconductor compound material having first polarization atoms. The first polarization atom in the first polarization layer directly forms a corresponding salt compound with the semiconductor material, so that the first polarization layer can have a higher threshold voltage, and then in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, the problem of the same threshold voltage of different gates is reduced, and the performance of the finally formed semiconductor structure is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 and Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0042] Figures 3 to 16 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0043] As described in the background art, the performance of the multi-threshold voltage FinFET formed in the prior art still needs to be improved.

[0044] With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and the corresponding spacing between adjacent fin structures is also getting smaller and smaller. In the prior art, the corresponding threshold voltage is adjusted by the number of stacked work function layers. However, due to the small spacing between adjacent fin structures, it is difficult for work function layers with a large number of stacked layers to be filled between the adjacent fin structures, making it difficult to reach the threshold voltage requirement, thereby affecting the performance of the final semiconductor structure.

[0045] In order to solve the above problems, another method for forming a semiconductor structure is proposed, which will be described in detail below with reference to the accompanying drawings.

[0046] Please refer to Figure 1, providing a substrate 100; forming a dielectric layer 101 on the substrate 100, wherein a first opening 102, a second opening 103 and a third opening 104 are formed in the dielectric layer 101, wherein the first opening 102, the second opening 103 and the third opening 104 expose the top surface of the substrate 100; forming a first gate oxide layer 105, a second gate oxide layer 106 and a third gate oxide layer 107, wherein the first gate oxide layer 105 is located in the first opening 102, the second gate oxide layer 106 is located in the second opening 103, and the third gate oxide layer 107 is located in the third opening 104; forming a first diffusion layer 108 and a second diffusion layer 109, wherein the first diffusion layer 108 is located on the first gate oxide layer 105 in the first opening 102, and the second diffusion layer 109 is located on the second gate oxide layer 106 in the second opening 103.

[0047] Please refer to Figure 2 The first diffusion layer 108 and the second diffusion layer 109 are annealed to modify the first gate oxide layer 105 into a first polarization layer 110 and the second gate oxide layer 106 into a second polarization layer 111. The first polarization layer 110 and the second polarization layer 111 contain first polarized atoms.

[0048] In the present embodiment, by forming a first polarization layer 110 and a second polarization layer 111, the first polarization layer 110 and the second polarization layer 111 have first polarization atoms therein, and the threshold voltage is jointly adjusted by forming a chemical bond between the first polarization atom and the gate oxide layer and the number of stacked layers of the subsequently formed work function layer, so that the number of stacked layers of the work function layer is not the only factor affecting the threshold voltage, thereby effectively reducing the number of stacked layers of the work function layer. However, in the present embodiment, the first polarization layer 110 and the second polarization layer 111 are formed by modifying the first gate oxide layer 105 and the second gate oxide layer 106, respectively, and the threshold voltage of the chemical bond formed is small, thereby making the adjustment range of multiple threshold voltages small, which easily causes the problem of the same threshold voltage of different gates, affecting the performance of the final semiconductor structure.

[0049] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein a first polarization layer is formed on the first region, and the material of the first polarization layer is a semiconductor compound material having first polarization atoms. The first polarization atom in the first polarization layer directly forms a corresponding salt compound with the semiconductor material, so that the first polarization layer can have a higher threshold voltage, and then in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, reducing the problem of the same threshold voltage of different gates, and effectively improving the performance of the semiconductor structure finally formed.

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] Figures 3 to 16 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0052] Please refer to Figure 3 and Figure 4 , Figure 3 is a top view of the semiconductor structure. Figure 4 is along Figure 3 A schematic cross-sectional view along line AA is provided, wherein a substrate is provided, and the substrate includes a first region I.

[0053] In this embodiment, the substrate further includes a second region II and a third region III, the second region II is located between the first region I and the third region III, and the first region I, the second region II and the third region III are used to form transistor structures with different threshold voltages.

[0054] In this embodiment, the base includes: a substrate 200 and a plurality of separate fin structures 201 located on the substrate 200 .

[0055] In other embodiments, the fin structure may further include a plurality of channel layers arranged at a certain distance along the normal direction of the substrate surface; in other embodiments, the fin structure may not be provided.

[0056] In this embodiment, the method for forming the substrate 200 and the fin structure 201 includes: providing an initial substrate (not shown), the initial substrate having a mask layer (not shown), the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin structure 201 located on the substrate 200.

[0057] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0058] In this embodiment, the material of the fin structure 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0059] Please refer to Figure 5 , Figure 5 and Figure 4In accordance with the viewing direction, an isolation layer 202 is formed on the substrate 200 , the isolation layer 202 covers a portion of the sidewall of the fin 201 , and the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0060] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate 200 ; etching and removing a portion of the initial isolation layer to form the isolation layer 202 , wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201 .

[0061] The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0062] Please refer to Figure 6 After forming the isolation layer 202, a first dummy gate structure 203, a second dummy gate structure 204 and a third dummy gate structure 205 are formed on the substrate 200 across the fin structure 201, wherein the first dummy gate structure 203 is located on the first region I, the second dummy gate structure 204 is located on the second region II, and the third dummy gate structure 205 is located on the third region III.

[0063] It should be noted that, in order to facilitate clear description in the drawings, the number of dummy gate structures formed on each region is set to be one; however, in the actual production process, multiple gate structures are formed on each region.

[0064] In this embodiment, the method for forming the first dummy gate structure 203 includes: forming a first dummy gate dielectric layer on the isolation layer 202; forming a first dummy gate layer on the first dummy gate dielectric layer; and forming a first sidewall (not shown) on the sidewalls of the first dummy gate dielectric layer and the first dummy gate layer.

[0065] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.

[0066] In this embodiment, the material of the first dummy gate layer is silicon.

[0067] In this embodiment, the method for forming the second dummy gate structure 204 includes: forming a second dummy gate dielectric layer on the isolation layer 202; forming a second dummy gate layer on the second dummy gate dielectric layer; and forming a second sidewall (not shown) on the sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

[0068] In this embodiment, the method for forming the third dummy gate structure 205 includes: forming a third dummy gate dielectric layer on the isolation layer; forming a third dummy gate layer on the third dummy gate dielectric layer; and forming a third sidewall (not marked) on the sidewalls of the third dummy gate dielectric layer and the third dummy gate layer.

[0069] In this embodiment, the material of the second dummy gate dielectric layer and the third dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer and the third dummy gate layer is also the same as that of the first dummy gate layer.

[0070] In this embodiment, the first dummy gate structure 203 , the second dummy gate structure 204 and the third dummy gate structure 205 are formed simultaneously, which can effectively improve production efficiency.

[0071] Please refer to Figure 7 After forming the first dummy gate structure 203, the second dummy gate structure 204 and the third dummy gate structure 205, the fin structure 201 is etched using the first dummy gate structure 203, the second dummy gate structure 204 and the third dummy gate structure 205 as masks to form a plurality of source and drain openings (not shown) in the fin structure 201; and the source and drain doping layer 206 is formed in the source and drain openings.

[0072] In this embodiment, the method for forming the source-drain doped layer 206 includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; in-situ doping the epitaxial layer during the epitaxial growth process, doping source-drain ions into the epitaxial layer to form the source-drain doped layer 206.

[0073] The source-drain ions include P-type ions or N-type ions. In this embodiment, the source-drain ion types of the source-drain doping layers formed on the first region, the second region, and the third region are different; in other embodiments, the source-drain ion types of the source-drain doping layers formed on the first region, the second region, and the third region may also be the same.

[0074] Please refer to Figure 8 After forming the source-drain doping layer 206 , a dielectric layer 207 is formed on the substrate 200 , and the dielectric layer 207 covers the sidewalls of the first dummy gate structure 203 , the second dummy gate structure 204 and the third dummy gate structure 205 .

[0075] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-K dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0076] Please refer to Fig. 9After forming the dielectric layer 207, the first dummy gate structure 203 is removed, and a first opening 208 is formed in the dielectric layer 207, and the first opening 208 is located on the first region I; the second dummy gate structure 204 is removed, and a second opening 209 is formed in the dielectric layer 207, and the second opening 209 is located on the second region II; the third dummy gate structure 205 is removed, and a third opening 210 is formed in the dielectric layer 207, and the third opening 210 is located on the third region III.

[0077] In this embodiment, specifically, the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 203 are removed; the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 204 are removed; and the third dummy gate dielectric layer and the third dummy gate layer of the third dummy gate structure 205 are removed.

[0078] After forming the first opening 208, the second opening 209 and the third opening 210, the method further includes: forming a first polarization layer and a first gate structure in the first opening 208, wherein the material of the first polarization layer is a semiconductor compound material having first polarization atoms; forming a second polarization layer and a second gate structure in the second opening 209, wherein the material of the second polarization layer has the first polarization atoms; and forming a first gate oxide layer and a third gate structure in the third opening 210. For the specific formation process, please refer to Figures 10 to 16 .

[0079] Please refer to Fig.10 A sacrificial layer 211 is formed in the first opening 208 , the second opening 209 and the third opening 210 , and the sacrificial layer 211 covers a portion of the sidewall and the top surface of the fin structure 201 .

[0080] In this embodiment, the sacrificial layer 211 is made of silicon oxide.

[0081] Please refer to Fig.11 , removing the sacrificial layer 211 located in the second opening 209 and the third opening 210 .

[0082] In this embodiment, the sacrificial layer 211 located in the second opening 209 and the third opening 210 is removed by a wet etching process; in other embodiments, the sacrificial layer located in the second opening and the third opening may also be removed by a dry etching process.

[0083] Please refer to Fig.12After removing the sacrificial layer 211 located in the second opening 209 and the third opening 210, the first gate oxide layer 212 is formed in the third opening 210, and the first gate oxide layer 212 covers a portion of the side walls and the top surface of the fin structure 201; and the second gate oxide layer 213 is formed in the second opening 209, and the second gate oxide layer 213 covers a portion of the side walls and the top surface of the fin structure 201.

[0084] In this embodiment, the material of the first gate oxide layer 212 and the second gate oxide layer 213 is silicon oxide.

[0085] In this embodiment, the first gate oxide layer 212 and the second gate oxide layer 213 are formed simultaneously.

[0086] Please refer to Fig.13 After forming the first gate oxide layer 212 and the second gate oxide layer 213, the sacrificial layer 211 located in the first opening 208 is removed; a first diffusion layer 214 is formed in the first opening 208, and the first diffusion layer 214 covers part of the sidewall and top surface of the fin structure 201; a second diffusion layer 215 is formed in the second opening 209, and the second diffusion layer 215 is located on the surface of the second gate oxide layer 213; a third diffusion layer 216 is formed in the third opening 210, and the third diffusion layer 216 is located on the surface of the first gate oxide layer 212.

[0087] In this embodiment, the first diffusion layer 214, the second diffusion layer 215 and the third diffusion layer 216 are formed simultaneously, and the materials of the first diffusion layer 214, the second diffusion layer 215 and the third diffusion layer 216 are lanthanum oxide. In other embodiments, the materials of the first diffusion layer, the second diffusion layer and the third diffusion layer can also be cerium oxide.

[0088] Please refer to Fig.14 , the third diffusion layer 216 located in the third opening 210 is removed.

[0089] In this embodiment, the third diffusion layer 216 located in the third opening 210 is removed by a wet etching process; in other embodiments, the third diffusion layer located in the third opening may also be removed by a dry etching process.

[0090] Please refer to Fig.15 After removing the third diffusion layer 216 , the first diffusion layer 214 and the second diffusion layer 215 are annealed to modify the first diffusion layer 214 into the first polarization layer 217 and modify the second gate oxide layer 213 into the second polarization layer 218 .

[0091] In this embodiment, the annealing treatment is used to cause the first diffusion layer 214 to react with the fin structure 201 to form the first polarization layer 217. The material of the first polarization layer 217 is a semiconductor compound material having first polarization atoms. The first polarization atoms in the first polarization layer 217 directly form corresponding salt compounds with the semiconductor material, so that the first polarization layer 217 can have a higher threshold voltage. In a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, the problem of the same threshold voltage of different gates is reduced, and the performance of the semiconductor structure finally formed is effectively improved.

[0092] In addition, the threshold voltage is jointly adjusted by the number of stacked layers of the first polarization layer 217 and the subsequently formed first work function layer, so that the number of stacked layers of the first work function layer is not the only factor affecting the threshold voltage, thereby effectively reducing the number of stacked layers of the first work function layer.

[0093] The material of the first polarization layer 217 includes: x Si y O z 、M x Ge y O z or M x Si y Ge z O w , where M is the first polarized atom, and x, y, z, and w are positive integers. In this embodiment, the material of the first polarized layer 217 is lanthanum silicate (La 2 SiO 5 ,La 2 Si 2 O7 and other lanthanum silicate compounds).

[0094] In this embodiment, the annealing treatment is used to diffuse the first polarized atoms in the second diffusion layer 215 into the second gate oxide layer 213 to form a second polarization layer 218. The threshold voltage is jointly adjusted by the number of stacked layers of the second polarization layer 218 and the subsequently formed second work function layer, so that the number of stacked layers of the second work function layer is not the only factor affecting the threshold voltage, thereby effectively reducing the number of stacked layers of the second work function layer.

[0095] In this embodiment, the first polarizable atom is La (lanthanum); in other embodiments, the first polarizable atom may also be Ce (cerium), Nb (niobium), Mg (magnesium), Sc (scandium) or Al (aluminum).

[0096] In this embodiment, the content of the first polarized atoms in the first polarized layer 217 is 2% to 30%.

[0097] In this embodiment, the content of the first polarization atoms in the second polarization layer 218 is less than 1%.

[0098] Please refer to Fig.16 After forming the first polarization layer 217 and the second polarization layer 218, the second diffusion layer 215 located on the second polarization layer 218 is removed; a first gate structure 219 is formed on the first polarization layer 217; a second gate structure 220 is formed on the second polarization layer 218; and a third gate structure 221 is formed on the first gate oxide layer 212.

[0099] In this embodiment, the first gate structure 219 includes: a first gate dielectric layer located on the first polarization layer 217; and a first gate layer (not shown) located on the first gate dielectric layer.

[0100] In this embodiment, the first gate structure 219 further includes: a first work function layer, the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer (not marked).

[0101] In this embodiment, the second gate structure 220 includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer (not shown) located on the second gate dielectric layer.

[0102] In this embodiment, the second gate structure 220 further includes: a second work function layer, the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer (not marked).

[0103] In this embodiment, the third gate structure 221 includes: a third gate dielectric layer located on the first gate oxide layer; and a third gate layer (not marked) located on the third gate dielectric layer.

[0104] In this embodiment, the third gate structure 221 further includes: a third work function layer, the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer (not marked).

[0105] In this embodiment, the material of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer is hafnium oxide; in other embodiments, the material of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer may also be lanthanum oxide or cerium oxide.

[0106] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.16, comprising: a substrate, the substrate comprising a first region I; a first polarization layer 217 located on the first region I, the material of the first polarization layer 217 being a semiconductor compound material having first polarization atoms; and a first gate structure 219 located on the first polarization layer 217.

[0107] The first polarization layer 217 is located on the first region I, and the material of the first polarization layer 217 is a semiconductor compound material having first polarization atoms. Since the first polarization atoms in the first polarization layer 217 directly form corresponding salt compounds with the semiconductor material, the first polarization layer 217 can have a higher threshold voltage, and then in a multi-threshold voltage environment, the adjustment range of each threshold voltage is increased, the problem of the same threshold voltage of different gates is reduced, and the performance of the finally formed semiconductor structure is effectively improved.

[0108] In this embodiment, the first polarizable atom is La (lanthanum); in other embodiments, the first polarizable atom may also be Ce (cerium), Nb (niobium), Mg (magnesium), Sc (scandium) or Al (aluminum).

[0109] The material of the first polarization layer 217 includes: x Si y O z 、M x Ge y O z or M x Si y Ge z O w , where M is the first polarized atom, and x, y, z, and w are positive integers. In this embodiment, the material of the first polarized layer 217 is lanthanum silicate (La 2 SiO 5 ,La 2 Si 2 O7 and other lanthanum silicate compounds).

[0110] In this embodiment, the substrate also includes: a second region II and a third region III; the semiconductor structure also includes: a second polarization layer 218 located on the second region II, the material of the second polarization layer 218 having the first polarization atoms; a second gate structure 220 located on the second polarization layer 218; a first gate oxide layer 212 located on the third region III; and a third gate structure 221 located on the first gate oxide layer 212.

[0111] In this embodiment, it also includes: a dielectric layer 207 located on the substrate, the dielectric layer 207 having a first opening 208, a second opening 209 and a third opening 210, the first opening 208 is located on the first region I, the second opening 209 is located on the second region II, and the third opening 210 is located on the third region III; the first polarization layer 217 and the first gate structure 219 are located in the first opening 208; the second polarization layer 218 and the second gate structure 220 are located in the second opening 209; the first gate oxide layer 212 and the third gate structure 221 are located in the third opening 210.

[0112] In this embodiment, the first gate structure 219 includes: a first gate dielectric layer located on the first polarization layer 217; and a first gate layer located on the first gate dielectric layer.

[0113] In this embodiment, the first gate structure 219 further includes: a first work function layer, the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer.

[0114] In this embodiment, the second gate structure 220 includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer located on the second gate dielectric layer.

[0115] In this embodiment, the second gate structure 220 further includes: a second work function layer, wherein the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer.

[0116] In this embodiment, the third gate structure 221 includes: a third gate dielectric layer located on the first gate oxide layer; and a third gate layer located on the third gate dielectric layer.

[0117] In this embodiment, the third gate structure 221 further includes: a third work function layer, the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer.

[0118] In this embodiment, the material of the first gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0119] In this embodiment, the material of the second gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0120] In this embodiment, the material of the third gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

[0121] In this embodiment, the content of the first polarized atoms in the first polarized layer 217 is 2% to 30%.

[0122] In this embodiment, the content of the first polarization atoms in the second polarization layer 218 is less than 1%.

[0123] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate comprising a first region; A first polarization layer located on the first region, wherein the material of the first polarization layer is a semiconductor compound material having first polarization atoms, and the first polarization atoms in the first polarization layer directly form a salt compound with the semiconductor material; A first gate structure is located on the first polarization layer.

2. The semiconductor structure according to claim 1, wherein: The first polarizable atoms include: La, Ce, Nb, Mg, Sc or Al.

3. The semiconductor structure according to claim 2, wherein: The material of the first polarization layer includes: x Si y O z 、M x Ge y O z or M x Si y Ge z O w , where M is the first polarizable atom, and x, y, z, and w are positive integers.

4. The semiconductor structure according to claim 2, characterized in that The substrate also includes: a second region and a third region; the semiconductor structure also includes: a second polarization layer located on the second region, the material of the second polarization layer having the first polarization atoms; a second gate structure located on the second polarization layer; a first gate oxide layer located on the third region; and a third gate structure located on the first gate oxide layer.

5. The semiconductor structure according to claim 4, characterized in that Also includes: a dielectric layer located on the substrate, wherein the dielectric layer has a first opening, a second opening and a third opening, wherein the first opening is located on the first region, the second opening is located on the second region, and the third opening is located on the third region; The first polarization layer and the first gate structure are located in the first opening; The second polarization layer and the second gate structure are located in the second opening; the first gate oxide layer and the third gate structure are located in the third opening.

6. The semiconductor structure according to claim 1, wherein: The first gate structure includes: a first gate dielectric layer located on the first polarization layer; and a first gate layer located on the first gate dielectric layer.

7. The semiconductor structure according to claim 6, wherein: The first gate structure further includes: a first work function layer, wherein the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer.

8. The semiconductor structure according to claim 4, wherein: The second gate structure includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer located on the second gate dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that The second gate structure further includes: a second work function layer, wherein the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer.

10. The semiconductor structure according to claim 4, wherein: The third gate structure includes: a third gate dielectric layer located on the first gate oxide layer; and a third gate layer located on the third gate dielectric layer.

11. The semiconductor structure according to claim 10, characterized in that The third gate structure further includes: a third work function layer, wherein the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer.

12. The semiconductor structure according to claim 6, wherein: The material of the first gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

13. The semiconductor structure according to claim 8, wherein: The material of the second gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

14. The semiconductor structure according to claim 10, wherein: The material of the third gate dielectric layer includes: lanthanum oxide, cerium oxide or hafnium oxide.

15. The semiconductor structure according to claim 1, wherein: The content of the first polarized atoms in the first polarized layer is 2% to 30%.

16. The semiconductor structure according to claim 4, wherein: The content of the first polarization atoms in the second polarization layer is less than 1%.

17. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region; forming a first polarization layer on the first region, wherein the material of the first polarization layer is a semiconductor compound material having first polarization atoms, and the first polarization atoms in the first polarization layer directly form a salt compound with the semiconductor material; A first gate structure is formed on the first polarization layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The first polarizable atoms include: La, Ce, Nb, Mg, Sc or Al.

19. The method for forming a semiconductor structure according to claim 18, wherein: The material of the first polarization layer includes: x Si y O z 、M x Ge y O z or M x Si y Ge z O w , where M is the first polarizable atom, and x, y, z, and w are positive integers.

20. The method for forming a semiconductor structure according to claim 18, wherein: The substrate also includes: a second region and a third region; the semiconductor structure also includes: a second polarization layer located on the second region, the material of the second polarization layer having the first polarization atoms; a second gate structure located on the second polarization layer; a first gate oxide layer located on the third region; and a third gate structure located on the first gate oxide layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: Also includes: Forming a dielectric layer on the substrate, wherein the dielectric layer has a first opening, a second opening and a third opening, wherein the first opening is located on the first region, the second opening is located on the second region, and the third opening is located on the third region; forming the first polarization layer and the first gate structure in the first opening; The second polarization layer and the second gate structure are formed in the second opening; and the first gate oxide layer and the third gate structure are formed in the third opening.

22. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the first polarization layer and the second polarization layer includes: forming a first diffusion layer on the first region; forming a second gate oxide layer in the second region; forming a second diffusion layer on the second gate oxide layer; annealing the first diffusion layer and the second diffusion layer to modify the second gate oxide layer into the second polarization layer and modify the first diffusion layer into the first polarization layer.

23. The method for forming a semiconductor structure according to claim 22, wherein: The material of the first diffusion layer includes lanthanum oxide or cerium oxide; the material of the second diffusion layer includes lanthanum oxide or cerium oxide.

24. The method for forming a semiconductor structure according to claim 17, wherein: The first gate structure includes: a first gate dielectric layer located on the first polarization layer; and a first gate layer located on the first gate dielectric layer.

25. The method for forming a semiconductor structure according to claim 24, wherein: The first gate structure further includes: a first work function layer, wherein the first work function layer is located on the first gate dielectric layer, and the first gate layer is located on the first work function layer.

26. The method for forming a semiconductor structure according to claim 20, wherein: The second gate structure includes: a second gate dielectric layer located on the second polarization layer; and a second gate layer located on the second gate dielectric layer.

27. The method for forming a semiconductor structure according to claim 26, wherein: The second gate structure further includes: a second work function layer, wherein the second work function layer is located on the second gate dielectric layer, and the second gate layer is located on the second work function layer.

28. The method for forming a semiconductor structure according to claim 20, wherein: The third gate structure includes: a third gate dielectric layer located on the first gate oxide layer; and a third gate layer located on the third gate dielectric layer.

29. The method for forming a semiconductor structure according to claim 28, wherein: The third gate structure further includes: a third work function layer, wherein the third work function layer is located on the third gate dielectric layer, and the third gate layer is located on the third work function layer.

30. The method for forming a semiconductor structure according to claim 17, wherein: The content of the first polarized atoms in the first polarized layer is 2% to 30%.

31. The method for forming a semiconductor structure according to claim 17, wherein: The content of the first polarization atoms in the second polarization layer is less than 1%.

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