Lateral enhancement-mode gallium oxide transistor with selective recessed current blocking region

Abstract

This invention belongs to the field of power semiconductor technology and relates to a lateral enhancement-mode gallium oxide transistor with a selectively recessed current blocking region. At zero bias, the current blocking region, combined with the depletion effect of the P-type semiconductor layer on the channel, achieves enhancement-mode functionality and increases the threshold voltage. During forward conduction, the selective recess and P-type semiconductor layer increase channel density, and the channel sidewalls form an electron accumulation layer conductive path, reducing on-resistance and increasing current capability. During forward blocking, the current blocking region suppresses leakage current, and the toothed heterogate stepped field plate, combined with the patterned source field plate and drain region stepped doping, alleviates electric field concentration and optimizes electric field distribution in the lateral, longitudinal, and vertical directions, thereby improving the device breakdown voltage. The beneficial effects of this invention are that the device possesses high threshold voltage, low on-resistance, and high breakdown voltage.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor technology and relates to a lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region. Background Technology

[0002] Gallium oxide (GaO) with an ultrawide bandgap is an emerging power semiconductor material that boasts advantages such as a high critical breakdown field strength (approximately 8 MV / cm) and flexible tunable N-type doping, significantly enhancing its breakdown voltage capability for the same drift region length. Therefore, the theoretical power figure of merit of GaO devices is significantly higher than that of GaN and silicon carbide devices, offering a significant advantage in high-voltage, high-power, and low-loss power device applications.

[0003] However, the development of gallium oxide power MOSFETs faces two major challenges: First, the actual breakdown voltage of the devices is far lower than the theoretical value, and the electric field concentration effect or the surge in leakage current leads to premature breakdown. Meanwhile, there is a constraint between high breakdown voltage and low on-resistance. Second, the lack of P-type gallium oxide makes it difficult to achieve enhancement-mode in gallium oxide power MOSFETs, and the large negative threshold voltage leads to difficulties in drive design and system application. Existing technologies often use grooved gates and heterojunction gates to achieve normally-off operation, but these can only deplete a relatively thin channel layer. The gate control effect weakens with increasing channel thickness, and the thin active region leads to limited current paths and increased on-resistance, further exacerbating the constraint between high breakdown voltage and low on-resistance. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region.

[0005] The technical solution of this application is as follows:

[0006] A lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region includes a gallium oxide substrate 1 and an unintentionally doped gallium oxide buffer layer 2 located above the gallium oxide substrate 1; characterized in that a current blocking region 3 and a gallium oxide epitaxial layer 7 are disposed side by side along the device lateral on the upper surface of the unintentionally doped gallium oxide buffer layer 2, and the lateral width of the gallium oxide epitaxial layer 7 is greater than the lateral width of the current blocking region 3.

[0007] A source N-doped region 4 is embedded on the upper layer of the current blocking region 3 at the end away from the gallium oxide epitaxial layer 7, and a source implanted N+ doped region 5 is embedded on the upper layer of the source N-doped region 4 at the end away from the gallium oxide epitaxial layer 7; a drain N-doped region 10 is embedded on the upper layer of the gallium oxide epitaxial layer 7 at the end away from the current blocking region 3, and a drain implanted N+ doped region 11 is embedded on the upper layer of the drain N-doped region 10 at the end away from the current blocking region 3; a drain metal 12 is provided on the upper surface of the drain implanted N+ doped region 11 and part of the upper surface of the drain N-doped region 10; a source metal 14 is provided on the upper surface of the source implanted N+ doped region 5 at the end away from the gallium oxide epitaxial layer 7.

[0008] Along the longitudinal direction of the device, the current blocking region 3 between the source N-doped region 4 and the gallium oxide epitaxial layer 7 has multiple intermittently arranged selective grooves.

[0009] Along the lateral direction of the device, the source implantation N+ doped region 5, the current blocking region 3, the gallium oxide epitaxial layer 7 and the drain N doped region 10 between the drain metal 12 and the source metal 14 have a first dielectric layer 8, and the first dielectric layer 8 fills the bottom and side of the selective groove.

[0010] A P-type semiconductor layer 9 is provided on the upper surface of the first dielectric layer 8 near the source metal 14. The P-type semiconductor layer 9 is spaced from the source metal 14 and extends along the device lateral direction toward the drain metal 12 to above the gallium oxide epitaxial layer 7. The P-type semiconductor layer 9 covers the bottom and sides of the first dielectric layer 8 in the selective groove. Along the device longitudinal direction, a protrusion is formed in the middle of the P-type semiconductor layer 9 above the gallium oxide epitaxial layer 7 to form a second gate field plate. Along the device lateral direction, the second gate field plate extends toward the side near the drain metal 12.

[0011] A gate metal 6 is provided on the upper surface of the P-type semiconductor layer 9 between the selective groove and the source metal 14, and there is a gap between the gate metal 6 and the selective groove; and in the transverse cross-sectional view of the device, the side of the first dielectric layer 8 adjacent to the source metal 14, the side of the P-type semiconductor layer 9 and the side of the gate metal 6 present a stepped shape.

[0012] A passivation layer 13 is covered on the upper surface of the device between the source metal 14 and the drain metal 12, and the passivation layer 13 extends along the upper surface of the drain metal 12 to the edge of the device;

[0013] The source metal 14 extends along the upper surface of the passivation layer 13 toward the drain metal 12, and the end of the extended portion of the source metal 14 forms a toothed source field plate with different extension lengths arranged at intervals along the longitudinal direction.

[0014] The transverse direction of the device is the direction from the source metal 14 to the drain metal 12, and the direction from the gallium oxide substrate 1 to the source metal 14 is the vertical direction of the device. Therefore, the longitudinal direction of the device is the third dimension direction that is perpendicular to both the transverse and vertical directions of the device.

[0015] Furthermore, the extended portion of the source metal 14 is defined as a first source field plate and a second source field plate according to the extension length. The lateral width of the second source field plate is greater than that of the first source field plate. Along the lateral direction of the device, the width of the second source field plate gradually changes in the longitudinal direction, and the width near the source is greater than that near the drain.

[0016] Furthermore, the depth, width, and length of the groove gradually change along the vertical direction, the horizontal direction, and the longitudinal direction of the device.

[0017] Furthermore, the width of the second gate field plate gradually changes in the longitudinal direction of the device, with the width near the source being greater than the width near the drain.

[0018] The beneficial effects of the present invention are that the lateral enhancement-mode gallium oxide transistor of the present invention has a selective groove, a current blocking region, a stepped heterogate and a field plate structure. The current blocking region suppresses leakage current, the selective groove and the stepped heterogate increase the channel density, and the electric field distribution is optimized by combining the gate-source field plate structure. The device has high threshold voltage, low on-resistance and high breakdown voltage. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0020] Figure 2 This is a structural schematic diagram of Embodiment 1 of the present invention with auxiliary lines;

[0021] Figure 3 This is a cross-sectional view along line AA' in Example 1;

[0022] Figure 4 This is a cross-sectional view along line BB' in Example 1;

[0023] Figure 5 This is a top view of Embodiment 1;

[0024] Figure 6 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0025] Figure 7 This is a schematic diagram of the structure of Embodiment 3 of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0027] Example 1:

[0028] For ease of description, the following definitions are used in this invention:

[0029] The transverse direction of the device is the direction from the source metal (14) to the drain metal (12), corresponding to the x direction of the coordinate system in the attached figure; the vertical direction of the device is the direction from the gallium oxide substrate (1) to the source metal (14), corresponding to the y direction of the coordinate system in the attached figure; then the longitudinal direction of the device is the third dimension direction that is perpendicular to both the transverse and vertical directions of the device, corresponding to the z direction of the coordinate system in the attached figure.

[0030] like Figure 1 As shown, a lateral enhancement gallium oxide transistor with a selective groove current blocking region includes a gallium oxide substrate 1 and an unintentionally doped gallium oxide buffer layer 2 located above the gallium oxide substrate 1; characterized in that a current blocking region 3 and a gallium oxide epitaxial layer 7 are disposed side by side along the lateral direction of the device on the upper surface of the unintentionally doped gallium oxide buffer layer 2, and the lateral width of the gallium oxide epitaxial layer 7 is greater than the lateral width of the current blocking region 3.

[0031] A source N-doped region 4 is embedded on the upper layer of the current blocking region 3 at the end away from the gallium oxide epitaxial layer 7, and a source implanted N+ doped region 5 is embedded on the upper layer of the source N-doped region 4 at the end away from the gallium oxide epitaxial layer 7; a drain N-doped region 10 is embedded on the upper layer of the gallium oxide epitaxial layer 7 at the end away from the current blocking region 3, and a drain implanted N+ doped region 11 is embedded on the upper layer of the drain N-doped region 10 at the end away from the current blocking region 3; a drain metal 12 is provided on the upper surface of the drain implanted N+ doped region 11 and part of the upper surface of the drain N-doped region 10; a source metal 14 is provided on the upper surface of the source implanted N+ doped region 5 at the end away from the gallium oxide epitaxial layer 7.

[0032] Along the longitudinal direction of the device, the current blocking region 3 between the source N-doped region 4 and the gallium oxide epitaxial layer 7 has multiple intermittently arranged grooves.

[0033] Along the lateral direction of the device, the source implantation N+ doped region 5, the current blocking region 3, the gallium oxide epitaxial layer 7 and the drain N doped region 10 between the drain metal 12 and the source metal 14 have a first dielectric layer 8, and the first dielectric layer 8 fills the bottom and side of the groove.

[0034] A P-type semiconductor layer 9 is provided on the upper surface of the first dielectric layer 8 near the source metal 14. The P-type semiconductor layer 9 is spaced from the source metal 14 and extends along the lateral direction of the device toward the drain metal 12 to above the gallium oxide epitaxial layer 7. The P-type semiconductor layer 9 covers the bottom and sides of the first dielectric layer 8 in the groove. Along the longitudinal direction of the device, a second gate field plate is formed by a protrusion in the middle of the P-type semiconductor layer 9 above the gallium oxide epitaxial layer 7. Along the lateral direction of the device, the second gate field plate extends toward the side near the drain metal 12.

[0035] A gate metal 6 is provided on the upper surface of the P-type semiconductor layer 9 between the groove and the source metal 14, and there is a gap between the gate metal 6 and the groove; and in the transverse cross-sectional view of the device, the side of the first dielectric layer 8 adjacent to the source metal 14, the side of the P-type semiconductor layer 9 and the side of the gate metal 6 are stepped.

[0036] A passivation layer 13 is covered on the upper surface of the device between the source metal 14 and the drain metal 12, and the passivation layer 13 extends along the upper surface of the drain metal 12 to the edge of the device;

[0037] The source metal 14 extends along the upper surface of the passivation layer 13 toward the drain metal 12, and the end of the extended portion of the source metal 14 forms a toothed source field plate with different extension lengths arranged at intervals along the longitudinal direction.

[0038] The extended portion of the source metal 14 is defined as the first source field plate and the second source field plate according to the extension length. The lateral width of the second source field plate is greater than that of the first source field plate. Along the lateral direction of the device, the width of the second source field plate gradually changes in the longitudinal direction, and the width near the source is greater than that near the drain.

[0039] The working principle of this example is as follows:

[0040] At zero bias, the current blocking region 3 restricts the current path, and together with the depletion effect of the P-type semiconductor layer 9 on the conductive channel, it achieves the device's normally-off state and high threshold voltage. During forward conduction, the selective trench and the P-type semiconductor layer 9 increase the channel density. Electron accumulation layers are formed on the surface of the current blocking region 3 on the sidewall of the selective trench and on the surface of the gallium oxide epitaxial layer 7 below the P-type semiconductor layer 9. At the same time, the blocking effect of the current blocking region 3 allows for a larger thickness of the gallium oxide epitaxial layer 7, and the depletion effect of the P-type semiconductor layer 9 allows for a higher doping concentration of the gallium oxide epitaxial layer 7, thereby improving gate control capability, reducing on-resistance, and enhancing device current capability. During forward blocking, the current blocking region 3 suppresses leakage current, the P-type semiconductor layer 9 forms a toothed heterogate stepped field plate, and the source metal 14 forms a patterned source field plate, which alleviates electric field concentration and optimizes electric field distribution in the lateral, longitudinal, and vertical directions, thereby improving the device breakdown voltage. In addition, the drain-implanted N⁺ doped region 11, the drain-N doped region 10, and the gallium oxide epitaxial layer 7 realize the drain region stepped doping, which further optimizes the drain region electric field distribution and improves the device breakdown voltage.

[0041] Example 2:

[0042] The difference between this embodiment and Embodiment 1 is that the groove in the current blocking region 3 is a trapezoidal groove. Along the transverse direction of the device, the width of the trapezoidal groove gradually increases from the side near the drain to the side near the source. The depth, spacing, and inclination angle of the trapezoidal grooves are optimized according to the requirements of withstand voltage and on-resistance, thereby increasing the channel density while further optimizing the electric field distribution at the end of the groove, alleviating the electric field concentration at the corner, and helping to improve the breakdown voltage of the device.

[0043] Example 3:

[0044] The difference between this embodiment and Embodiment 1 is that, along the lateral direction of the device, the width of the second gate field plate in the longitudinal direction is linearly gradual, and the width near the source is greater than the width near the drain. The width gradient of the second gate field plate can also be a stepped gradient or an arc-shaped gradient, further optimizing the surface electric field of the device and improving the device breakdown characteristics.

Claims

1. A lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region, comprising a gallium oxide substrate (1) and an unintentionally doped gallium oxide buffer layer (2) located above the gallium oxide substrate (1); characterized in that, A current blocking region (3) and a gallium oxide epitaxial layer (7) are arranged side by side along the lateral direction of the device on the upper surface of the unintentionally doped gallium oxide buffer layer (2), and the lateral width of the gallium oxide epitaxial layer (7) is greater than the lateral width of the current blocking region (3). A source N-doped region (4) is embedded on the upper layer of the current blocking region (3) away from the gallium oxide epitaxial layer (7), and a source implanted N+ doped region (5) is embedded on the upper layer of the source N-doped region (4) away from the gallium oxide epitaxial layer (7); a drain N-doped region (10) is embedded on the upper layer of the gallium oxide epitaxial layer (7) away from the current blocking region (3), and a drain implanted N+ doped region (11) is embedded on the upper layer of the drain N-doped region (10) away from the current blocking region (3); a drain metal (12) is present on the upper surface of the drain implanted N+ doped region (11) and part of the upper surface of the drain N-doped region (10); a source metal (14) is present on the upper surface of the source implanted N+ doped region (5) away from the gallium oxide epitaxial layer (7); Along the longitudinal direction of the device, there are multiple discontinuously arranged selective grooves in the current blocking region (3) between the source N-doped region (4) and the gallium oxide epitaxial layer (7); Along the lateral direction of the device, the source implanted N+ doped region (5), current blocking region (3), gallium oxide epitaxial layer (7) and drain N doped region (10) between the drain metal (12) and the source metal (14) have a first dielectric layer (8), and the first dielectric layer (8) fills the bottom and sides of the selective groove; A P-type semiconductor layer (9) is provided on the upper surface of the first dielectric layer (8) near the source metal (14). The P-type semiconductor layer (9) is spaced from the source metal (14) and extends along the device lateral direction toward the drain metal (12) to above the gallium oxide epitaxial layer (7). The P-type semiconductor layer (9) covers the bottom and sides of the first dielectric layer (8) in the selective groove. Along the device longitudinal direction, the P-type semiconductor layer (9) above the gallium oxide epitaxial layer (7) protrudes in the middle to form a second gate field plate. Along the device lateral direction, the second gate field plate extends toward the side near the drain metal (12). A gate metal (6) is provided on the upper surface of the P-type semiconductor layer (9) between the selective groove and the source metal (14), and there is a gap between the gate metal (6) and the selective groove; and in the transverse cross-section of the device, the side of the first dielectric layer (8) adjacent to the source metal (14), the side of the P-type semiconductor layer (9) and the side of the gate metal (6) are stepped. A passivation layer (13) is covered on the upper surface of the device between the source metal (14) and the drain metal (12), and the passivation layer (13) extends along the upper surface of the drain metal (12) to the edge of the device; The source metal (14) extends along the upper surface of the passivation layer (13) toward the drain metal (12), and the ends of the extended portion of the source metal (14) form toothed source field plates with different extension lengths arranged in the longitudinal direction. The transverse direction of the device is the direction from the source metal (14) to the drain metal (12), and the direction from the gallium oxide substrate (1) to the source metal (14) is the vertical direction of the device. Therefore, the longitudinal direction of the device is the third dimension direction that is perpendicular to both the transverse direction and the vertical direction of the device.

2. A lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region according to claim 1, characterized in that, The extended portion of the source metal (14) is defined as the first source field plate and the second source field plate according to the extension length. The lateral width of the second source field plate is greater than that of the first source field plate. Along the lateral direction of the device, the width of the second source field plate gradually changes in the longitudinal direction, and the width near the source is greater than that near the drain.

3. A lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region according to claim 1, characterized in that, The depth, width, and length of the selective groove gradually change along the vertical direction, the horizontal direction, and the longitudinal direction of the device.

4. A lateral enhancement-mode gallium oxide transistor with a selective groove current blocking region according to claim 1, characterized in that, The width of the second gate field plate gradually changes in the longitudinal direction of the device, with the width near the source being greater than the width near the drain.

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