An ldmos device and a method of manufacturing the same

Abstract

This application belongs to the field of semiconductor technology and provides an LDMOS device and its fabrication method. The LDMOS device includes: a semiconductor substrate, a buried oxide region, a P-type well region, a source region, a P-type base region, a drain region, a drift region, a gate oxide layer, a gate region, a source electrode, a drain electrode, a gate electrode, and a gate extension region. By setting a gate extension region between the gate region and the drain electrode, a low-resistance, high-concentration electron channel from the drain region to the source region can be formed above the drift region, thereby reducing the on-resistance of the LDMOS device. Furthermore, by alternating the semiconductor substrate and the drift region, breakdown caused by electric field spikes formed within the device is avoided. Thus, while increasing the breakdown voltage of the LDMOS device, the on-resistance is reduced, solving the problem of existing LDMOS devices failing to achieve a balance between breakdown voltage and on-resistance.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to an LDMOS device and its fabrication method. Background Technology

[0002] With the increasing integration density of integrated circuits, laterally diffused metal-oxide-semiconductor (LDMOS) is frequently used in the design of high-voltage power integrated circuits due to its outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. It is particularly prevalent in high-voltage power amplifiers. One important parameter of LDMOS is its on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOS.

[0003] For high-performance power devices, in addition to high breakdown voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between breakdown voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between breakdown voltage and on-resistance, minimizing on-resistance while maintaining a certain breakdown voltage to obtain the maximum possible output power. Some literature has studied the on-resistance of conventionally doped LDMOS and yielded many results, but it has not fundamentally resolved the contradiction between on-resistance and breakdown voltage. The demand for high-performance devices has led to a research focus on simultaneously achieving high breakdown voltage and low on-resistance in LDMOS.

[0004] This shows that existing LDMOS devices cannot achieve a balance between breakdown voltage and on-resistance. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides an LDMOS device and its fabrication method, which can solve the problem that existing LDMOS devices cannot achieve a balance between breakdown voltage and on-resistance.

[0006] This application provides an LDMOS device, the LDMOS device comprising:

[0007] The oxygen-buried area has an "L"-shaped structure.

[0008] A semiconductor substrate is disposed on the back side of the buried oxide region;

[0009] A P-type trap region is provided on the horizontal part of the buried oxygen region, wherein the P-type trap region has an "L" shaped structure;

[0010] The source region is located on the horizontal portion of the P-type well region;

[0011] A P-type base region is disposed on the horizontal portion of the buried oxide region and is in contact with the P-type well region and the source region, respectively.

[0012] The drain region is located on the vertical portion of the buried oxide region;

[0013] A drift region is provided on the vertical part of the buried oxide region and is located between the P-type well region and the drain region;

[0014] A gate oxide layer is disposed on the source region, the P-type well region, and the drift region; wherein the gate oxide layer has an "L"-shaped structure.

[0015] The gate region is located on the horizontal portion of the gate oxide layer;

[0016] The source electrode is in contact with the source region;

[0017] The drain electrode is in contact with the drain region;

[0018] The gate electrode is in contact with the gate region;

[0019] A gate extension region is disposed between the gate region and the drain electrode, and is located on the gate oxide layer;

[0020] The semiconductor substrate and the drift region are arranged alternately.

[0021] In one embodiment, the gate extension region includes:

[0022] A first P-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the gate region;

[0023] The second P-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the first P-type doped region;

[0024] The first N-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the second P-type doped region;

[0025] The third P-type doped region is located on the horizontal portion of the gate oxide layer and is in contact with the first N-type doped region.

[0026] In one embodiment, the thickness of the drift region is less than the thickness of the vertical portion of the P-type well region.

[0027] In one embodiment, the thickness of the drift region is 0.08 μm to 0.12 μm.

[0028] In one embodiment, the width of the drift region is smaller than the width of the gate extension region.

[0029] In one embodiment, the width of the semiconductor substrate is the sum of the widths of the vertical portions of the P-type base region, the source region, and the P-type well region.

[0030] In one embodiment, the sum of the width of the horizontal portion of the buried oxide region and the width of the vertical portion of the buried oxide region is equal to the sum of the width of the semiconductor substrate, the width of the drift region, and the width of the drain region.

[0031] In one embodiment, the thickness of the P-type base region is greater than the thickness of the source region.

[0032] In one embodiment, the thickness of the drift region is equal to the thickness of the drain region.

[0033] A second aspect of this application provides a method for fabricating an LDMOS device, comprising:

[0034] A buried oxide region is formed on a semiconductor substrate; wherein the back side of the buried oxide region is in contact with the semiconductor substrate, and the buried oxide region has an "L" shaped structure;

[0035] A P-type well region and a P-type base region are formed on the horizontal portion of the buried oxygen region; wherein, the P-type well region has an "L"-shaped structure, and the P-type base region is arranged adjacent to the P-type well region;

[0036] A source region is formed on the horizontal portion of the P-type well region, and the source region is in contact with the P-type base region;

[0037] A drift region and a drain region are formed on the vertical portion of the buried oxygen region; wherein the drift region and the drain region are arranged adjacent to each other;

[0038] A gate oxide layer is formed on the source region, the P-type well region, and the drift region; wherein the gate oxide layer has an "L"-shaped structure.

[0039] A gate region and a gate extension region are formed on the horizontal portion of the gate oxide layer; wherein the gate region is in contact with the vertical portion of the gate oxide layer;

[0040] A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region; wherein, the gate extension region is located between the gate region and the drain electrode;

[0041] The semiconductor substrate is selectively etched so that the semiconductor substrate and the drift region are staggered.

[0042] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting a gate extension region between the gate region and the drain electrode, a low-resistance, high-concentration electron channel from the drain region to the source region can be formed above the drift region, thereby reducing the on-resistance of the LDMOS device. Furthermore, by interleaving the semiconductor substrate with the drift region, the device is prevented from breaking down due to electric field spikes formed inside it. Thus, while improving the breakdown voltage of the LDMOS device, the on-resistance of the LDMOS device is reduced, solving the problem that existing LDMOS devices cannot achieve a balance between breakdown voltage and on-resistance. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of an LDMOS device provided in one embodiment of this application. Figure 1 ;

[0044] Figure 2 This is a schematic diagram of the structure of an LDMOS device provided in one embodiment of this application. Figure 2 ;

[0045] Figure 3 This is a schematic diagram of the structure of an LDMOS device provided in one embodiment of this application. Figure 3 ;

[0046] Figure 4 This is a schematic diagram of the fabrication steps of an LDMOS device according to an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the formation of the buried oxygen zone provided in one embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the formation of a P-type well region, a P-type base region, a source region, a drift region, and a drain region according to an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of the gate oxide layer after its formation, provided in one embodiment of this application;

[0050] Figure 8 This is a schematic diagram of the formation of the gate region and the gate extension region provided in one embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the formation of a gate electrode, a drain electrode, and a source electrode provided in one embodiment of this application;

[0052] Figure 10 This is a schematic diagram of selective etching on the back side of a semiconductor substrate according to one embodiment of this application. Detailed Implementation

[0053] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0054] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0057] With the increasing integration density of integrated circuits, laterally diffused metal-oxide-semiconductor (LDMOS) is frequently used in the design of high-voltage power integrated circuits due to its outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. It is particularly prevalent in high-voltage power amplifiers. One important parameter of LDMOS is its on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOS.

[0058] For high-performance power devices, in addition to high breakdown voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between breakdown voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between breakdown voltage and on-resistance, minimizing on-resistance while maintaining a certain breakdown voltage to obtain the maximum possible output power. Some literature has studied the on-resistance of conventionally doped LDMOS and yielded many results, but it has not fundamentally resolved the contradiction between on-resistance and breakdown voltage. The demand for high-performance devices has made the research focus of LDMOS to simultaneously achieve high breakdown voltage and low on-resistance. The breakdown voltage in the off-state and the on-state on-resistance of LDMOS are both inversely proportional to the drift region concentration. Early LDMOS devices had low breakdown voltages due to excessively high drift region concentration. Subsequent RESURF LDMOS devices improved the breakdown voltage by reducing the drift region concentration, but this significantly increased the on-resistance.

[0059] This shows that existing LDMOS devices cannot achieve a balance between breakdown voltage and on-resistance.

[0060] To address the aforementioned technical problems, this application provides an LDMOS device, as shown in the following embodiment. Figure 1 As shown, the LDMOS device includes: a semiconductor substrate 10, a buried oxide region 20, a P-type well region 50, a source region 60, a P-type base region 70, a drain region 40, a drift region 30, a gate oxide layer 80, a gate region 100, a source electrode S, a drain electrode D, a gate electrode G, and a gate extension region 90.

[0061] Specifically, the buried oxide region 20 has an "L"-shaped structure; the semiconductor substrate 10 is disposed on the back side of the buried oxide region 20; the P-type well region 50 is disposed on the horizontal portion of the buried oxide region 20, wherein the P-type well region 50 has an "L"-shaped structure; the source region 60 is disposed on the horizontal portion of the P-type well region 50; the P-type base region 70 is disposed on the horizontal portion of the buried oxide region 20, and the P-type base region 70 is in contact with both the P-type well region 50 and the source region 60; the drain region 40 is disposed on the vertical portion of the buried oxide region 20; the drift region 30 is disposed on the vertical portion of the buried oxide region 20, and the drift region 30 is located between the P-type well region 50 and the drain region 40; the gate... An oxide layer 80 is disposed on the source region 60, the P-type well region 50, the drift region 30, and the drain region 40; wherein, the gate oxide layer 80 has an "L"-shaped structure; the gate region 100 is located on the horizontal portion of the gate oxide layer 80; the source electrode S is in contact with the source region 60, and the source electrode S is also in contact with the P-type base region 70; the drain electrode D is in contact with the drain region 40; the gate electrode G is in contact with the gate region 100; the gate extension region 90 is disposed between the gate region 100 and the drain electrode D, and the gate extension region 90 is located on the gate oxide layer 80; wherein, the semiconductor substrate 10 and the drift region 30 are alternately arranged.

[0062] In this embodiment, the buried oxide region 20 has an "L"-shaped structure, which includes a vertical part and a horizontal part. The P-type well region 50 and the P-type base region 70 are disposed on the horizontal part of the "L"-shaped structure of the buried oxide region 20. The width of the P-type base region 70 and the maximum width of the P-type well region 50 are the same as the width of the horizontal part of the buried oxide region 20. The P-type well region 50 has an "L"-shaped structure with a horizontal part and a vertical part. The source region 60 is disposed on the horizontal part of the P-type well region 50. In a specific application embodiment, the upper surface of the source region 60 is flush with the upper surface of the vertical part of the P-type well region 50, and the width of the source region 60 is equal to the width of the horizontal part of the P-type well region 50. At this time, the source region 60 and the P-type well region 50 form a cuboid.

[0063] In this embodiment, the drift region 30 is disposed between the P-type well region 50 and the drain region 40, such that the drain region 40, the drift region 30, the P-type well region 50, the source region 60 and the P-type base region 70 are at the same horizontal height, and the gate oxide layer 80 is disposed on the source region 60, the P-type well region 50 and the drift region 30.

[0064] In this embodiment, the gate oxide layer 80 has an "L"-shaped structure, which has a horizontal portion and a vertical portion. The gate region 100 and the gate extension region 90 are both disposed on the horizontal portion of the gate oxide layer 80, and the gate region 100 is in contact with the vertical portion of the gate oxide layer 80, and the gate extension region 90 is in contact with the gate region 100. In a specific application embodiment, the upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the gate oxide layer 80, and the sum of the widths of the gate region 100 and the gate extension region 90 is equal to the sum of the widths of the horizontal portion of the gate oxide layer 80. At this time, the gate region 100, the gate extension region 90, and the gate oxide layer 80 together form a cuboid.

[0065] In this embodiment, the gate electrode G is disposed on the gate region 100 and the gate extension region 90, and the gate electrode G is in contact with the gate region 100 and the gate extension region 90, respectively.

[0066] In this embodiment, the gate extension region 90 is disposed on the horizontal portion of the gate oxide layer 80 and is in contact with the gate region 100. By providing the gate extension region 90, a low-resistance, high-concentration electron channel from the drain region 40 to the source region 60 can be formed above the drift region 30, thereby reducing the on-resistance of the LDMOS device. In this embodiment, the on-resistance of the LDMOS device is reduced by providing the gate extension region 90.

[0067] In this embodiment, the semiconductor substrate 10 and the drift region 30 are staggered. Specifically, there is no semiconductor substrate 10 directly below the drift region 30. The semiconductor substrate 10 directly below the drift region 30 is removed by etching, and the width of the etching is the same as the width of the drift region 30. This results in the remaining semiconductor substrate 10 being staggered with the drift region 30. In this way, the equipotential lines in the buried oxide region 20 can be released, preventing them from being trapped inside the device and forming electric field spikes that could cause breakdown. In this embodiment, by setting the semiconductor substrate 10 and the drift region 30 to be staggered, the breakdown voltage of the LDMOS device can be improved, preventing breakdown.

[0068] In one embodiment, for the material of the buried oxide region 20, silicon oxide is a commonly used material with mature technology. Alternatively, a low-K dielectric with a dielectric constant lower than that of silicon oxide can be used to improve the longitudinal withstand voltage and reduce the thickness of the buried oxide region 20.

[0069] In one embodiment, reference Figure 2 As shown, the gate extension region 90 includes: a first P-type doped region 91, a second P-type doped region 92, a first N-type doped region 93, and a third P-type doped region 94.

[0070] Specifically, a first P-type doped region 91 is disposed on the horizontal portion of the gate oxide layer 80 and is in contact with the gate region 100; a second P-type doped region 92 is disposed on the horizontal portion of the gate oxide layer 80 and is in contact with the first P-type doped region 91; a first N-type doped region 93 is disposed on the horizontal portion of the gate oxide layer 80 and is in contact with the second P-type doped region 92; and a third P-type doped region 94 is disposed on the horizontal portion of the gate oxide layer 80 and is in contact with the first N-type doped region 93.

[0071] In this embodiment, the first P-type doped region 91 and the second P-type doped region 92 are doped with P-type dopant ions, wherein the doping concentration of the first P-type doped region 91 is greater than that of the second P-type doped region 92. The first N-type doped region 93 can be doped with N-type dopant ions, such as nitrogen ions or phosphorus ions. The third P-type doped region 94 can be doped with P-type dopant ions, such as aluminum ions. By doping with different elements, the first N-type doped region 93 and the third P-type doped region 94 form a PN junction, which can enhance the electric field above the gate oxide layer 80, thereby forming a low-resistance electron channel above the drift region 30 and reducing the on-resistance.

[0072] In one embodiment, the second P-type doped region 92 has the same doped ions as the first P-type doped region 91, but a different doping concentration. This differs from the doped ions in the first N-type doped region 93, thus avoiding the adverse effects on the longitudinal electric field strength of the drift region 30 after the second P-type doped region 92 is depleted in the device's off-voltage state. Therefore, the device's breakdown voltage can be improved. However, due to the different doping type in the first N-type doped region 93, the process requirements are more complex.

[0073] In one embodiment, the thickness of the drift region 30 is less than the thickness of the vertical portion of the P-type well region 50.

[0074] In this embodiment, the drift region 30 is made of silicon. According to the dielectric layer field strength enhancement theorem (ENDIF), when the drift region 30 contacts the gate oxide layer 80, the critical breakdown electric field of the drift region 30 will be increased. By setting the thickness of the drift region 30 to be less than the thickness of the vertical portion of the P-type well region 50, it is helpful to improve the breakdown voltage of the LDMOS device.

[0075] In one embodiment, the thickness of the drift region 30 is 0.08 μm to 0.12 μm.

[0076] In a specific application, when the drift region 30 can be a silicon layer and the thickness of the drift region 30 is set to 0.1 μm, when the ultrathin Si layer contacts the gate oxide layer 80, the critical breakdown electric field of Si will be increased. For example, when Si is 0.1 μm, the breakdown electric field of Si can be increased to close to 140 V / μm, thus greatly improving the breakdown voltage of the device.

[0077] In a specific application, in order to ensure a high breakdown voltage, the entire drift region 30 needs to be uniformly doped.

[0078] In one embodiment, the width of the drift region 30 is smaller than the width of the gate extension region 90.

[0079] In this embodiment, by setting the width of the drift region 30 to be smaller than the width of the gate extension region 90, it is helpful for the gate extension region 90 to form a low-resistance electronic channel above the drift region 30, thereby reducing the on-resistance. In this way, while increasing the breakdown voltage, the on-resistance is reduced, solving the problem that existing LDMOS devices cannot achieve a balance between breakdown voltage and on-resistance.

[0080] In one embodiment, the width of the semiconductor substrate 10 is the sum of the widths of the vertical portions of the P-type base region 70, the source region 60, and the P-type well region 50. Specifically, after the LDMOS device is fabricated, the semiconductor substrate 10 corresponding to the vertical direction of the drift region 30 and the drain region 40 is etched away, leaving only the semiconductor substrate 10 corresponding to the vertical portions of the P-type base region 70, the source region 60, and the P-type well region 50. This releases the equipotential lines in the buried oxide region 20, preventing them from being trapped inside the device and forming electric field spikes that could cause breakdown.

[0081] In one embodiment, the sum of the width of the horizontal portion of the buried oxide region 20 and the width of the vertical portion of the buried oxide region 20 is equal to the sum of the widths of the semiconductor substrate 10, the drift region 30, and the drain region 40. The width of the semiconductor substrate 10 is equal to the sum of the widths of the vertical portions of the P-type base region 70, the source region 60, and the P-type well region 50. This facilitates the release of equipotential lines in the buried oxide region 20, preventing them from being trapped inside the device and forming electric field spikes that could cause breakdown.

[0082] In one embodiment, the thickness of the P-type base region 70 is greater than the thickness of the source region 60. Specifically, the thickness of the P-type base region 70 is the sum of the thicknesses of the source region 60 and the horizontal portion of the P-type well region 50. Since the P-type base region 70 is the voltage access point of the LDMOS device, by setting the thickness of the P-type base region 70 to be the sum of the thicknesses of the horizontal portions of the source region 60 and the P-type well region 50, the voltage can be better accessed, maintaining the stability of the LDMOS device and improving its performance.

[0083] In one embodiment, the thickness of the drift region 30 is equal to the thickness of the drain region 40. Specifically, setting the thickness of the drift region 30 to be very small allows the critical breakdown electric field of the drift region 30 to be increased when the ultra-thin drift region 30 contacts the gate oxide layer 80. By setting the thickness of the drift region 30 to be less than the thickness of the vertical portion of the P-type well region 50, it helps to improve the breakdown voltage of the LDMOS device.

[0084] In one embodiment, reference Figure 3As shown, the LDMOS device also includes: multiple shallow trench isolation regions 110, wherein the multiple shallow trench isolation regions 110 are all disposed within the second P-type doped region 92, wherein the depth of the multiple shallow trench isolation regions 110 gradually increases from the source region 60 to the drain region 40, specifically, the depth of the shallow trench isolation region 110 near the source region 60 is less than the depth of the shallow trench isolation region 110 near the drain region 40, wherein the multiple shallow trench isolation regions 110 are formed by depositing, patterning, and etching silicon using a silicon nitride mask, and filling the trenches with deposited oxide. By setting multiple shallow trench isolation regions 110 within the second P-type doped region 92, a high electric field can be formed at the multiple shallow trench isolation regions 110, which can modulate the electric field distribution of the LDMOS device and improve the breakdown voltage of the LDMOS device.

[0085] In one embodiment, the gate oxide layer 80 is made of a high-k dielectric material. By using a high-k dielectric, the concentration of electron channels formed above the drift region 30 can be increased and the resistance can be reduced. In this way, the on-resistance of the LDMOS device can be reduced more effectively.

[0086] In one embodiment, the semiconductor substrate 10 may be a silicon-based substrate or a silicon carbide substrate.

[0087] In one embodiment, the buried oxide region 20 is silicon oxide.

[0088] In one embodiment, the drift region 30 is Si.

[0089] In one embodiment, the gate electrode G can be at least one of copper, gold, and silver.

[0090] In one embodiment, the drain electrode D can be at least one of copper, gold, and silver.

[0091] In one embodiment, the source electrode S can be at least one of copper, gold, and silver.

[0092] In one embodiment, the source region 60, drain region 40, and gate region 100 can serve as pads for the corresponding electrodes. Specifically, the source region 60, drain region 40, and gate region 100 can be made of semiconductor materials, such as gallium nitride, or they can be made of metal materials.

[0093] This application also provides a method for fabricating an LDMOS device, see the following embodiments: Figure 4 As shown, the preparation method in this embodiment includes steps S100-S600.

[0094] Step S100: Reference Figure 5As shown, a buried oxide region 20 is formed on the semiconductor substrate 10; wherein, the back side of the buried oxide region 20 is in contact with the semiconductor substrate 10, and the buried oxide region 20 has an "L" shaped structure.

[0095] In this embodiment, the semiconductor substrate 10 can be an N-type silicon substrate, combined with Figure 5 As shown, in specific applications, a buried oxide region 20 can be formed on the semiconductor substrate 10 by depositing silicon dioxide material or by oxidizing the N-type silicon substrate. The thickness of the buried oxide region 20 can be set according to the application requirements of the device.

[0096] In one specific application embodiment, the material used in the buried oxide region 20 can also be a low-K dielectric material with a dielectric constant lower than that of SiO2. By using a low-K dielectric material, the longitudinal breakdown voltage of the device can be improved, and the thickness of the buried oxide region 20 can be reduced.

[0097] Step S200: Reference Figure 6 As shown, a drift region 30, a source region 60, a P-type well region 50, a P-type base region 70, and a drain region 40 are formed on the horizontal portion of the buried oxide region 20.

[0098] Specifically, the P-type well region 50 has an "L"-shaped structure; a source region 60 is formed on the horizontal part of the P-type well region 50; a P-type base region 70 is formed on the horizontal part of the buried oxide region 20, and the P-type base region 70 is in contact with the P-type well region 50 and the source region 60 respectively; a drift region 30 is formed on the vertical part of the buried oxide region 20; a drain region 40 is formed on the vertical part of the buried oxide region 20 and is in contact with the drift region 30, and the drift region 30 and the drain region 40 are arranged adjacent to each other.

[0099] In this embodiment, a drift region 30, a source region 60, a P-type well region 50, a P-type base region 70, and a drain region 40 can be formed in a predetermined region on the buried oxide region 20 by depositing semiconductor or metal materials.

[0100] In one embodiment, by selectively etching the buried oxide region 20, regions of P-type well region 50, P-type base region 70, drift region 30 and drain region 40 are etched respectively, and then corresponding ionic materials are deposited to form the corresponding regions. For example, drain region 40 is formed by depositing N-type ions, drift region 30 is formed by depositing silicon ions, and P-type well region 50 and P-type base region 70 are formed by depositing P-type ions.

[0101] Step S300: Reference Figure 7 As shown, a gate oxide layer 80 is formed on the source region 60, the P-type well region 50, and the drift region 30; wherein the gate oxide layer 80 has an "L"-shaped structure.

[0102] In this embodiment, the gate oxide layer 80 has an "L" shaped structure. The gate region 100 and the gate extension region 90 are both disposed on the horizontal portion of the gate oxide layer 80, and the gate region 100 is in contact with the vertical portion of the gate oxide layer 80, while the gate extension region 90 is in contact with the gate region 100. The upper surfaces of the gate region 100 and the gate extension region 90 are flush with the upper surface of the vertical portion of the gate oxide layer 80, and the widths of the gate region 100 and the gate extension region 90 are equal to the width of the horizontal portion of the gate oxide layer 80. At this time, the gate region 100, the gate extension region 90, and the gate oxide layer 80 together form a cuboid.

[0103] Step S400: Reference Figure 8 As shown, a gate region 100 and a gate extension region 90 are formed on the horizontal portion of the gate oxide layer 80.

[0104] Specifically, the gate region 100 is in contact with the vertical portion of the gate oxide layer 80, and the gate extension region 90 is in contact with the gate region 100.

[0105] In this embodiment, the gate extension region 90 is disposed on the horizontal portion of the gate extension region 80 and contacts the gate region 100. By providing the gate extension region 90, the electric field above the gate extension region 80 can be enhanced, thereby forming a low-resistance electron channel above the drift region 30, and thus reducing the on-resistance of the LDMOS device. In this embodiment, by providing the gate extension region 90, the on-resistance of the LDMOS device is reduced, and by providing multiple metal field plates 110, the breakdown voltage of the LDMOS device is increased, so that the breakdown voltage and on-resistance are balanced, providing an LDMOS device that reduces on-resistance and increases breakdown voltage.

[0106] Step S500: Reference Figure 9 As shown, a source electrode S is formed on the source region 60, a drain electrode D is formed on the drain region 40, and a gate electrode G is formed on the gate region 100.

[0107] In one specific application, a mask is used to determine the shape of the source electrode S, the gate electrode G, and the drain electrode D, and metal is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D.

[0108] In this embodiment, a mask is used to define the shapes of the source electrode S, the gate electrode G, and the drain electrode D, thereby depositing metal material on the mask to form the source electrode S, the gate electrode G, and the drain electrode D, and then removing the mask.

[0109] Step S600: Reference Figure 10 As shown, selective etching is performed on the back side of the semiconductor substrate 10 so that the semiconductor substrate 10 and the drift region 30 are staggered.

[0110] In one embodiment, in step S600, selective etching is performed on the back side of the semiconductor substrate 10 so that the semiconductor substrate 10 and the drift region 30 are staggered. Specifically, the area to be etched can be determined on the semiconductor substrate 10 using a mask, and a chemical etching solution is diffused onto the surface of the area to be etched on the semiconductor substrate 10. The etching solution reacts chemically with the area to be etched, and the reaction products diffuse from the surface of the etched area into the solution and are discharged with the solution, thus completing the etching of the semiconductor substrate 10. By staggering the semiconductor substrate 10 and the drift region 30, the equipotential lines in the buried oxide region 20 can be released, preventing them from being trapped inside the device and forming electric field spikes that could cause breakdown. In this embodiment, by setting the semiconductor substrate 10 and the drift region 30 to be staggered, the breakdown voltage of the LDMOS device can be improved, preventing breakdown.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0112] The units described as separate components may or may not be physically separate. The components that display data may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0113] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An LDMOS device, characterized in that, The LDMOS device includes: The oxygen-buried area has an "L"-shaped structure. A semiconductor substrate is disposed on the back side of the buried oxide region; A P-type trap region is provided on the horizontal part of the buried oxygen region, wherein the P-type trap region has an "L" shaped structure; The source region is located on the horizontal portion of the P-type well region; A P-type base region is disposed on the horizontal portion of the buried oxide region and is in contact with the P-type well region and the source region, respectively. The drain region is located on the vertical portion of the buried oxide region; A drift region is provided on the vertical part of the buried oxide region and is located between the P-type well region and the drain region; A gate oxide layer is disposed on the source region, the P-type well region, the drain region, and the drift region; wherein the gate oxide layer has an "L"-shaped structure. The gate region is located on the horizontal portion of the gate oxide layer; The source electrode is in contact with the source region; The drain electrode is in contact with the drain region; The gate electrode is in contact with the gate region; A gate extension region is disposed between the gate region and the drain electrode, and is located on the gate oxide layer; Wherein, the projection of the semiconductor substrate and the drift region onto the buried oxide region do not overlap.

2. The LDMOS device as described in claim 1, characterized in that, The gate extension region includes: A first P-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the gate region; The second P-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the first P-type doped region; The first N-type doped region is disposed on the horizontal portion of the gate oxide layer and is in contact with the second P-type doped region; The third P-type doped region is located on the horizontal portion of the gate oxide layer and is in contact with the first N-type doped region.

3. The LDMOS device as described in claim 1, characterized in that, The thickness of the drift region is less than the thickness of the vertical portion of the P-type well region.

4. The LDMOS device as described in claim 3, characterized in that, The thickness of the drift region is 0.08μm-0.12μm.

5. The LDMOS device as described in claim 3, characterized in that, The width of the drift region is smaller than the width of the gate extension region.

6. The LDMOS device as described in claim 1, characterized in that, The width of the semiconductor substrate is the sum of the widths of the vertical portions of the P-type base region, the source region, and the P-type well region.

7. The LDMOS device as described in claim 1, characterized in that, The sum of the width of the horizontal portion of the buried oxide region and the width of the vertical portion of the buried oxide region is equal to the sum of the width of the semiconductor substrate, the width of the drift region, and the width of the drain region.

8. The LDMOS device as described in claim 1, characterized in that, The thickness of the P-type base region is greater than the thickness of the source region.

9. The LDMOS device as described in claim 1, characterized in that, The thickness of the drift region is equal to the thickness of the drain region.

10. A method for fabricating an LDMOS device, characterized in that, include: A buried oxide region is formed on a semiconductor substrate; wherein the back side of the buried oxide region is in contact with the semiconductor substrate, and the buried oxide region has an "L" shaped structure; A P-type well region and a P-type base region are formed on the horizontal portion of the buried oxygen region; wherein, the P-type well region has an "L" shaped structure, and the P-type base region is arranged adjacent to the P-type well region; A source region is formed on the horizontal portion of the P-type well region, and the source region is in contact with the P-type base region; A drift region and a drain region are formed on the vertical portion of the buried oxygen region; wherein the drift region and the drain region are arranged adjacent to each other; A gate oxide layer is formed on the source region, the P-type well region, the drain region, and the drift region; wherein the gate oxide layer has an "L"-shaped structure. A gate region and a gate extension region are formed on the horizontal portion of the gate oxide layer; wherein the gate region is in contact with the vertical portion of the gate oxide layer; A source electrode is formed on the source region, a drain electrode is formed on the drain region, and a gate electrode is formed on the gate region; wherein, the gate extension region is located between the gate region and the drain electrode; The semiconductor substrate is selectively etched so that the projection of the semiconductor substrate onto the buried oxide region does not overlap with the projection of the drift region onto the buried oxide region.

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