Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: forming a first auxiliary gate structure in a first lead-out region; forming a source doped region in an active region and on a body region surrounding each main gate structure; after forming the source doped region, forming a first groove in the first auxiliary gate structure, the first groove extending along a second direction; forming a second groove in the source doped region and body region between adjacent main gate structures, the second groove extending along a first direction; implanting first doped ions into an epitaxial layer under the first and second grooves to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure; after forming the first implantation region, forming a first conductive plug and a first conductive layer on the first conductive plug in the first groove, and forming a second conductive plug and a second conductive layer on the second conductive plug in the second groove. This method improves device performance while saving manufacturing costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the increasing demand for consumer electronics products, the demand for power MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) is growing, in applications such as disk drives, automotive electronics, and power devices. Trench MOSFETs, due to their high integration density, low on-resistance, low gate-drain charge density, and large current capacity, exhibit lower switching losses and faster switching speeds, making them widely used in low-voltage power applications.

[0003] A trench-gate MOSFET is a device with a vertically conductive channel, where current flows vertically from the drain to the source when the device is on. The on-resistance (Rsp) and breakdown voltage (BV) of a trench-gate MOSFET are among its key parameters; achieving higher breakdown voltage and lower on-resistance improves product competitiveness. To improve the on-resistance of medium- to high-voltage (50V–200V) trench-gate MOSFETs, the concept of a superjunction-trench-gate MOSFET was proposed. Taking an N-channel trench gate as an example, the bottom of the P-type ion implantation region (P-pillar) used for depletion of the auxiliary drift region is placed as close as possible to the highly doped substrate to maximize the length of the depletable N-type drift region. To improve the characteristics of a superjunction-trench-gate MOSFET, the bottom of the P-type ion implantation region is placed as close as possible to the highly doped substrate, thereby increasing the overall epitaxial layer concentration.

[0004] However, P-type ion implantation increases manufacturing costs, reducing the advantages of superjunction trench gate MOSFETs. Therefore, the fabrication process for existing trench gate MOSFET devices needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the manufacturing cost of trench gate MOSFET devices.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate and an epitaxial layer located on the substrate, the epitaxial layer including an active region and a peripheral region surrounding the active region, the peripheral region including two first lead-out regions, the two first lead-out regions being located on both sides of the active region, and the first lead-out regions and the active region being arranged along a first direction; a body region located within the epitaxial layer; a plurality of main gate structures located within the active region, the plurality of main gate structures penetrating the body region in a direction perpendicular to the surface of the substrate, the plurality of main gate structures being parallel to the first direction and arranged along a second direction, the first direction and the second direction being perpendicular to each other; and a first auxiliary gate structure located within the first lead-out region, the first auxiliary gate structure penetrating the body region in a direction perpendicular to the surface of the substrate, the first auxiliary gate structure being parallel to the second direction and electrically interconnected with the main gate structure; A first conductive plug located within the first auxiliary gate structure, the first conductive plug extending along the second direction; a source doped region located on the body region within the active region, the source doped region being located around the main gate structure; a second conductive plug located between adjacent main gate structures, the second conductive plug being located within the source doped region and the body region, the second conductive plug extending along the first direction; a first conductive layer located on the epitaxial layer, the first conductive layer including a first lead-out parallel to the second direction, the first lead-out and the first auxiliary gate structure being electrically connected through the first conductive plug; a second conductive layer located on the epitaxial layer, the second conductive layer being electrically connected to the source doped region and the body region through the plurality of second conductive plugs; a first implantation region located within the epitaxial layer, the first implantation region being located at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure.

[0007] Optionally, the peripheral region further includes a second lead-out region, which is parallel to the first direction and located on one side of the active region and the first lead-out region; the first conductive layer further includes an end located on the second lead-out region, which is parallel to the first direction and electrically interconnected with the first lead-out portion.

[0008] Optionally, the peripheral region further includes a plurality of shielding regions arranged from the outside to the inside, each of the shielding regions including a first shielding region and a second shielding region surrounding the first shielding region; the semiconductor structure further includes: a first shielding structure located in the first shielding region, the first shielding structure including a second injection region and a third conductive plug located on the second injection region, the second injection region being located at the bottom of the body region; and a second shielding structure located in the second shielding region, the second shielding structure including a dummy gate structure, the dummy gate structure penetrating the body region in a direction perpendicular to the substrate surface.

[0009] Optionally, the first shielding region includes a first region and a second region that are mutually separate, and the first region and the second region are arranged along the first direction; the third conductive plug is located in the first region and the second region; the end is electrically interconnected with the third conductive plug in the first region; the first region also has a second auxiliary gate structure, the second auxiliary gate structure includes a second auxiliary gate dielectric layer and a second auxiliary gate located on the second auxiliary gate dielectric layer; the third conductive plug is also located in the second auxiliary gate structure, and a portion of the second injection region is located at the bottom of the second auxiliary gate structure.

[0010] Optionally, the active region further includes a charge balance region; the source doped region and the main gate structure are located in the active region outside the charge balance region; the first conductive layer further includes a second lead-out portion located on the charge balance region, the second lead-out portion being electrically interconnected with the end.

[0011] Optionally, it further includes: a charge balancing structure located within the charge balancing region, the charge balancing structure including a third injection region located at the bottom of the body region and a fourth conductive plug located within the body region, the charge balancing structure including a plurality of third regions parallel to the first direction and two fourth regions located on both sides of the plurality of third regions, the two fourth regions and the plurality of third regions being arranged along the first direction and respectively connected to one end of the plurality of third regions, the fourth conductive plug being electrically interconnected with the second lead-out portion, and the fourth conductive plug being isolated from the second conductive plug.

[0012] Optionally, the charge balancing structure further includes a third auxiliary gate structure, the fourth conductive plug is located within the third auxiliary gate structure, and the third injection region is located at the bottom of the third auxiliary gate structure. The third auxiliary gate structure isolates the third injection region from the body region and is electrically interconnected with the main gate structure. The third auxiliary gate structure includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer.

[0013] Optionally, it further includes: an interlayer dielectric layer located on the epitaxial layer, wherein the first conductive layer, the first conductive plug, the second conductive layer, and the second conductive plug are also located within the interlayer dielectric layer.

[0014] Optionally, the substrate and the source doped region are of a first conductivity type, and the body region and the first implantation region are of a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

[0015] Optionally, the main gate structure includes a main gate dielectric layer and a main gate located on the main gate dielectric layer; the first auxiliary gate structure includes a first auxiliary gate dielectric layer and a first auxiliary gate located on the first auxiliary gate dielectric layer.

[0016] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer including an active region and a peripheral region surrounding the active region, the peripheral region including two first lead-out regions, the two first lead-out regions being respectively located on both sides of the active region, and the first lead-out regions and the active region being arranged along a first direction; forming a body region within the epitaxial layer; forming a plurality of main gate structures within the active region, the plurality of main gate structures penetrating the body region in a direction perpendicular to the substrate surface, the plurality of main gate structures being parallel to the first direction and arranged along a second direction, the first direction and the second direction being perpendicular to each other; forming a first auxiliary gate structure within the first lead-out region, the first auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the first auxiliary gate structure being parallel to the first lead-out region and arranged along a second direction, the first direction and the second direction being perpendicular to each other; forming a first auxiliary gate structure within the first lead-out region, the first auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the first auxiliary gate structure being parallel to the first lead-out region and arranged along a second direction, the first lead-out region ... The structure is bidirectional and electrically interconnected with the main gate structure; a source doped region is formed in the active region and on the body region surrounding each main gate structure; after forming the source doped region, a first groove is formed in the first auxiliary gate structure, the first groove extending along the second direction; a second groove is formed in the source doped region and the body region between adjacent main gate structures, the second groove extending along the first direction; first doped ions are implanted into the epitaxial layer under the first groove and the second groove to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure; after forming the first implantation region, a first conductive plug and a first conductive layer on the first conductive plug are formed in the first groove; a second conductive plug and a second conductive layer on the second conductive plug are formed in the second groove.

[0017] Optionally, the peripheral region further includes a second lead-out region, which is parallel to the first direction and located on one side of the active region and the first lead-out region; the first conductive layer on the first lead-out region is used as the first lead-out portion, and the first conductive layer further includes an end located on the second lead-out region, which is parallel to the first direction and electrically interconnected with the first lead-out portion.

[0018] Optionally, the peripheral area further includes a plurality of shielding areas arranged from the outside to the inside, each of the shielding areas including a first shielding area and a second shielding area surrounding the first shielding area; the method includes: forming a shielding structure in each of the shielding areas, the shielding structure including a first shielding structure located in the first shielding area and a second shielding structure located in the second shielding area.

[0019] Optionally, the first shielding region includes a first region and a second region that are mutually separate, and the first region and the second region are arranged along the first direction; the end is electrically interconnected with the first shielding structure in the first region; the method of forming the first shielding structure includes: after forming the source doped region, forming a third groove in the body region of the first region and the second region; implanting a second doped ion into the epitaxial layer under the third groove to form a second implantation region at the bottom of the body region; after forming the second implantation region, forming a third conductive plug in the third groove, with the third conductive plug and the second implantation region forming the first shielding structure.

[0020] Optionally, the method for forming the first shielding structure further includes: after forming the body region and before forming the source doped region, forming a second auxiliary gate structure in the first region, the second auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the second auxiliary gate structure including a second auxiliary gate dielectric layer and a second auxiliary gate located on the second auxiliary gate dielectric layer; the third groove is also located within the second auxiliary gate structure; the second implantation region is also located at the bottom of the second auxiliary gate structure.

[0021] Optionally, the method for forming the second shielding structure includes: after forming the body region and before forming the source doped region, forming the second shielding structure in the second shielding region, the second shielding structure including a pseudo-gate structure that penetrates the body region in a direction perpendicular to the substrate surface.

[0022] Optionally, the active region further includes a charge balance region, which is adjacent to the second lead-out region; the source doped region and the main gate structure are located in the active region outside the charge balance region; the first conductive layer further includes a second lead-out portion located on the charge balance region, which is electrically interconnected with the end portion.

[0023] Optionally, after forming the body region and before forming the first conductive layer, the method further includes: forming a charge balancing structure within the charge balancing region, the charge balancing structure including a third injection region located at the bottom of the body region and a fourth conductive plug located within the body region, the charge balancing structure including a plurality of third regions parallel to the first direction and two fourth regions located on both sides of the plurality of third regions, the two fourth regions and the plurality of third regions being arranged along the first direction and respectively connected to one end of the plurality of third regions, the fourth conductive plug being electrically interconnected with the second lead-out portion, and the fourth conductive plug being isolated from the second conductive plug.

[0024] Optionally, the charge balancing structure further includes a third auxiliary gate structure, the fourth conductive plug is located within the third auxiliary gate structure, and the third injection region is located at the bottom of the third auxiliary gate structure. The third auxiliary gate structure isolates the third injection region from the body region and is electrically interconnected with the main gate structure. The third auxiliary gate structure includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer.

[0025] Optionally, the method for forming the charge balance structure includes: after forming the body region and before forming the source doped region, forming a third auxiliary gate structure in the third region and the fourth region, the third auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface and electrically interconnected with the main gate structure; after forming the source doped region, forming a fourth groove in the third auxiliary gate structure; implanting third doped ions into the fourth groove to form the third implantation region; forming the fourth conductive plug in the fourth groove, the second lead-out portion of the first conductive layer being located on the fourth conductive plug.

[0026] Optionally, the method further includes: after forming the source doped region, forming an interlayer dielectric layer on the epitaxial layer, wherein the first groove and the second groove are also located within the interlayer dielectric layer.

[0027] Optionally, the substrate and the source doped region are of a first conductivity type, and the body region and the first implantation region are of a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

[0028] Optionally, the main gate structure includes a main gate dielectric layer and a main gate located on the main gate dielectric layer; the first auxiliary gate structure includes a first auxiliary gate dielectric layer and a first auxiliary gate located on the first auxiliary gate dielectric layer.

[0029] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0030] In the semiconductor structure formation method provided by the present invention, first doped ions are implanted into the epitaxial layer under the first and second grooves to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure. After forming the first implantation region, a first conductive plug and a first conductive layer on the first conductive plug are formed in the first groove, and a second conductive plug and a second conductive layer on the second conductive plug are formed in the second groove. The first implantation region is used for auxiliary drift region depletion, which can increase the drift region concentration and reduce the on-resistance of the device. The positions of the first implantation region, the first conductive plug and the second conductive plug depend on the position of the first groove (or the second groove). Since the first groove and the second groove can be formed in the same photolithography process, the formation of the first implantation region does not require the introduction of a new photomask. While reducing the on-resistance of the device, it is beneficial to save manufacturing costs in the production process. Attached Figure Description

[0031] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.

[0032] Figures 4 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0033] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0034] As described in the background section, the fabrication process of existing trench gate MOSFET devices needs further improvement. This will now be explained and analyzed in conjunction with a semiconductor structure.

[0035] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.

[0036] Please refer to Figures 1 to 3 , Figure 1 This is a top-down structural diagram. Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of local region i along the DD1 direction. Figure 3 for Figure 1The schematic diagram of the cross-sectional structure of local region ii along the EE1 direction shows that the semiconductor structure includes: a substrate 100 having opposing first surfaces 100a and second surfaces 100b; an epitaxial layer 101 located on the first surface 100a, the epitaxial layer 101 having a plurality of gate trenches (not shown in the figure), the plurality of gate trenches being parallel to a first direction X and arranged along a second direction Y, the first direction X and the second direction Y being perpendicular to each other, and the plurality of gate trenches extending from the first surface 100a to the second surface 100b. Extending inwards; a gate structure located within the plurality of gate trenches, the gate structure including a gate dielectric layer 102 and a gate 103 located on the surface of the gate dielectric layer 102; a body region 104 located within the epitaxial layer 101; source regions 105 located within the body regions 104 on both sides of the gate structure; a dielectric layer 106 located on the epitaxial layer 101; a plurality of first conductive plugs 107 located within the dielectric layer 106 and the source regions 105, the plurality of first conductive plugs 107 further extending into the body regions 104 below the source regions 105. A plurality of second conductive plugs 108 located within the dielectric layer 106 and the gate structure; a first conductive layer 109 and a second conductive layer 110 located on the dielectric layer 106, wherein the first conductive layer 109 is electrically connected to the body region 104 and the source region 105 through the plurality of first conductive plugs 107, and the second conductive layer 110 is electrically connected to the gate structure through the plurality of second conductive plugs 108; a lead-out region 111 located within the body region 104 and on the surface of the plurality of first conductive plugs 107; located on the outer An implantation region 112 within the extension layer 101 extends from the body region 104 toward the substrate 100, and the projection of the implantation region 112 onto the surface of the substrate 100 lies between the projections of adjacent gate structures onto the surface of the substrate 100; an isolation structure is located around the plurality of gate trenches, the isolation structure including a plurality of first isolation regions 113 and a plurality of second isolation regions 114, each of the first isolation regions 113 being located between adjacent second isolation regions 114; and a third conductive layer 115 is located on the second surface 100b.

[0037] It should be noted that, Figure 1 Only the relative positions or connections between the gate 103, the injection region 112, the first conductive layer 109, the second conductive layer 110, and the isolation structure are shown.

[0038] The above structure is a superjunction-trench gate MOSFET device. The injection region 112 is used to deplete the auxiliary drift region and reduce the on-resistance of the device. However, the injection region 112 requires additional processes for injection, increasing mask and process costs, and thus increasing manufacturing costs, thereby reducing the advantages of the superjunction-trench gate MOSFET.

[0039] To address the aforementioned problems, the present invention provides a semiconductor structure and its formation method, in which first doped ions are implanted into the epitaxial layer under the first and second grooves to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure. After forming the first implantation region, a first conductive plug and a first conductive layer on the first conductive plug are formed in the first groove, and a second conductive plug and a second conductive layer on the second conductive plug are formed in the second groove. The first implantation region is used for auxiliary drift region depletion, which can increase the drift region concentration and reduce the on-resistance of the device. The positions of the first implantation region, the first conductive plug, and the second conductive plug depend on the position of the first groove (or the second groove). Since the first groove and the second groove can be formed in the same photolithography process, the formation of the first implantation region does not require the introduction of a new photomask, which helps to reduce the on-resistance of the device and save manufacturing costs.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 4 and Figure 5 , Figure 4 This is a top-down structural diagram. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the NN1 direction is provided, showing the substrate 200.

[0043] In this embodiment, the substrate 200 is of the first conductivity type.

[0044] In this embodiment, the first conductivity type is N-type, and the substrate 200 is used to form the drain of the trench gate MOSFET device. In other embodiments, the first conductivity type can be P-type.

[0045] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] Please continue to refer to this. Figure 4 and Figure 5An epitaxial layer 201 is formed on the substrate 200. The epitaxial layer 201 includes an active region 201a and a peripheral region 201b surrounding the active region 201a. The peripheral region 201b includes two first lead-out regions I, which are located on both sides of the active region 201a, and the first lead-out regions I and the active region 201a are arranged along a first direction X. A volume region 202 is formed within the epitaxial layer 201.

[0047] In this embodiment, the body region 202 has a second conductivity type, which is different from the first conductivity type.

[0048] In this embodiment, the second conductivity type is P-type.

[0049] In this embodiment, the peripheral region 201b further includes a second lead-out region II, which is parallel to the first direction X and located on one side of the active region 201a and the first lead-out region I.

[0050] Subsequently, a first conductive layer is formed on the two first lead-out regions I and the second lead-out region II. The first conductive layer is used for the lead-out of the device gate electrical signal.

[0051] In this embodiment, the first conductive layer on the first lead-out region I is used as the first lead-out portion. The first conductive layer also includes an end located on the second lead-out region II. The end is parallel to the first direction X and is electrically interconnected with the first lead-out portion.

[0052] In this embodiment, the peripheral area 201b further includes a plurality of shielding areas arranged from the outside to the inside, each of the shielding areas including a first shielding area i and a second shielding area ii surrounding the first shielding area i.

[0053] Subsequently, a shielding structure is formed within each of the shielding zones, the shielding structure including a first shielding structure located within the first shielding zone and a second shielding structure located within the second shielding zone.

[0054] In this embodiment, the first shielding area i includes a first area A and a second area (not shown in the figure) that are mutually separate, and the first area A and the second area are arranged along the first direction X.

[0055] In this embodiment, the end is electrically interconnected with the first shielding structure within the first region A.

[0056] The first shielding region i is used to form the second implantation region, which contains doped ions to provide a shielding effect.

[0057] In this embodiment, the active region 201a also has a charge balance region B, which is adjacent to the second lead-out region II.

[0058] In this embodiment, the first conductive layer further includes a second lead-out portion located on the charge balance region B, and the second lead-out portion is electrically interconnected with the end.

[0059] Subsequently, a charge balance structure is formed within the charge balance region B, and the second lead-out portion is electrically interconnected with the charge balance structure.

[0060] Please Figure 4 Based on this, continue to refer to Figures 6 to 8 , Figure 6 This is a top-down structural diagram. Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure along the MM1 direction in a partial section (dashed box m). Figure 8 for Figure 6 A partial cross-sectional view (dashed box n) along the NN1 direction shows that a plurality of main gate structures 203 are formed in the active region 201a. The plurality of main gate structures 203 penetrate the body region 202 in a direction perpendicular to the surface of the substrate 200. The plurality of main gate structures 203 are parallel to the first direction X and arranged along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other. A first auxiliary gate structure 204 is formed in the first lead-out region a. The first auxiliary gate structure 204 penetrates the body region 202 in a direction perpendicular to the surface of the substrate 200. The first auxiliary gate structure 204 is parallel to the second direction Y and is electrically interconnected with the main gate structures 203.

[0061] In this embodiment, the main gate structure 203 is located in the active region 201a outside the charge balance region B.

[0062] In this embodiment, the main gate structure 203 includes a main gate dielectric layer 203a and a main gate 203b located on the main gate dielectric layer 203a; the first auxiliary gate structure 204 includes a first auxiliary gate dielectric layer 204a and a first auxiliary gate 204b located on the first auxiliary gate dielectric layer 204a.

[0063] Subsequently, a source doped region is formed within the active region 201a and on the body region 202 surrounding each main gate structure 203.

[0064] In this embodiment, after the body region 202 is formed and before the source doped region is formed, a second auxiliary gate structure 205 is also formed in the first region A. The second auxiliary gate structure 205 penetrates the body region 202 in a direction perpendicular to the surface of the substrate 200.

[0065] In this embodiment, the second auxiliary gate structure 205 includes a second auxiliary gate dielectric layer (not shown in the figure) and a second auxiliary gate (not shown in the figure) located on the second auxiliary gate dielectric layer. The second auxiliary gate structure 205 is used to isolate the first region A from the second region.

[0066] In this embodiment, the first auxiliary gate structure 204 further extends onto a portion of the second lead-out region II. Specifically, the first auxiliary gate structure 204 is electrically interconnected with the second auxiliary gate structure 205 on the adjacent second lead-out region II.

[0067] In this embodiment, after the body region 202 is formed and before the source doping region is formed, a second shielding structure is also formed in the second shielding region ii. The second shielding structure includes a pseudo gate structure 206, which penetrates the body region 202 in a direction perpendicular to the surface of the substrate 200.

[0068] In this embodiment, the dummy gate structure 206 includes a dummy gate dielectric layer (not shown in the figure) and a dummy gate (not shown in the figure) located on the dummy gate dielectric layer. The dummy gate structure 206 serves as an insulating shield.

[0069] In this embodiment, after the body region 202 is formed and before the source doped region is formed, a third auxiliary gate structure 207 is also formed in the charge balance region B. The third auxiliary gate structure 207 penetrates the body region 202 in a direction perpendicular to the surface of the substrate 200 and is electrically interconnected with the main gate structure 203.

[0070] In this embodiment, the third auxiliary gate structure 207 includes a third gate dielectric layer (not shown in the figure) and a third auxiliary gate located on the third gate dielectric layer (not shown in the figure).

[0071] In this embodiment, the third auxiliary gate structure 207 is also electrically interconnected with the second auxiliary gate structure 205 on the adjacent second lead-out region II.

[0072] The method for forming the plurality of main gate structures 203 includes: forming a plurality of gate trenches (not shown in the figure) in the active region 201a, the plurality of gate trenches being parallel to the first direction X and arranged along the second direction Y, the plurality of gate trenches penetrating the body region 202 in a direction perpendicular to the surface of the substrate 200; forming a gate dielectric material layer (not shown in the figure) and a gate material layer (not shown in the figure) located on the gate dielectric material layer in the plurality of gate trenches and on the surface of the epitaxial layer 201; planarizing the gate material layer and the gate dielectric material layer until the surface of the epitaxial layer 201 is exposed.

[0073] In this embodiment, the plurality of main gate structures 203, the first auxiliary gate structure 204, the second auxiliary gate structure 205, the dummy gate structure 206, and the third auxiliary gate structure 207 are formed in the same process. The methods for forming the first auxiliary gate structure 204, the second auxiliary gate structure 205, the dummy gate structure 206, and the third auxiliary gate structure 207 are described in the description of the method for forming the plurality of main gate structures 203, and will not be repeated here.

[0074] Please refer to Figures 9 to 11 , Figure 9 This is a top-down structural diagram. Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure along the MM1 direction in a partial section (dashed box m). Figure 11 for Figure 9 A partial cross-sectional view (dashed box n) along the NN1 direction shows that a source doped region 208 is formed in the active region 201a and on the body region 202 surrounding each main gate structure 203. After the source doped region 208 is formed, a first groove 209 is formed in the first auxiliary gate structure 204, and the first groove 209 extends along the second direction Y. A second groove 210 is formed in the source doped region 208 and the body region 202 between adjacent main gate structures 203, and the second groove 210 extends along the first direction X.

[0075] In this embodiment, the source doped region 208 is located in the charge balance region B (e.g., Figure 4 The active region 201a outside the area shown.

[0076] The method for forming the source doped region 208 includes: forming a mask layer (not shown in the figure) on the surface of the epitaxial layer 201, the mask layer exposing the surface of the active region 201a outside the charge balance region B; and implanting a fourth dopant ion into the epitaxial layer 201.

[0077] In this embodiment, the source doped region 208 is of a first conductivity type. Specifically, the first conductivity type is N-type.

[0078] In this embodiment, after the source doped region 208 is formed, an interlayer dielectric layer 211 is formed on the epitaxial layer 201, and the first groove 209 and the second groove 210 are also located within the interlayer dielectric layer 211.

[0079] The first groove 209 is used to form a first conductive plug and to position the first injection area; the second groove 210 is used to form a second conductive plug and to position the second injection area.

[0080] In this embodiment, after forming the source doped region 208, in the first region A (e.g. Figure 4 A third groove 212 is formed within the body region 202 of the second region (as shown). The third groove 212 is used to form the first shielding structure.

[0081] In this embodiment, the third groove 212 is also located within the second auxiliary gate structure 205.

[0082] In this embodiment, after forming the source doped region 208, a fourth groove 213 is also formed within the third auxiliary gate structure 207. The fourth groove 213 is used to locate the third implantation region and the fourth conductive plug.

[0083] Specifically, the fourth groove 213 includes a plurality of first sub-grooves (not shown in the figure) extending along the first direction X, and two second sub-grooves (not shown in the figure) located at both ends of the first sub-grooves and respectively connected to each end of the first sub-grooves, the second sub-grooves being parallel to the second direction Y.

[0084] In this embodiment, the first groove 209, the second groove 210, the third groove 212 and the fourth groove 213 are formed in the same photolithography process.

[0085] Please continue to refer to this. Figures 9 to 11 First doped ions are injected into the epitaxial layer 201 under the first groove 209 and the second groove 210 to form a first injection region 214 at the bottom of the body region 202 between adjacent main gate structures 203 and at the bottom of the first auxiliary gate structure 204.

[0086] In this embodiment, the first injection region 214 is of the second conductivity type. The second conductivity type is P-type.

[0087] In this embodiment, a fifth doped ion is also injected into the bottom of the first groove 209 to form a heavily doped region 215 at the bottom of the source doped region 208.

[0088] In this embodiment, the heavily doped region 215 has a P-type conductivity. The heavily doped region 215 is used to reduce the contact resistance between the subsequently formed first conductive plug and the body region 202.

[0089] In this embodiment, second doped ions are also implanted into the epitaxial layer 201 under the third groove 212 to form a second implantation region (not shown in the figure) at the bottom of the body region 202. The second implantation region is used to form a protective ring to protect the device.

[0090] In this embodiment, the second injection region is also located at the bottom of the second auxiliary gate structure 205.

[0091] In this embodiment, a third doped ion is also injected into the fourth groove 213 to form the third implantation region (not shown in the figure).

[0092] In this embodiment, the first injection region 214, the second injection region, and the third injection region are formed in the same process to reduce process steps and save production costs.

[0093] Please refer to Figures 12 to 14 , Figure 12 This is a top-down structural diagram. Figure 13 for Figure 12 A schematic diagram of the cross-sectional structure along the MM1 direction in a partial section (dashed box m). Figure 14 for Figure 12 A partial cross-sectional view (dashed box n) along the NN1 direction shows that after the first injection region 214 is formed, a first conductive plug 216 and a first conductive layer 217 on the first conductive plug 216 are formed in the first groove 209, and a second conductive plug 218 and a second conductive layer 219 on the second conductive plug 218 are formed in the second groove 210.

[0094] In the method for forming the semiconductor structure, the first injection region 214 is used to deplete the drift region, which can increase the drift region concentration and reduce the on-resistance of the device. The positions of the first injection region 214, the first conductive plug 216, and the second conductive plug 218 depend on the position of the first groove 209 (or the second groove 210). Since the first groove 209 and the second groove 210 can be formed in the same photolithography process, the formation of the first injection region 214 does not require the introduction of a new photomask. While reducing the on-resistance of the device, it is beneficial to save manufacturing costs in the production process.

[0095] The design of the first conductive plug 216 and the second conductive plug 218 being perpendicular to each other is beneficial to improving the charge balance of the device.

[0096] In this embodiment, after the second injection area is formed, a third conductive plug 221 is also formed in the third groove 212, and the third conductive plug 221 and the second injection area form the first shielding structure.

[0097] In this embodiment, the first conductive layer 219 on the first lead-out region I is used as the first lead-out part, and the first lead-out part leads out the electrical signals of the plurality of main gate structures 203 through the first conductive plug 216.

[0098] The first conductive layer 219 also includes an end located on the second lead-out region II, the end being parallel to the first direction X and electrically interconnected with the first lead-out portion.

[0099] In this embodiment, the end is electrically interconnected with the first shielding structure within the first region A. Specifically, the end is electrically interconnected with the third conductive plug 221 within the first region A.

[0100] In this embodiment, a fourth conductive plug 222 is also formed in the fourth groove 213, and the second lead-out portion of the first conductive layer 217 is located on the fourth conductive plug 222.

[0101] In this embodiment, a charge balance structure is formed by the third injection region and the fourth conductive plug 222. The charge balance structure includes a plurality of third regions (not shown in the figure) parallel to the first direction X and two fourth regions (not shown in the figure) located on both sides of the plurality of third regions. The two fourth regions and the plurality of third regions are arranged along the first direction X and are respectively connected to one end of the plurality of third regions. The fourth conductive plug 222 is electrically interconnected with the second lead-out portion, and the fourth conductive plug 222 is isolated from the second conductive plug 218.

[0102] The charge balance structure includes a plurality of third regions parallel to the first direction X and two fourth regions located on both sides of the plurality of third regions. The two fourth regions and the plurality of third regions are arranged along the first direction X and are respectively connected to one end of the plurality of third regions, which is beneficial to improving the charge balance of the device.

[0103] In this embodiment, the charge balance structure further includes a third auxiliary gate structure 207, the fourth conductive plug is located inside the third auxiliary gate structure 207, and the third injection region is located at the bottom of the third auxiliary gate structure 207. The third auxiliary gate structure 207 isolates the third injection region from the body region 202 and is electrically interconnected with the main gate structure 203.

[0104] In this embodiment, the third auxiliary gate structure 207 includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer. The third gate dielectric layer in the third auxiliary gate structure 207 is used to isolate the second conductive plug 218 and the fourth conductive plug 222.

[0105] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method. Please refer to [the documentation for further details]. Figures 12 to 14The system includes: a substrate 200 and an epitaxial layer 201 located on the substrate 200. The epitaxial layer 201 includes an active region 201a and a peripheral region 201b surrounding the active region 201a. The peripheral region 201b includes two first lead-out regions I, which are located on both sides of the active region 201a, and the first lead-out regions I and the active region 201a are arranged along a first direction X; a body region 202 located within the epitaxial layer 201; and a plurality of main gate structures 203 located within the active region 201a, wherein the plurality of main gate structures 203 are arranged vertically... A plurality of main gate structures 203 penetrate the body region 202 in a direction perpendicular to the surface of the substrate 200, and are arranged parallel to the first direction X and along the second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other; a first auxiliary gate structure 204 is located within the first lead-out region I, the first auxiliary gate structure 204 penetrates the body region 202 in a direction perpendicular to the surface of the substrate 200, the first auxiliary gate structure 204 is parallel to the second direction Y, and is electrically interconnected with the main gate structure 203; a first conductive insert is located within the first auxiliary gate structure 204. A first conductive plug 216 extends along the second direction Y; a source doped region 208 is located on the body region 202 within the active region 201a, the source doped region 208 being located around the main gate structure 203; a second conductive plug 218 is located between adjacent main gate structures 203, and the second conductive plug 218 is located within the source doped region 208 and the body region 202, the second conductive plug 218 extending along the first direction X; a first conductive layer 217 is located on the epitaxial layer 201, the first conductive layer 217 including a flat... A first lead-out portion (not shown in the figure) is located in the second direction Y. The first lead-out portion and the first auxiliary gate structure 204 are electrically connected through the first conductive plug 218. A second conductive layer 219 is located on the epitaxial layer 201. The second conductive layer 219 is electrically connected to the source doped region 208 and the body region 202 through the plurality of second conductive plugs 218. A first implantation region 214 is located in the epitaxial layer 201. The first implantation region 214 is located at the bottom of the body region 202 and the bottom of the first auxiliary gate structure 204 between adjacent main gate structures 204.

[0106] In this embodiment, the peripheral region 201 further includes a second lead-out region II, which is parallel to the first direction X and located on one side of the active region 201a and the first lead-out region I.

[0107] In this embodiment, the first conductive layer 217 further includes an end portion (not shown in the figure) located on the second lead-out region II, the end portion II being parallel to the first direction X and electrically interconnected with the first lead-out portion.

[0108] In this embodiment, the peripheral area 201b further includes a plurality of shielding areas arranged from the outside to the inside, each of the shielding areas including a first shielding area i (e.g., Figure 4 (as shown) and a second shielding area ii surrounding the first shielding area i (as shown) Figure 4 (As shown).

[0109] In this embodiment, the semiconductor structure further includes: a first shielding structure located in the first shielding region i, the first shielding structure including a second injection region (not shown in the figure) and a third conductive plug 221 located on the second injection region, the second injection region being located at the bottom of the body region 202.

[0110] In this embodiment, the semiconductor structure further includes a second shielding structure located in the second shielding region ii, the second shielding structure including a pseudo-gate structure 206, the pseudo-gate structure 206 penetrating the body region 202 in a direction perpendicular to the surface of the substrate 200.

[0111] In this embodiment, the first shielding region i includes a first region A and a second region (not shown in the figure) that are mutually independent, and the first region A and the second region are arranged along the first direction; the third conductive plug 221 is located in the first region A and the second region; the end is electrically interconnected with the third conductive plug 221 in the first region A; the first region A also has a second auxiliary gate structure 205, the second auxiliary gate structure 205 includes a second auxiliary gate dielectric layer (not shown in the figure) and a second auxiliary gate (not shown in the figure) located on the second auxiliary gate dielectric layer; the third conductive plug 221 is also located in the second auxiliary gate structure 205, and a portion of the second injection region is located at the bottom of the second auxiliary gate structure 205.

[0112] In this embodiment, the active region 201a also has a charge balance region B (such as...). Figure 4 (as shown); the source doped region 208 and the main gate structure 203 are located in the active region 201a outside the charge balance region B; the first conductive layer 217 also includes a second lead-out portion (not shown in the figure) located on the charge balance region B, the second lead-out portion being electrically interconnected with the end.

[0113] In this embodiment, the semiconductor structure further includes a charge balance structure located within the charge balance region B. The charge balance structure includes a plurality of third regions (not shown in the figure) parallel to the first direction X and two fourth regions (not shown in the figure) located on both sides of the plurality of third regions. The two fourth regions and the plurality of third regions are arranged along the first direction X and are respectively connected to one end of the plurality of third regions. The fourth conductive plug 222 is electrically interconnected with the second lead-out portion, and the fourth conductive plug 222 is isolated from the second conductive plug 218.

[0114] The charge balance structure includes a plurality of third regions parallel to the first direction X and two fourth regions located on both sides of the plurality of third regions. The two fourth regions and the plurality of third regions are arranged along the first direction X and are respectively connected to one end of the plurality of third regions, which is beneficial to improving the charge balance of the device.

[0115] In this embodiment, the charge balance structure further includes a third auxiliary gate structure 207, the fourth conductive plug is located inside the third auxiliary gate structure 207, and the third injection region is located at the bottom of the third auxiliary gate structure 207. The third auxiliary gate structure 207 isolates the third injection region from the body region 202 and is electrically interconnected with the main gate structure 203.

[0116] In this embodiment, the third auxiliary gate structure 207 includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer. The third gate dielectric layer in the third auxiliary gate structure 207 is used to isolate the second conductive plug 218 and the fourth conductive plug 222.

[0117] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 211 located on the epitaxial layer, wherein the first conductive layer 217, the first conductive plug 216, the second conductive layer 219, and the second conductive plug 218 are also located within the interlayer dielectric layer 211.

[0118] In this embodiment, the substrate 200 and the source doped region 208 are of the first conductivity type, and the body region 202 and the first implantation region 214 are of the second conductivity type. The first conductivity type and the second conductivity type are different.

[0119] In this embodiment, the main gate structure 203 includes a main gate dielectric layer 203a and a main gate 203b located on the main gate dielectric layer 203a; the first auxiliary gate structure 204 includes a first auxiliary gate dielectric layer 204a and a first auxiliary gate 204b located on the first auxiliary gate dielectric layer 204a.

[0120] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and an epitaxial layer located on the substrate, the epitaxial layer including an active region and a peripheral region surrounding the active region, the peripheral region including two first lead-out regions, the two first lead-out regions being located on both sides of the active region, and the first lead-out regions and the active region being arranged along a first direction; The volume region located within the epitaxial layer; A plurality of main gate structures are located within the active region. The plurality of main gate structures penetrate the body region in a direction perpendicular to the substrate surface. The plurality of main gate structures are parallel to the first direction and arranged along the second direction. The first direction and the second direction are perpendicular to each other. A first auxiliary gate structure located within the first lead-out region, the first auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the first auxiliary gate structure being parallel to the second direction and electrically interconnected with the main gate structure; A first conductive plug is located within the first auxiliary gate structure, and the first conductive plug extends along the second direction; A source doped region located on the body region within the active region, the source doped region being located around the main gate structure; A second conductive plug is located between adjacent main gate structures, and the second conductive plug is located within the source doped region and the body region, and the second conductive plug extends along the first direction; A first conductive layer is located on the epitaxial layer, the first conductive layer includes a first lead-out portion parallel to the second direction, and the first lead-out portion and the first auxiliary gate structure are electrically connected through the first conductive plug; A second conductive layer is located on the epitaxial layer, and the second conductive layer is electrically connected to the source doped region and the body region through the plurality of second conductive plugs; A first injection region is located within the epitaxial layer, the first injection region being located at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The peripheral area further includes a second lead-out area, which is parallel to the first direction and located on one side of the active area and the first lead-out area; the first conductive layer further includes an end located on the second lead-out area, which is parallel to the first direction and electrically interconnected with the first lead-out portion.

3. The semiconductor structure as described in claim 2, characterized in that, The peripheral region further includes a plurality of shielding regions arranged from the outside to the inside, each of the shielding regions including a first shielding region and a second shielding region surrounding the first shielding region; the semiconductor structure further includes: a first shielding structure located in the first shielding region, the first shielding structure including a second injection region and a third conductive plug located on the second injection region, the second injection region being located at the bottom of the body region; and a second shielding structure located in the second shielding region, the second shielding structure including a dummy gate structure, the dummy gate structure penetrating the body region in a direction perpendicular to the surface of the substrate.

4. The semiconductor structure as described in claim 3, characterized in that, The first shielding region includes a first region and a second region that are mutually independent, and the first region and the second region are arranged along the first direction; the third conductive plug is located in the first region and the second region; the end is electrically interconnected with the third conductive plug in the first region; the first region also has a second auxiliary gate structure, the second auxiliary gate structure includes a second auxiliary gate dielectric layer and a second auxiliary gate located on the second auxiliary gate dielectric layer; the third conductive plug is also located in the second auxiliary gate structure, and a portion of the second injection region is located at the bottom of the second auxiliary gate structure.

5. The semiconductor structure as described in claim 2, characterized in that, The active region also has a charge balance region; the source doped region and the main gate structure are located in the active region outside the charge balance region; the first conductive layer also includes a second lead-out portion located on the charge balance region, and the second lead-out portion is electrically interconnected with the end.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: A charge balancing structure located within the charge balancing region includes a third injection region located at the bottom of the body region and a fourth conductive plug located within the body region. The charge balancing structure includes a plurality of third regions parallel to the first direction and two fourth regions located on both sides of the plurality of third regions. The two fourth regions and the plurality of third regions are arranged along the first direction and are respectively connected to one end of the plurality of third regions. The fourth conductive plug is electrically interconnected with the second lead-out portion and is isolated from the second conductive plug.

7. The semiconductor structure as described in claim 6, characterized in that, The charge balance structure further includes a third auxiliary gate structure, the fourth conductive plug is located within the third auxiliary gate structure, and the third injection region is located at the bottom of the third auxiliary gate structure. The third auxiliary gate structure isolates the third injection region and the body region and is electrically interconnected with the main gate structure. The third auxiliary gate structure includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: An interlayer dielectric layer is located on the epitaxial layer, and the first conductive layer, the first conductive plug, the second conductive layer, and the second conductive plug are also located within the interlayer dielectric layer.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate and the source doped region are of a first conductivity type, and the body region and the first implanted region are of a second conductivity type. The first conductivity type and the second conductivity type are different.

10. The semiconductor structure as claimed in claim 1, characterized in that, The main gate structure includes a main gate dielectric layer and a main gate located on the main gate dielectric layer; the first auxiliary gate structure includes a first auxiliary gate dielectric layer and a first auxiliary gate located on the first auxiliary gate dielectric layer.

11. A method for forming a semiconductor structure, characterized in that, include: Provide a base; An epitaxial layer is formed on the substrate. The epitaxial layer includes an active region and a peripheral region surrounding the active region. The peripheral region includes two first lead-out regions, which are located on both sides of the active region, and the first lead-out regions and the active region are arranged along a first direction. A volume region is formed within the epitaxial layer; A plurality of main gate structures are formed in the active region. The plurality of main gate structures penetrate the body region in a direction perpendicular to the surface of the substrate. The plurality of main gate structures are parallel to the first direction and arranged along the second direction. The first direction and the second direction are perpendicular to each other. A first auxiliary gate structure is formed in the first lead-out region. The first auxiliary gate structure penetrates the body region in a direction perpendicular to the substrate surface. The first auxiliary gate structure is parallel to the second direction and is electrically interconnected with the main gate structure. A source doped region is formed within the active region and on the body region surrounding each main gate structure; After the source doped region is formed, a first groove is formed in the first auxiliary gate structure, the first groove extending along the second direction, and a second groove is formed in the source doped region and the body region between adjacent main gate structures, the second groove extending along the first direction. First doped ions are implanted into the epitaxial layer under the first and second grooves to form a first implantation region at the bottom of the body region between adjacent main gate structures and at the bottom of the first auxiliary gate structure; After the first injection region is formed, a first conductive plug and a first conductive layer on the first conductive plug are formed in the first groove, and a second conductive plug and a second conductive layer on the second conductive plug are formed in the second groove.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The peripheral area further includes a second lead-out area, which is parallel to the first direction and located on one side of the active area and the first lead-out area; the first conductive layer on the first lead-out area is used as the first lead-out portion, and the first conductive layer further includes an end located on the second lead-out area, which is parallel to the first direction and electrically interconnected with the first lead-out portion.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The peripheral area further includes a plurality of shielding areas arranged from the outside in, each of the shielding areas including a first shielding area and a second shielding area surrounding the first shielding area; the method includes: forming a shielding structure in each of the shielding areas, the shielding structure including a first shielding structure located in the first shielding area and a second shielding structure located in the second shielding area.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The first shielding region includes a first region and a second region that are mutually independent, and the first region and the second region are arranged along the first direction; the end is electrically interconnected with the first shielding structure in the first region; the method of forming the first shielding structure includes: after forming the source doped region, forming a third groove in the body region of the first region and the second region; implanting a second doped ion into the epitaxial layer under the third groove to form a second implantation region at the bottom of the body region; after forming the second implantation region, forming a third conductive plug in the third groove, with the third conductive plug and the second implantation region forming the first shielding structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the first shielding structure further includes: after forming the body region and before forming the source doped region, forming a second auxiliary gate structure in the first region, the second auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface, the second auxiliary gate structure including a second auxiliary gate dielectric layer and a second auxiliary gate located on the second auxiliary gate dielectric layer; the third groove is also located in the second auxiliary gate structure; the second implantation region is also located at the bottom of the second auxiliary gate structure.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the second shielding structure includes: after forming the body region and before forming the source doping region, forming the second shielding structure in the second shielding region, the second shielding structure including a pseudo gate structure that penetrates the body region in a direction perpendicular to the surface of the substrate.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The active region also includes a charge balance region, which is adjacent to the second lead-out region; the source doped region and the main gate structure are located in the active region outside the charge balance region; the first conductive layer also includes a second lead-out portion located on the charge balance region, which is electrically interconnected with the end.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, After forming the body region and before forming the first conductive layer, the method further includes: forming a charge balancing structure within the charge balancing region, the charge balancing structure including a third injection region located at the bottom of the body region and a fourth conductive plug located within the body region, the charge balancing structure including a plurality of third regions parallel to the first direction and two fourth regions located on both sides of the plurality of third regions, the two fourth regions and the plurality of third regions being arranged along the first direction and respectively connected to one end of the plurality of third regions, the fourth conductive plug being electrically interconnected with the second lead-out portion, and the fourth conductive plug being isolated from the second conductive plug.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The charge balance structure further includes a third auxiliary gate structure, the fourth conductive plug is located within the third auxiliary gate structure, and the third injection region is located at the bottom of the third auxiliary gate structure. The third auxiliary gate structure isolates the third injection region and the body region and is electrically interconnected with the main gate structure. The third auxiliary gate structure includes a third gate dielectric layer and a third auxiliary gate located on the third gate dielectric layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The method for forming the charge balance structure includes: after forming the body region and before forming the source doped region, forming a third auxiliary gate structure in the third region and the fourth region, the third auxiliary gate structure penetrating the body region in a direction perpendicular to the substrate surface and electrically interconnected with the main gate structure; after forming the source doped region, forming a fourth groove in the third auxiliary gate structure; implanting third doped ions into the fourth groove to form the third implantation region; forming the fourth conductive plug in the fourth groove, the second lead-out portion of the first conductive layer being located on the fourth conductive plug.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method further includes: after forming the source doped region, forming an interlayer dielectric layer on the epitaxial layer, wherein the first groove and the second groove are also located within the interlayer dielectric layer.

22. The method for forming a semiconductor structure as described in claim 11, characterized in that, The substrate and the source doped region are of a first conductivity type, and the body region and the first implanted region are of a second conductivity type. The first conductivity type and the second conductivity type are different.

23. The method for forming a semiconductor structure as described in claim 11, characterized in that, The main gate structure includes a main gate dielectric layer and a main gate located on the main gate dielectric layer; the first auxiliary gate structure includes a first auxiliary gate dielectric layer and a first auxiliary gate located on the first auxiliary gate dielectric layer.

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