A high voltage TFT driven addressable flat panel X-ray source and its preparation method

Abstract

The present invention relates to the technical field of vacuum micro-nanoelectronics, and more specifically, to an addressable flat-panel X-ray source driven by a high-voltage TFT and a preparation method thereof. The high-voltage TFT comprises a bottom gate electrode and a top gate electrode. An active layer arranged on the top of a gate insulating layer comprises a plurality of parallel channels, and a gap is formed between adjacent channels. The bottom gate electrode and the top gate electrode together form a double-gate structure, which enhances the regulation effect on the gate-controlled channel of the high-voltage TFT, can effectively improve the threshold voltage and subthreshold swing of the high-voltage TFT, and increase the saturation current; the gap between adjacent channels can enhance the heat dissipation effect, ensure that the device will not have the problem of thermal breakdown, and the parallel channel structure enables the double-gate high-voltage TFT to achieve a large current while ensuring its withstand voltage performance, thereby meeting the requirements of the flat-panel X-ray source for a high operating voltage and a large operating current of a driving unit, and realizing an addressable flat-panel X-ray source with high voltage, large current, high resolution and accurate current regulation.

Description

Technical Field

[0001] The present invention relates to the technical field of vacuum micro-nanoelectronics, and more specifically, to an addressable flat-panel X-ray source driven by a high-voltage TFT and a preparation method thereof. Background Art

[0002] X-ray imaging has been widely used in people's production and life, such as medical diagnosis and treatment, material property analysis, safety inspection and industrial non-destructive inspection, etc. With the development of science and technology, X-ray imaging is developing in the direction of low dose, high resolution, fast speed and portability.

[0003] At present, the most widely used is the hot cathode X-ray source, which uses a tungsten wire with a high melting point as the cathode, generates hot electrons at a high temperature of up to 2000°C, and accelerates the bombardment of the anode target under the action of the electric field, thereby generating X-rays. This method has the advantages of being simple and mature, but it also has disadvantages such as low conversion efficiency, high operating temperature, large size, and high energy consumption. The flat-panel X-ray source using an addressable cold cathode electron source can achieve addressable emission of X-rays, and can simultaneously control X-rays in space, time, and energy. It has the advantages of controllable irradiation range, low-dose imaging, short imaging working distance, fast imaging speed, and small system size.

[0004] The addressable flat-panel X-ray source consists of a row-column addressable cold cathode electron source array and an anode. The addressing of the cold cathode electron source includes: diode addressing (addressing is achieved by crossing the anode electrode and the cathode electrode), gate structure addressing drive, and transistor addressing drive. The diode addressable cold cathode electron source has the problem of too high driving voltage and difficulty in achieving high resolution. The gate structure addressable cold cathode electron source can solve the problem of high resolution, but it also has problems such as too high driving voltage (80V), unstable emission current, and uneven field emission characteristics.

[0005] Field effect transistors can realize voltage control over current and have the advantage of low voltage regulation, so they are widely used in various fields as active control devices. Therefore, in order to reduce the driving voltage of cold cathode electron sources, field effect transistors, junction field effect transistors and thin film transistors (TFTs) are used as active control devices for cold cathode electron sources. Existing studies have integrated field effect transistors (MOSFETs), junction field effect transistors (JFETs) with cold cathode field emission arrays to achieve low voltage drive and high stability field emission current cold cathode electron sources, but MOSFET and JFET use silicon-based substrates, which makes it difficult to achieve large-area cold cathode electron source preparation; currently, high-voltage TFTs that drive cold cathode electron sources with biased drain structures or high-voltage TFTs with field plates are mainly integrated with large-area cold cathode field emission arrays to achieve large-area active drive addressable electron source arrays.

[0006] Chinese patent CN202111267038.1 discloses a cold cathode flat-panel X-ray source driven by a high-voltage TFT and a preparation method thereof, wherein the cold cathode flat-panel X-ray source comprises an addressable nano cold cathode electron source array substrate and an anode substrate provided with a metal film target layer, wherein the addressable nano cold cathode electron source array substrate is driven by a high-voltage TFT with a field plate structure, the addressable nano cold cathode electron source array substrate is arranged parallel to the anode substrate, and an insulating spacer is arranged between the cold cathode electron source array substrate and the anode substrate, and the cold cathode electron source array substrate emits focused electrons under the action of the high-voltage TFT to bombard the metal film target layer in the anode substrate to generate addressable X-rays. In this scheme, applying a negative voltage to the field plate structure can effectively increase the breakdown voltage of the high-voltage TFT, but the operating current of the device is low, which limits the field emission current and is not suitable for driving a high-current emission cathode. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an addressable flat-panel X-ray source driven by a high-voltage TFT and a preparation method thereof, which is suitable for low-voltage driving of a large-current emission cathode and meets the requirements of the flat-panel X-ray source for a high operating voltage and a large operating current of the driving unit.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] Provided is an addressable flat-panel X-ray source driven by a high-voltage TFT, comprising an addressable nano cold cathode electron source array substrate and an anode substrate provided with a metal film target layer, wherein the addressable nano cold cathode electron source array substrate is arranged parallel to and opposite to the anode substrate, and an insulating spacer is arranged between the cold cathode electron source array substrate and the anode substrate, and the cold cathode electron source array substrate emits focused electrons under the action of the high-voltage TFT to bombard the metal film target layer in the anode substrate to generate addressable X-rays; the addressable nano cold cathode electron source array substrate comprises a nano cold cathode array and a cathode electrode located on the same cathode substrate as the high-voltage TFT; the high-voltage TFT comprises a bottom gate electrode, a gate insulating layer, an active layer, a source electrode, a drain electrode and a passivation layer, wherein the bottom gate electrode is located on the top of the cathode substrate, and the gate insulating layer covers the cathode electrode. The bottom gate electrode, the active layer is arranged on the top of the gate insulating layer, the source electrode and the drain electrode are arranged on the top of the active layer, a biased drain structure is arranged between the drain electrode and the bottom gate electrode, the drain electrode extends to the preparation area of ​​the nano cold cathode, the source electrode, the drain electrode and the drain electrode extension area are covered with a passivation layer, the passivation layer is etched with a through hole to expose the drain electrode, the cathode electrode is located on the top of the passivation layer, and the cathode electrode is connected to the drain electrode through the through hole, a growth film is arranged on the top of the cathode electrode, and the nano cold cathode array is integrated above the growth film; the high-voltage TFT also includes a top gate electrode arranged on the top of the passivation layer, and the top gate electrode extends to the preparation area of ​​the nano cold cathode; the active layer includes a plurality of parallel channels, and a gap is formed between adjacent channels.

[0010] The high-voltage TFT-driven addressable flat-panel X-ray source of the present invention, when working, applies high-voltage direct current or pulse voltage to the anode substrate, applies low-voltage direct current or pulse voltage to the bottom gate electrode and the top gate electrode, and the corresponding nano cold cathode electron source can realize electron emission and regulation under the drive of the high-voltage TFT; applying a positive bias voltage to the top gate electrode can effectively increase the saturation current of the high-voltage TFT and optimize the threshold voltage and subthreshold swing of the high-voltage TFT; at the same time, the active layer is split into a parallel structure of several narrow channels, and the gap between adjacent channels can enhance the heat dissipation effect, ensuring that the device will not have the problem of thermal breakdown, and the parallel channel structure makes the double-gate high-voltage TF While achieving high current, the voltage resistance of the T is restored to the same level as that of ordinary high-voltage TFTs of the same size, ensuring its voltage resistance performance, thereby meeting the requirements of the flat-panel X-ray source for high operating voltage and high operating current of the driving unit; by selectively applying voltage to the bottom gate electrode and the top gate electrode of the high-voltage TFT synchronously, the addressable emission of the cold cathode electron source can be driven at low voltage. At the same time, the top gate extends to the preparation area of ​​the nano cold cathode, and the top gate electrode is also the control gate of the nano cold cathode. By regulating the bias voltage of the top gate electrode, the operating current of the high-voltage TFT can achieve a larger regulation range, and a larger dose regulation range can be obtained in the addressable flat-panel X-ray source. The present invention forms a dual-gate structure and a channel parallel structure of the active layer by the bottom gate electrode and the top gate electrode together, and can realize an addressable flat-panel X-ray source with high voltage, large current, high resolution and accurate current regulation.

[0011] Furthermore, the addressable flat-panel X-ray source operates under vacuum packaging or dynamic vacuum.

[0012] Furthermore, the anode substrate further comprises an anode substrate and an anode protection layer, the metal film target layer is arranged on the anode substrate, and the anode protection layer covers the metal film target layer.

[0013] The present invention also provides a method for preparing a high-voltage TFT-driven addressable flat-panel X-ray source, comprising the following steps:

[0014] S51: manufacturing an addressable nano cold cathode electron source array substrate and an anode substrate, wherein the manufacturing of the addressable nano cold cathode electron source array substrate includes the following steps:

[0015] 1) Clean the cathode substrate;

[0016] 2) fabricating a bottom gate electrode on the cathode substrate;

[0017] 3) covering the bottom gate electrode with a gate insulating layer;

[0018] 4) forming an active layer on the gate insulating layer, wherein the active layer is split into a plurality of parallel channels with gaps between the channels;

[0019] 5) making a source electrode and a drain electrode above the active layer, extending the drain electrode to the nano cold cathode preparation area, and setting a bias drain structure between the drain electrode and the bottom gate electrode;

[0020] 6) Covering the source electrode, the drain electrode and the drain electrode extension region with a passivation layer, wherein a through hole is etched in the passivation layer to expose the drain electrode;

[0021] 7) manufacturing a top gate electrode and a cathode electrode above the passivation layer, wherein the top gate electrode extends to the nano cold cathode preparation area, and the cathode electrode is connected to the drain electrode through the through hole;

[0022] 8) locally forming a growth film on the cathode electrode;

[0023] 9) Reaction growth is performed on the growth film to obtain an array of nano cold cathodes;

[0024] The production of the anode substrate includes the following steps:

[0025] a) fabricating a metal thin film target layer on an anode substrate;

[0026] b) forming an anode protection layer on the metal film target layer;

[0027] S52: The anode substrate is parallel to and opposite to the addressable nano cold cathode electron source array substrate, and an insulating spacer is disposed between the anode substrate and the addressable nano cold cathode electron source array substrate.

[0028] The method for preparing an addressable flat-panel X-ray source driven by a high-voltage TFT of the present invention has a top gate electrode arranged on the top of a passivation layer, and the bottom gate electrode and the top gate electrode together form a dual-gate structure, which enhances the regulation effect on the gate-controlled channel of the high-voltage TFT, can effectively improve the threshold voltage and subthreshold swing of the high-voltage TFT, and increase the saturation current; however, due to the increase in the saturation current, the power of the high-voltage TFT will increase, and the heat generated by the device during operation will also increase, thereby causing premature thermal breakdown, and compared with ordinary high-voltage TFTs of the same size, its withstand voltage value decreases by about 50%, and the active layer is split into a parallel structure of several narrower channels, and the gap between adjacent channels can enhance the heat dissipation effect, and the parallel channel structure enables the dual-gate high-voltage TFT to achieve a large current while also restoring its withstand voltage to the same level as ordinary high-voltage TFTs of the same size; in addition, the top gate electrode extends to the preparation area of ​​the nano cold cathode, and the top gate electrode is also the control gate of the nano cold cathode, which can further increase the field emission current of the nano cold cathode. The present invention is suitable for low-voltage driving of a high-current emission cathode, and meets the requirements of a flat-panel X-ray source for a driving unit with high operating voltage and large operating current.

[0029] Preferably, each unit of the nano cold cathode array is driven by a separate high-voltage TFT, wherein the top gate electrode is also the control gate of the nano cold cathode, the length of the top gate electrode ranges from 1% to 99% of the channel length, and the top gate electrode is connected in parallel with the bottom gate electrode; or a voltage of -1kV to 1kV is independently applied to the top gate electrode.

[0030] Preferably, the width of the channel is in the range of 1 nm to 1 mm, the number of the channels is in the range of 2 to 1000, and the width of the gaps between the channels is in the range of 1 nm to 1 mm.

[0031] Preferably, the gate electrode, source electrode and drain electrode are in the shape of annular rings or circles with the centers coinciding, or the gate electrode, source electrode and drain electrode are in the shape of squares, and the length of the biased drain structure ranges from 1% to 99% of the channel length.

[0032] Preferably, the bottom gate electrode, source electrode, drain electrode and top gate electrode are made of a material having conductive properties and compatible with micromachining processes, including Mo, Cr, Al, Cu, Ti, ITO, IZO or AZO.

[0033] Preferably, the gate insulating layer and the passivation layer are made of a material having high resistance characteristics or a mixed material thereof, including silicon oxide, silicon nitride or aluminum oxide, wherein the thickness of the gate insulating layer is 0.1 to 1000 μm, and the thickness of the passivation layer is 0.1 to 1000 μm.

[0034] Preferably, the active layer includes a-IGZO, a-IZTO, a-Si or p-Si.

[0035] Compared with the background technology, the high-voltage TFT-driven cold cathode flat-panel X-ray source and the preparation method thereof of the present invention have the following beneficial effects:

[0036] Applying a positive bias voltage to the top gate electrode can effectively increase the saturation current of the high-voltage TFT and optimize the threshold voltage and subthreshold swing of the high-voltage TFT; at the same time, the active layer is split into a parallel structure of several narrower channels, and the gap between adjacent channels can enhance the heat dissipation effect to ensure that the device will not have the problem of thermal breakdown. The parallel channel structure enables the dual-gate high-voltage TFT to achieve large current while ensuring its voltage resistance, thereby meeting the requirements of the flat-panel X-ray source for the high operating voltage and large operating current of the driving unit; by selectively applying voltage to the bottom gate electrode and the top gate electrode of the high-voltage TFT synchronously, the addressable emission of the cold cathode electron source can be driven at a low voltage. At the same time, the top gate extends to the preparation area of ​​the nano cold cathode, and the top gate electrode is also the control gate of the nano cold cathode. By regulating the bias voltage of the top gate electrode, the operating current of the high-voltage TFT can achieve a larger regulation range, and a larger dose regulation range can be obtained in the addressable flat-panel X-ray source. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic structural diagram of an addressable flat-panel X-ray source driven by a high-voltage TFT in an embodiment of the present invention at a first viewing angle;

[0038] Figure 2 It is a schematic structural diagram of an addressable flat-panel X-ray source driven by a high-voltage TFT in an embodiment of the present invention at a second viewing angle;

[0039] Figure 3 This is a schematic structural diagram of the high-voltage TFT in the first embodiment at a first viewing angle;

[0040] Figure 4 A schematic diagram of the structure of the high-voltage TFT in the first embodiment at a second viewing angle

[0041] Figure 5 It is a partial schematic diagram of the addressable nano cold cathode electron source array substrate in the first embodiment;

[0042] Figure 6 It is a partial schematic diagram of the addressable nano cold cathode electron source array substrate in the second embodiment;

[0043] Figure 7 It is a schematic diagram of the structure of the high-voltage TFT in the second embodiment;

[0044] Figure 8 It is a partial enlarged view of the addressable nano cold cathode electron source array substrate in the second embodiment;

[0045] Fig. 9 It is a schematic structural diagram of the addressable nano cold cathode electron source array substrate in the second embodiment;

[0046] Fig.10 This is a flow chart of manufacturing the addressable nano cold cathode electron source array substrate in Example 3;

[0047] Fig.11 is a flow chart of manufacturing a high voltage TFT in Embodiment 4;

[0048] Fig.12 is a transfer characteristic diagram of the high voltage TFT in the fourth embodiment;

[0049] Fig.13 is a breakdown characteristic curve diagram of the high voltage TFT in Example 5;

[0050] Fig.14 is a transfer characteristic diagram of a high voltage TFT with a parallel channel structure and double gates in Example 6;

[0051] Fig.15 is a breakdown characteristic curve diagram of a high voltage TFT having a parallel channel structure in Example 6;

[0052] In the accompanying drawings: 1-cathode substrate; 2-bottom gate electrode; 3-gate insulating layer; 4-active layer; 5-source electrode; 6-drain electrode; 7-biased drain structure; 8-passivation layer; 9-top gate electrode; 10-channel; 11-cathode electrode; 12-grown film; 13-through hole; 14-nano cold cathode; 15-source electrode strip; 16-bottom gate electrode strip; 17-top gate electrode strip; 18-anode substrate; 19-metal film target layer; 20-anode protection layer; 21-insulating insulator. DETAILED DESCRIPTION

[0053] The present invention is further described below in conjunction with specific implementation methods. The accompanying drawings are only used for exemplary descriptions and are only schematic diagrams, not actual drawings, and cannot be understood as limiting this patent; in order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0054] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0055] Embodiment 1

[0056] A high voltage TFT driven addressable flat panel X-ray source, such as Figure 1 , Figure 2As shown, it includes an addressable nano cold cathode electron source array substrate and an anode substrate provided with a metal film target layer 19. The addressable nano cold cathode electron source array substrate is arranged parallel to the anode substrate, and an insulating spacer 21 is arranged between the cold cathode electron source array substrate and the anode substrate. Under the action of the high-voltage TFT, the cold cathode electron source array substrate emits focused electrons to bombard the metal film target layer 19 in the anode substrate to generate addressable X-rays; the addressable nano cold cathode electron source array substrate includes an array of nano cold cathodes 14 located on the same cathode substrate 1 as the high-voltage TFT and a cathode electrode 11; it is characterized in that the high-voltage TFT includes a bottom gate electrode 2, a gate insulating layer 3, an active layer 4, a source electrode 5, a drain electrode 6, a passivation layer 8 and a top gate electrode 9, the bottom gate electrode 2 is located on the top of the cathode substrate 1, the gate insulating layer 3 covers the bottom gate electrode 2, and the The source layer 4 is arranged on the top of the gate insulating layer 3, the active layer 4 includes a plurality of parallel channels 10, and a gap is formed between adjacent channels 10. The source electrode 5 and the drain electrode 6 are arranged on the top of the active layer 4, and a biased drain structure 7 is provided between the drain electrode 6 and the bottom gate electrode 2, and the drain electrode 6 extends to the preparation area of ​​the nano cold cathode 14. The source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6 are covered with a passivation layer 8, and the passivation layer 8 is etched with a through hole 13 to expose the drain electrode 6. A top gate electrode 9 is provided on the top of the passivation layer 8, and the top gate electrode 9 extends to the preparation area of ​​the nano cold cathode 14. The cathode electrode 11 is located on the top of the passivation layer 8, and the cathode electrode 11 is connected to the drain electrode 6 through the through hole 13. A growth film 12 is provided on the top of the cathode electrode 11, and the array of the nano cold cathode 14 is integrated above the growth film 12.

[0057] The above-mentioned addressable flat-panel X-ray source driven by high-voltage TFT includes an anode substrate and an addressable nano cold cathode electron source array substrate. An insulating spacer 21 is used to maintain a certain distance between the anode substrate and the addressable nano cold cathode electron source array substrate. When a high-voltage DC or pulse voltage is applied to the anode substrate, and a low-voltage DC or pulse voltage is applied to the bottom gate electrode 2 and the top gate electrode 9, the corresponding nano cold cathode electron source will realize electron emission and regulation under the drive of the high-voltage TFT; applying a positive bias voltage to the top gate electrode 9 can effectively increase the saturation current of the high-voltage TFT and optimize the threshold voltage and subthreshold swing of the high-voltage TFT; at the same time, the active layer 4 is split into a parallel structure of several narrower channels 10, and the adjacent channels 10 are connected. The gap between the two electrodes can enhance the heat dissipation effect and ensure that the device will not have the problem of thermal breakdown. The parallel channel 10 structure enables the dual-gate high-voltage TFT to achieve a large current while ensuring its withstand voltage performance, thereby meeting the requirements of the flat-panel X-ray source for the high operating voltage and large operating current of the driving unit; by selectively applying voltage to the bottom gate electrode 2 and the top gate electrode 9 of the high-voltage TFT synchronously, the addressable emission of the cold cathode electron source can be driven at a low voltage. At the same time, the top gate extends to the preparation area of ​​the nano cold cathode 14, and the top gate electrode 9 is also the control gate of the nano cold cathode 14. By regulating the bias voltage of the top gate electrode 9, the operating current of the high-voltage TFT can achieve a larger regulation range, and a larger dose regulation range can be obtained in the addressable flat-panel X-ray source. In this embodiment, the bottom gate electrode 2 and the top gate electrode 9 form a dual-gate structure and a parallel structure of the channel 10 of the active layer 4, so that an addressable flat-panel X-ray source with high voltage, large current, high resolution and accurate current control can be realized.

[0058] The addressable flat-panel X-ray source works under vacuum packaging or dynamic vacuum. Dynamic vacuum means there is no packaging and it runs in a vacuum chamber, which requires a vacuum pump to maintain the vacuum of the operating environment. Vacuum packaging uses vacuum separation to package the device to form a portable device, which does not require a vacuum pump to maintain the vacuum. Each unit of the nano cold cathode 14 array is driven by a separate high-voltage TFT. In the entire addressable cold cathode flat-panel X-ray source, each unit has a separate high-voltage TFT control, so each unit can be controlled individually to achieve addressable function, while making the driving process more efficient and stable.

[0059] like Figure 1 , Figure 2As shown, the anode substrate also includes an anode substrate 18 and an anode protection layer 20, a metal film target layer 19 is arranged on the anode substrate 18, and the anode protection layer 20 covers the metal film target layer 19. The anode substrate 18 can be a glass substrate, the metal film target layer 19 is a metal film of one or any combination of tungsten, molybdenum, rhodium, silver, copper, gold, chromium, aluminum, niobium, tantalum, and rhenium, and the anode protection layer 20 is an aluminum film or an alloy film resistant to high-temperature oxidation, which is used to protect the metal film target layer 19 from being oxidized during the high-temperature packaging process.

[0060] The bottom gate electrode 2 and the source electrode 5 are annular, the drain electrode 6 is circular, and the centers of the bottom gate electrode 2, the source electrode 5 and the drain electrode 6 coincide with each other. There is a bias drain structure 7 between the bottom gate electrode 2 and the drain electrode 6, as shown in FIG. Figures 3 to 5 As shown, the nano cold cathode 14 is vertically integrated just above the high-voltage TFT, the cathode electrode 11 connects the nano cold cathode 14 to the drain electrode 6 through the through hole 13, and there is a top gate electrode 9 on the top of the passivation layer 8, which is also the control gate of the nano cold cathode 14.

[0061] Embodiment 2

[0062] This embodiment is similar to the first embodiment, except that Figures 6 to 9 As shown, the bottom gate electrode 2, the source electrode 5 and the drain electrode 6 are in a square shape, there is a bias drain structure 7 between the bottom gate electrode 2 and the drain electrode 6, the nano cold cathode 14 is vertically integrated above the drain electrode 6 or in an extended area of ​​the drain electrode 6, the cathode electrode 11 connects the nano cold cathode 14 to the drain electrode 6 through a through hole 13, there is a top gate electrode 9 on the top of the passivation layer 8, and it is also the control gate of the nano cold cathode 14. Since the nano cold cathode 14 is driven by a high-voltage TFT, under a constant anode voltage, the voltages of the bottom gate electrode 2 and the top gate electrode 9 of the high-voltage TFT are regulated to achieve addressable regulation of the nano cold cathode 14.

[0063] like Fig. 9 As shown, the source electrode strip 15 connects the source electrodes 5 of all high-voltage TFTs in the same column, and the bottom gate electrode strip 16 connects the bottom gate electrodes 2 of all high-voltage TFTs in the same row, so that a pulse voltage can be applied to the bottom gate electrode strip 16 to achieve addressability of the nano cold cathode 14 array, and the top gate electrode strip 17 connects the top gate electrodes 9 of all high-voltage TFTs in the same row.

[0064] Embodiment 3

[0065] This embodiment is a method for preparing an addressable flat-panel X-ray source driven by a high-voltage TFT, including the preparation of an addressable nano cold cathode electron source array substrate and an anode substrate, wherein: Fig.10 As shown, the preparation of the addressable nano cold cathode electron source array substrate includes the following steps:

[0066] First, the cathode substrate 1 is cleaned;

[0067] A bottom gate electrode 2 is fabricated on the cathode substrate 1. The bottom gate electrode 2 may be made of a material having conductive properties and compatible with micromachining processes, such as Mo, Cr, Al, Ti, Cu, ITO, IZO, and AZO. The bottom gate electrode 2 may be fabricated by electron beam evaporation, sputtering, and chemical vapor deposition.

[0068] The bottom gate electrode 2 is covered with a gate insulating layer 3, which is made of silicon oxide, silicon nitride, aluminum oxide or other materials with high resistance characteristics and their mixed materials by electron beam evaporation, sputtering and chemical vapor deposition, and the thickness of the gate insulating layer 3 is 0.1-1000 μm;

[0069] An active layer 4 is formed on the gate insulating layer 3. The active layer 4 is formed by connecting a plurality of narrow channels 10 in parallel, and gaps are left between adjacent channels 10. The active layer 4 includes semiconductor materials such as a-IGZO, a-IZTO, a-Si or p-Si, and can be prepared by sputtering and chemical vapor deposition, and a patterned active layer 4 is obtained by a local etching method. The method for etching the active layer 4 can be wet etching, reactive ion etching, etc. The width of the channel 10 ranges from 1nm to 1mm, the number of the channels 10 ranges from 2 to 1000, and the width of the gaps between the channels 10 ranges from 1nm to 1mm;

[0070] A source electrode 5 and a drain electrode 6 are fabricated on the active layer 4, and a biased drain structure 7 is disposed between the drain electrode 6 and the bottom gate electrode 2. The source electrode 5 and the drain electrode 6 can be made of materials such as Mo, Cr, Al, Ti, Cu, ITO, IZO and AZO that have conductive properties and are compatible with micro-machining processes by electron beam evaporation, sputtering and chemical vapor deposition. At the same time, the drain electrode 6 extends to the preparation area of ​​the nano cold cathode 14; the length of the biased drain structure 7 ranges from 1 to 99% of the length of the channel 10;

[0071] A passivation layer 8 is covered on the source electrode 5, the drain electrode 6 and the extended region of the drain electrode 6. The passivation layer 8 is made of silicon oxide, silicon nitride, aluminum oxide or other materials with high resistance characteristics and mixed materials thereof by electron beam evaporation, sputtering and chemical vapor deposition. The thickness of the passivation layer 88 is 0.1 to 1000 μm.

[0072] Etching the passivation layer 8 locally by wet etching, reactive ion etching or other etching methods on the passivation layer 8 to obtain a through hole 13;

[0073] A top gate electrode 9 and a cathode electrode 11 are formed on the passivation layer 8. The cathode electrode 11 is connected to the drain electrode 6 through a through hole 13. The material of the cathode electrode 11 is one of materials with good conductivity such as ITO, IZO, AZO, etc., which have good high temperature oxidation resistance.

[0074] Photolithography is performed to locate the growth area of ​​the nano cold cathode 14 on the cathode electrode 11, and then the growth film 12 is produced by electron beam evaporation, sputtering, chemical vapor deposition and stripping techniques; the stripping technique is used to obtain an array of the growth film 12;

[0075] The addressable nano cold cathode 14 electron source array substrate is heated to 200°C to 650°C in an oxygen-containing atmosphere and kept warm for 30 minutes to 12 hours. Finally, it is cooled naturally to react and grow on the array of the growth film 12 to obtain an array of nano cold cathodes 14, wherein the nano cold cathode 14 array is made of one-dimensional nano materials ZnO, WOx, CNTs or two-dimensional nano cold cathode film materials graphene, diamond film.

[0076] The production of the anode substrate includes the following steps:

[0077] A metal film target layer 19 is made on the anode substrate 18 using one or any combination of tungsten, molybdenum, rhodium, silver, copper, gold, chromium, aluminum, niobium, tantalum, and rhenium. The thickness of the metal film target layer 19 is 0.1 μm to 1500 μm.

[0078] An anode protection layer 20 is made on the metal film target layer 19. The anode protection layer 20 is an aluminum film or an alloy film resistant to high temperature oxidation, and has a thickness of 20 nm to 500 nm.

[0079] The anode substrate and the addressable nano cold cathode electron source array substrate are arranged parallel to each other, and the insulating spacer 21 is arranged between the anode substrate and the addressable nano cold cathode electron source array substrate. The insulating spacer 21 is glass, quartz, ceramic or insulating plastic with a thickness of 0.1mm to 500mm.

[0080] It should be noted that the actual manufacturing process is not limited to the above embodiment, and other similar micro-machining methods can be used to realize the device structure, and other similar growth means can be used to realize the growth of the array of nano cold cathodes 14.

[0081] Embodiment 4

[0082] This embodiment provides a process for manufacturing a high-voltage TFT in which the bottom gate electrode 2, the source electrode 5 and the drain electrode 6 are in the shape of a square. Fig.11 shown.

[0083] First, a glass substrate is ultrasonically cleaned with acetone, ethanol and deionized water for 20 minutes respectively, and the glass substrate is blown dry with nitrogen; on the glass substrate, a bottom gate electrode 2 is prepared by DC magnetron sputtering vacuum coating technology, photolithography and wet etching, and the material of the bottom gate electrode 2 is molybdenum with a thickness of 200nm; a gate insulating layer 3 is deposited on the bottom gate electrode 2 by plasma enhanced chemical vapor deposition method, and the gate insulating layer 3 is a silicon dioxide film with a thickness of 300nm; an active layer 4 is prepared on the gate insulating layer 3 by radio frequency magnetron sputtering vacuum coating technology, photolithography and wet etching, and the active layer 4 is composed of 10 channels 10 with a width of 10μm connected in parallel, the gap between adjacent channels 10 is 5μm, and the material of the active layer 4 is a-IGZ O, with a thickness of 50nm; on the active layer 4, molybdenum is used as the material, and the DC magnetron sputtering vacuum coating technology, photolithography and wet etching are used to prepare the source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6, with a thickness of 200nm; a passivation layer 8 is deposited on the source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6 by plasma enhanced chemical vapor deposition, and the passivation layer 8 is a silicon dioxide film with a thickness of 300nm; the silicon dioxide is etched by reactive ion etching technology to obtain a through hole 13; on the passivation layer 8, molybdenum is used as the material, and the DC magnetron sputtering vacuum coating technology, photolithography and wet etching are used to prepare the top gate electrode 9 with a thickness of 200nm, and finally annealing in a nitrogen atmosphere at 350°C for 1h to complete the preparation of the device.

[0084] The electrical characteristics of the dual-gate high-voltage TFT are tested using a high-voltage TFT test system. Fig.12 As shown in the figure, compared with ordinary high-voltage TFTs, the threshold voltage of dual-gate high-voltage TFTs is closer to 0V, the subthreshold swing is reduced from 0.9V / dec to 0.4V / dec, and the on-state current is increased by 2 to 3 times. At the same time, the breakdown test results are shown in Fig.13 As shown, due to the increase in the current of the dual-gate high-voltage TFT, the heat generation of the device increases, resulting in premature thermal breakdown of the device. Compared with ordinary high-voltage TFTs, the breakdown voltage of the dual-gate high-voltage TFT is reduced by about 50%; when the active layer 4 is split into a parallel structure of several channels 10, as shown Fig.14 , 15 As shown, the parallel connection of the channels 10 of the active layer 4 will not affect the threshold voltage, subthreshold swing and on-state current of the dual-gate high-voltage TFT, and can restore the breakdown voltage of the dual-gate high-voltage TFT to the same level as that of a common high-voltage TFT of the same size. Therefore, by forming a dual-gate structure together with the bottom gate electrode 2 and the top gate electrode 9 and the parallel connection structure of the channels 10 of the active layer 4, the operating current of the device can be further increased while maintaining the withstand voltage performance, meeting the requirements of the addressable flat-panel X-ray source for high voltage and high current of the active drive device.

[0085] Embodiment 5

[0086] This embodiment provides a method for preparing a high-voltage TFT-driven addressable flat-panel X-ray source using zinc oxide nanowires as a cold cathode material.

[0087] First, a glass substrate is ultrasonically cleaned with acetone, ethanol and deionized water for 20 minutes respectively, and the glass substrate is blown dry with nitrogen; on the glass substrate, a bottom gate electrode 2 is prepared by DC magnetron sputtering vacuum coating technology, photolithography and wet etching, and the material of the bottom gate electrode 2 is molybdenum with a thickness of 200nm; a gate insulating layer 3 is deposited on the bottom gate electrode 2 by a plasma enhanced chemical vapor deposition method, and the gate insulating layer 3 is a silicon dioxide film with a thickness of 300nm; an active layer 4 is prepared on the gate insulating layer 3 by radio frequency magnetron sputtering vacuum coating technology, photolithography and wet etching, and the active layer 4 is Ten channels 10 with a width of 10 μm are connected in parallel, and the gap between adjacent channels 10 is 5 μm. The material of the active layer 4 is a-IGZO with a thickness of 50 nm. Molybdenum is used as the material above the active layer 4, and the source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6 are prepared by DC magnetron sputtering vacuum coating technology, photolithography and wet etching, with a thickness of 200 nm. A passivation layer 8 is deposited on the source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6 by plasma enhanced chemical vapor deposition. The passivation layer 8 is a silicon dioxide film with a thickness of 300 nm. Reaction is used to form a passivation layer 8 on the source electrode 5, the drain electrode 6 and the extended area of ​​the drain electrode 6. The silicon dioxide is etched by ion etching technology to obtain a through hole 13; on the passivation layer 8, molybdenum is used as the material, and a top gate electrode 9 with a thickness of 200nm is prepared by DC magnetron sputtering vacuum coating technology, photolithography and wet etching. The top gate electrode 9 and the cathode electrode 11 are prepared by photolithography, DC magnetron sputtering vacuum coating technology and stripping process; during the preparation and deposition process of the cathode electrode 11, the cathode electrode 11 will also be deposited on the opening edge and inner wall of the through hole 13 on the passivation layer 8 and the extended area of ​​the local high-voltage TFT drain electrode 6 exposed at the bottom of the through hole 13, so that the cathode electrode 11 can be well connected with the high-voltage TF The drain electrode 6 of T is connected, the cathode electrode 11 is made of ITO with a thickness of 300nm; the growth area of ​​the nano cold cathode 14 is positioned by photolithography on the cathode electrode 11, and the growth film 12 is plated by electron beam evaporation vacuum coating technology. The growth film 12 is a zinc film, and an array of the growth zinc film is obtained by a stripping method; finally, the glass substrate with the above-mentioned thin film structure is placed in a tubular furnace for oxidation to obtain a zinc oxide nanowire cold cathode electron source array, and the thermal oxidation process first increases from room temperature to 470°C, then keeps warm at 470°C for 2h, and finally cools naturally. The above-mentioned entire oxidation process is carried out in air.

[0088] The preparation method of the anode substrate is as follows: the glass substrate is ultrasonically cleaned with acetone, ethanol and deionized water for 20 minutes respectively, and then blown dry with nitrogen. On the glass substrate, a metal film target layer 19 is prepared by DC magnetron sputtering vacuum coating technology. The metal target layer material is tungsten and has a thickness of 500nm; then the anode protection layer 20 is prepared by DC magnetron sputtering vacuum coating technology; the anode protection layer 20 material is aluminum and has a thickness of 100nm. The insulating insulator 21 is a ceramic insulator with a thickness of 1mm. Under a constant anode voltage, a pulse voltage is applied to the bottom gate electrode 2 and the top gate electrode 9 of the high-voltage TFT so that the array of nano cold cathodes 14 emits focused electrons to bombard the metal film target layer 19, thereby realizing a large current, high-resolution addressable flat-panel X-ray source that emits X-rays.

[0089] In the specific contents of the above-mentioned specific implementation methods, the various technical features can be combined in any non-contradictory manner. In order to make the description concise, not all possible combinations of the above-mentioned technical features are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. An addressable flat-panel X-ray source driven by a high-voltage TFT, comprising an addressable nano cold cathode electron source array substrate and an anode substrate provided with a metal film target layer (19), wherein the addressable nano cold cathode electron source array substrate and the anode substrate are arranged parallel to each other, and an insulating spacer (21) is arranged between the cold cathode electron source array substrate and the anode substrate, and the cold cathode electron source array substrate emits focused electrons under the action of the high-voltage TFT to bombard the metal film target layer (19) in the anode substrate, thereby generating addressable X-rays; the addressable nano cold cathode electron source array substrate comprises an array of nano cold cathodes (14) located on the same cathode substrate (1) as the high-voltage TFT and a cathode electrode (11); the high-voltage TFT comprises a bottom gate electrode (2), a gate insulating layer (3), an active layer (4), a source electrode (5), a drain electrode (6) and a passivation layer (8), wherein the bottom gate electrode (2) is located on the top of the cathode substrate (1), The gate insulating layer (3) covers the bottom gate electrode (2); the active layer (4) is arranged on the top of the gate insulating layer (3); the source electrode (5) and the drain electrode (6) are arranged on the top of the active layer (4); a bias drain structure (7) is provided between the drain electrode (6) and the bottom gate electrode (2); the drain electrode (6) extends to the preparation area of ​​the nano cold cathode (14); the source electrode (5), the drain electrode (6) and the extension area of ​​the drain electrode (6) are covered with a passivation layer (8); a through hole (13) is etched in the passivation layer (8) to expose the drain electrode (6); the cathode electrode (11) is located on the top of the passivation layer (8); and the cathode electrode (11) is connected to the drain electrode (6) through the through hole (13); a growth film (12) is provided on the top of the cathode electrode (11); and an array of the nano cold cathodes (14) is integrated above the growth film (12); characterized in that: The high-voltage TFT further comprises a top gate electrode (9) disposed on the top of the passivation layer (8), the top gate electrode (9) extending to the preparation area of ​​the nano cold cathode (14), the active layer (4) comprising a plurality of parallel channels (10), a gap being formed between adjacent channels (10); and the length of the bias drain structure (7) ranges from 1% to 99% of the length of the channel (10).

2. The high voltage TFT driven addressable flat panel X-ray source according to claim 1, characterized in that: The addressable flat panel X-ray source operates under vacuum packaging or dynamic vacuum.

3. The high voltage TFT driven addressable flat panel X-ray source according to claim 1, characterized in that: The anode substrate further comprises an anode substrate (18) and an anode protection layer (20); the metal film target layer (19) is arranged on the anode substrate (18); and the anode protection layer (20) covers the metal film target layer (19).

4. A method for preparing a high-voltage TFT-driven addressable flat-panel X-ray source, characterized in that: The following steps are involved: S41: manufacturing an addressable nano cold cathode electron source array substrate and an anode substrate, wherein the manufacturing of the addressable nano cold cathode electron source array substrate includes the following steps: 1) Cleaning the cathode substrate (1); 2) manufacturing a bottom gate electrode (2) on the cathode substrate (1); 3) covering the bottom gate electrode (2) with a gate insulating layer (3); 4) forming an active layer (4) on the gate insulating layer (3), wherein the active layer (4) is split into a plurality of parallel channels (10), with gaps being left between the channels (10); 5) forming a source electrode (5) and a drain electrode (6) above the active layer (4), so that the drain electrode (6) extends to the preparation area of ​​the nano cold cathode (14), and providing a bias drain structure (7) between the drain electrode (6) and the bottom gate electrode (2); the length of the bias drain structure (7) ranges from 1% to 99% of the length of the channel (10); 6) covering the source electrode (5), the drain electrode (6) and the extended region of the drain electrode (6) with a passivation layer (8), wherein a through hole (13) is etched in the passivation layer (8) to expose the drain electrode (6); 7) manufacturing a top gate electrode (9) and a cathode electrode (11) above the passivation layer (8), wherein the top gate electrode (9) extends to a region where a nano cold cathode (14) is prepared, and the cathode electrode (11) is connected to the drain electrode (6) through the through hole (13); 8) locally forming a growth film (12) on the cathode electrode (11); 9) Reaction growth is performed on the growth film (12) to obtain an array of nano cold cathodes (14); The production of the anode substrate includes the following steps: a) forming a metal thin film target layer (19) on an anode substrate (18); b) forming an anode protection layer (20) on the metal thin film target layer (19); S42: The anode substrate and the addressable nano cold cathode electron source array substrate are parallel and opposite to each other, and an insulating spacer (21) is arranged between the anode substrate and the addressable nano cold cathode electron source array substrate.

5. The method for preparing a high voltage TFT driven addressable flat panel X-ray source according to claim 4, characterized in that: Each unit of the nano cold cathode (14) array is driven by a separate high-voltage TFT, wherein the top gate electrode (9) is also the control gate of the nano cold cathode (14), the length of the top gate electrode (9) ranges from 1% to 99% of the length of the channel (10), and the top gate electrode (9) is connected in parallel with the bottom gate electrode (2); or a voltage of -1 kV to 1 kV is independently applied to the top gate electrode (9).

6. The method for preparing a high voltage TFT driven addressable flat panel X-ray source according to claim 4, characterized in that: The width of the channel (10) ranges from 1 nm to 1 mm, the number of the channels (10) ranges from 2 to 1000, and the width of the gaps between the channels (10) ranges from 1 nm to 1 mm.

7. The method for preparing a high voltage TFT driven addressable flat panel X-ray source according to claim 4, characterized in that: The bottom gate electrode (2), the source electrode (5), the drain electrode (6), and the top gate electrode (9) are made of materials having conductive properties and compatible with micromachining processes, including Mo, Cr, Al, Cu, Ti, ITO, IZO, or AZO.

8. The method for preparing a high voltage TFT driven addressable flat panel X-ray source according to claim 4, characterized in that: The gate insulating layer (3) and the passivation layer (8) are made of a material having high resistance characteristics or a mixed material thereof, including silicon oxide, silicon nitride or aluminum oxide, wherein the thickness of the gate insulating layer (3) is 0.1 to 1000 μm, and the thickness of the passivation layer (8) is 0.1 to 1000 μm.

9. The method for preparing a high voltage TFT driven addressable flat panel X-ray source according to any one of claims 4 to 8, characterized in that: The active layer (4) comprises a-IGZO, a-IZTO, a-Si or p-Si.

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