Display panel and display device

Abstract

The present application discloses a display panel and a display device, comprising common lines, wherein a plurality of data lines and a plurality of scan lines are crisscrossed to form a plurality of pixel areas, and a sub-common line is arranged corresponding to each pixel area; wherein, there are m data lines and n scan lines; each of the horizontal routing lines is arranged to cross the data lines to connect two adjacent sub-common lines in the direction of the scan lines; among the plurality of vertical routing lines, each of the vertical routing lines is arranged to cross the scan lines to connect two adjacent sub-common lines in the direction of the data lines; the number of the horizontal routing lines is less than or equal to m; the number of the vertical routing lines is less than or equal to n-1; the plurality of horizontal routing lines and the vertical routing lines connect all the sub-common lines to form the common lines, and the delay of the data lines and the scan lines is reduced by reducing the number of the horizontal routing lines and the vertical routing lines.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] TFT-LCD (Thin Film Transisitor Liquid Crystal Display) is a thin film field effect transistor LCD, which is a type of active matrix liquid crystal display. It has excellent performance, good large-scale production characteristics, high degree of automation, low raw material cost, and broad development space. It has become the mainstream product in the new century.

[0003] For TFT-LCD, the scan lines and data lines control the charging of pixels through thin film transistors. When charging, the load size of the data lines and scan lines has a decisive influence on the charging efficiency of the pixels, and determines whether the pixels are sufficiently charged. However, due to parasitic capacitance and resistance, the data lines and scan lines have a large load, which affects the charging effect. Therefore, there is a problem of insufficient pixel charging. Summary of the invention

[0004] The purpose of the present application is to provide a display panel and a display device, which reduce the load of data lines and scan lines and improve the problem of insufficient pixel charging.

[0005] The present application discloses a display panel, comprising a plurality of data lines, a plurality of scan lines and a common line, wherein the common line comprises a plurality of sub-common lines; the plurality of data lines and the plurality of scan lines are crisscrossed to form a plurality of pixel areas, and each of the pixel areas is correspondingly provided with a sub-common line; wherein there are m data lines and n scan lines; the common line further comprises: a plurality of horizontal routing lines and a plurality of vertical routing lines, each of the horizontal routing lines is correspondingly arranged to cross with the data line, connecting two adjacent sub-common lines along the scan line direction; among the plurality of vertical routing lines, each of the vertical routing lines is correspondingly arranged to cross with the scan line, connecting two adjacent sub-common lines along the data line direction; the number of the horizontal routing lines is less than or equal to m; the number of the vertical routing lines is less than or equal to n-1; the plurality of horizontal routing lines and the vertical routing lines connect all the sub-common lines to form the common line, and the common line receives a common voltage signal.

[0006] Optionally, the number of the horizontal lines along a scan line direction is m / 2, and the number of the vertical lines along a data line direction is n / 2; one horizontal line is provided for every data line, and one vertical line is provided for every scan line.

[0007] Optionally, there are m pixel areas along the direction of a scan line, and n pixel areas along the direction of a data line, forming a matrix of n rows and m columns of pixel areas; wherein, in the pixel areas along the odd rows, the m / 2 horizontal lines correspond to the data lines of the odd columns respectively; in the pixel areas along the even rows, the m / 2 horizontal lines correspond to the data lines of the even columns respectively; in the pixel areas of the odd columns, the m / 2 vertical lines correspond to the scan lines of the odd rows respectively; and in the pixel areas along the data lines of the even columns, the m / 2 horizontal lines correspond to the scan lines of the even rows respectively.

[0008] Optionally, in the pixel areas of each column, a continuous number of x pixel areas are formed into a pixel area group; the x sub-common lines in a pixel area group are connected by x-1 vertical lines; a horizontal line is arranged between each of the adjacent pixel area groups along the scan line direction to connect the sub-common lines corresponding to the pixel area groups arranged along the scan line direction; the pixel areas of each column are divided into n / x pixel area groups, x is a natural number greater than or equal to 2 and less than or equal to n, and n / x is an integer.

[0009] Optionally, the display area includes multiple pixels, and the pixels include vertically arranged red sub-pixels, green sub-pixels and blue sub-pixels; m pixel regions are arranged along the scan line direction, and n pixel regions are arranged along the data line direction, forming an n-row and m-column pixel region matrix; m / 3 pixels are arranged along the data line direction, and n pixels are arranged along the scan line direction, and one red sub-pixel, green sub-pixel or blue sub-pixel is arranged in each pixel region; the value of x is 3, and each pixel region group includes vertically arranged red sub-pixels, green sub-pixels and blue sub-pixels; one vertical wiring is arranged between the red sub-pixel and the green sub-pixel, and one vertical wiring is arranged between the green sub-pixel and the blue sub-pixel, so as to connect the three sub-common lines in the pixel region group.

[0010] Optionally, the pixel area in the 3y-2th row is provided with m horizontal wirings, which are respectively arranged between the pixel area groups adjacent to each other along the scanning line direction, so as to connect the sub-common lines corresponding to the pixel area groups arranged along the scanning line direction, where 3y≤m, and y is a natural number greater than zero.

[0011] Optionally, each of the sub-common lines includes a first sub-common line segment and a third sub-common line segment parallel to the scan line, and a second sub-common line segment and a fourth sub-common line segment parallel to the data line. The first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are connected end to end in sequence and are arranged around the pixel area; the horizontal line connects the third sub-common line segment of a sub-common line with the first sub-common line segment of another adjacent sub-common line segment; the vertical line connects the second sub-common line segment of a sub-common line with the fourth sub-common line segment of another adjacent sub-common line segment.

[0012] Optionally, the display panel includes a first metal layer, a second metal layer and a transparent electrode layer arranged in sequence from bottom to top; the scan line and the common line are formed in the first metal layer; the data line is formed in the second metal layer; the pixel electrode is formed in the transparent electrode layer; the pixel electrode and the common line form a storage capacitor; the horizontal line is formed in the first metal layer; the vertical line is formed in the transparent electrode layer; the vertical line connects two adjacent sub-common lines through a via.

[0013] The present application also discloses a display panel, including a display area and a non-display area, wherein the display area is provided with: m data lines, n scan lines and common lines; the m data lines and the n scan lines are crisscrossed to form a plurality of pixel areas; the common lines receive common voltage signals;

[0014] The common line includes: a plurality of sub-common lines, a plurality of horizontal lines and a plurality of vertical lines; each pixel region is provided with a sub-common line; each of the horizontal lines is provided to cross the data line to connect two adjacent sub-common lines in the direction of the scan line; each of the vertical lines is provided to cross the scan line to connect two adjacent sub-common lines in the direction of the data line, and the plurality of horizontal lines and vertical lines connect all the sub-common lines to form the common line;

[0015] Wherein, each of the sub-common lines comprises a first sub-common line segment and a third sub-common line segment parallel to the data line, and a second sub-common line segment and a fourth sub-common line segment parallel to the scan line, and the first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are connected end to end and arranged around the pixel area; the horizontal line connects the third sub-common line segment of a sub-common line with the first sub-common line segment of another adjacent sub-common line segment; the vertical line connects the second sub-common line segment of a sub-common line with the fourth sub-common line segment of another adjacent sub-common line segment;

[0016] The number of the horizontal lines along the direction of one of the scan lines is m / 2, and the number of the vertical lines along the direction of one of the data lines is n / 2; one horizontal line is provided for every data line, and one vertical line is provided for every scan line; the number of the horizontal lines along the direction of one of the data lines is n / 2, and the number of the vertical lines along the direction of one of the scan lines is m / 2; one horizontal line is provided for every two scan lines, and one vertical line is provided for every two data lines;

[0017] The display panel includes a first metal layer, a second metal layer and a transparent electrode layer which are arranged in sequence from bottom to top; the scan line and the common line are formed in the first metal layer; the data line is formed in the second metal layer; the pixel electrode is formed in the transparent electrode layer; the pixel electrode and the common line form a storage capacitor; the horizontal wiring is formed in the first metal layer; the vertical wiring is formed in the transparent electrode layer; the vertical wiring connects two adjacent sub-common lines through a via hole.

[0018] The present application also discloses a display device, comprising the above-mentioned display panel and a driving circuit for driving the display panel.

[0019] Compared with the conventional technical solution of setting up a complete grid-like common line (the sub-common lines in two adjacent pixel areas are connected by horizontal lines or vertical lines), the present application reduces the number of horizontal lines and vertical lines, thereby reducing the parasitic capacitance generated between the horizontal lines and the data lines, thereby reducing the load (loading) of the data lines, and can reduce the parasitic capacitance generated between the vertical lines and the scanning lines, thereby reducing the load (loading) of the scanning lines; that is, by reducing the overlapping area between the common lines and the data lines or the scanning lines, the effect of reducing the parasitic capacitance is achieved, thereby reducing the load of the data lines and / or the scanning lines, thereby improving the pixel charging efficiency and improving the problem of insufficient pixel charging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0021] Figure 1 is a schematic diagram of a display panel according to an embodiment of the present application;

[0022] Figure 2is a schematic diagram of a display device according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a sub-common line of an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a sub-common line of another embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a sub-common line of another embodiment of the present application;

[0026] Figure 6 is a schematic diagram of a sub-common line of another embodiment of the present application;

[0027] Figure 7 It is a schematic diagram of a sub-common line of another embodiment of the present application.

[0028] Among them, 10, display device; 100, display panel; 101, display area; 102, non-display area; 103, first metal layer; 104, second metal layer; 105, transparent electrode layer; 110, data line; 120, scan line; 130, common line; 131, sub-common line; 132, horizontal wiring; 133, vertical wiring; 134, first sub-common line segment; 135, second sub-common line segment; 136, third sub-common line segment; 137, fourth sub-common line segment; 140, pixel area; 150, pixel area group; 160, pixel; 161, red sub-pixel; 162, green sub-pixel; 163, blue sub-pixel; 200, driving circuit. DETAILED DESCRIPTION

[0029] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0030] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.

[0031] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present application.

[0032] In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0034] like Figure 1 As shown, Figure 1 The RGB pixels are arranged vertically, which is a three-gate architecture, that is, the number of gate scanning lines 120 becomes three times of the original number, and the number of data lines 110 becomes one-third of the original number. Because the number of data lines is reduced, the number of source driver chips can be reduced to one-third of the original design architecture, the number of source driver chips is reduced, and the number of gate driver chips is increased. However, the source driver chip is much more complex than the gate driver chip and is very expensive. Therefore, reducing the number of source driver chips can greatly reduce the cost. However, the vertical arrangement of RGB will result in the charging time of each row being only one-third of the original panel, which is easy to cause insufficient charging. Therefore, the present application discloses a method such as Figure 1The display panel 100 shown in the figure comprises a plurality of data lines 110, a plurality of scan lines 120 and a common line 130, wherein the common line 130 comprises a plurality of sub-common lines 131; the plurality of data lines 110 and the plurality of scan lines 120 are crisscrossed to form a plurality of pixel regions 140, and each pixel region 140 is provided with a corresponding sub-common line 131; wherein the number of data lines 110 is m, the number of scan lines 120 is n; the common line 130 further comprises a plurality of horizontal wirings 132, each of which is A horizontal line 132 is arranged to cross the data line 110, connecting two adjacent sub-common lines 131 along the direction of the scan line 120; a plurality of vertical lines 133, each of which is arranged to cross the scan line 120, connecting two adjacent sub-common lines 131 along the direction of the data line; the plurality of horizontal lines 132 and the vertical lines connect all the sub-common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal; Figure 1 Each sub-common line 131 is connected to two horizontal lines 132 and a vertical line 133, and all the sub-common lines 131 are connected, thereby increasing the area of ​​the common line 130, and then reducing the resistance of the common line 130, so that the loss of the common line 130 of the display panel 100 with a three-gate structure is reduced; however, there will be parasitic capacitance between too many horizontal lines 132 and vertical lines 133 and the data line 110 and the scan line 120, resulting in an increase in the load of the data line 110. In this regard, the applicant has disclosed the following solutions.

[0035] like Figure 2 and Figure 3The present application discloses a display device 10, comprising a driving circuit 200 and a display panel 100, wherein the display panel 100 comprises a display area 101 and a non-display area 102; a plurality of data lines 110, a plurality of scan lines 120 and a common line 130 are arranged in the display area 101, wherein the common line 130 comprises a plurality of sub-common lines 131; the plurality of data lines 110 and the plurality of scan lines 120 are crisscrossed to form a plurality of pixel areas 140, wherein each pixel area 140 is correspondingly provided with a sub-common line 131; wherein the number of data lines 110 is m, the number of scan lines 120 is n; the common line 130 also comprises a plurality of horizontal Routing 132, each of the horizontal routing lines 132 is cross-arranged corresponding to the data line 110, connecting two adjacent sub-common lines 131 along the direction of the scan line 120; multiple vertical routing lines 133, each of the vertical routing lines 133 is cross-arranged corresponding to the scan line 120, connecting two adjacent sub-common lines 131 along the direction of the data line; the number of the horizontal routing lines 132 is less than or equal to m; the number of the vertical routing lines 133 is less than or equal to n-1; the multiple horizontal routing lines 132 and the vertical routing lines connect all the sub-common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal.

[0036] Compared with the conventional solution of setting a whole common line 130 in the direction of the scan line 120 or the data line, the present application reduces the number of horizontal lines 132 and vertical lines 133, thereby reducing the parasitic capacitance generated between the horizontal line 132 and the data line 110, thereby reducing the load of the data line 110, and can reduce the parasitic capacitance generated between the vertical line 133 and the scan line 120, thereby reducing the load of the scan line 120; that is, by reducing the overlapping area between the common line 130 and the data line 110 or the scan line 120, the effect of reducing the parasitic capacitance is achieved, thereby reducing the load of the data line 110 and the scan line 120.

[0037] like Figure 3As shown, the display panel 100 includes a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105 which are sequentially arranged from bottom to top; the scan line 120 and the common line 130 are formed in the first metal layer 103; the data line 110 is formed in the second metal layer 104; the pixel electrode is formed in the transparent electrode layer 105; the scan line 120 and the data line 110 cross to form a pixel area 140; the pixel electrode and the common line 130 are correspondingly arranged in the pixel area 140; the display panel 100 includes a display area 101 and a non-display area 102; a plurality of data lines 110, a plurality of scan lines 120 and a common line 130 are arranged in the display area 101, and the common line 130 includes a plurality of sub-common lines 131; a plurality of the data lines 110 and the plurality of the scan lines 120 are crisscrossed to form a plurality of pixel areas 140, and a sub-common line 131 is correspondingly arranged in each pixel area 140.

[0038] Among them, Figure 3 As shown, the number of horizontal lines 132 along a scan line 120 is m / 2, and the number of vertical lines 133 along a data line is n / 2; one horizontal line 132 is arranged for every data line 110, and one vertical line 133 is arranged for every scan line 120.

[0039] In the above embodiment, with respect to the scheme that the four sides of each sub-common line 131 are connected to the adjacent sub-common line 131 through two horizontal lines 132 and two vertical lines 133; each sub-common line 131 is connected to another adjacent sub-common line 131 only through one horizontal line 132; each sub-common line 131 is connected to another adjacent sub-common line 131 only through one vertical line 133, so that each sub-common line 131 is connected to only one horizontal line 132 and one vertical line 133, half the number of horizontal lines 132 of the data lines 110 and half the number of vertical lines 133 of the scan lines 120 can also be used. All sub-common lines 131 are connected, and a horizontal line 132 is set for every other data line 110, and a vertical line 133 is set for every other scan line 120. The number of horizontal lines 132 and vertical lines 133 is halved, which not only reduces the parasitic capacitance to the data lines 110 and the scan lines 120, but also makes the spacing uniform, so that the parasitic capacitance of the data lines 110 and the scan lines 120 in the display area 101 is more uniform, making the display more uniform, reducing the load on the data lines 110 and the scan lines 120, improving the problem of insufficient charging, and avoiding the problem of uneven display brightness caused by the brightness of one area increasing while the brightness of another area does not increase.

[0040] like Figure 3As shown, on the basis of the above embodiment, it is further arranged that: m pixel areas 140 are arranged along a scan line 120 direction, and n pixel areas 140 are arranged along a data line direction; wherein, in the pixel areas 140 along the odd-numbered scan lines 120, m / 2 horizontal wirings 132 are respectively arranged corresponding to the data lines 110 of the odd-numbered columns; in the pixel areas 140 along the even-numbered scan lines 120, m / 2 horizontal wirings 132 are respectively arranged corresponding to the data lines 110 of the even-numbered columns; in the pixel areas 140 along the odd-numbered data lines 110, m / 2 vertical wirings 133 are respectively arranged corresponding to the scan lines 120 of the odd-numbered rows; in the pixel areas 140 along the even-numbered data lines 110, m / 2 horizontal wirings 132 are respectively arranged corresponding to the scan lines 120 of the even-numbered rows.

[0041] like Figure 3 As shown, in the above embodiment, the first row and first column sub-common line 131 is connected to the second row and first column sub-common line 131 through a vertical line 133, the second row and first column sub-common line 131 is connected to the second row and second column sub-common line 131, and the second row and second column sub-common line 131 is connected to the third row and second column sub-common line 131 through a vertical line 133, and the sub-common lines 131 on the diagonal of the display panel 100 are connected to form a common line 130 through horizontal lines 132 and vertical lines 133 in sequence, and all the sub-common lines 131 are connected through a stepped connection routing method, while reducing the horizontal lines 132 and the vertical lines 133, the problem of large resistance caused by connecting some areas only in series is avoided as much as possible, and the resistance of the common line 130 is reduced by parallel connection, thereby reducing impedance loss. In addition, similar to the above, the load of the data line 110 and the scan line 120 can also be reduced, so as to achieve a uniform display effect.

[0042] It should be noted that Figure 3 Each pixel area 140 is a red sub-pixel 161 or a green sub-pixel 162 or a blue sub-pixel 163. A pixel 160 includes a red sub-pixel 161, a green sub-pixel 162 and a blue sub-pixel 163 arranged vertically. In this embodiment, the pixels are arranged in a vertical RGB arrangement mode, which is a three-gate structure, so that the number of scan lines 120 becomes 3 times the original number, and the number of data lines 110 becomes 1 / 3 of the original number, but the number of pixels in each column remains unchanged, so that the ultra-high-definition display originally arranged horizontally with RGB still maintains the ultra-high-definition pixel standard after the vertical arrangement of RGB. For the three-gate structure, the charging time of each row is only one-third of the charging time of the horizontal RGB arrangement, which can easily cause insufficient charging. The present application reduces the parasitic capacitance of the data line 110 and the scan line 120, so that the load of the data line 110 and the scan line 120 is reduced, the charging delay is reduced, and the charging efficiency is improved.

[0043] like Figure 4 This application Figure 3 A partial enlarged schematic diagram of Figure 4 Each of the sub-common lines 131 includes a first sub-common line segment 134 and a third sub-common line segment 136 parallel to the data line 110, and a second sub-common line segment 135 and a fourth sub-common line segment 137 parallel to the scan line 120. The first sub-common line segment 134, the second sub-common line segment 135, the third sub-common line segment 136 and the fourth sub-common line segment 137 are connected end to end; the horizontal wiring 132 connects the third sub-common line segment 136 of a sub-common line 131 with the first sub-common line segment 134 of another adjacent sub-common line 131; the vertical wiring 133 connects the second sub-common line segment 135 of a sub-common line 131 with the fourth sub-common line segment 137 of another adjacent sub-common line 131; by lengthening the length of the sub-common line 131, the overlapping area of ​​the sub-common line 131 and the pixel electrode is larger, thereby making the storage capacitor larger, and more electrical energy is stored during display. In addition, Figure 4 As shown, the horizontal routing line 132 is arranged in the middle position of the third sub-common line segment 136, away from the active switch arranged in the pixel area 140, and the vertical routing line 133 is also arranged in the fourth sub-common line segment 137 away from one end of the active switch in the pixel area 140. The horizontal routing line 132 and the vertical routing line 133 avoid the active switch to prevent the routing from interfering with the active switch and also reduce the generation of parasitic capacitance.

[0044] like Figure 5 The present application also discloses Figure 3In another different implementation manner, in each column of the pixel area 140, x consecutive pixel area groups 150 are grouped into one pixel area group 150; the x sub-common lines 131 in one pixel area group 150 are connected via x-1 vertical lines 133; a horizontal line 132 is provided between each of the adjacent pixel area groups 150 along the direction of the scan line 120 to connect the sub-common lines 131 corresponding to the pixel area groups 150 provided along the direction of the scan line 120; the pixel area 140 in each column is divided into n / x pixel area groups 150, where x is a natural number greater than or equal to 2 and less than or equal to n, and n / x is an integer. Different from the previous embodiment, the number of vertical lines 133 in this embodiment is relatively large, and the number of horizontal lines 132 is relatively small. The vertical lines 133 are arranged on the transparent electrode layer 105, which is far away from the scanning lines 120 of the first metal layer 103, and the generated parasitic capacitance is small. The horizontal lines 132 are arranged on the first metal layer 103, which is close to the data lines 110 arranged on the second metal layer 104, and the generated parasitic capacitance is large. Setting the number of horizontal lines 132 to be smaller is beneficial to reducing the load of the data lines 110, and thus can also improve the charging efficiency.

[0045] like Figure 5 As shown, when x is equal to 3, the display area 101 includes a plurality of pixels, and the pixels include vertically arranged red sub-pixels, green sub-pixels and blue sub-pixels; that is, one pixel area 140 is a red sub-pixel or a green sub-pixel or a blue sub-pixel, and each of the pixel area groups 150 includes the vertically arranged red sub-pixels, green sub-pixels and blue sub-pixels; m pixel areas 140 are arranged along the scan line 120 direction, and n pixel areas 140 are arranged along the data line direction; m / 3 pixels are arranged along the data line direction, and n pixel areas are arranged along the scan line 120 direction, and one red sub-pixel, green sub-pixel or blue sub-pixel is arranged in each of the pixel areas 140. In this embodiment, the pixels are arranged in a vertical RGB arrangement mode, which is a three-gate structure, so that the number of scan lines 120 becomes three times of the original number, and the number of data lines 110 becomes 1 / 3 of the original number, but the number of pixels in each column remains unchanged, so that the ultra-high-definition display that originally arranged RGB horizontally can still maintain the ultra-high-definition pixel standard after arranging RGB vertically. For the three-gate structure, the charging time of each row is only one-third of the charging time of the display panel 100 (RGB sub-pixels are arranged in the horizontal direction) of the ordinary gate structure, which can easily cause insufficient charging. However, the present application reduces the parasitic capacitance of the data line 110 and the scan line 120, so that the load of the data line 110 and the scan line 120 is reduced, the charging delay is reduced, and the charging efficiency is improved.

[0046] like Figure 5 As shown, one implementation of the present application is: m horizontal lines 132 are arranged between the 3y-2th row of scan lines 120 and the second row of scan lines 120, wherein 3y=m, y is a natural number greater than zero, and, along the direction of each of the data lines 110, m horizontal lines 132 are arranged every three scan lines 120; one horizontal line 132 is arranged for every three rows of scan lines 120, and the horizontal lines 132 are arranged in the first row; two adjacent sub-common lines 131 are connected by a horizontal line 132. Figure 6 The sub-common lines 131 of every three rows are connected through the horizontal wiring 132 of the first row, so that the sub-common lines 131 of each pixel area group 150 corresponding to each pixel area 140 are connected, and each pixel area group 150, that is, the internal sub-common lines 131 of each pixel are connected together, so that the common lines 130 of the entire display area 101 are connected through a small number of horizontal wirings 132 and vertical wirings 133, while reducing the load of the data lines 110 and the scan lines 120, ensuring that the function of the common lines 130 is not affected.

[0047] Of course, the present application is also applicable to horizontally arranged RGB pixels, such as Figure 6 As shown, the display area 101 includes a plurality of pixels 160, and the pixels include a red sub-pixel 161, a green sub-pixel 162, and a blue sub-pixel 163 arranged horizontally; the pixel area 140 is arranged in the direction of the data line, and n / 3 pixels are arranged in the direction of the scan line 120; the pixels are arranged in the direction of the data line, and n / 3 pixels are arranged in the direction of the scan line 120, and one pixel 160 is arranged in each pixel area 140.

[0048] It should be noted that the present embodiment also includes a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105 which are sequentially arranged from bottom to top; the scan line 120 and the common line 130 are formed in the first metal layer 103; the data line 110 is formed in the second metal layer 104; the pixel electrode is formed in the transparent electrode layer 105; the pixel electrode and the common line 130 form a storage capacitor; the horizontal wiring 132 is formed in the first metal layer 103; the vertical wiring 133 is formed in the transparent electrode layer 105; the vertical wiring 133 connects two adjacent sub-common lines 131 through a via.

[0049] like Figure 7 As shown, the present application discloses a display panel 100,

[0050] It includes a display area 101 and a non-display area 102, wherein the display area 101 is provided with: m data lines 110, n scan lines 120 and a common line 130; the m data lines 110 and the n scan lines 120 are crisscrossed to form a plurality of pixel areas 140, and each pixel area 140 is correspondingly provided with a sub-common line 131; the common lines 130130 receive a common voltage signal;

[0051] The common line includes: a plurality of sub-common lines 131, a plurality of horizontal lines 132 and a plurality of vertical lines 133; each of the horizontal lines 132 is arranged to cross the data line 110, and connects two adjacent sub-common lines 131 along the direction of the scan line 120; each of the vertical lines 133 is arranged to cross the scan line 120, and connects two adjacent sub-common lines 131 along the direction of the data line 110, and the plurality of horizontal lines 132 and vertical lines 133 connect all the sub-common lines 131 to form the common line 130;

[0052] Each of the sub-common lines 131 includes a first sub-common line segment 134 and a third sub-common line segment 136 parallel to the data line 110, and a second sub-common line segment 135 and a fourth sub-common line segment 137 parallel to the scan line. The first sub-common line segment 134, the second sub-common line segment 135, the third sub-common line segment 135 and the fourth sub-common line segment 136 are connected end to end and are arranged around the pixel area 140; the horizontal wiring 132 connects the third sub-common line segment 136 of a sub-common line with the first sub-common line segment 134 of another adjacent sub-common line segment; the vertical wiring 133 connects the second sub-common line segment 135 of a sub-common line with the fourth sub-common line segment 137 of another adjacent sub-common line segment;

[0053] The number of the horizontal lines 132 along the direction of one of the scan lines 120 is m / 2, and the number of the vertical lines 133 along the direction of one of the data lines 110 is n / 2; one horizontal line 132 is provided for every data line 110, and one vertical line 133 is provided for every scan line 120; the number of the horizontal lines 132 along the direction of one of the data lines 110 is n / 2, and the number of the vertical lines 133 along the direction of one of the scan lines 110 is m / 2; one horizontal line 132 is provided for every two scan lines 120, and one vertical line 133 is provided for every two data lines 110;

[0054] The display panel includes a first metal layer 103, a second metal layer 104 and a transparent electrode layer 105 which are arranged in sequence from bottom to top; the scan line 120 and the common line 130 are formed in the first metal layer 103; the data line 110 is formed in the second metal layer 104; the pixel electrode is formed in the transparent electrode layer; the pixel electrode and the common line 130 form a storage capacitor; the horizontal wiring 132 is formed in the first metal layer 103; the vertical wiring 133 is formed in the transparent electrode layer 105; the vertical wiring 133 connects two adjacent sub-common lines 131 through a via.

[0055] Each of the sub-common lines 131 includes a first sub-common line segment 134 and a third sub-common line segment 136 parallel to the data line 110, and a second sub-common line segment 135 and a fourth sub-common line segment 137 parallel to the scan line 120. The first sub-common line segment 134, the second sub-common line segment 135, the third sub-common line segment 136 and the fourth sub-common line segment 137 are connected end to end; the horizontal routing line 132 connects the third sub-common line segment 136 of a sub-common line 131 with the first sub-common line segment 134 of another adjacent sub-common line 131; the vertical routing line 133 connects the second sub-common line segment 135 of a sub-common line 131 with the fourth sub-common line segment 137 of another adjacent sub-common line 131; a plurality of the horizontal routing lines 132 and the vertical routing lines 133 connect all the sub-common lines 131 to form the common line 130, and the common line 130 is connected to a common voltage signal. By reducing the horizontal lines 132 and the vertical lines 133, the load on the data lines 110 and the scan lines 120 is reduced, and by evenly and reasonably arranging the horizontal lines 132 and the vertical lines 133, excessive local resistance of the common lines 130 is avoided to ensure display uniformity.

[0056] The technical solution of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, can all be applicable to the above solution.

[0057] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: Multiple data lines; Multiple scan lines; as well as A common line, including multiple sub-common lines; The plurality of data lines and the plurality of scan lines are crisscrossed to form a plurality of pixel regions, and each pixel region is correspondingly provided with one sub-common line; wherein the number of the data lines is m, the number of the scan lines is n, and m and n are natural numbers greater than or equal to 1; The common line also includes: A plurality of horizontal lines, each of which is arranged to cross the data line and connect two adjacent sub-common lines along the scan line direction; A plurality of vertical lines, each of which is arranged to cross the scan line and connect two adjacent sub-common lines along the data line direction; The number of the horizontal lines is less than or equal to m; the number of the vertical lines is less than or equal to n-1; the plurality of horizontal lines and vertical lines connect all the sub-common lines to form the common line, and the common line receives a common voltage signal; In each column of the pixel regions, x consecutive pixel regions are grouped into a pixel region group; The x sub-common lines in one pixel region group are connected via x-1 vertical wirings; A horizontal line is arranged between each of the adjacent pixel area groups along the scan line direction to connect the sub-common lines corresponding to the pixel area groups arranged along the scan line direction; each column of the pixel areas is divided into n / x pixel area groups, x is a natural number greater than or equal to 2 and less than or equal to n, and n / x is an integer.

2. A display panel according to claim 1, characterized in that: The display panel includes a plurality of pixels, each of which includes a red sub-pixel, a green sub-pixel and a blue sub-pixel arranged vertically; m pixel regions are arranged along the scanning line direction, and n pixel regions are arranged along the data line direction, forming a pixel region matrix with n rows and m columns; There are n / 3 pixels arranged along the data line direction and m pixels arranged along the scan line direction, and one red sub-pixel, green sub-pixel or blue sub-pixel is arranged in each pixel area; the value of x is 3, and each pixel area group includes the red sub-pixels, green sub-pixels and blue sub-pixels arranged vertically; one vertical wiring is arranged between the red sub-pixels and the green sub-pixels, and one vertical wiring is arranged between the green sub-pixels and the blue sub-pixels, so as to connect the three sub-common lines in the pixel area group.

3. A display panel as claimed in claim 2, characterized in that: The pixel area in the 3y-2th row is provided with m horizontal wirings, which are respectively arranged between the pixel area groups adjacent to each other along the scanning line direction to connect the sub-common lines corresponding to the pixel area groups arranged along the scanning line direction, where 3y≤n, and y is a natural number greater than zero.

4. The display panel according to claim 1, characterized in that: Each of the sub-common lines includes a first sub-common line segment and a third sub-common line segment parallel to the data line, and a second sub-common line segment and a fourth sub-common line segment parallel to the scan line. The first sub-common line segment, the second sub-common line segment, the third sub-common line segment and the fourth sub-common line segment are connected end to end in sequence and are arranged around the pixel area.

5. The display panel according to claim 3, characterized in that: 3y=n.

6. The display panel according to claim 4, characterized in that: The horizontal line connects the third sub-common line segment of one of the sub-common line segments and the first sub-common line segment of another adjacent sub-common line segment; the vertical line connects the second sub-common line segment of one of the sub-common line segments and the fourth sub-common line segment of another adjacent sub-common line segment.

7. A display panel as claimed in claim 6, characterized in that: One end of the horizontal line is connected to the middle position of the third sub-common line segment of one of the sub-common lines, and the other end is connected to the middle position of the first sub-common line segment of another adjacent sub-common line segment; One end of the vertical line is connected to one end of the second sub-common line segment of one of the sub-common lines, and the other end is connected to one end of the fourth sub-common line segment of another adjacent sub-common line segment.

8. A display panel as claimed in claim 7, characterized in that: The vertical wiring is arranged at an end of the fourth sub-common line segment away from the active switch in the corresponding pixel region.

9. A display panel, characterized in that: include: Multiple data lines; Multiple scan lines; as well as A common line, including multiple sub-common lines; The plurality of data lines and the plurality of scan lines are crisscrossed to form a plurality of pixel regions, and each pixel region is correspondingly provided with one sub-common line; wherein the number of the data lines is m, the number of the scan lines is n, and m and n are natural numbers greater than or equal to 1; The common line also includes: A plurality of horizontal lines, each of which is arranged to cross the data line and connect two adjacent sub-common lines along the scan line direction; A plurality of vertical lines, each of which is arranged to cross the scan line and connect two adjacent sub-common lines along the data line direction; The number of the horizontal lines is less than or equal to m; the number of the vertical lines is less than or equal to n-1; the plurality of horizontal lines and vertical lines connect all the sub-common lines to form the common line, and the common line receives a common voltage signal; In each row of the pixel areas, three consecutive pixel areas are grouped into a pixel area group; One vertical line is provided between each of the pixel area groups adjacent to each other along the data line direction. The display panel includes a plurality of pixels, each of which includes a red sub-pixel, a green sub-pixel and a blue sub-pixel arranged horizontally; m pixel regions are arranged along the scanning line direction, and n pixel regions are arranged along the data line direction, forming a pixel region matrix with n rows and m columns; There are n pixels arranged along the data line direction and m / 3 pixels arranged along the scan line direction, and one red sub-pixel, green sub-pixel or blue sub-pixel is arranged in each pixel area; one horizontal wiring is arranged between the red sub-pixel and the green sub-pixel, and one horizontal wiring is arranged between the green sub-pixel and the blue sub-pixel to connect the three sub-common lines in the pixel area group.

10. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 9 and a driving circuit for driving the display panel.

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