A data transmission method, DMA controller, and computer-readable storage medium

Abstract

The present invention provides a data transmission method, a DMA controller and a medium. The method is applied to the DMA controller and includes: obtaining a first descriptor from the AXI read channel to the memory using a pre-stored descriptor address, and setting the first descriptor as the descriptor to be processed; requesting corresponding data from the storage device according to the descriptor to be processed, and updating the descriptor address, and using the updated descriptor address to request the next descriptor from the AXI read channel to the memory; writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed, and simultaneously receiving the next descriptor sent by the memory from the AXI read channel; updating the descriptor to be processed using the next descriptor, and performing the step of requesting corresponding data from the storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed; the AXI bus with separated read and write channels can be used to simultaneously write data to the memory and obtain descriptors, thereby improving the DMA transmission performance.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and particularly to a data transmission method, a DMA controller, and a computer-readable storage medium. Background Art

[0002] Direct Memory Access (DMA) is a mechanism for fast data transmission. When accessing data, it does not require the intervention of a processor, and data can be directly transmitted between a source device and a destination device. In related technologies, when a DMA controller executes data transmission processes such as P2M (Peripheral to Memory) and M2M (Memory to Memory), it reads data from a storage device according to the address indicated by a descriptor fetched from memory and writes it back to the corresponding address in memory. After completing the previous round of data transmission, it fetches the next descriptor from memory for data transmission. However, when facing small file transmission, the ratio of the descriptor reading time to the data transmission time in the above data transmission process will increase significantly, which easily affects the data transmission performance. Summary of the Invention

[0003] The purpose of the present invention is to provide a data transmission method, a DMA controller, and a computer-readable storage medium, wherein the DMA controller can simultaneously write data to memory and obtain descriptors by using an AXI bus with separated read and write channels, thereby improving the DMA transmission performance.

[0004] To solve the above technical problems, the present invention provides a data transmission method, which is applied to a DMA controller. The method includes:

[0005] Obtaining a first descriptor from the memory through an AXI read channel by using a pre-stored descriptor address, and setting the first descriptor as a descriptor to be processed;

[0006] Requesting corresponding data from a storage device according to the descriptor to be processed, updating the descriptor address, and requesting the next descriptor from the memory through the AXI read channel by using the updated descriptor address;

[0007] Writing the data sent by the storage device into the memory through an AXI write channel according to the descriptor to be processed, and simultaneously receiving the next descriptor sent by the memory through the AXI read channel;

[0008] Updating the descriptor to be processed by using the next descriptor, and executing the step of requesting corresponding data from the storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed.

[0009] Optionally, the updating the descriptor address includes:

[0010] Add a preset value to the descriptor address.

[0011] Optionally, the obtaining the first descriptor from the AXI read channel to the memory by using the pre-stored descriptor address includes:

[0012] Read the descriptor address from the register corresponding to the DMA controller, and obtain the first descriptor from the AXI read channel to the memory by using the descriptor address.

[0013] Optionally, the requesting corresponding data from the storage device according to the to-be-processed descriptor includes:

[0014] Extract the source address and the data length from the to-be-processed descriptor, and request the data from the storage device according to the source address and the data length.

[0015] Optionally, the writing the data sent by the storage device from the AXI write channel to the memory according to the to-be-processed descriptor includes:

[0016] Write the data sent by the storage device from the AXI write channel to the memory according to the to-be-processed descriptor;

[0017] When receiving the completion flag sent by the memory through the AXI write channel, execute the step of updating the to-be-processed descriptor by using the next descriptor.

[0018] Optionally, the writing the data sent by the storage device from the AXI write channel to the memory according to the to-be-processed descriptor includes:

[0019] Extract the target address from the to-be-processed descriptor, and write the data from the AXI write channel to the corresponding position of the target address in the memory.

[0020] Optionally, the determining that all descriptors in the memory are processed includes:

[0021] Judge whether the to-be-processed descriptor contains an end flag;

[0022] If it contains, determine that all descriptors in the memory are processed.

[0023] The present invention further provides a DMA controller, including:

[0024] An initialization module, configured to obtain the first descriptor from the memory by using the pre-stored descriptor address, and set the first descriptor as the to-be-processed descriptor;

[0025] A request module, configured to request corresponding data from a storage device according to the to-be-processed descriptor, update the descriptor address, and use the updated descriptor address to request the next descriptor from the AXI read channel to the memory;

[0026] A read / write module, configured to write the data sent by the storage device from the AXI write channel to the memory according to the to-be-processed descriptor, and simultaneously receive the next descriptor sent by the memory from the AXI read channel;

[0027] A loop module, configured to update the to-be-processed descriptor with the next descriptor, and execute the step of requesting corresponding data from the storage device according to the to-be-processed descriptor until it is determined that all descriptors in the memory have been processed.

[0028] Optionally, the request module includes:

[0029] An address update sub-module, configured to add a preset value to the descriptor address.

[0030] The present invention further provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are loaded and executed by a processor, the data transmission method as described above is implemented.

[0031] The present invention provides a data transmission method applied to a DMA controller. The method includes: obtaining a first descriptor from the AXI read channel to the memory using a pre-stored descriptor address, and setting the first descriptor as the to-be-processed descriptor; requesting corresponding data from a storage device according to the to-be-processed descriptor, updating the descriptor address, and using the updated descriptor address to request the next descriptor from the AXI read channel to the memory; writing the data sent by the storage device from the AXI write channel to the memory according to the to-be-processed descriptor, and simultaneously receiving the next descriptor sent by the memory from the AXI read channel; updating the to-be-processed descriptor with the next descriptor, and executing the step of requesting corresponding data from the storage device according to the to-be-processed descriptor until it is determined that all descriptors in the memory have been processed.

[0032] It can be seen that the present invention uses the read channel and write channel of AXI to complete data transmission between the DMA controller and the memory. When making a data request, the DMA controller can use the previous descriptor obtained from the memory to request corresponding data from the storage device, and at the same time obtain the next descriptor from the memory through the AXI read channel; when performing data transmission, the DMA controller can write the data corresponding to the previous descriptor into the memory through the AXI write channel, and at the same time receive the next descriptor sent by the memory through the AXI read channel. In other words, the present invention utilizes the characteristic of the separation of the read and write channels of the AXI bus, can simultaneously complete data writing and descriptor acquisition for the memory, reduce the impact of descriptor reading operations on data transmission efficiency, and thus can effectively improve the transmission performance of the DMA controller for small files. The present invention also provides a DMA controller and a computer-readable storage medium, which have the above beneficial effects. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0034] Figure 1 It is a flowchart of a data transmission method provided by an embodiment of the present invention;

[0035] Figure 2 It is a comparison diagram of the existing DMA data transmission process and the DMA data transmission process of the present invention provided by an embodiment of the present invention;

[0036] Figure 3 It is a structural block diagram of a DMA controller provided by an embodiment of the present invention. Detailed Embodiments

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0038] In the related art, when a DMA controller executes a P2M (Peripheral to Memory) or M2M (Memory to Memory) data transfer process, it reads data from a storage device according to the address indicated by a descriptor fetched from memory and writes the data back to the corresponding address in memory. After completing the previous round of data transfer, it fetches the next descriptor from memory for data transfer. However, when dealing with small file transfers, the ratio of the descriptor reading time to the data transfer time in the above data transfer process will increase significantly, which is likely to affect the data transfer performance. In view of this, the present invention provides a data transfer method, in which the DMA controller can simultaneously write data to memory and obtain descriptors by using an AXI bus with separated read and write channels, thereby improving the DMA transfer performance. Please refer to Figure 1 , Figure 1 which is a flowchart of a data transfer method provided by an embodiment of the present invention. The method is applied to a DMA controller and includes:

[0039] S101. Obtain the first descriptor from memory through the AXI read channel using the pre-stored descriptor address, and set the first descriptor as the descriptor to be processed.

[0040] Embodiments of the present invention use the AXI interface to improve the performance of the DMA controller in writing data to memory, especially to improve the transmission efficiency of the DMA controller for small chunks of data. AXI (Advanced eXtensible Interface) is a bus protocol, and the interface operating based on this protocol is the AXI interface. This interface has the characteristic of full duplex, that is, it has separate read and write channels, and these two channels can work simultaneously. Embodiments of the present invention do not limit the specific read channel and write channel structures of the AXI interface, nor the working mode of the AXI interface, and relevant technologies of the AXI interface can be referred to. Since the DMA controller executes the data transfer processes of P2M (Peripheral to Memory) and M2M (Memory to Memory), it usually uses the read channel of the AXI interface to obtain descriptors from memory and writes relevant data to memory through the write channel of the AXI interface. Therefore, embodiments of the present invention can utilize the characteristic of the separation of the read and write channels of AXI to achieve writing the data corresponding to the previous descriptor to memory and requesting the next descriptor from memory simultaneously, which can effectively reduce the waiting time of the descriptor acquisition for the DMA data transfer process, and further improve the data transfer performance of the DMA controller. It should be noted that a descriptor contains parameters required for the DMA controller to carry out data transfer, such as the source address of the data in the source memory, the data length, and the target address of the data in the target memory. Of course, the descriptor can also contain other contents, and relevant technologies of the DMA descriptor can be referred to.

[0041] Furthermore, it can be understood that for facilitating the rapid processing of data transfer tasks, the DMA controller is usually provided with relevant registers, and then the processor can write the address of the first descriptor in memory into the registers, so that the DMA controller reads the address from the relevant registers and processes it.

[0042] In a possible case, obtaining the first descriptor from memory through the AXI read channel using the pre-stored descriptor address may include:

[0043] Step 11: Read the descriptor address from the register corresponding to the DMA controller, and use the descriptor address to obtain the first descriptor from memory through the AXI read channel.

[0044] It should be noted that embodiments of the present invention do not limit how the processor configures the registers of the DMA controller, nor the specific registers, and relevant technologies of the DMA can be referred to. Of course, other configuration information may also be included in the registers, such as DMA enable information, information on whether the DMA generates an interrupt, and it can be configured according to the configuration information recognizable by the DMA controller. Embodiments of the present invention do not limit this.

[0045] Further, embodiments of the present invention do not limit how the DMA controller interacts with the memory through the AXI read channel to obtain descriptors. For example, the DMA controller sends a descriptor acquisition request according to the descriptor address, and the memory interface requests and sends the corresponding descriptor to the DMA controller. Reference can be made to the related technologies of DMA and AXI.

[0046] S102. Request corresponding data from the storage device according to the descriptor to be processed, update the descriptor address, and request the next descriptor from the memory through the AXI read channel using the updated descriptor address.

[0047] After obtaining the descriptor to be processed, the DMA controller can obtain the corresponding data from the target storage device. Specifically, the source address and data length where the data is located can be extracted from the descriptor, and the corresponding data can be obtained from the storage device according to the source address and data length.

[0048] In a possible case, requesting corresponding data from the storage device according to the descriptor to be processed may include:

[0049] Step 21: Extract the source address and data length from the descriptor to be processed, and request data from the storage device according to the source address and data length.

[0050] Of course, when the DMA controller requests data from the storage device, other information can also be extracted from the descriptor to be processed for the request. Reference can be made to the related technologies of DMA.

[0051] Further, embodiments of the present invention do not limit the specific storage device. For example, it can be an external storage device or another memory. When the storage device is an external storage device, the DMA controller executes the P2M data transfer process; when the storage device is another memory, the DMA controller executes the M2M data transfer process. In other words, the present invention can enhance the data transfer performance of both the P2M and M2M data transfer modes at the same time. It should be noted that embodiments of the present invention do not limit the specific process of the DMA requesting data from the storage device. For example, the DMA controller generates a corresponding data acquisition request according to the descriptor to be processed and sends it to the storage device, and the storage device sends the corresponding data to the DMA controller according to the received request. Reference can be made to the related technologies of DMA.

[0052] Further, to improve the data acquisition efficiency, descriptors are usually stored in memory in a continuous storage form. Since the size of each descriptor is fixed, in other words, the address corresponding to the next descriptor can be directly determined by updating the address of the previous descriptor. Specifically, since the descriptor size is fixed, a preset value can be added to the address of the previous descriptor to obtain the address of the next descriptor. The embodiments of the present invention do not limit the specific preset value, and this data is related to the size of the descriptor. For example, if the descriptor occupies 1 byte, the preset value is 1; if the descriptor occupies 4 bytes, the preset value is 4, which can be set according to actual application requirements.

[0053] In a possible case, updating the descriptor address may include:

[0054] Step 31: Add a preset value to the descriptor address.

[0055] Further, it should be noted that the step of requesting corresponding data from the storage device is executed in parallel with the step of requesting the next descriptor from the AXI read channel to the memory. In other words, when the DMA controller starts to obtain corresponding data from the storage device, it can simultaneously start to request the next descriptor from the memory.

[0056] S103: Write the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed, and simultaneously receive the next descriptor sent by the memory from the AXI read channel.

[0057] Since the read channel and write channel of the AXI interface can work simultaneously, the DMA controller writes data to the memory through the write channel and simultaneously receives the next descriptor sent by the memory from the read channel. It should be noted that the request and reception of descriptors are carried out in parallel with the request and writing of data, that is, the DMA controller can request descriptors from the memory through the read channel, receive the descriptors sent by the memory through the read channel, simultaneously request data from the storage device, and write the data to the memory through the write channel. The request and reception of descriptors and the request and writing of data in this round can start after the previous round of data writing is completed.

[0058] Further, to ensure that each round of data is properly written to the memory, it can be determined that the data writing in this round is completed when the completion flag sent by the memory through the write channel is received. The embodiments of the present invention do not limit the specific form of the completion flag, nor how the memory sends the completion flag. For example, it can be sent through the write response channel of the AXI write channel, and relevant technologies of DMA can be referred to.

[0059] In a possible case, writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed may include:

[0060] Step 41: Write the data sent by the storage device from the AXI write channel into the memory according to the descriptor to be processed;

[0061] Step 42: When receiving the completion flag sent by the memory through the AXI write channel, execute the step of updating the descriptor to be processed with the next descriptor.

[0062] Furthermore, the data can be written to the corresponding position in the memory at the target address according to the target address in the descriptor to be processed.

[0063] In a possible case, writing the data sent by the storage device from the AXI write channel into the memory according to the descriptor to be processed may include:

[0064] Step 51: Extract the target address from the descriptor to be processed, and write the data from the AXI write channel to the corresponding position in the memory at the target address.

[0065] S104: Update the descriptor to be processed with the next descriptor, and execute the step of requesting the corresponding data from the storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed.

[0066] It can be understood that after updating the descriptor to be processed, it can be judged whether this descriptor is the last unprocessed descriptor in the memory, so as to judge whether all descriptors in the memory have been processed. Specifically, the memory may include an end flag in the last descriptor. When the DMA controller can extract this end flag, it can be determined that all descriptors have been processed, and after completing the data transmission processing of the current descriptor to be processed, the processing flow exits. The embodiments of the present invention do not limit the specific form of the end flag, as long as it can identify that this descriptor is the last one.

[0067] In a possible case, determining that all descriptors in the memory have been processed may include:

[0068] Step 61: Judge whether the descriptor to be processed contains an end flag; if it contains, enter Step 62; if it does not contain, enter Step 63;

[0069] Step 62: Determine that all descriptors in the memory have been processed;

[0070] Step 63: Determine that there are unprocessed descriptors in the memory.

[0071] Based on the above embodiments, the present invention uses the read channel and write channel of AXI to complete the data transfer between the DMA controller and the memory. When making a data request, the DMA controller can use the previous descriptor obtained from the memory to request the corresponding data from the storage device, and at the same time obtain the next descriptor from the memory through the AXI read channel; when performing data transfer, the DMA controller can write the data corresponding to the previous descriptor into the memory through the AXI write channel, and at the same time receive the next descriptor sent by the memory through the AXI read channel. In other words, the present invention utilizes the characteristic of separating the read and write channels of the AXI bus, can simultaneously complete the data writing and descriptor acquisition of the memory, reduce the influence of descriptor reading operations on data transfer efficiency, and thus can effectively improve the transfer performance of the DMA controller for small files.

[0072] The following introduces the data transfer method provided by the present invention based on specific comparison diagrams. Please refer to Figure 2 , Figure 2 is a comparison diagram of the existing DMA data transfer process and the DMA data transfer process of the present invention provided by the embodiments of the present invention, where the left half is the existing DMA data transfer process, and the right side is the DMA data transfer process provided by the embodiments of the present invention (both processes are in the P2M mode). The data transfer process of the present invention may include:

[0073] 1. The DMA fetches the address where the first descriptor is stored from the register in the memory;

[0074] 2. The DMA sends a descriptor read request to the memory through the AXI read channel;

[0075] 3. The memory returns the descriptor through the AXI read channel;

[0076] 4. The DMA parses the descriptor, and based on the parsed source address, data length and other information, sends a read data request to the peripheral device. At the same time, the DMA increments the descriptor address by 1 and sends a read request for the next descriptor to the memory through the AXI read channel;

[0077] 5. The peripheral device returns the read data, and at the same time the memory also returns the next descriptor through the AXI read channel;

[0078] 6. The DMA writes the received data into the destination address parsed according to the descriptor through the AXI interface;

[0079] 7. The memory returns a data reception completion flag (write response, Write Response) through the AXI write response channel, and the DMA parses the content of the next descriptor, repeating steps 4-7 until all descriptors are processed.

[0080] It can be seen that in the existing process, when the DMA reads data from the peripheral, its AXI read / write interface on the memory side (Memory) is idle, and only the AXI write channel is used after the data is returned. For example, only after the descriptor 1 and the corresponding data 1 complete the transmission process can the transmission process of descriptor 2 and the corresponding data 2 start. In the transmission process of the present invention, when the DMA reads data from the peripheral (Peripheral), the AXI read channel is used to prefetch the next descriptor from the memory side for later use. For example, when requesting data 1 from the peripheral, descriptor 2 is obtained from the memory side at the same time. In this way, even if the DMA has not completed the operation of reading back the next descriptor when the data returns from the peripheral, it does not affect the DMA using the write channel to write the returned data into the memory, and the latency gap between the completion time of the previous round of data writing and the completion time of the current round of data writing can be effectively shortened.

[0081] Next, a DMA controller and a computer-readable storage medium provided by an embodiment of the present invention will be introduced. The DMA controller and the computer-readable storage medium described below can be correspondingly referred to the data transmission method described above.

[0082] Please refer to Figure 3 , Figure 3 which is a structural block diagram of a DMA controller provided by an embodiment of the present invention. The DMA controller may include:

[0083] An initialization module 301, configured to obtain the first descriptor from the memory through the AXI read channel using the pre-stored descriptor address, and set the first descriptor as the descriptor to be processed;

[0084] A request module 302, configured to request corresponding data from the storage device according to the descriptor to be processed, update the descriptor address, and request the next descriptor from the memory through the AXI read channel using the updated descriptor address;

[0085] A read / write module 303, configured to write the data sent by the storage device into the memory through the AXI write channel according to the descriptor to be processed, and receive the next descriptor sent by the memory through the AXI read channel at the same time;

[0086] A loop module 304, configured to update the descriptor to be processed using the next descriptor, and execute the step of requesting corresponding data from the storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed.

[0087] Optionally, the request module 302 may include:

[0088] An address update sub-module, configured to add a preset value to the descriptor address.

[0089] Optionally, the initialization module 301 may include:

[0090] An initialization sub-module, configured to read a descriptor address from a register corresponding to a DMA controller, and obtain a first descriptor from an AXI read channel to memory by using the descriptor address.

[0091] Optionally, the request module 302 may include:

[0092] A data request sub-module, configured to extract a source address and a data length from a descriptor to be processed, and request data from a storage device according to the source address and the data length;

[0093] Optionally, the read / write module 303 may include:

[0094] A write sub-module, configured to write data sent by the storage device from an AXI write channel into memory according to a descriptor to be processed;

[0095] A response receiving sub-module, configured to, when receiving a completion flag sent by memory through an AXI write channel, perform a step of updating the descriptor to be processed by using a next descriptor.

[0096] Optionally, the write sub-module may include:

[0097] A write unit, configured to extract a target address from a descriptor to be processed, and write data from an AXI write channel to a corresponding position in memory at the target address.

[0098] Optionally, the loop module 304 may include:

[0099] A judgment sub-module, configured to judge whether an end flag is included in a descriptor to be processed;

[0100] A determination module, configured to, if included, determine that all descriptors in memory have been processed.

[0101] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data transmission method in any of the above embodiments are implemented.

[0102] Since the embodiments in the computer-readable storage medium part correspond to the embodiments in the data transmission method part, for the embodiments in the computer-readable storage medium part, please refer to the description of the embodiments in the data transmission method part, and details are not described herein again.

[0103] The embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.

[0104] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present invention.

[0105] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0106] The above has introduced in detail a data transmission method, a DMA controller, and a computer-readable storage medium provided by the present invention. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A data transmission method, characterized in that, Applied to a DMA controller, the method includes: Obtaining a first descriptor from the AXI read channel to the memory using a pre-stored descriptor address, and setting the first descriptor as the descriptor to be processed; Requesting corresponding data from a storage device according to the descriptor to be processed, and updating the descriptor address, and using the updated descriptor address to request the next descriptor from the AXI read channel to the memory; Writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed, and simultaneously receiving the next descriptor sent by the memory from the AXI read channel; Updating the descriptor to be processed using the next descriptor, and performing the step of requesting corresponding data from the storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed.

2. The data transmission method according to claim 1, wherein The updating the descriptor address includes: Adding a preset value to the descriptor address.

3. The data transmission method according to claim 1, characterized in that The obtaining a first descriptor from the AXI read channel to the memory using a pre-stored descriptor address includes: Reading the descriptor address from a register corresponding to the DMA controller, and obtaining the first descriptor from the AXI read channel to the memory using the descriptor address.

4. The data transmission method according to claim 1, wherein The requesting corresponding data from a storage device according to the descriptor to be processed includes: Extracting a source address and a data length from the descriptor to be processed, and requesting the data from the storage device according to the source address and the data length.

5. The data transmission method according to claim 1, wherein The writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed includes: Writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed; When receiving a completion flag sent by the memory through the AXI write channel, performing the step of updating the descriptor to be processed using the next descriptor.

6. The data transmission method according to claim 5, wherein The writing the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed includes: Extracting a target address from the descriptor to be processed, and writing the data from the AXI write channel to a corresponding position in the memory at the target address.

7. The data transmission method according to claim 1, characterized in that The determining that all descriptors in the memory have been processed includes: Judging whether an end flag is included in the descriptor to be processed; If included, determining that all descriptors in the memory have been processed.

8. A DMA controller, characterized in that, Includes: An initialization module, configured to obtain a first descriptor from the AXI read channel to the memory using a pre-stored descriptor address, and set the first descriptor as the descriptor to be processed; A request module, configured to request corresponding data from a storage device according to the descriptor to be processed, and update the descriptor address, and use the updated descriptor address to request the next descriptor from the AXI read channel to the memory; A read / write module, configured to write the data sent by the storage device from the AXI write channel to the memory according to the descriptor to be processed, and simultaneously receive the next descriptor sent by the memory from the AXI read channel; A loop module, configured to update the descriptor to be processed by using the next descriptor, and perform the step of requesting corresponding data from a storage device according to the descriptor to be processed until it is determined that all descriptors in the memory have been processed.

9. The DMA controller according to claim 8, wherein The request module includes: An address update sub-module, configured to add a preset value to the descriptor address.

10. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium. When the computer-executable instructions are loaded and executed by a processor, the data transmission method according to any one of claims 1 to 7 is implemented.

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