Optimization Method for PDN Decoupling Network of Microsystems Based on CPS Co-Simulation

Abstract

The present invention discloses a method for optimizing the decoupling network of a microsystem PDN based on CPS co-simulation, including the following processes: establishing an ECPM model of the chip VCC; extracting the S-parameter models of the TSV silicon substrate PDN, the package PDN, and the PCB board PDN; building a PDN full-path analysis circuit according to the ECPM model of the chip VCC, the S-parameter models of the TSV silicon substrate PDN, the package PDN, and the PCB board PDN; adding a parametric capacitor model to the PDN full-path analysis circuit; performing time-domain analysis and capacitor optimization on the PDN full-path analysis circuit with the parametric capacitor model added to obtain the final design scheme of the microsystem PDN decoupling network. The present invention can achieve the performance of the microsystem PDN decoupling network and ensure the minimization of PDN noise.

Description

Technical Field

[0001] The present invention belongs to the field of microsystem simulation and optimization, and particularly relates to a method for optimizing the PDN decoupling network of a microsystem based on CPS co-simulation. Background Art

[0002] The reduction of feature size accounts for an increasingly small proportion in the improvement of chip performance. The three-dimensional integrated microsystem technology using advanced packaging has become an important development direction of electronic systems. Based on processes such as TSV silicon substrates, packages, and vertical stacking and assembly, chips with different process nodes, different materials, and different functions are integrated in a single package housing to achieve high-density heterogeneous integrated microsystems. While significantly reducing the volume, it also brings corresponding design challenges. The power integrity design of the power impedance and noise decoupling of the microsystem PDN has become a difficult problem.

[0003] The complete PDN circuit structure is as Figure 2 shown. The microsystem PDN is as Figure 2 the part within the dashed circle in. The power distribution network reaches the chip through the PCB board PDN, package PDN, and TSV silicon substrate PDN. The goal of PDN impedance design is not to exceed the target impedance, and the voltage fluctuation during transient large-scale power supply does not exceed the noise tolerance of the supply voltage. The transient voltage fluctuation is ΔV, the transient current change amount is ΔI, and the PDN impedance is Z PDN , ΔV = Z PDN ·ΔI. When the PDN transient current changes due to the change in the load operating state, to ensure that the voltage change range at the chip end is within the allowable range, the power impedance must be small enough and not exceed a certain required value, that is, the target impedance. The PDN target impedance design method is as Figure 3 shown. The definition of the target impedance is as follows:

[0004]

[0005] wherein, Vcc is the power supply voltage, Ripple is the allowable voltage fluctuation, and ΔI max is the maximum transient current change amount of the load chip.

[0006] There are two drawbacks in the existing target impedance design methods: (1) The chip manual does not provide the maximum transient current change amount. In the engineering application of the target impedance method, ΔI maxTake half of the maximum operating current of the chip, resulting in a constant and inaccurate target impedance value. In fact, the current requirements and variations of the chip at different frequency points are not the same. This constant target impedance method is a conservative design method that often causes over-design. (2) The complete PDN is cross-scale, and power supply noise decoupling cannot be completely solved at one level. The existing technology independently designs and optimizes the impedance of each level of the PDN, using a constant target impedance. On the one hand, it ignores the correlation and coupling between levels; on the other hand, it is difficult to determine the decoupling frequency range of each level, making it difficult to evaluate the performance of the PDN design.

[0007] The introduction of advanced packaging has made the packaging scale of microsystems closer and closer to the chip process scale and much smaller than that of the PCB. The coupling between the characteristics of the chip and the parasitic effects of the micro-scale packaging structure is getting stronger and stronger. Under the micro-nano scale process, the number and capacitance value of capacitors that can be placed in the microsystem package PDN and the TSV silicon substrate PDN are very limited. It is difficult for the existing technology to achieve the performance of the microsystem PDN decoupling network and ensure the minimization of PDN noise. Summary of the Invention

[0008] To solve the problems existing in the prior art, the purpose of the present invention is to provide an optimization method for the microsystem PDN decoupling network based on CPS co-simulation. The present invention can achieve the performance of the microsystem PDN decoupling network and ensure the minimization of PDN noise.

[0009] The technical solution adopted by the present invention is as follows:

[0010] The optimization method for the microsystem PDN decoupling network based on CPS co-simulation includes the following processes:

[0011] Establish an ECPM model for the chip VCC;

[0012] Extract the S-parameter model of the TSV silicon substrate PDN;

[0013] Extract the S-parameter model of the package PDN;

[0014] Extract the S-parameter model of the PCB board PDN;

[0015] Build a PDN full-path analysis circuit according to the ECPM model of the chip VCC, the S-parameter model of the TSV silicon substrate PDN, the S-parameter model of the package PDN, and the S-parameter model of the PCB board PDN;

[0016] Add a parametric capacitor model to the PDN full-path analysis circuit;

[0017] Perform time-domain analysis and capacitor optimization on the PDN full-path analysis circuit with the parametric capacitor model added to obtain the final design scheme of the microsystem PDN decoupling network.

[0018] Preferably, the process of establishing the ECPM model of the chip VCC includes:

[0019] Establish the CPM model of the chip;

[0020] According to the power supply characteristics when the chip switches between different working states, modulate the CPM model based on the chip Clock Gate information to establish the ECPM model of the chip VCC.

[0021] Preferably, when establishing the CPM model of the chip, divide the chip VCC into M×N regions, and divide the VCC die pads with the same current into one region;

[0022] Among them, M and N are positive integers, the minimum value is 1, and the maximum value is the number of VCC die pads.

[0023] Preferably, the process of extracting the S-parameter model of the TSV silicon substrate PDN includes the following steps:

[0024] First, at the chip end of the TSV silicon substrate layout, according to the M×N region division, in each region, create a pin group for the VCC pins to obtain the VCC pin group; create a pin group for the GND pins to obtain the GND pin group; add a Port between each VCC pin group and the nearest GND pin group; second, divide the VCC and GND at the external lead-out end of the TSV silicon substrate into M×N regions respectively, form a VCC pin group and a GND pin group in each region, and add a Port; then, add a Port indicating the position of the decoupling capacitor;

[0025] Finally, extract the S-parameter model and output the *.sXp file of the TSV silicon substrate PDN;

[0026] Among them, when adding a Port indicating the position of the decoupling capacitor, the following two situations are included:

[0027] (1) When there is no capacitor on the TSV silicon substrate, evenly add M×N Ports around the chip on the TSV silicon substrate, and connect the two ends of each Port to VCC and GND respectively;

[0028] (2) When there are capacitors placed on the TSV silicon substrate, remove the capacitors and add a Port between the VCC pad and the GND pad of the capacitor;

[0029] When there is no capacitor on the TSV silicon substrate, in the *.sXp file of the TSV silicon substrate PDN, X = (3×M×N);

[0030] When capacitors are placed on the TSV silicon substrate, in the *.sXp file of the PDN of the TSV silicon substrate, X = (2×M×N + the number of capacitors).

[0031] Preferably, the process of extracting the S-parameter model of the package PDN includes the following steps: First, at the pin ends of the TSV silicon substrate in the package layout, according to the M×N area division, within each area, create a pin group for the VCC pins to obtain the VCC pin group; create a pin group for the GND pins to obtain the GND pin group; add a Port between each VCC pin group and the nearest GND pin group. Second, create a pin group for the VCC of the package's external lead-out end and a pin group for the GND, and add a Port between the VCC pin group and the GND pin group. Then, add a Port indicating the location of the decoupling capacitor.

[0032] Finally, extract the S-parameter model and output the *.sYp file of the package PDN.

[0033] Among them, when adding a Port indicating the location of the decoupling capacitor, the following two situations are included:

[0034] (1) When there is no capacitor on the package itself, evenly add M×N Ports around the chip on the package, and connect VCC and GND to both ends of the Port respectively.

[0035] (2) When capacitors are placed on the package itself, remove the capacitors and add a Port between the VCC pad and the GND pad of the capacitor.

[0036] When there is no capacitor on the package, in the *.sYp file of the package PDN, Y = (2×M×N + 1);

[0037] When capacitors are placed on the package, in the *.sYp file of the package PDN, Y = (M×N + the number of capacitors + 1).

[0038] Preferably, the process of extracting the S-parameter model of the PDN of the TSV silicon substrate includes the following steps:

[0039] First, at the pin ends of the microsystem module in the PCB layout, create a VCC pin group and a GND pin group respectively, and add a Port. Second, add a Port between the VCC and GND pins of the power supply module. Then, add a Port indicating the location of the decoupling capacitor.

[0040] Finally, extract the S-parameter model and output the *.sZp file of the PDN of the PCB board, Y = (the number of capacitors + 2).

[0041] Preferably, the process of building a PDN full-path analysis circuit based on the ECPM model of the chip VCC, the S-parameter model of the TSV silicon substrate PDN, the S-parameter model of the package PDN, and the S-parameter model of the PCB board PDN includes:

[0042] First, cascade the S-parameter model of the PCB board PDN, the S-parameter model of the package PDN, and the S-parameter model of the TSV silicon substrate PDN in the order of the PCB board PDN, the package PDN, and the TSV silicon substrate PDN, and connect the corresponding Ports.

[0043] Then, simulate the output of the power supply module on the PCB board with a DC voltage source, and the voltage value is the same as VCC.

[0044] Then, load the ECPM model and connect the Port at the chip VCC end in the S-parameters of the TSV silicon substrate to form the PDN full-path analysis circuit.

[0045] Preferably, when adding a parametric capacitance model to the PDN full-path analysis circuit, add a parametric capacitance model to all the Ports connecting capacitors in the PDN full-path analysis circuit.

[0046] Preferably, the parametric capacitance model includes an equivalent series resistance ESR, a capacitor C, and a parasitic inductance ESL connected in series in sequence. One end of the equivalent series resistance ESR is connected to the PDN full-path analysis circuit, and the parasitic inductance ESL is connected to GND. Among them, the capacitance value of the capacitor C is set as a variable parameter.

[0047] Preferably, when performing time-domain analysis and capacitance optimization on the PDN full-path analysis circuit with the added parametric capacitance model to obtain the final design scheme of the micro-system PDN decoupling network:

[0048] Select a set of capacitance values with the VCC voltage ripple noise less than the VCC noise tolerance and the positions of these capacitance values on the TSV silicon substrate, the package, and the PCB board as the final design scheme of the micro-system PDN decoupling network.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] In the process of micro-system PDN design, there are problems that it is difficult to achieve the optimal design with limited decoupling capacitors and it is difficult to guarantee the performance of the PDN full-path impedance design based on the constant target impedance design method. The present invention proposes a PDN design optimization method for chip-package-system (CPS) collaboration, which can achieve the optimal design of the PDN decoupling network and the low-noise design of the PDN full-path within a wide frequency band, greatly improving the reliability and stability of the micro-system power supply network. Description of the Drawings

[0051] Figure 1 Schematic diagram of the PDN three-dimensional interconnection structure in the present invention.

[0052] Figure 2 Full-path circuit structure of the PDN in the present invention.

[0053] Figure 3 PDN target impedance design method of the present invention.

[0054] Figure 4 General flow of the method for optimizing the decoupling network of the PDN of the microsystem based on CPS co-simulation in the present invention.

[0055] Figure 5 Method flow for extracting the chip ECPM in the present invention.

[0056] Figure 6 Power supply characteristics when the chip works in the present invention, and the power supply change parts expressed by CPM and ECPM.

[0057] Figure 7 Method flow for extracting the S-parameter model of the TSV silicon substrate PDN in the present invention.

[0058] Figure 8 Full circuit composed of the coupling model and the decoupling capacitor network of the PDN in the present invention.

[0059] Figure 9 Equivalent circuit structure of the capacitor to be optimized in the present invention.

[0060] Figure 10 Example of the implementation effect of the present invention. Specific implementation manners

[0061] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0062] The simulation and optimization methods of the present invention are applicable to the design and optimization of the filtering decoupling capacitor network of the power distribution network (PDN) in the microsystem within a wide frequency band. Among them, the PDN refers to the interconnection for supplying power to a certain power supply (VCC is used in the present invention) of the power-consuming chip, and the entire interconnection path from the power supply module to the VCC pin of the power-consuming chip, such as Figure 1 , including three levels of PDN, namely the PCB board PDN, the package PDN, and the TSV silicon substrate PDN. Each level of PDN interconnection includes planes, traces, and vias. The microsystem PDN is the part within the dotted box, including the package PDN and the TSV silicon substrate PDN.

[0063] In the following description, the power supply name of the PDN to be optimized is represented by VCC, and its corresponding reference ground is represented by GND.

[0064] Aiming at the problem that the constant target impedance cannot express the current change of the chip VCC power supply, resulting in over-design or difficult design of the PDN, the present invention proposes to model the voltage and current dynamic changes of the chip VCC power supply and the decoupling information on the die, and extract the ECPM (extended chip power model) model of the chip VCC. Aiming at the problem that the impedance of each layer of the PDN is analyzed independently, lacking coupling and the decoupling frequency range is difficult to determine, a method for constructing a full-circuit coupling model of the PDN and CPS co-simulation optimization is proposed.

[0065] Specifically, the general flow chart of the micro-system PDN decoupling network optimization method based on CPS co-simulation is as Figure 4 shown, including seven steps:

[0066] The first step is to extract the ECPM model of the chip VCC;

[0067] The second step is to extract the S-parameter model of the TSV silicon substrate PDN;

[0068] The third step is to extract the S-parameter model of the package PDN;

[0069] The fourth step is to extract the S-parameter model of the PCB board PDN;

[0070] The fifth step is to build a PDN full-path analysis circuit according to the ECPM model of the chip VCC, the S-parameter model of the TSV silicon substrate PDN, the S-parameter model of the package PDN, and the S-parameter model of the PCB board PDN;

[0071] The sixth step is to add a parametric capacitance model to the PDN full-path analysis circuit;

[0072] The seventh step is to perform time-domain analysis and capacitance optimization on the PDN full-path analysis circuit with the parametric capacitance model added to obtain the final design scheme of the micro-system PDN decoupling network. Output the capacitance values of the decoupling capacitance network that meet the VCC noise tolerance requirements. The specific methods of each step are described below.

[0073] The first step:

[0074] Aiming at the problem that the constant target impedance cannot express the current change of the chip VCC power supply, resulting in over-design or difficult design of the PDN, a method is proposed to model the voltage and current dynamic changes of the chip VCC power supply and the decoupling information on the die, and extract the ECPM (extended chip power model) model of the chip VCC. The method flow is as Figure 5 shown. For the VCC characteristics of the chip in high-frequency steady-state operation, such as Figure 6For the solid-line horizontal rectangular box part, based on the Ansys RedHawk tool, a CPM (chip power model) model is established; for the power supply characteristics when the chip switches between different operating states, such as Figure 6 For the dashed-line vertical rectangular box part, based on the Ansys CMA tool, the CPM model is modulated according to the chip Clock Gate information to establish an ECPM model, and the current change characteristics of the chip power supply across the entire frequency band are constructed. When extracting the CPM model, the chip VCC is divided into M×N regions, where M and N are determined by the VCC current requirements of different regions of the chip. The VCC die pads with basically the same current are divided into one region. M and N can be equal, with a minimum value of 1 and a maximum value equal to the number of VCC die pads, that is, each die pad is a separate region; the larger the values of M and N, the more refined the description of the CPM.

[0075] Step 2:

[0076] Extract the S-parameter model of the TSV silicon substrate PDN. The method flow is as Figure 7 . Based on electromagnetic field software, such as Ansys SIwave, import the layout design data of the TSV silicon substrate. At the chip end, according to the above M×N region division, within each region, group the VCC pins into a pin group and also group the GND pins into a pin group. Add a Port between each VCC pin group and the nearest GND pin group; similarly, divide the externally led VCC and GND of the TSV silicon substrate into M×N regions, form a VCC pin group and a GND pin group in each region respectively, and add a Port; add a Port indicating the location of the decoupling capacitor, which is divided into two cases: (1) When there is no capacitor on the TSV silicon substrate itself, evenly add M×N Ports around the chip on the TSV silicon substrate, with both ends of the Port connected to VCC and GND respectively; (2) When there are capacitors placed on the TSV silicon substrate itself, remove the capacitors and add a Port between the VCC pad and the GND pad of the capacitor; simulate and extract the S-parameter model, and output the TSV silicon substrate PDN*.sXp file, where X=(3×M×N) when there is no capacitor on the TSV silicon substrate, and X=(2×M×N + the number of capacitors) when there are capacitors placed on the TSV silicon substrate.

[0077] Step 3:

[0078] Extract the S-parameter model of the package PDN: The method flow is as Figure 7, based on electromagnetic field software, such as Ansys SIwave, import the package layout design data; at the TSV silicon substrate pin ends, according to the M×N area division, within each area, create pin groups for the VCC pins to obtain the VCC pin groups; create a pin group for the GND pins to obtain the GND pin groups; add Ports between each VCC pin group and the nearest GND pin group; secondly, create pin groups for the VCC and GND of the package external lead-out ends, and add Ports between the VCC pin group and the GND pin group; then, add Ports indicating the positions of the decoupling capacitors, which are divided into two cases: (1) when there is no capacitor on the package itself, evenly add M×N Ports around the TSV silicon substrate on the package, with both ends of the Port connected to VCC and GND respectively; (2) when there are capacitors placed on the package itself, remove the capacitors and add Ports between the VCC pads and GND pads of the capacitors; simulate and extract the S-parameter model, and output the *.sYp file of the package PDN. When there is no capacitor on the package, Y=(2×M×N + 1), and when there are capacitors placed on the package, X=(M×N + the number of capacitors + 1).

[0079] Step 4:

[0080] Extract the S-parameter model of the PCB PDN: The method process is as Figure 7 , import the PCB layout design data, at the micro-system module pin ends, create VCC pin groups and GND pin groups respectively, and add Ports; secondly, add Ports between the VCC and GND pins of the power supply module; then, add Ports indicating the positions of the decoupling capacitors; the focus of this patent lies in the optimization of the micro-system PDN decoupling network. It is considered that there are capacitors placed on the PCB itself, remove the capacitors, and add Ports between the VCC pads and GND pads of the capacitors; simulate and extract the S-parameter model, and output the *.sZp file of the PCB PDN, where Z=(the number of capacitors + 2).

[0081] Step 5:

[0082] Build a full-link coupling model of chip - package - system: Based on circuit analysis software, such as Ansys AEDTCircuit, load the above-mentioned S-parameter files, cascade the S-parameter models of each level in the order of PCB PDN, package PDN, and TSV silicon substrate PDN, and connect the corresponding Ports; use the DC voltage source in the circuit software library to simulate the output of the power supply module on the PCB, and the voltage value is the same as VCC; load the ECPM model and connect the Port at the chip VCC end in the TSV silicon substrate S-parameters. Form the PDN full circuit (except for the capacitor model) as Figure 8 shown.

[0083] Step 6:

[0084] In the above-mentioned PDN full circuit, at all Ports connected to capacitors, add a capacitor model as shown in Figure 9 . Each capacitor model includes an equivalent series resistance ESR, a capacitor C, and a parasitic inductance ESL connected in series in sequence. Among them, the equivalent series resistance ESR, the capacitor C, and the parasitic inductance ESL use the RLC model built in the circuit software. According to the package series of the capacitors to be used on the microsystem module and the PCB board, the magnitudes of the resistance and inductance are given; the capacitance value of the capacitor is set as a variable parameter, and the value is selected in the way of One per decade or Three per decade in the Multi-Pole (MP) method. One or three capacitance values are selected within each decade capacitance range. The capacitance value range of the TSV silicon substrate and the package capacitor covers 100 pF to 10 μF, and the capacitance value range of the PCB capacitor covers 10 nF to hundreds of μF.

[0085] Step 7:

[0086] At Figure 8 the VCC observation point shown, add a voltage Probe; perform a time-domain transient analysis, and perform a sweep analysis on the variable parameter of the capacitor capacitance value; select a set of capacitance values with the VCC voltage ripple noise less than the VCC noise tolerance and their positions on the TSV silicon substrate, the package, and the PCB board as the final design scheme of the PDN decoupling capacitor network.

[0087] Embodiment

[0088] This embodiment is a method for optimizing the PDN decoupling network of a microsystem based on CPS co-simulation, which is used for optimizing the power decoupling capacitors in a microsystem module designed based on a TSV silicon substrate and a package, so as to reduce the power supply ripple noise in the full frequency band of the PDN current change. This method has been applied to the development of multiple microsystem modules. Taking the processor core power supply CORE_1V2 of a microsystem module as an example, the implementation effect is described. CORE_1V2 is a 1.2V / 16A power supply. Based on the Ansys RedHawk and CMA tools, the chip CORE_1V2 and GND are processed as a whole, that is, M = N = 1 for the region division, and an ECPM model of CORE_1V2 is established; based on the Ansys SIwave software, the S parameters of the PDNs of the TSV silicon substrate, the HTCC package, and the test PCB are extracted respectively; based on the Ansys AEDT Circuit software, a PDN full-link structure is built, and the model and parametric capacitance value of the capacitor to be optimized are added; after the capacitor parameter sweep analysis, it is obtained that no capacitor is added on the TSV silicon substrate, 2 capacitors of 0.1 μF and 1 capacitor of 1 μF are added on the package, and 2 capacitors of 220 μF, 4 capacitors of 10 μF, and 10 capacitors of 0.1 μF are added on the PCB, so that the power supply noise is reduced by 60 mV compared with that before optimization, as shown in Figure 10 .

Claims

1. Method for optimizing decoupling network of micro-system PDN based on CPS co-simulation, characterized in that, it includes the following processes: Establish an ECPM model of the chip VCC; Extract the S-parameter model of the TSV silicon substrate PDN; Extract the S-parameter model of the package PDN; Extract the S-parameter model of the PCB board PDN; Build a PDN full-path analysis circuit according to the ECPM model of the chip VCC, the S-parameter model of the TSV silicon substrate PDN, the S-parameter model of the package PDN, and the S-parameter model of the PCB board PDN; Add a parametric capacitor model to the PDN full-path analysis circuit; Perform time-domain analysis and capacitor optimization on the PDN full-path analysis circuit with the parametric capacitor model added to obtain the final design scheme of the micro-system PDN decoupling network.

2. The method for optimizing the decoupling network of the micro-system PDN based on CPS co-simulation according to claim 1, characterized in that, The process of establishing the ECPM model of the chip VCC includes: Establish a CPM model of the chip; Modulate the CPM model according to the chip Clock Gate information for the power supply characteristics when the chip switches between different working states to establish the ECPM model of the chip VCC.

3. The method for optimizing the decoupling network of the micro-system PDN based on CPS co-simulation according to claim 2, characterized in that, When establishing the CPM model of the chip, divide the chip VCC into M×N regions, and divide the VCC die pads with the same current into one region; wherein, M and N are positive integers, the minimum value is 1, and the maximum value is the number of VCC die pads.

4. The method for optimizing the decoupling network of the micro-system PDN based on CPS co-simulation according to claim 3, characterized in that, The process of extracting the S-parameter model of the TSV silicon substrate PDN includes the following steps: First, at the chip end of the TSV silicon substrate layout, according to the M×N region division, in each region, create a pin group for the VCC pins to obtain the VCC pin group; create a pin group for the GND pins to obtain the GND pin group; add a Port between each VCC pin group and the nearest GND pin group. Secondly, divide the VCC and GND at the external lead-out end of the TSV silicon substrate into M×N regions respectively, form a VCC pin group and a GND pin group in each region, and add a port Port. Then, add a Port indicating the position of the decoupling capacitor; Finally, extract the S-parameter model and output the *.sXp file of the TSV silicon substrate PDN; wherein, when adding a Port indicating the position of the decoupling capacitor, it includes the following two situations: (1) When there is no capacitor on the TSV silicon substrate itself, evenly add M×N Ports around the chip on the TSV silicon substrate, and connect the two ends of the Port to VCC and GND respectively; (2) When there are capacitors placed on the TSV silicon substrate itself, remove the capacitors and add a Port between the VCC pad and the GND pad of the capacitor; When there is no capacitor on the TSV silicon substrate, in the *.sXp file of the TSV silicon substrate PDN, X = (3 × M × N); When capacitors are placed on the TSV silicon substrate, in the *.sXp file of the TSV silicon substrate PDN, X = (2 × M × N + the number of capacitors).

5. The method for optimizing the PDN decoupling network of a microsystem based on CPS co - simulation according to claim 3, characterized in that, The process of extracting the S - parameter model of the package PDN includes the following steps: First, at the pin ends of the TSV silicon substrate on the package layout, according to the M × N area division, within each area, create a pin group for the VCC pins to obtain the VCC pin group; create a pin group for the GND pins to obtain the GND pin group; add a Port between each VCC pin group and the nearest GND pin group. Second, form a VCC pin group for the VCC pins at the external lead - out end of the package and a GND pin group for the GND pins, and add a Port between the VCC pin group and the GND pin group. Then, add a Port indicating the location of the decoupling capacitor. Finally, extract the S - parameter model and output the *.sYp file of the package PDN; Among them, when adding a Port indicating the location of the decoupling capacitor, it includes the following two situations: (1) When there is no capacitor on the package itself, evenly add M × N Ports around the chip on the package, and connect the two ends of each Port to VCC and GND respectively; (2) When capacitors are placed on the package itself, remove the capacitors and add a Port between the VCC pad and the GND pad of the capacitor; When there is no capacitor on the package, in the *.sYp file of the package PDN, Y = (2 × M × N + 1); When capacitors are placed on the package, in the *.sYp file of the package PDN, Y = (M × N + the number of capacitors + 1).

6. The method for optimizing the PDN decoupling network of a microsystem based on CPS co - simulation according to claim 1, characterized in that, The process of extracting the S - parameter model of the PCB PDN includes the following steps: First, at the pin ends of the microsystem module on the PCB layout, form a VCC pin group and a GND pin group respectively, and add a Port. Second, add a Port between the VCC and GND pins of the power supply module. Then, add a Port indicating the location of the decoupling capacitor. Finally, extract the S - parameter model and output the *.sZp file of the PCB PDN, Z = (the number of capacitors + 2).

7. The method for optimizing the PDN decoupling network of a microsystem based on CPS co - simulation according to claim 1, characterized in that, The process of building the PDN full - path analysis circuit according to the ECPM model of the chip VCC, the S - parameter model of the TSV silicon substrate PDN, the S - parameter model of the package PDN, and the S - parameter model of the PCB PDN includes: First, cascade the S - parameter model of the PCB PDN, the S - parameter model of the package PDN, and the S - parameter model of the TSV silicon substrate PDN in the order of PCB PDN, package PDN, and TSV silicon substrate PDN, and connect the corresponding Ports; Then, a DC voltage source is used to simulate the output of the power supply module on the PCB board, and the voltage value is the same as VCC; Finally, the ECPM model is loaded, and the Port at the chip VCC end in the S-parameters of the TSV silicon substrate is connected to form the PDN full-path analysis circuit.

8. The method for optimizing the decoupling network of the PDN of the microsystem based on CPS co-simulation according to claim 1, characterized in that, when adding a parametric capacitor model to the PDN full-path analysis circuit, a parametric capacitor model is added to all the Ports connecting capacitors in the PDN full-path analysis circuit.

9. The method for optimizing the decoupling network of the PDN of the microsystem based on CPS co-simulation according to claim 1, characterized in that, the parametric capacitor model includes an equivalent series resistance ESR, a capacitor C, and a parasitic inductance ESL connected in series in sequence. One end of the equivalent series resistance ESR is connected to the PDN full-path analysis circuit, and the parasitic inductance ESL is connected to GND. Among them, the capacitance value of the capacitor C is set as a variable parameter.

10. The method for optimizing the decoupling network of the PDN of the microsystem based on CPS co-simulation according to claim 1, characterized in that, when performing time-domain analysis and capacitor optimization on the PDN full-path analysis circuit with the parametric capacitor model added to obtain the final design scheme of the microsystem PDN decoupling network: Select a set of capacitance values with the VCC voltage ripple noise less than the VCC noise tolerance and the positions of the capacitance values on the TSV silicon substrate, the package, and the PCB board as the final design scheme of the microsystem PDN decoupling network.

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