A method and system for reading output current of a storage and computing array supporting negative value excitation

Abstract

The present invention discloses a storage and calculation array output current reading method and system supporting negative excitation, and the system includes: a complement coding module, a control module, a current reversal module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module. The excitation is input bit by bit in the form of a binary complement, and the output current is converted to a voltage through a current reversal module and an accumulation module, and then read out through an activation module, a pooling module and a digital-to-analog conversion module. The use of complement coding can effectively represent negative excitations, avoiding the problem of low neural network reasoning accuracy caused by discarding negative excitations; the current reversal module is enabled when reading out the sign bit current, and the binary complement is converted to decimal in conjunction with the coding method, and the output current is accumulated in the analog domain, reducing the number of analog-to-digital conversions required for the readout process, thereby reducing the power consumption and delay of the readout system. Based on the above two points, the readout system of the present invention achieves more complete support for negative excitations.

Description

Technical Field

[0001] The invention relates to a storage and calculation array output current reading method and system supporting negative value excitation, belonging to the field of hardware implementation of neural network algorithms. Background Art

[0002] In recent years, the integrated storage and computing architecture has received widespread attention and research. The basic idea is to store some simple but data-intensive logical computing functions in the memory by storing weight mapping in the storage and computing array, so as to reduce the amount of data transmission and the transmission distance between the memory and the processor.

[0003] The operating principle of the classic non-volatile storage array is as follows Figure 1 As shown, to calculate the two multiplication matrices The values ​​of the weight matrix W are stored in the storage array in the form of conductance, and then the excitation The value of is input to the input end of the storage and calculation array in the form of voltage, and the calculation result in the form of current is obtained from the output end of the storage and calculation array. The readout system reads the output current of the storage and calculation array to complete the storage and calculation integration process. The storage and calculation integration architecture is also suitable for matrix operations and is very compatible with neural network algorithms. It is often used as the hardware implementation architecture of neural network algorithms.

[0004] With the development of neural network algorithms, negative inputs (stimuli of the current layer) and outputs (stimuli passed to the next layer) play an increasingly important role in training and reasoning. This development trend of neural network algorithms is also reflected in the application of activation functions: more and more activation functions with negative outputs, such as Tanh function, Leaky_Relu function, etc., are used to build network structures. This is because when the problems faced by the algorithm are more complex or the algorithm is used in certain feature areas, these negative values ​​carry some key information, which is indispensable for realizing the entire network function.

[0005] However, due to the difficulty of implementing binary representation of negative values ​​in the hardware domain, the existing storage array output current readout system cannot support negative excitation well. When facing possible negative excitation, the current readout system mainly has two processing methods as shown in Figure 2.

[0006] As shown in Figure 2(a), the first processing method is to simply replace the activation function with a non-negative output, such as replacing the Leaky_Relu function with the Relu function, to ensure that no negative excitation is passed to the next layer after passing through the activation function. This processing method avoids the problem of negative excitation, but essentially only discards the negative value and does not solve the problem of the need for negative value operations. When facing certain neural network algorithms applied to specific fields, the use of this processing method may result in poor network training results and low reasoning accuracy. From the perspective of interpretable deep learning, this is because simply discarding negative excitations causes too much information loss, while the neural network itself needs this part of information to update the network parameters. Therefore, this processing method is only applicable to a small number of scenarios and has considerable limitations.

[0007] As shown in Figure 2(b), the second processing method is to first convert the output result of the storage array through an analog-to-digital converter, and then process the negative excitation in the digital domain rather than the analog domain. The shortcomings of this processing method are: 1. Each bit of data needs to be converted to an analog-to-digital conversion, and too many analog-to-digital conversions will bring huge power consumption and a very high delay; 2. The digital domain itself is limited by binary, and the processing of negative values ​​is relatively complicated. The circuit implementation requires more logic units, resulting in an increase in circuit cost and area. Therefore, this processing method will seriously affect the circuit's energy efficiency ratio, computing power and other performance, and is not suitable for hardware implementation scenarios of large-scale neural networks. Summary of the invention

[0008] In order to solve the problem that the existing storage and computing array output current reading system cannot support negative value excitation well, resulting in poor training effect, low reasoning accuracy, high power consumption and other problems when the neural network algorithm is implemented in hardware, the present invention provides a storage and computing array output current reading method and system supporting negative value excitation.

[0009] The first object of the present invention is to provide a storage and calculation array output current reading method and system supporting negative value excitation, characterized in that the system comprises: a complement encoding module, a control module, a current reversal module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;

[0010] The current reversal module, the accumulation module, the activation module, the pooling module and the analog-to-digital conversion module are connected in sequence;

[0011] The control module is used to provide a control signal; the complement encoding module is used to convert the original excitation into a complement form and input it into the storage array; the current reversal module is used to achieve the reversal of the output current of the storage array; the accumulation module is used to accumulate the current bit by bit; the activation module is used to implement the activation function operation in the hardware implementation algorithm; the pooling module is used to implement the pooling operation in the hardware implementation algorithm; the analog-to-digital conversion module is used for the conversion between analog signals and digital signals. Optionally, the input excitation complement generated by the complement encoding module contains an N-bit value, including a 1-bit sign bit and N-1-bit data bits.

[0012] Optionally, the process of inputting the complement of the original stimulus into the storage array includes: inputting bit by bit, first inputting the lowest bit of the data bit, inputting each data bit in sequence from low to high, and finally inputting the sign bit.

[0013] Optionally, the control signal provided by the control module includes: an enable signal of a current reversal module.

[0014] Optionally, the enable signal of the current reversal module controls whether the current reversal module works, and the specific process includes:

[0015] When the data bit is input, the current reversal module is not enabled and does not work;

[0016] When a sign bit is input, a current reversal module is enabled, and the current reversal module works to reverse the output current of the storage and calculation array corresponding to the sign bit.

[0017] Optionally, the working process of the system includes:

[0018] S1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 sign bit and N-1 data bits;

[0019] S2: The two's complement form stimulus is input bit by bit into the storage array for calculation: first input the lowest bit of the data bit, then input each data bit from low to high, and finally input the sign bit;

[0020] S3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low bit of the data to the high bit of the data and then to the sign bit;

[0021] For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed;

[0022] For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed;

[0023] S4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained;

[0024] S5: V_out is passed to the analog-to-digital conversion module, converted into a digital code value and then output. If the output result needs to be passed to the lower layer network, the above process is repeated.

[0025] Optionally, the input excitation complement code is an 8-bit complement code.

[0026] The second object of the present invention is to provide a method for reading output current of a storage and computing array supporting negative value excitation, characterized in that the method is implemented based on the above-mentioned storage and computing array output current reading system supporting negative value excitation, and the method comprises:

[0027] Step 1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 bit sign bit and N-1 bits data bit;

[0028] Step 2: Input the complement code form stimulus bit by bit into the storage array for calculation: first input the lowest bit of the data, then input each data bit from low to high, and finally input the sign bit;

[0029] Step 3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low data bit to the high data bit and then to the sign bit;

[0030] For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed;

[0031] For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed;

[0032] Step 4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained;

[0033] Step 5: Pass V_out to the analog-to-digital conversion module, convert it into a digital code value and output it. If the output result needs to be passed to the lower network, repeat the above process.

[0034] The third object of the present invention is to provide a neural network computing device, characterized in that the device comprises:

[0035] A receiving port for receiving input stimulus;

[0036] Storage and calculation array; the above-mentioned storage and calculation array output current readout system supporting negative value excitation is used to output calculation results.

[0037] A fourth object of the present invention is to provide a neural network hardware system, characterized in that the hardware system comprises:

[0038] The neural network computing device described above;

[0039] A memory for storing input data;

[0040] A processor is used to read the input data from the memory and input the input data into the neural network computing device to calculate the input data.

[0041] Optionally, the memory is further used to: store a computer program;

[0042] The processor is also used to call the computer program from the memory to run the neural network computing device.

[0043] The beneficial effects of the present invention are:

[0044] Compared with the existing readout system solution, firstly, the excitation input to the storage and calculation array in the readout system of the present invention adopts the binary complement form, which can effectively represent negative values, thereby avoiding the problems of poor neural network training effect and low reasoning accuracy caused by discarding negative value excitations;

[0045] Secondly, the introduction of the current reversal module helps realize the process of converting the binary complement code to the decimal system in the hardware domain. The readout system of the present invention completes the accumulation of the array output current in the analog domain, reducing the number of analog-to-digital conversions required. For N-bit complement code form excitation, the existing scheme requires N analog-to-digital conversions, while the scheme of the present invention only requires one analog-to-digital conversion after the accumulation is completed, thereby reducing the power consumption and delay of the readout system. Based on the above two points, the readout system of the present invention realizes more complete support for negative value excitation.

[0046] In addition, the current reversal module introduced by the present invention can be realized by only a few MOS tubes, and the circuit cost is low. In addition, during the operation of the readout system, for each group of output currents, the reversal module only needs to work once, and the module power consumption is low. The control module additionally leads to a signal of only 1 bit for enabling the current reversal module, and the control timing is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic diagram showing the operating principle of a non-volatile storage and computing array is shown.

[0049] Figure 2 shows a block diagram of two processing methods of the existing readout system for negative excitation; Figure 2(a) is a block diagram of processing by replacing the activation function with no negative output, and Figure 2(b) is a block diagram of processing negative excitation in the digital domain through analog-to-digital conversion.

[0050] Figure 3 A block diagram of a readout system of the present invention is shown.

[0051] Figure 4 A circuit diagram of an 8T current reversal module according to an embodiment of the present invention is shown.

[0052] Figure 5 A flowchart of the reading system of the present invention is shown. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0054] Embodiment 1:

[0055] This embodiment provides a storage and calculation array output current readout system supporting negative value excitation, characterized in that the system includes: a complement encoding module, a control module, a current reversal module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;

[0056] The current reversal module, the accumulation module, the activation module, the pooling module and the analog-to-digital conversion module are connected in sequence;

[0057] The control module is used to provide a control signal; the complement encoding module is used to convert the original excitation into a complement form and input it into the storage and computing array; the current reversal module is used to achieve the reversal of the output current of the storage and computing array; the accumulation module is used to accumulate the current bit by bit; the activation module is used for the hardware implementation of the activation function operation in the algorithm; the pooling module is used for the hardware implementation of the pooling operation in the algorithm; the analog-to-digital conversion module is used for the conversion of analog signals and digital signals.

[0058] The readout system described in this embodiment uses the complement code as input at the input end of the storage and calculation array, which can effectively represent negative excitations, avoiding the problems of poor neural network training effect and low reasoning accuracy caused by discarding negative excitations; at the same time, during the system readout process, the accumulation of the storage and calculation array output current is completed in the analog domain, reducing the number of analog-to-digital conversions required. Combined with the complement code form excitation and the current inversion module, the system achieves good support for negative excitations.

[0059] Embodiment 2:

[0060] This embodiment provides a storage and calculation array output current readout system supporting negative value excitation, characterized in that the system includes: a complement encoding module, a control module, a current reversal module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;

[0061] The current reversal module, the accumulation module, the activation module, the pooling module and the analog-to-digital conversion module are connected in sequence;

[0062] The control module is used to provide control signals for the current reversal module, the accumulation module, the activation module, the pooling module, and the analog-to-digital converter;

[0063] The complement encoding module is used to convert the original stimulus into a complement form and input it into the storage array, and the input stimulus complement contains an N-bit value, including a 1-bit sign bit and N-1-bit data bits;

[0064] The process of inputting the complement code of the original stimulus into the storage array includes: inputting bit by bit, first inputting the lowest bit of the data bit, inputting each data bit in order from low to high, and finally inputting the sign bit.

[0065] The current reversal module is used to achieve the reversal of the output current of the storage and computing array; the circuit diagram of the current reversal module in this embodiment is shown in the attached figure. Figure 4 The enable signal of the current reversal module controls whether the current reversal module works, and the specific process includes:

[0066] When the data bit is input, the current reversal module is not enabled and does not work;

[0067] When a sign bit is input, a current reversal module is enabled, and the current reversal module works to reverse the output current of the storage and calculation array corresponding to the sign bit.

[0068] The accumulation module is used to accumulate the current bit by bit; the analog-to-digital conversion module is used to convert analog signals into digital signals.

[0069] The working process of the storage and calculation array output current reading system based on the current inversion module of this embodiment includes:

[0070] S1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 sign bit and N-1 data bits;

[0071] S2: The two's complement form stimulus is input bit by bit into the storage array for calculation: first input the lowest bit of the data bit, then input each data bit from low to high, and finally input the sign bit;

[0072] S3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low bit of the data to the high bit of the data and then to the sign bit;

[0073] For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed;

[0074] For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed;

[0075] S4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained;

[0076] S5: V_out is passed to the analog-to-digital conversion module, converted into a digital code value and then output. If the output result needs to be passed to the lower layer network, the above process is repeated.

[0077] The readout system described in this embodiment uses the complement code as input at the input end of the storage and calculation array, which can effectively represent negative excitations, avoiding the problems of poor neural network training effect and low reasoning accuracy caused by discarding negative excitations; at the same time, during the system readout process, the accumulation of the storage and calculation array output current is completed in the analog domain, reducing the number of analog-to-digital conversions required. Combined with the complement code form excitation and the current inversion module, the system achieves good support for negative excitations.

[0078] In addition, the current reversal module in this embodiment uses only 8 MOS tubes, and the circuit cost is low; during the operation of the readout system, the input current reversal module only needs to work once for each set of complementary code form excitation, and the module power consumption is low. The control module additionally leads to a signal of only 1 bit for enabling the current reversal module, and the control timing is simple.

[0079] Embodiment three:

[0080] This embodiment provides a method for reading output current of a storage computing array supporting negative value excitation. This embodiment is implemented based on the storage computing array output current reading system supporting negative value excitation of the second embodiment. The method of this embodiment includes the following steps:

[0081] Step 1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 bit sign bit and N-1 bits data bit;

[0082] Step 2: Input the complement code form stimulus bit by bit into the storage array for calculation: first input the lowest bit of the data, then input each data bit from low to high, and finally input the sign bit;

[0083] Step 3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low data bit to the high data bit and then to the sign bit;

[0084] For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed;

[0085] For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed;

[0086] Step 4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained;

[0087] Step 5: Pass V_out to the analog-to-digital conversion module, convert it into a digital code value and output it. If the output result needs to be passed to the lower network, repeat the above process.

[0088] Embodiment 4:

[0089] This embodiment provides a method and system for reading output current of a storage and calculation array supporting negative value excitation proposed by the present invention.

[0090] Take the multiplication of two 2*2 matrices as an example, calculate and The convolution result is:

[0091] Y=-2*3+0+2*5+0=4

[0092] Represent the matrix X in 4-bits complement form, as shown in the following four tables:

[0093] Sign bit:

[0094] 1 0 0 0

[0095] Data bit 2:

[0096] 1 0 0 0

[0097] Data bit 1:

[0098] 1 0 0 0

[0099] Data bit 0:

[0100] 0 0 1 1

[0101] The excitation signal is input bit by bit, and the operation is performed with the matrix W respectively, and the operation results of each bit are added. The operation results from the sign bit to the data bit 0 are: 3, 5, 3, 2 respectively.

[0102] After accumulation, the output result is: Out = 3*(-8)+5*4+3*2+2*1=4

[0103] It can be seen from the above calculation results that the convolution result calculated using the traditional mathematical calculation method is equal to the convolution result obtained using the method proposed in the present invention, so the correctness of the solution of the present invention can be verified.

[0104] Example 5: Verifying the feasibility of the readout system from a mathematical perspective

[0105] For ease of understanding, this embodiment uses two matrices of the size of the minimum matrix unit 2*2 as the operation object; uses 8-bit complement as the specific encoding form, which includes 1 sign bit and 7 data bits. In actual use, this readout system has no restrictions on the size of the matrix, and matrix operations of different sizes do not affect the feasibility of this solution. In actual use, this readout system has no restrictions on the number of coding bits, and the specific number of coding bits depends on the size of the operation parameters.

[0106] For any matrix and Convolution, the result is shown in the following formula (1):

[0107] Y=X 11 *W 11 +X 12 *W 12 +X 21 *W 21 +X 22 *W 22 (1)

[0108] When the elements in the matrix X are converted to two's complement, the base relationship is as shown in equation (2):

[0109] where b s Refers to the sign bit, b 0 ~b 6 Refers to data bits.

[0110] X=b s *(-2 7 )+b 6 *2 6 +b 5 *2 5 +b 4 *2 4 +b 3 *2 3 +b 2 *2 2 +b 1 *2 1 +b 0 *20 (2)

[0111] When the complement code is input bit by bit and accumulated, the output result is shown in the following formula (3):

[0112]

[0113]

[0114]

[0115] in, Point to X ij The xth position of Point to X 11 The sign bit of .

[0116] It can be seen from the above calculation results that formula (1) is equal to formula (3), which can verify the correctness of the calculation method of the present invention.

[0117] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage array output current readout system supporting negative value excitation, It is characterized in that The system comprises: a complement encoding module, a control module, a current reversal module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module; The current reversal module, the accumulation module, the activation module, the pooling module and the analog-to-digital conversion module are connected in sequence; The control module is used to provide a control signal; the complement encoding module is used to convert the original excitation into a complement form and input it into the storage array; the current reversal module is used to achieve the reversal of the output current of the storage array; the accumulation module is used to accumulate the current bit by bit; the activation module is used to implement the activation function operation in the hardware implementation algorithm; the pooling module is used to implement the pooling operation in the hardware implementation algorithm; the analog-to-digital conversion module is used to convert analog signals into digital signals; The working process of the system includes: S1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 sign bit and N-1 data bits; S2: The two's complement form stimulus is input bit by bit into the storage array for calculation: first input the lowest bit of the data bit, then input each data bit from low to high, and finally input the sign bit; S3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low bit of the data to the high bit of the data and then to the sign bit; For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed; For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed; S4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained; S5: Pass V_out to the analog-to-digital conversion module, convert it into a digital code value and output it. If the output result needs to be passed to the lower-level network, repeat the above process.

2. The system according to claim 1, It is characterized in that The input excitation complement code generated by the complement code encoding module includes an N-bit value, including a 1-bit sign bit and N-1-bit data bits.

3. The system according to claim 2, It is characterized in that The process of inputting the complement code of the original stimulus into the storage and calculation array includes: inputting bit by bit, first inputting the lowest bit of the data bit, inputting each data bit in sequence from low to high, and finally inputting the sign bit.

4. The system according to claim 3, It is characterized in that The control signal provided by the control module includes: an enable signal of the current reversal module.

5. The system according to claim 4, It is characterized in that The enable signal of the current reversal module controls whether the current reversal module works, and the specific process includes: When the data bit is input, the current reversal module is not enabled and does not work; When a sign bit is input, a current reversal module is enabled, and the current reversal module works to reverse the output current of the storage and calculation array corresponding to the sign bit.

6. A method for reading output current of a storage and computing array supporting negative excitation, It is characterized in that The method is implemented based on a storage and calculation array output current readout system supporting negative value excitation as described in any one of claims 1 to 5, and the method comprises: Step 1: The original stimulus is converted into a complementary code stimulus after passing through the complementary code encoding module. The code width of the complementary code is N bits, including 1 bit sign bit and N-1 bits data bit; Step 2: Input the complement code form stimulus bit by bit into the storage array for calculation: first input the lowest bit of the data, then input each data bit from low to high, and finally input the sign bit; Step 3: Process the output current of the storage array bit by bit, and accumulate the output current in the accumulation module in the order from the low data bit to the high data bit and then to the sign bit; For the output current corresponding to N-1 data bits, the current reversal module is not enabled, and the output current is not reversed; For the output current corresponding to 1 sign bit, the current reversal module is enabled, and the output current flows into the accumulation module after being reversed; Step 4: After all data bits and sign bits are accumulated, the accumulated value is passed to the subsequent activation module and pooling module. After activation and pooling processing, the operation result V_out of this layer network is obtained; Step 5: Pass V_out to the analog-to-digital conversion module, convert it into a digital code value and output it. If the output result needs to be passed to the lower-level network, repeat the above process.

7. A neural network computing device, It is characterized in that include: A receiving port for receiving input stimulus; Storage and computing array; A storage and calculation array output current readout system supporting negative value excitation as described in any of claims 1-5 is used to output calculation results.

8. A neural network hardware system, It is characterized in that include: The neural network computing device as claimed in claim 7; A memory for storing input data; A processor is used to read the input data from the memory and input the input data into the neural network computing device to calculate the input data.

9. The neural network hardware system according to claim 8, It is characterized in that The memory is also used to: store computer programs; The processor is also used to call the computer program from the memory to run the neural network computing device.

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