An ultrashort channel VSe2-WSe2 two-dimensional material and its preparation and application

Abstract

The present invention belongs to the field of two-dimensional material preparation and device performance research, and specifically discloses a method for manufacturing an ultra-short channel WSe2 field-effect transistor using a non-photolithography method. The steps are: VCl3 raw material is volatilized at a volatilization temperature of 530-580°C, and Se raw material is volatilized at a volatilization temperature of 360-380°C; the volatilized raw materials are reacted and deposited on the surface of the WSe2 two-dimensional material with a carrier gas and a deposition temperature of 600-620°C, followed by cooling. The grain boundaries of the deposited adjacent VSe2 are cracked to form an ultra-short channel, thereby obtaining the ultra-short channel VSe2-WSe2 two-dimensional material. The present invention also includes materials obtained by the method and applications of the materials. The method of the present invention, through the combined control of the materials and processes, can unexpectedly obtain narrow channel materials without photolithography, and devices made from the materials obtained by the method have better performance.

Description

Technical Field

[0001] The present invention belongs to the field of nanomaterials, and specifically relates to ultrashort channel VSe2-WSe2 two-dimensional materials. Technical Background

[0002] Two-dimensional semiconductors (2DSCs) derived from layered transition metal dichalcogenides (TMDs) (e.g., MoS2, WSe2) have attracted considerable interest as atomically thin channels for ultimate transistor scaling due to their excellent immunity to short-channel effects. 1-3 2DSCs typically have a dangling bond-free surface and exhibit little degradation in mobility (μ) when decreasing the bulk thickness (tb), in stark contrast to conventional 3D semiconductors where carrier mobility decreases with tb. b (μ~t b 6 ), which represents a key fundamental limitation for continued transistor scaling to the sub-10nm channel length regime. 4,5 In this regard, although multilayer TMDs may not exhibit competitive performance advantages (e.g., high carrier mobility) compared to 3D bulk semiconductors such as Si or GaAs, single-layer or few-layer 2D-TMDs have shown promising performance in the sub-3 nm bulk thickness regime. 5 , which is crucial for continued transistor scaling 3,6,7 In particular, in the limit t b Maintaining high electronic performance at confinement (<1.0nm) could enable transistors with gate lengths below 10nm or below 5nm with low leakage current, which is difficult to achieve with silicon electronics, even using state-of-the-art Fin-FET designs.

[0003] However, despite extensive effort and numerous proof-of-concept demonstrations of different 2D-TMDs in a vast literature that frequently reports high carrier mobility or low contact resistance, the technological potential of 2D-TMDs remains elusive. Whether and how 2D transistors can match, compete with, or surpass silicon transistors is currently an open question. Two recent perspectives from academia and industry clearly illustrate the exciting opportunities and associated challenges of 2D transistors. It is pointed out that many commonly used evaluation parameters (e.g., carrier mobility, contact resistance) are highly derived values ​​that can often be misestimated or misinterpreted, resulting in considerable uncertainty in many key device parameters reported to date. These technical uncertainties have led to ambiguous and sometimes contradictory claims, raising questions about the potential advantages of 2D-TMDs. For example, frequently claimed high mobility or low contact resistance are often not fully supported by improved current density or total resistance.

[0004] To resolve this ambiguity and to convincingly demonstrate the full potential of 2D-TMDs in functional transistors, it has been suggested that the on-state current density (I on ) or saturation current density can provide a more direct and reliable measure for evaluating the actual potential of 2DSCs and properly benchmarking them with silicon transistors. In particular, I on is a key parameter that directly determines the transistor speed and intrinsic gate delay (τ=(CV on ) / I on =CR on ), where C is the gate capacitance, V on is the bias voltage, R on (ON-state resistance). In this regard, R on It is also an important performance parameter for evaluating the intrinsic potential of a given channel material. Importantly, compared to mobility or contact resistance, I on or R on is a directly measured parameter with minimal derivative and associated uncertainty, and therefore represents a more reliable and practically more relevant parameter for measuring the potential of 2D transistors.

[0005] In general, the ion channel length (L ch ) and drain-source bias (V ds ) are still inferior to silicon devices when compared to single-layer materials, which poses a key obstacle to their practical application. In addition, it is also noted that the highest current densities reported in 2D-TMDs are generally multilayer materials (thickness>3nm). This is not surprising considering that thicker materials generally have smaller band gaps and are more immune to fabrication-induced damage or interface scattering compared to single-layer materials. However, the use of multilayer channels defeats the purpose of 2D transistors: to use atomically thin bodies to overcome scaling limitations. Therefore, in order to fully exploit the advantages of 2D-TMDs, it is important to focus on thinner 2D channels, ideally single or double layers, where 2DSCs may provide significant advantages. To the best of our knowledge, the highest ion reported in single / double-layer TMDs at room temperature is 1.135mA / μm for single-layer MoS2 transistors (at L ch =35nm and V ds =5.0V), and 0.90mA / μm double-layer WSe2 transistor (L ch =1,800nm ​​and V ds =7.5V), for this reason, a set of 1.0mAμm has been proposed for 2D transistors -1 、1.5mAμm -1 and 3.0mAμm -1 In particular, 1.5mAμm -1The key goal marks the tipping point at which 2D transistors may begin to show competitive performance with silicon devices.

[0006] References

[0007] 1. Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).

[0008] 2.Wang,H.et al.Integrated circuits based on bilayer MoS2transistors.Nano Lett.12,4674–4680(2012).

[0009] 3.Huang,J,K.et al.Large-area synthesis of highly crystallineWSe2monolayers and device applications.ACS Nano 8,923–930(2014).

[0010] 4. Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 1, 16052 (2016).

[0011] 5. Liu, Y. et al. Two-dimensional transistors beyond graphene and TMDCs. Chem. Soc. Rev. 47, 6388–6409 (2018).

[0012] 6. Liu, H., Neal, AT&Ye, PDCChannel length scaling of MoS2MOSFETs. ACSNano 6, 8563–8569 (2012).

[0013] 7. Kappera, R. et al. Phase-engineered low-resistance contacts for ultrathin MoS2 transistors. Nat. Mater. 13, 1128–1134 (2014). Summary of the Invention

[0014] The first purpose of the present invention is to provide a method for preparing an ultra-short channel VSe2-WSe2 two-dimensional material, aiming to provide a VSe2-WSe2 two-dimensional material that can obtain an ultra-short channel without the need for photolithography.

[0015] The second purpose of the present invention is to provide an ultra-short channel VSe2-WSe2 two-dimensional material prepared by the preparation method.

[0016] The third purpose of the present invention is to provide the application of the ultra-short channel VSe2-WSe2 two-dimensional material in the preparation of VSe2 contact ultra-short channel WSe2 field effect transistors.

[0017] Currently, the preparation of narrow channels is usually achieved through photolithography, which can damage the underlying two-dimensional material. To solve this problem, the present invention provides the following solution:

[0018] A method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material without photolithography: VCl3 raw material is volatilized at a volatilization temperature of 530-580°C, and Se raw material is volatilized at a volatilization temperature of 360-380°C; the volatilized raw materials are reacted and deposited on the surface of the WSe2 two-dimensional material at a deposition temperature of 600-620°C using a carrier gas, and then cooled, so that the grain boundaries of adjacent deposited VSe2s are cracked to form an ultrashort channel, thereby preparing the ultrashort channel VSe2-WSe2 two-dimensional material;

[0019] The planar size of the WSe2 two-dimensional material is greater than or equal to 80 μm;

[0020] The carrier gas is a mixture of hydrogen and protective gas, wherein the flow rate of the protective gas is 80 to 130 sccm and the flow rate of H2 is 1 to 4 sccm;

[0021] The mass ratio of VCl3 and Se is 1:0.5~2.

[0022] The present invention unexpectedly discovered that under the joint control of the material ratio, volatilization temperature, carrier gas, substrate and deposition temperature, the grain boundaries of adjacent VSe2 grown on the surface of WSe2 two-dimensional material will crack to form ultra-short channels, thereby constructing ultra-short channels less than or equal to 100nm or even as low as 10nm without the need for photolithography. The ultra-short channel material constructed by this method can exhibit excellent performance.

[0023] In the present invention, the adaptation of the VSe2 and WSe2 materials and the combined coordination of the volatilization temperature, carrier gas, substrate and deposition temperature are the key to achieving ultra-short channel construction without photolithography.

[0024] In the present invention, the VCl3 can be a powder material.

[0025] Maintaining an appropriate mass ratio of VCl3 to Se powder facilitates the production of ultrashort-channel WSe2. The study also found that when the quality of the raw Se powder is relatively high, thicker and larger VSe2 nanosheets are more readily obtained, while ultrashort WSe2 transistors with VSe2 contacts are more difficult to obtain.

[0026] Preferably, the mass ratio of VCl3 to Se powder is 1:0.5-1; more preferably, it is 1:0.5-0.6.

[0027] The inventors have also found through extensive research that by controlling the VCl3 and Se powder in an optimal ratio, a short-channel VSe2-WSe2 transistor with a more regular morphology, adjacent VSe2 products and a channel width less than 100 nm can be obtained.

[0028] In the present invention, the volatilization temperature of the raw materials has a great influence on the successful preparation of VSe2 two-dimensional materials.

[0029] The study found that when the VCl3 raw material temperature (the volatilization temperature of VCl3) is higher than the upper limit of the selected range, the generated VSe2 is less and thicker, and basically no adjacent VSe2 nanosheets are produced, so ultra-short channel WSe2 transistors cannot be obtained.

[0030] More preferably, the volatilization temperature of VCl3 is 530-540°C, and even more preferably 530-535°C.

[0031] Preferably, the volatilization temperature of the Se powder is 370-380°C, more preferably 375-380°C. Within this temperature range, the grown VSe2 is thick and has a regular hexagonal morphology, with uniform cracking at the grain boundaries of adjacent VSe2. This makes it easier to obtain ultra-short channel WSe2 transistors.

[0032] Further research also found that the size of WSe2 affects the epitaxial growth of VSe2. WSe2 with a size greater than or equal to 80μm helps the deposition of adjacent VSe2 nanosheets, thereby generating an ultrashort channel.

[0033] Preferably, the planar size of WSe2 is preferably 100 to 500 μm.

[0034] In the present invention, in the carrier gas, the protective gas is preferably at least one of nitrogen and an inert gas, such as argon.

[0035] Research has shown that using a carrier gas mixed with hydrogen and further controlling the flow rate and ratio are conducive to the successful preparation of VSe2 two-dimensional materials and the preparation of ultrashort channel VSe2-WSe2.

[0036] The inventors found that when preparing ultrashort channel WSe2 contacted with VSe2, under appropriate growth temperature and carrier gas flow rate, it helps to improve the morphology of the prepared VSe2 nanosheets, control the thickness of the nanosheets, and improve the width of the cracks between adjacent VSe2 grain boundaries of the material.

[0037] Preferably, the flow rate of the shielding gas in the carrier gas is 80-110 sccm, more preferably 100-105 sccm. The flow rate of H2 is 2-3 sccm. Studies have found that this flow rate helps improve crystallinity and facilitates the production of ultra-narrow channel materials.

[0038] The volatilized raw materials are reacted at a suitable deposition temperature under the carrier gas and deposited on the substrate surface. The appropriate deposition temperature helps to successfully prepare ultra-short channel WSe2 transistors with VSe2 contacts. Studies have found that if the growth temperature is too high (for example, higher than the upper limit of the range required by the present invention), the resulting VSe2 density is low and very thick, reaching the micron level; below the lower limit of the temperature, the resulting VSe2 nanosheets are small in quantity and irregular in shape. This affects the preparation of ultra-short channel WSe2 with VSe2 contacts.

[0039] Preferably, the deposition temperature is 605-615°C, more preferably 605-610°C.

[0040] Preferably, the deposition time is 3 to 6 minutes, more preferably 4 to 5 minutes.

[0041] Preferably, the cooling may be natural cooling or accelerated cooling.

[0042] Preferably, the deposition substrate is SiNx / Si.

[0043] The preferred preparation method of the ultrashort channel VSe2-WSe2 two-dimensional material of the present invention is as follows: the transition metal VCl3 raw material is volatilized at a volatilization temperature of 530-580°C (preferably 530-540°C) and the Se raw material is volatilized at a volatilization temperature of 360-380°C (preferably 370-380°C); the volatilized raw materials react and deposit and grow on the WSe2 surface at a mixed carrier gas flow rate of 80-130sccm of protective gas and 1-4sccm of hydrogen and a WSe2 deposition temperature of 605-620°C (preferably 605-610°C); when VSe2 is epitaxially grown on WSe2, the grain boundaries of adjacent VSe2 will crack with changes in temperature, and the grain boundaries of VSe2 can be precisely and controllably widened to a scale of several nanometers according to parameters such as temperature, thereby preparing the ultrashort channel VSe2-WSe2 two-dimensional material and then preparing the ultrashort channel WSe2 field effect transistor with VSe2 as the contact electrode.

[0044] The present invention also provides an ultrashort channel VSe2-WSe2 two-dimensional material prepared by the preparation method.

[0045] The ultrashort channel VSe2-WSe2 two-dimensional material prepared by the present invention includes a WSe2 two-dimensional material substrate and a VSe2 two-dimensional material vertically deposited on its surface. The VSe2 two-dimensional material has a hexagonal or approximately hexagonal morphology, and the nano-width of the cracks at the merged VSe2 grain boundaries has an ultrashort channel less than or equal to 100nm.

[0046] The present invention also provides an application of the ultra-short channel VSe2-WSe2 two-dimensional material, which is used to prepare a VSe2 contact ultra-short channel WSe2 field effect transistor.

[0047] In the present invention, the VSe2-WSe2 two-dimensional material of the present invention can be made into a VSe2-contacted ultra-short channel WSe2 field-effect transistor using existing means. For example, after exposing and marking the surface of the ultra-short channel VSe2-WSe2 two-dimensional material, metal is deposited on the surface to produce the VSe2-contacted ultra-short channel WSe2 field-effect transistor.

[0048] The metal is preferably Cr and Au, and the metal is preferably deposited by vacuum coating.

[0049] The present invention also provides a VSe2 contact ultra-short channel WSe2 field effect transistor, comprising a back gate substrate, the ultra-short channel VSe2-WSe2 two-dimensional material deposited on the surface of the back gate substrate, and Cr and Au film electrodes deposited on the surface of the ultra-short channel VSe2-WSe2 two-dimensional material.

[0050] There is no special requirement for the back gate substrate, and it can be, for example, 75nm SiNx / Si.

[0051] The VSe2 contact ultra-short channel WSe2 field effect transistor described in the present invention can be endowed with excellent electrical properties thanks to the non-photolithographic ultra-short channel material.

[0052] In the present invention, the VSe2-contacted ultrashort-channel WSe2 field-effect transistor can be prepared using existing methods. For example, the preparation process includes electron beam exposure on VSe2 nanosheets of ultrashort-channel VSe2-WSe2 two-dimensional material prepared by CVD, followed by metal deposition, to obtain a VSe2-contacted ultrashort-channel WSe2 field-effect transistor. This method is simple to operate and has good reproducibility.

[0053] Preferably, metal is deposited on the ultrashort channel WSe2 two-dimensional material contacted with VSe2 by a vacuum coating machine;

[0054] Preferably, the metal is Cr / Au.

[0055] More preferably, the thickness of Cr is 10 nm; the thickness of Au is 50 nm.

[0056] The present invention also includes an electrical application of the ultra-short channel WSe2 two-dimensional material with the VSe2 contact obtained.

[0057] Beneficial effects

[0058] 1. The present invention has discovered an unexpected compatibility between VSe2 and WSe2. When VSe2 is grown on a WSe2 surface under the combined conditions specified in the present invention, grain boundary cracking unexpectedly occurs during cooling. This allows for the production of ultrashort channel VSe2-WSe2 materials with a channel width of less than or equal to 100 nm without photolithography. The material produced by the present invention exhibits uniform morphology, controllable thickness, good crystallinity, and adjustable channel width.

[0059] 2. The narrow WSe2 channel prepared by the present invention can have a channel width controlled below 100nm and is straight. This method can be used to prepare WSe2 field-effect transistors with a metal VSe2 contact channel width less than 100nm. The present invention can obtain ultrashort transistors on atomically thin 2DSC WSe2 channels without conventional photolithography or metallization processes. The resulting sub-100nm double-layer WSe2 transistor can easily provide an ultra-high on-state current density exceeding 1.00mA / μm at a bias voltage of approximately 1.0V or less. In particular, at room temperature, a highest on-state current density of 1.72mA / μm and a lowest linear resistance of 0.50kΩ·μm were achieved in a 20nm long, 1.3nm thick double-layer WSe2 transistor. This breakthrough, for the first time, breaks through the performance limitations of 2D transistors and delivers a current density exceeding the critical target of 1.5 mA / μm. This demonstrates that atomically thin 2D transistors can achieve competitive on-state current density with silicon devices, highlighting the enormous potential of 2DSCs for future electronic products. The preparation process of this invention eliminates the need for complex steps or expensive raw materials, resulting in simple equipment, easy operation, and excellent reproducibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 Schematic diagram of the atmospheric pressure chemical vapor deposition apparatus for preparing ultrashort channel WSe2 contacts with VSe2;

[0061] Figure 2 This is an optical schematic diagram of preparing VSe2 contact with ultrashort channel WSe2 in Example 1-1;

[0062] Figure 3 Optical schematic diagram of preparing VSe2 contact with ultrashort channel WSe2 for Example 1-2;

[0063] Figure 4 Optical schematic diagram of preparing VSe2 contact with ultrashort channel WSe2 in Example 1-3;

[0064] Figure 5 Optical schematic diagram of preparing VSe2 contact with ultrashort channel WSe2 in Example 1-4;

[0065] Figure 6 This is an optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 in Comparative Example 1-1;

[0066] Figure 7 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative example 1-2;

[0067] Figure 8 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative examples 1-3;

[0068] Figure 9 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative examples 1-4;

[0069] Figure 10 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative examples 1-5;

[0070] Figure 11 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative examples 1-6;

[0071] Figure 12 Optical schematic diagram of the preparation of VSe2 contacting ultrashort channel WSe2 for comparative examples 1-7;

[0072] Figure 13 This is a picture of the preparation of the VSe2 contact ultra-short channel WSe2 field effect transistor in Example 2-1

[0073] Figure 14 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in implementation case 2-1.

[0074] Figure 15 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in implementation case 2-2.

[0075] Figure 16 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in implementation case 2-3.

[0076] Figure 17 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in implementation case 2-4.

[0077] Figure 18 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in comparative example 2-1.

[0078] Figure 19 The electrical output and transfer characteristic curves of the VSe2 contact WSe2 field effect transistor in comparative example 2-2. Specific implementation methods

[0079] Example 1-1

[0080] A porcelain boat containing VCl3 powder and Se powder in a mass ratio of 1:0.5 is placed in the transition temperature zone and the left constant temperature zone T1 of the tube furnace respectively. A 70nm SiNx / Si with WSe2 nanosheets (size 80μm and above) is placed on another porcelain boat as the growth substrate of VSe2 and placed in the variable temperature zone T2 of the tube furnace to obtain an appropriate crystal growth temperature. Before heating, the air in the quartz tube is exhausted with a large flow of argon. Then the temperature is controlled so that the temperature of the center of the left Se powder is 380℃ (T1: Se volatilization temperature), and the center of the right WSe2 / SiNx is 380℃ (T1: Se volatilization temperature). X The deposition temperature of / Si is 605℃ (T2), VCl3 is located at the transition point between the left and right temperature zones (VCl3 volatilization temperature, 530℃), the argon flow rate is 100sccm, and the hydrogen flow rate is 3sccm. The temperature is kept constant for 4 minutes and the furnace is cooled. Adjacent VSe2 nanosheets will crack on the WSe2 substrate to form narrow channels. 100 samples were randomly selected for channel statistics. The average channel width is 19±14nm, and the narrowest channel can reach less than 10nm. The experimental device of VSe2 nanosheet is shown in the figure below. Figure 1 As shown in the figure, the optical photograph of the prepared narrow channel nanosheet is as follows Figure 2 shown.

[0081] Figure 2 Optical schematic diagram of the prepared VSe2 nanosheets and the corresponding SEM image characterization, Figure 2 In a (left figure), point 1 represents WSe2, and point 2 represents the grown VSe2. The VSe2 nanosheets obtained under this condition have good crystallinity. Point 3 represents the slight cracks at the adjacent VSe2 grain boundaries. Its SEM image ( Figure 2 b) shows a channel width of 10 nm. Figure 2 c is the statistical graph of nanogap width of 100 randomly selected samples.

[0082] Example 1-2

[0083] Compared to Example 1-1, the only difference is that the temperature of the WSe2 nanosheets was 610°C (deposition temperature), the argon flow rate was 100 sccm, and the hydrogen flow rate was 3 sccm for 4 minutes. Channel statistics were conducted on 100 randomly selected samples of adjacent VSe2 nanosheets deposited on the WSe2 substrate, and the average channel width was 47±18 nm. Figure 3 The optical schematic diagram of VSe2 nanosheets prepared on WSe2 / SiNx / Si substrate. In Figure a, 1 represents WSe2, and 2 represents the grown VSe2. The VSe2 nanosheets obtained under this condition have good crystallinity. 3 represents the slight cracks at the adjacent VSe2 grain boundaries. Its SEM image ( Figure 3 b) shows that the channel width is 33 nm. Figure 3c is the statistical graph of nanogap width of 100 randomly selected samples.

[0084] Examples 1-3

[0085] Compared to Example 1-1, the only difference is that the temperature of the WSe2 nanosheets was 615°C (deposition temperature), the argon flow rate was 100 sccm, and the hydrogen flow rate was 3 sccm for 4 minutes. Channel statistics were conducted on 100 randomly selected samples of adjacent VSe2 nanosheets deposited on the WSe2 substrate, and the average channel width was 66±19 nm. Figure 4 It can be seen from a that the VSe2 nanosheets have good crystallinity and slight cracks at the adjacent VSe2 grain boundaries. The VSe2 nanosheets obtained under this condition have good crystallinity and thick thickness. Its SEM image ( Figure 4 b) shows a channel width of 77 nm.

[0086] Examples 1-4

[0087] Compared to Example 1-1, the only difference is that the temperature of the WSe2 nanosheets was 620°C (deposition temperature), the argon flow rate was 100 sccm, and the hydrogen flow rate was 3 sccm for 4 minutes. Channel statistics were conducted on 100 randomly selected samples of adjacent VSe2 nanosheets deposited on the WSe2 substrate, and the average channel width was 91±28nm. Figure 5 Schematic diagram of the optical structure of VSe2 nanosheets prepared on WSe2 / SiNx / Si substrate, Figure 5 As shown in a, the obtained VSe2 nanosheets have good crystallinity and slight cracks at the adjacent VSe2 grain boundaries. The VSe2 nanosheets obtained under this condition have good crystallinity and are relatively thick. Its SEM image b shows that the average channel width is 95nm. Figure 5 c is the statistical graph of nanogap width of 100 randomly selected samples.

[0088] Examples 1-5

[0089] Compared to Example 1-1, the only difference is that the mass ratio of Se and VCl3 powders is 1:1. The temperature is then controlled to maintain 380°C (Se volatilization temperature) for the Se powder, 580°C (Volatilization temperature) for the VCl3, and 605°C (deposition temperature) for the WSe2 nanosheets. Argon flow rates are 100 sccm, and hydrogen flow rates are 3 sccm. The temperature is maintained constant for 4 minutes. Nanocracks at the grain boundaries of adjacent VSe2 nanosheets deposited on a WSe2 / SiNx / Si substrate are sub-100 nm wide.

[0090] Examples 1-6

[0091] Compared to Example 1-1, the only difference is that the temperature of the WSe2 nanosheets was 605°C (deposition temperature), the argon flow rate was 80 sccm, and the hydrogen flow rate was 3 sccm for 4 minutes. The nanocracks at the grain boundaries of adjacent VSe2 nanosheets deposited on the WSe2 / SiNx / Si substrate were sub-100 nm wide.

[0092] Examples 1-7

[0093] Compared to Example 1-1, the only difference is that the temperature of the WSe2 nanosheets was 605°C (deposition temperature), the argon flow rate was 130 sccm, and the hydrogen flow rate was 3 sccm for 4 minutes. The nanocracks at the grain boundaries of adjacent VSe2 nanosheets deposited on the WSe2 / SiNx / Si substrate were less than 100 nm wide.

[0094] Examples 1-8

[0095] Compared to Example 1-1, the only difference was that the temperature of the Se powder was set at 360°C (Se volatilization temperature), the temperature of the VCl3 was set at 580°C (VCl3 volatilization temperature), and the temperature of the WSe2 nanosheets was set at 605°C (deposition temperature). The argon flow rate was 100 sccm, and the hydrogen flow rate was 3 sccm, and the temperature was maintained constant for 4 minutes. Nanocracks at the grain boundaries of adjacent VSe2 nanosheets deposited on the WSe2 / SiNx / Si substrate were sub-100 nm.

[0096] Examples 1-9

[0097] Compared to Example 1-1, the only difference was that the temperature of the Se powder was set at 370°C (Se volatilization temperature), the temperature of the VCl3 was set at 580°C (VCl3 volatilization temperature), and the temperature of the WSe2 nanosheets was set at 605°C (deposition temperature). The argon flow rate was 100 sccm, and the hydrogen flow rate was 3 sccm, and the temperature was maintained constant for 4 minutes. The nanocracks at the grain boundaries of adjacent VSe2 nanosheets deposited on the WSe2 / SiNx / Si substrate were sub-100 nm.

[0098] Comparative Example 1-1

[0099] Compared with Example 1-1, the only difference is that the temperature of the WSe2 nanosheet is 630℃ (deposition temperature), the argon flow rate is 100 sccm, and the hydrogen flow rate is 3 sccm for 4 minutes. Adjacent VSe2 nanosheets deposited on the WSe2 substrate. Figure 6 Optical schematic diagram of VSe2 nanosheets prepared on WSe2 / SiNx / Si substrate. Figure 6The medium yellow block represents the grown VSe2. The VSe2 nanosheets obtained under this condition have good crystallinity, and obvious cracks can be observed at the VSe2 grain boundaries. The VSe2 nanosheets obtained under this condition have good crystallinity and are relatively thick, but the width is relatively wide, all above 100 nm.

[0100] Comparative Example 1-2

[0101] Compared with Example 1-1, the only difference is that the deposition temperature is 580° C., the argon flow rate is 100 sccm, the hydrogen flow rate is 3 sccm, and the deposition time is 4 minutes. Figure 7 This is an optical schematic diagram of VSe2 nanosheets prepared on WSe2 / SiNx / Si substrate. 1 represents WSe2 and 2 represents the grown VSe2. The VSe2 nanosheets obtained under this condition have poor crystallinity, are thin, and have irregular shapes, making it difficult to form narrow channels.

[0102] Comparative Examples 1-3

[0103] Compared with Example 1-1, the differences are that the mass ratio of VCl3 and Se powder is 1:0.5, the growth temperature is 605°C, the argon flow rate is 60 sccm, the hydrogen flow rate is 3 sccm, and the deposition time is 4 min. Figure 8 This is an optical schematic diagram of VSe2 nanosheets prepared on a WSe2 / SiNx / Si substrate. In the figure, 1 represents WSe2 and 2 represents the grown VSe2. Under this condition, the nucleation density of VSe2 obtained is low, and it is not easy to obtain VSe2 nanosheets with adjacent grain boundaries.

[0104] Comparative Examples 1-4

[0105] Compared with Example 1-1, the differences are that the mass ratio of VCl3 and Se powder is 1:0.5, the growth temperature is 605°C, the argon flow rate is 140 sccm, the hydrogen flow rate is 3 sccm, and the deposition time is 4 min. Figure 9 This is an optical schematic diagram of VSe2 nanosheets prepared on WSe2 / SiNx / Si substrate, where 1 represents WSe2 and 2 represents the grown VSe2. Under this condition, the nucleation density of VSe2 obtained is high, but the shape of VSe2 at adjacent grain boundaries is irregular.

[0106] Comparative Examples 1-5

[0107] Compared with Example 1-1, the difference is that the mass ratio of Se and VCl3 powder is greater than 2:1 (such as 3:1), the growth temperature is 605°C, the argon flow rate is 100 sccm, the hydrogen flow rate is 3 sccm, and the deposition time is 4 minutes. Figure 10This is an optical schematic diagram of VSe2 nanosheets prepared on a WSe2 / SiNx / Si substrate, where 1 represents WSe2 and 2 represents the grown VSe2. Under these conditions, the VSe2 nucleation density will decrease, the VSe2 will be thicker, and it will not be easy to form adjacent VSe2.

[0108] Comparative Examples 1-6

[0109] Compared with Example 1-1, the difference is that the mass ratio of Se and VCl3 powder is less than 0.5:1 (such as 0.3:1), the growth temperature is 605°C, the argon flow rate is 100 sccm, the hydrogen flow rate is 3 sccm, and the deposition time is 4 minutes. Figure 11 This is an optical schematic diagram of VSe2 nanosheets prepared on a WSe2 / SiNx / Si substrate, where 1 represents WSe2 and 2 represents the grown VSe2. The raw materials obtained under this condition do not react fully, and colored strips are deposited on the surface of WSe2, which is not conducive to the deposition of VSe2 nanosheets. Therefore, it is not easy to obtain VSe2 adjacent to the grain boundaries, and it is difficult to obtain an ultra-short channel WSe2 structure with VSe2 contact.

[0110] Comparative Examples 1-7

[0111] Compared with Example 1-1, the difference is that the mass ratio of VCl3 and Se powder is 0.5:1, the growth temperature is 605℃, the argon flow rate is 100sccm, the hydrogen flow rate is 3sccm, and the deposition time is 4min. The WSe2 size is smaller, less than 80μm. Figure 12 This is an optical schematic diagram of VSe2 nanosheets prepared on a WSe2 / SiNx / Si substrate. Under these conditions, VSe2 nucleates at the edge of the WSe2 sheet or completely covers the WSe2 surface, and VSe2 nanosheets with adjacent grain boundaries cannot be obtained. Therefore, it is difficult to obtain an ultra-short channel WSe2 structure with VSe2 contact. Figure 12 The scale bars in a and b are 20 μm.

[0112] Example 2-1

[0113] Fabrication of sub-100nm bilayer WSe2 transistors with VSe2 vdW contacts

[0114] The specific process of device preparation is as follows: the double-layer WSe2 in the crack serves as the active semiconductor channel, the adjacent VSe2 nanoplates separated by the crack serve as the vdW source and drain contacts, the Cr / Au electrodes are defined by photolithography, and then the metal Cr (10nm) / Au (50nm) is deposited by electron beam exposure to obtain the VSe2 contact WSe2 field effect transistor ( Figure 13 ). WSe2 outside the crack area is etched away by reactive ion etching to define the channel width.

[0115] The channel length of 20nm VSe2-WSe2 prepared in Example 1-1 was selected. Under a bias voltage of 1.2V, the current density can reach 1.72mA / μm. The obtained VSe2 vdW was used as a contact point for the sub-100nm WSe2 sample. Figure 14 a, b are the output and transfer curves with a channel length of 20 nm.

[0116] Example 2-2

[0117] The method for preparing a field effect transistor, under the conditions of Example 2-1, uses the 31nm channel length VSe2-WSe2 obtained in Example 1-2, and at a bias voltage of 1.2V, the current density can reach 1.60mA / μm, and the obtained VSe2 vdW is used as a contact sub-100nm WSe2 sample. Figure 15 a, b are the output and transfer curves with a channel length of 30 nm.

[0118] Example 2-3

[0119] The method for preparing a field effect transistor, under the conditions of Example 2-1, uses the 48nm channel length VSe2-WSe2 of Example 1-2, and can obtain a current density of 1.35mA / μm at a bias voltage of 1.2V. The obtained VSe2 vdW is used as a contact point for a sub-100nm WSe2 sample. Figure 16 a, b are the output and transfer curves with a channel length of 48 nm.

[0120] Examples 2-4

[0121] The method for preparing a field effect transistor, under the conditions of Example 2-1, selected the VSe2-WSe2 with a channel length of 76nm in Example 1-3, and at a bias voltage of 1.2V, the current density reached 1.26mA / μm. The obtained VSe2 vdW was used as a contact point for the sub-100nm WSe2 sample. Figure 17 a, b are the output and transfer curves with a channel length of 76 nm.

[0122] Comparative Example 2-1

[0123] Compared with Example 2-1, a VSe2-WSe2 with a channel length of 1 μm was selected. The applied bias voltage was 10 times greater than that in the short channel, and the current density was 0.8 mA / μm at a bias voltage of 10 V. Figure 18 a, b are the output and transfer curves for a channel length of 1 μm.

[0124] Comparative Example 2-2

[0125] Compared with Example 2-1, the difference is that the substrate is replaced with SiO2 / Si, and the current density is 0.1 mA / μm at a bias voltage of 3 V, and there is almost no on-off ratio. Figure 19 a, b are the output and transfer curves of narrow channel in SiO2 / Si.

[0126] In summary, the study found that in order to successfully prepare VSe2 nanosheets by epitaxially growing on double-layer WSe2 and achieving a channel width less than 100nm, it is necessary to coordinate the control of the volatilization temperature of the metal VCl3 raw material, the flow rate of the carrier gas, the deposition temperature of the volatilized material, the size of WSe2 and the uniformity of the surface thickness. On this basis, by further regulating parameters such as the ratio of raw materials, the composition of the carrier gas, and the deposition time, samples with narrower channels can be obtained. For example, the channel width can be further reduced to less than 100nm by volatilizing VCl3 at a volatilization temperature of 530-580℃ and Se powder at a volatilization temperature of 360-380℃; the volatilized raw materials react and grow on the surface of the WSe2 substrate at a carrier gas flow rate of 80-130sccm and a deposition temperature of 600-620℃, which helps to obtain samples with narrower channels; further studies have found that by volatilizing VCl3 at a volatilization temperature of 530-540℃ and Se powder at a volatilization temperature of 370-380℃; the volatilized raw materials react and grow on the surface of the WSe2 substrate at a carrier gas flow rate of 100-130sccm (Ar flow rate is 80-100sccm, H2 flow rate is 2-3sccm) and a deposition temperature of 605-610℃, the thickness of the obtained VSe2 nanosheets can be further improved, so that the channel width can be reduced to 10nm.

Claims

1. A method for preparing ultrashort channel VSe2-WSe2 two-dimensional materials, characterized by: The VCl3 raw material is volatilized at a volatilization temperature of 530-580°C, and the Se raw material is volatilized at a volatilization temperature of 360-380°C. The volatilized raw materials are reacted and deposited on the surface of the WSe2 two-dimensional material at a deposition temperature of 600-620°C using a carrier gas. The material is then cooled, and the grain boundaries of adjacent deposited VSe2s are cracked to form ultrashort channels, thereby producing an ultrashort channel VSe2-WSe2 two-dimensional material with a channel width of less than 100 nm. The plane size of the WSe2 two-dimensional material is 100~500 μm; The carrier gas is a mixture of hydrogen and protective gas, wherein the flow rate of the protective gas is 80-130 sccm and the flow rate of H2 is 1-4 sccm; The mass ratio of VCl3 and Se is 1:0.5~1.

2. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The mass ratio of VCl3 and Se powder is 1:0.5~0.

6.

3. The method for preparing the ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The volatilization temperature of the VCl3 raw material is 530-540°C; The volatilization temperature of Se powder is 370-380℃.

4. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The protective gas is at least one of nitrogen and inert gas; The flow rate of the protective gas in the carrier gas is 80~110 sccm; The flow rate of H2 is 2-3 sccm.

5. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The deposition temperature is 605~615℃.

6. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 5, characterized in that: The deposition temperature is 605~610℃.

7. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The deposition time is 3 to 6 minutes.

8. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The deposition time is 4 to 5 minutes.

9. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The deposition substrate is SiNx / Si.

10. The method for preparing an ultrashort channel VSe2-WSe2 two-dimensional material according to claim 1, wherein: The cooling is natural cooling or accelerated cooling.

11. An ultrashort channel VSe2-WSe2 two-dimensional material prepared by the preparation method according to any one of claims 1 to 10.

12. An application of an ultrashort channel VSe2-WSe2 two-dimensional material prepared by the preparation method according to any one of claims 1 to 10, characterized in that: It was used to prepare VSe2 contact ultrashort channel WSe2 field effect transistors.

13. The use according to claim 12, characterized in that After exposing and marking the surface of the ultrashort channel VSe2-WSe2 two-dimensional material, metal is deposited on the surface to produce the VSe2 contact ultrashort channel WSe2 field effect transistor; The metals are Cr and Au, and the metals are deposited by vacuum coating.

14. A VSe2 contact ultrashort channel WSe2 field effect transistor, characterized in that: It includes a back gate substrate, the ultra-short channel VSe2-WSe2 two-dimensional material according to claim 11 deposited on the surface of the back gate substrate, and Cr and Au film electrodes deposited on the surface of the ultra-short channel VSe2-WSe2 two-dimensional material.

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