A method of manufacturing a semiconductor device

Abstract

The embodiment of the present application provides a manufacturing method of a semiconductor device, a photoetching coating is formed on a structure to be led out, the photoetching coating comprises a first film layer, a photoetching film layer and a second film layer, the refractive indexes of the first film layer and the second film layer are both less than 1, so that the photoetching coating forms an optical structure with a relatively high reflection coefficient, the photoetching coating is exposed by using light of a target wavelength and a mask, the structure to be led out is reflected by the photoetching coating, the structure to be led out is imaged to the photoetching film layer as a mask, meanwhile, the pattern of the mask is also imaged to the photoetching film layer, that is, the structure to be led out and the pattern of the mask are both imaged to a target region of the photoetching film layer, the target region corresponds to the structure to be led out, the self-alignment of a layer of the structure to be led out and a layer where a contact hole is located is realized, only the overlapping region where the structure to be led out and the pattern of the mask are simultaneously imaged to the photoetching film layer in the process of one-time exposure corresponds to the structure to be led out, the alignment precision between different layers can be improved, and the alignment error can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular, to a manufacturing method of a semiconductor device. BACKGROUND

[0002] In the process of manufacturing semiconductor devices, it is particularly important to ensure the alignment between different layers. If there is a large alignment error between different layers, it may result in that different layers cannot be electrically connected, and ultimately lead to the performance of the manufactured semiconductor device being reduced. Self-alignment process is an important technical means to achieve the alignment between different layers, and at present, the self-alignment process is often used to achieve the alignment between metal layers and interconnection layers.

[0003] However, due to the limitation of the self-alignment process, in the process of manufacturing semiconductor devices, for example, in the process of forming a contact hole, the error of the self-alignment process is large, which leads to a low yield of the manufactured semiconductor devices.

[0004] Therefore, there is an urgent need for a manufacturing method of a semiconductor device, which can improve the alignment accuracy between different layers and reduce the alignment error. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a manufacturing method of a semiconductor device to improve the alignment accuracy between different layers and reduce the alignment error.

[0006] To achieve the above purpose, the present application has the following technical solutions:

[0007] The embodiment of the present application provides a manufacturing method of a semiconductor device, characterized in that the semiconductor device comprises a substrate and a to-be-led-out structure located on one side of the substrate, and the method comprises the following steps:

[0008] forming a photoetching coating layer on the to-be-led-out structure, wherein the photoetching coating layer comprises a first film layer, a photoetching film layer and a second film layer which are stacked in sequence, and the refractive index of the first film layer and the second film layer is less than 1;

[0009] exposing the photoetching coating layer by using light of a target wavelength and a mask to image the to-be-led-out structure and the pattern of the mask together to a target area of the photoetching film layer; the target area corresponds to the to-be-led-out structure.

[0010] Optionally, the thickness of the photoetching coating layer is determined according to the light intensity in the photoetching film layer when the to-be-led-out structure is imaged to the photoetching film layer by light of the target wavelength and the light intensity in the photoetching film layer when the pattern of the mask is imaged to the photoetching film layer.

[0011] Optionally, before forming the photoetching coating layer on the to-be-led-out structure, the method further comprises:

[0012] forming a dielectric layer on the to-be-extracted structure, the dielectric layer being between the to-be-extracted structure and the photoetching coating layer;

[0013] after exposing the photoetching coating layer to light of the target wavelength and a mask, the method further comprises:

[0014] etching the dielectric layer corresponding to the target region by using the photoetching film layer, to obtain a contact hole penetrating through the dielectric layer, the contact hole exposing the to-be-extracted structure.

[0015] Optionally, before etching the dielectric layer corresponding to the target region by using the photoetching film layer, the method further comprises:

[0016] removing the second film layer.

[0017] Optionally, after etching the dielectric layer corresponding to the target region by using the photoetching film layer, to obtain a contact hole penetrating through the dielectric layer, the method further comprises:

[0018] filling metal in the contact hole to form a metal contact, the metal contact being connected with the to-be-extracted structure.

[0019] Optionally, the material of the photoetching film layer is photoresist, and the material of the first film layer and the second film layer is metal material.

[0020] Optionally, the light of the target wavelength is red light or ultraviolet light.

[0021] Optionally, the to-be-extracted structure is at least one of a gate structure, a source structure and a drain structure.

[0022] Optionally, the feature size of the pattern of the mask varies in the range of 100%-160%.

[0023] Optionally, the center position of the pattern of the mask is offset in the range of -20%-20%.

[0024] The embodiment of the present application provides a manufacturing method of a semiconductor device, the semiconductor device comprising a substrate and a to-be-led-out structure on one side of the substrate, a photoetching coating is formed on the to-be-led-out structure, the photoetching coating comprises a first film layer, a photoetching film layer and a second film layer which are stacked in sequence, wherein the refractive indexes of the first film layer and the second film layer are both less than 1, so that the photoetching coating forms an optical structure with a relatively high reflection coefficient, then the photoetching coating is exposed by using light with a target wavelength and a mask, at this time, the to-be-led-out structure is reflected by the photoetching coating, the to-be-led-out structure is imaged to the photoetching film layer as a mask, and the pattern of the mask is also imaged to the photoetching film layer, that is, the to-be-led-out structure and the pattern of the mask are both imaged to a target region of the photoetching film layer, and the target region corresponds to the to-be-led-out structure. That is, after the exposure of the light with the target wavelength, the position of the to-be-led-out structure is imaged to the photoetching film layer, and the pattern of the mask is also imaged to the photoetching film layer, and the region where the to-be-led-out structure and the pattern of the mask are both imaged corresponds to the to-be-led-out structure, that is, the self-alignment of the layer of the to-be-led-out structure and the layer where the contact hole is located is realized, so that only the overlapping region where the to-be-led-out structure and the pattern of the mask are both imaged to the photoetching film layer during the exposure process corresponds to the to-be-led-out structure, the alignment precision between different layers can be improved, and the alignment error can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0026] Figure 1 A flow chart of a manufacturing method of a semiconductor device provided by the embodiment of the present application is shown;

[0027] Figure 2 A top view structural diagram of a semiconductor device provided by the embodiment of the present application is shown;

[0028] Figure 3 A cross-sectional view of the semiconductor device provided by the embodiment of the present application along the AA direction is shown; Figure 2 A cross-sectional view of the semiconductor device provided by the embodiment of the present application along the AA direction is shown;

[0029] Figures 4-5 A structural schematic diagram of a semiconductor device manufactured by the manufacturing method of the semiconductor device provided by the embodiment of the present application is shown;

[0030] Figure 6 A schematic diagram of light intensity change in the photoetching film layer provided by the embodiment of the present application is shown;

[0031] Figure 7 A schematic diagram of light intensity distribution in the photoetching film layer provided by the embodiment of the present application is shown;

[0032] Figure 8 A top view of a semiconductor device and a mask provided by an embodiment of the present application is shown;

[0033] Figure 9 A corresponding relationship diagram between a feature size and an imaging size of a pattern of a mask provided by an embodiment of the present application is shown;

[0034] Figure 10 A corresponding relationship diagram between a center position offset and an imaging size of a pattern of a mask provided by an embodiment of the present application is shown;

[0035] Figures 11-13 A structure diagram of a semiconductor device manufactured by a manufacturing method of a semiconductor device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] In the following description, a lot of specific details are set forth in order to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0038] Secondly, the present application is described in detail in combination with schematic diagrams, in the detailed description of the embodiments of the present application, for the convenience of description, the cross-sectional view showing the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacturing.

[0039] At present, self-alignment process is an important technical means to realize the alignment between different layers, and the self-alignment process is often used to realize the alignment between metal layer and interconnection layer.

[0040] However, for the semiconductor device after forming the source, drain or gate, in order to perform the contact hole process for leading out the source, drain or gate, there is a lack of effective self-alignment process which can realize the accurate alignment of the contact hole and the source, drain or gate.

[0041] Based on the above technical problems, this application provides a method for manufacturing a semiconductor device. The semiconductor device includes a substrate and a structure to be led out located on one side of the substrate. A photolithographic coating is formed on the structure to be led out. The photolithographic coating includes a first film layer, a photolithographic film layer, and a second film layer stacked sequentially. The refractive indices of the first film layer and the second film layer are both less than 1, so that the photolithographic coating forms an optical structure with a high reflectivity. Then, the photolithographic coating is exposed using light of a target wavelength and a mask. At this time, the structure to be led out is reflected by the photolithographic coating. The structure to be led out is used as a mask to be imaged onto the photolithographic film layer. At the same time, the pattern of the mask is also imaged onto the photolithographic film layer. That is, the structure to be led out and the pattern of the mask are both imaged onto the target area of ​​the photolithographic film layer, and the target area corresponds to the structure to be led out. In other words, after exposure to light of the target wavelength, the position of the structure to be extracted is imaged onto the photolithography layer, and the mask pattern is also imaged onto the photolithography layer at the same time. The area where both the structure to be extracted and the mask pattern are imaged corresponds to the structure to be extracted, thus achieving self-alignment between the layer of the structure to be extracted and the layer where the contact hole is located. Therefore, the structure to be extracted will only correspond to the structure to be extracted in the overlapping area where the structure to be extracted and the mask pattern are imaged on the photolithography layer at the same time during the exposure process. This can improve the alignment accuracy between different layers and reduce alignment errors.

[0042] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0043] refer to Figure 1 The diagram shown is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application. The semiconductor device provided in this embodiment includes a substrate 110 and a lead-out structure 120 located on one side of the substrate 110. (Refer to...) Figure 2 and Figure 3 As shown, Figure 2 This is a top view of the semiconductor device 100 provided in an embodiment of this application. Figure 3 for Figure 2 A cross-sectional view of the semiconductor device along the AA direction is provided. In the embodiments of this application, the structure to be led out 120 can be at least one of a gate structure, a source structure, and a drain structure. The material of the structure to be led out 120 can be a metal material with good conductivity. In other embodiments, the structure to be led out can be the structure of a layer to be aligned.

[0044] In the embodiments of the present application, the substrate 110 is a semiconductor substrate, which can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as quartz, GaAs, InP, SiC, or the like, can also be a stacked structure, such as Si / SiGe, or the like, and can also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), or the like. In the embodiments, the substrate 110 is a silicon substrate.

[0045] In actual applications, other film layers can also be formed between the substrate 110 and the to-be-extracted structure 120 to form various semiconductor devices.

[0046] As an example, a stack layer and a channel structure penetrating the stack layer are formed between the substrate 110 and the to-be-extracted structure 120, and the semiconductor device can be a three-dimensional memory device.

[0047] As another example, a doped layer or other dielectric film layer is formed between the substrate 110 and the to-be-extracted structure 120, and the semiconductor device can be a logic device, such as a transistor.

[0048] The method comprises the following steps:

[0049] S101, forming a photoresist coating layer 130 on the to-be-extracted structure 120, as shown in Figure 4 .

[0050] In the embodiments of the present application, the photoresist coating layer 130 is formed on the to-be-extracted structure 120, and the photoresist coating layer 130 is patterned to form a metal contact using the patterned photoresist coating layer 130 to electrically extract the to-be-extracted structure 130.

[0051] In actual applications, before forming the photoresist coating layer 130 on the to-be-extracted structure 120, a dielectric layer 140 is first formed on the to-be-extracted structure 130, i.e., the dielectric layer 140 is located between the to-be-extracted structure 120 and the photoresist coating layer 130, as shown in Figure 4 . The material of the dielectric layer 140 can be a material with good insulation, such as silicon oxide. The dielectric layer 140 can be formed by depositing a dielectric material using a deposition process. When the dielectric material is deposited on the to-be-extracted structure 120, the dielectric layer 140 formed will be conformal to the to-be-extracted structure 120, so that the topography of the dielectric layer 140 is similar to that of the to-be-extracted structure 120. At this time, the dielectric layer 140 can be polished using a chemical mechanical polishing device, and finally a dielectric layer 140 with high flatness is obtained, which is beneficial to the subsequent formation of the photoresist coating layer 130 on the relatively flat dielectric layer 140.

[0052] In the embodiment of the present application, the photoetching coating 130 comprises a first film layer 131, a photoetching film layer 132 and a second film layer 133 which are stacked in sequence, wherein the refractive index of the first film layer 131 and the second film layer 132 is less than 1. The photoetching coating 130 constitutes a sandwich-like optical structure by the first film layer 131, the photoetching film layer 132 and the second film layer 133, both sides of which are film layers with refractive index less than 1. After the light is incident, a reflection oscillation can be formed in the photoetching coating 130, and the reflection oscillation can be used to enhance the light intensity of the incident light.

[0053] The material of the photoetching film layer 132 is photoresist, and the materials of the first film layer 131 and the second film layer 133 can be metal materials or super materials. The metal materials such as gold, silver or copper have refractive index less than 1 under the irradiation of deep ultraviolet light, visible light or infrared light. The super materials can be certain compound materials and certain combinations of materials, and the super materials can be artificially synthesized materials to form the effect of refractive index less than 1 under the irradiation of light at certain wavelengths.

[0054] In actual application, the first film layer 131, the photoetching film layer 132 and the second film layer 133 which are stacked in sequence can be formed by using a spin coating process, a deposition process or an ion sputtering process. Then, the first film layer 131, the photoetching film layer 132 and the second film layer 133 can be polished by using a chemical mechanical polishing device to further control the flatness and thickness of the first film layer 131, the photoetching film layer 132 and the second film layer 133.

[0055] S102, exposing the photoetching coating 130 by using light of a target wavelength and a mask 150, as shown in Figure 5

[0056] In the embodiment of the present application, after the photoetching coating 130 is formed on the to-be-extracted structure 120, the photoetching coating 130 can be exposed by using a photoetching process.

[0057] The photoetching coating 130 is exposed by using light of a target wavelength and a mask 150 once, and the to-be-extracted structure 120 and the pattern of the mask 150 are imaged together to a target region 132-1 of the photoetching film layer 132, and the target region 132-1 corresponds to the to-be-extracted structure 120.

[0058] The photoetching coating 130 is exposed by using light of a target wavelength. When the exposure is specifically performed, the reflectivity of the photoetching coating 130 to the light of the target wavelength is high, and the structure of the to-be-extracted structure 120 under the photoetching coating 130 can be imaged to the target region 132-1 of the photoetching film layer 132, as shown in Figure 5 ​That is, when the photoresist coating 130 is exposed by the light of the target wavelength, the to-be-extracted structure 120 corresponds to a mask, and the light of the target wavelength photochemically reacts in the target region 132-1 to image the to-be-extracted structure 120 to the photoresist film layer 132.

[0059] Meanwhile, the light of the target wavelength can also image the pattern of the mask 150 to the target region 132-1 of the photoresist film layer 132, and only the target region 132-1, that is, the overlapping region of the to-be-extracted structure 120 and the pattern of the mask 150 in the photoresist film layer 132, can photochemically react and can be developed in the subsequent development process.

[0060] In the embodiment of the present application, the photoresist film layer 132 can have an optical response to the light of the target wavelength, and when the light of the target wavelength is exposed, the photoresist film layer 132 photochemically reacts, and the position of the to-be-extracted structure 120 and the position of the contact hole are determined, and the target region 132-1 is the region where the photochemical reaction occurs, which is the extraction region, and the extraction region corresponds to the to-be-extracted structure 120.

[0061] That is, only the overlapping region of the exposure in the photoresist film layer imaging corresponds to the to-be-extracted structure, and only the photoresist film layer of the extraction region can be developed in the subsequent development process, and other regions that are not imaged will not be developed. In this way, the layer of the to-be-extracted structure and the layer where the contact hole is located are self-aligned, so as to improve the alignment accuracy between different layers and reduce the alignment error.

[0062] In the embodiment of the present application, the thicknesses of the first film layer 131, the photoresist film layer 132, and the second film layer 133 in the photoresist coating 130 can be simulated by simulation software, and the thickness of the photoresist film layer 132 is usually greater than the thicknesses of the first film layer 131 and the second film layer 133. The thickness of the photoresist coating 130 can be determined according to the light intensity in the photoresist film layer 132 when the to-be-extracted structure 120 is imaged to the photoresist film layer 132 by the light of the target wavelength and the light intensity in the photoresist film layer 120 when the pattern of the mask 150 is imaged to the photoresist film layer 120.

[0063] First, the light intensity of the light of the target wavelength that needs to pass through the light-transmitting region of the mask 150 is relatively large in the photoresist film layer 132, which can image the pattern of the mask 150 to the photoresist film layer 132, and second, the reflected light imaging to the photoresist film layer 132 when the light of the target wavelength irradiates the to-be-extracted structure 120 is stronger in the region with the imaging of the to-be-extracted structure 120.

[0064] In the embodiment of the present application, the light intensity when the pattern of the mask 150 is imaged to the photoresist film layer 132 and the light intensity when the to-be-extracted structure 120 is imaged to the photoresist film layer 132 are equal or close, so as to jointly determine the target region to be extracted.

[0065] In the embodiments of the present application, the thickness of the photoresist coating layer 130 can affect the light intensity change in the photoresist film layer 132 when the target wavelength light is exposed. When the thickness of the photoresist coating layer 130 is fixed, whether there is the to-be-etched structure 120 can also affect the light intensity change in the photoresist film layer 132. That is, the thickness of the photoresist coating layer 130 and whether there is the to-be-etched structure 120 are both factors affecting the light intensity in the photoresist film layer 132.

[0066] When simulating the thicknesses of the first film layer 131, the photoresist film layer 132 and the second film layer 133 in the photoresist coating layer 130 by using simulation software, a control variable method can be used, for example, the thicknesses of the first film layer 131 and the second film layer 133 can be fixed, and only the thickness of the photoresist film layer 132 is changed to obtain the relationship between the light intensity in the photoresist film layer 132 and the thickness of the photoresist film layer 132. Alternatively, the thicknesses of the first film layer 131, the photoresist film layer 132 and the second film layer 133 can be changed simultaneously to obtain the relationship between the light intensity in the photoresist film layer 132 and the thicknesses of the three layers.

[0067] When performing simulation, the factor of whether there is the to-be-etched structure 120 can also be added, the light intensity of the region where there is the to-be-etched structure 120 and the region where there is not the to-be-etched structure 120 when imaging to the photoresist film layer 132 can be calculated, and the light intensity difference can be calculated to optimize the thickness of the photoresist coating layer 130.

[0068] Reference is made to FIG. 1, which is a schematic diagram of the light intensity change in the photoresist film layer according to the embodiments of the present application. Figure 6 As shown in the figure, the region 100 represents the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132, and the light intensity is the largest. The region 200 represents the region where there is not the to-be-etched structure 120 when imaging to the photoresist film layer 132, and the light intensity is the smallest. In the embodiments of the present application, since the contact hole needs to be formed above the to-be-etched structure 120 subsequently, the light intensity of the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132 is larger, so as to improve the efficiency of exposure imaging. That is, in order to ensure that the light intensity of the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132 is larger, the thickness of the photoresist coating layer 130 corresponding to the region 100 can be selected. Figure 6

[0069] After the thickness of the photoresist coating layer 130 is determined, the light intensity in the photoresist film layer 132 is simulated by using the thickness, and reference is made to FIG. 2, which is a schematic diagram of the light intensity distribution in the photoresist film layer provided by the embodiments of the present application. As shown in the figure, the light intensity of the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132 is larger, and the light intensity of the region where there is not the to-be-etched structure 120 when imaging to the photoresist film layer 132 is smaller, which is consistent with the simulation result of the photoresist coating layer 130. Figure 7 As shown in the figure, the region 100 represents the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132, and the light intensity is the largest. The region 200 represents the region where there is not the to-be-etched structure 120 when imaging to the photoresist film layer 132, and the light intensity is the smallest. In the embodiments of the present application, since the contact hole needs to be formed above the to-be-etched structure 120 subsequently, the light intensity of the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132 is larger, so as to improve the efficiency of exposure imaging. That is, in order to ensure that the light intensity of the region where there is the to-be-etched structure 120 when imaging to the photoresist film layer 132 is larger, the thickness of the photoresist coating layer 130 corresponding to the region 100 can be selected.​Figure 6 The effect of determining the thickness of the photoetching coating 130 is consistent.

[0070] In the embodiments of the present application, the light of the target wavelength can not only image the to-be-extracted structure 120 to the photoetching film layer 132, but also image the pattern of the mask 150 to the photoetching film layer 132. For example, the light of the target wavelength can be visible light or ultraviolet light, and the visible light can be red light, for example. For example, the target wavelength can be 633 nanometers, 532 nanometers, 436 nanometers, 365 nanometers, 248 nanometers, or 193 nanometers.

[0071] In the embodiments of the present application, as shown in reference 8, Figure 8 The top view schematic diagram of the semiconductor device and the mask provided in the embodiments of the present application, Figure 7 is Figure 8 The cross-sectional view along the BB direction, the position of the pattern of the mask 150 exposed is located in the target area 132-1 of the photoetching film layer 132, and the feature size of the pattern of the mask 150 can be greater than the feature size of the to-be-extracted structure 120, so that even if the pattern of the mask 150 is offset from the center point of the to-be-extracted structure 120, that is, the center position of the mask 150, the maximum overlapping area of the pattern of the mask 150 and the to-be-extracted structure 120 can be ensured, and self-alignment is realized.

[0072] As Figure 8 shown, the pattern of the mask can be a hole type so as to form a contact hole subsequently, the mask can be a binary mask or an attenuance-dependent mask, the mask substrate can adopt quartz or other light-transmitting materials, and the material of the light-blocking area in the mask can be a metal material, for example, metal chromium.

[0073] In the embodiments of the present application, the feature size of the pattern of the mask 150 can be changed when the exposure of the light of the target wavelength is performed, and within a certain change range, the final imaged pattern size in the photoetching film layer 132 is not greatly affected.

[0074] Reference Figure 9 As shown in the figure, the feature size of the pattern of the mask changes in the range of 100%-160%. When the feature size of the pattern of the mask 150 is increased by 50%, the imaged size is almost unchanged, that is, the feature size of the pattern of the mask 150 can be increased by 50%, which indicates that even if the size error of the pattern of the mask 150 occurs when the mask 150 is manufactured, the final imaged size will not be affected. In actual application, the influence of the alignment error between different layers can also be reduced by increasing the feature size of the pattern of the mask 150.

[0075] In the embodiment of the present application, the center position of the pattern of the mask 150 can be offset when the exposure of the light of the target wavelength is performed, and the final imaging of the pattern into the photoresist layer 132 has no great influence on the size of the pattern within a certain offset range.

[0076] Referring to Figure 10 FIG. 2 is a diagram of the corresponding relationship between the center position offset of the pattern of the mask and the imaging size according to the embodiment of the present application. As can be seen from the diagram, the center position offset range of the pattern of the mask is -20%-20%. When the center position of the pattern of the mask 150 changes by 20% in the horizontal direction, the change of the imaging size is within the range of 5%, which is less than the requirement of 10% for the size change in the field of integrated circuits.

[0077] When both the feature size and the center position of the pattern of the mask 150 change, the maximum value of the center position offset of the mask 150 is half of the change of the feature size of the mask 150.

[0078] In the embodiment of the present application, after the exposure of the photoresist coating 130, the second film layer 133 can be removed so as to perform a developing process on the photoresist layer 132 to form a patterned photoresist layer 160. Referring to Figure 11 FIG. 3, after the developing process, the photoresist layer 132 corresponding to the target region 132-1 is removed.

[0079] Then, the patterned photoresist layer 160 can be used to etch the dielectric layer 140 corresponding to the target region 132-1 to obtain a contact hole 170 penetrating through the dielectric layer 140, and the contact hole 170 exposes the to-be-lead-out structure 120. Referring to Figure 12 FIG. 4, when the etching is performed by using the patterned photoresist layer 160, the first film layer 131 is also etched. After the contact hole 170 penetrating through the dielectric layer 140 is obtained, the remaining photoresist layer 160 and the first film layer 131 can be removed, and only the dielectric layer 140 including the contact hole 170 can be reserved.

[0080] After the contact hole 170 is formed at the position corresponding to the to-be-lead-out structure 120, a metal material can be filled in the contact hole 170 to form a metal contact 180, and the metal contact 180 is connected with the to-be-lead-out structure 120, that is, the electrical lead-out of the to-be-lead-out structure 120 is formed. Referring to Figure 13 FIG. 5.

[0081] In the embodiment of the present application, the photoetching process for forming the metal contact can be an extreme ultraviolet lithography process, a deep ultraviolet lithography process, a nanoimprint process, an ultrahard diffraction lithography process or other processes using optical imaging. When the exposure is performed by using the photoetching process, a lens can be used to form parallel light to irradiate the semiconductor device. If the metal surface plasmon ultrahard diffraction lithography is used as the photoetching process, the lens can not be used.

[0082] Therefore, the manufacturing method of the semiconductor device provided in the embodiments of the present application can make the area where the to-be-projected structure exists and the area where the to-be-projected structure does not exist have different light intensities when imaging to the photoresist film layer by adjusting the thickness of the photoresist coating by using one-time exposure process, and the self-alignment of the two layers is realized by using the light intensity difference. Compared with the two photoetching and etching processes required for the self-alignment by using the double damascene process, the one-time photoetching process of the embodiments of the present application is more convenient and saves process time. Moreover, the change of the feature size and the center position of the pattern of the mask has less influence on the final imaging size in the embodiments of the present application, which can reduce the process difficulty of the self-alignment and improve the precision of the alignment of the metal contact and the to-be-projected structure.

[0083] Therefore, the manufacturing method of the semiconductor device provided in the embodiments of the present application can make the area where the to-be-projected structure exists and the area where the to-be-projected structure does not exist have different light intensities when imaging to the photoresist film layer by adjusting the thickness of the photoresist coating by using one-time exposure process, and the self-alignment of the two layers is realized by using the light intensity difference. Compared with the two photoetching and etching processes required for the self-alignment by using the double damascene process, the one-time photoetching process of the embodiments of the present application is more convenient and saves process time. Moreover, the change of the feature size and the center position of the pattern of the mask has less influence on the final imaging size in the embodiments of the present application, which can reduce the process difficulty of the self-alignment and improve the precision of the alignment of the metal contact and the to-be-projected structure.

[0084] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between each of the embodiments can be referred to each other. Each of the embodiments mainly describes the difference from other embodiments. Especially, the device embodiments are described more simply because they are basically similar to the method embodiments, and the related parts can be referred to the part of the method embodiments.

[0085] The above description is only the preferred embodiment of the present application, although the present application has been disclosed as above with the preferred embodiment, however, not to limit the present application. Any skilled person in the art, without departing from the scope of the technical scheme of the present application, can utilize the above disclosed methods and technical contents to make many possible changes and modifications to the technical scheme of the present application, or modify as equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical scheme of the present application, still belongs to the scope of protection of the technical scheme of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a substrate and a structure to be brought out located on one side of the substrate, and the method includes: A photolithographic coating is formed on the structure to be extracted. The photolithographic coating includes a first film layer, a photolithographic film layer, and a second film layer stacked sequentially. The refractive indices of the first film layer and the second film layer are less than 1. The photolithographic coating is exposed using light of the target wavelength and a mask to image the structure to be extracted and the pattern of the mask onto the target area of ​​the photolithographic film; the target area corresponds to the structure to be extracted.

2. The manufacturing method according to claim 1, characterized in that, The thickness of the photolithography coating is determined by the light intensity in the photolithography layer when the structure to be extracted is imaged onto the photolithography layer at the target wavelength, and by the light intensity in the photolithography layer when the mask pattern is imaged onto the photolithography layer.

3. The manufacturing method according to claim 1, characterized in that, Before forming a photolithographic coating on the structure to be extracted, the method further includes: A dielectric layer is formed on the structure to be brought out, the dielectric layer being located between the structure to be brought out and the photolithographic coating; After exposing the photolithographic coating to light of the target wavelength and a mask, the method further includes: Using the photolithography layer, the dielectric layer corresponding to the target area is etched to obtain a contact hole that penetrates the dielectric layer, and the contact hole exposes the structure to be led out.

4. The manufacturing method according to claim 3, characterized in that, Before etching the dielectric layer corresponding to the target region using the photolithography film layer, the method further includes: Remove the second film layer.

5. The manufacturing method according to claim 3, characterized in that, After etching the dielectric layer corresponding to the target region using the photolithographic film layer to obtain a contact hole penetrating the dielectric layer, the method further includes: Metal is filled into the contact hole to form a metal contact, which is connected to the structure to be led out.

6. The manufacturing method according to any one of claims 1-5, characterized in that, The photolithography film is made of photoresist, and the first and second films are made of metal.

7. The manufacturing method according to any one of claims 1-5, characterized in that, The target wavelength of light is red light or ultraviolet light.

8. The manufacturing method according to any one of claims 1-5, characterized in that, The structure to be extracted is at least one of a gate structure, a source structure, and a drain structure.

9. The manufacturing method according to any one of claims 1-5, characterized in that, The feature size of the mask pattern varies from 100% to 160%.

10. The manufacturing method according to any one of claims 1-5, characterized in that, The offset of the center position of the mask pattern is in the range of -20% to 20%.

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