Semiconductor packaging method and semiconductor packaging structure

Abstract

The present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: forming an encapsulation structure, the encapsulation structure including an encapsulation layer and a chip, a plurality of pads being disposed on a front surface of the chip, and the encapsulation layer covering at least a side surface of the chip; forming a redistribution layer on a side of the encapsulation structure close to the front surface of the chip, the redistribution layer leading out the pads of the chip; forming a dielectric layer, the dielectric layer covering the redistribution layer, and a through hole exposing the redistribution layer being formed in the dielectric layer; and forming a pin layer on a side of the dielectric layer facing away from the chip, the pin layer being electrically connected to the redistribution layer through the through hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor packaging method and a semiconductor packaging structure. Background Art

[0002] Common semiconductor packaging technologies, such as chip packaging technology, mainly include the following process: For the process of processing the front side of the chip, first, the front side of the chip is mounted on a carrier board, hot press molding is performed, the carrier board is peeled off, and then a redistribution layer and a pin layer on the side of the redistribution layer away from the chip are formed on the front side of the chip. After that, an insulating layer is formed, the insulating layer covers the redistribution layer, and the surface of the pin layer away from the chip exposes the insulating layer.

[0003] In the existing chip packaging technology, since the pin layer is formed on the side of the redistribution layer away from the chip and the area of the redistribution layer is larger than that of the pin layer, generally, the area of the redistribution layer is relatively large, and the contact area between the redistribution layer and the adjacent insulating layer is relatively large. Due to the large difference in the thermal expansion coefficients between the redistribution layer and the insulating layer, when the temperature of the redistribution layer rises during the manufacturing process or the chip operation, the stress difference between the redistribution layer and the insulating layer will be relatively large, which may cause delamination between the redistribution layer and the insulating layer or warping of the redistribution layer, affecting the normal operation of the product. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor packaging method and a semiconductor packaging structure.

[0005] According to the first aspect of the embodiments of this application, a semiconductor packaging method is provided, including:

[0006] Forming an encapsulation structure, the encapsulation structure including an encapsulation layer and a chip, and a plurality of pads being provided on the front side of the chip, the encapsulation layer covering at least the side surface of the chip;

[0007] Forming a redistribution layer on one side of the encapsulation structure close to the front side of the chip, the redistribution layer leading out the pads of the chip;

[0008] Forming a dielectric layer, the dielectric layer covering the redistribution layer, and a through hole exposing the redistribution layer being provided on the dielectric layer;

[0009] Forming a pin layer on the side of the dielectric layer away from the chip, the pin layer being electrically connected to the redistribution layer through the through hole.

[0010] In one embodiment, the pin layer includes a plurality of spaced conductive studs protruding from the dielectric layer; after forming the pin layer on the side of the dielectric layer away from the chip, the semiconductor packaging method further includes:

[0011] A solder layer is formed, and the solder layer covers the surface of the conductive posts protruding from the dielectric layer.

[0012] In one embodiment, the pin layer includes a plurality of spaced-apart conductive posts protruding from the dielectric layer; a conductive portion is provided in the through hole, and the pin layer is electrically connected to the redistribution layer through the conductive portion, and a depression is formed at a position corresponding to the through hole; after the pin layer is formed on a side of the dielectric layer away from the chip, the semiconductor packaging method further includes:

[0013] A solder layer is formed, the solder layer covers the surface of the conductive posts protruding from the dielectric layer, and the solder layer fills the depression.

[0014] In one embodiment, the ratio of the width to the depth of the through hole is greater than or equal to 1 / 3.

[0015] In one embodiment, the depth range of the through hole is 60 μm to 100 μm; the thickness range of the portion of the conductive portion located at the bottom wall of the through hole is 10 μm to 50 μm.

[0016] In one embodiment, the thickness of the pin layer is greater than 30 μm.

[0017] In one embodiment, the semiconductor packaging method further includes: forming a heat dissipation layer on a side of the dielectric layer away from the chip;

[0018] After the heat dissipation layer is formed on a side of the dielectric layer away from the chip, the semiconductor packaging method further includes: forming a solder layer, the material of the solder layer is tin, and the solder layer covers the surface of the portion of the heat dissipation layer exposed from the dielectric layer.

[0019] In one embodiment, the redistribution layer includes a plurality of spaced-apart redistribution structures, and the redistribution structures are provided with hollow portions.

[0020] According to a second aspect of the embodiments of the present application, a semiconductor packaging structure is provided, and the semiconductor packaging structure includes:

[0021] An encapsulation structure, the encapsulation structure includes an encapsulation layer and a chip, a plurality of pads are provided on a front surface of the chip, and the encapsulation layer covers a back surface and side surfaces of the chip;

[0022] A redistribution layer, located on a side of the encapsulation structure close to the front surface of the chip, and the redistribution layer leads out the pads of the chip;

[0023] A dielectric layer, covering the redistribution layer, and through holes exposing the redistribution layer are provided on the dielectric layer;

[0024] The pin layer is located on a side of the dielectric layer away from the chip, and the pin layer is electrically connected to the redistribution layer through the through hole.

[0025] In one embodiment, the pin layer includes a plurality of conductive protrusions arranged at intervals, and the conductive protrusions protrude from the dielectric layer; the semiconductor packaging structure also includes a solder layer, and the solder layer covers the surface of the conductive protrusions protruding from the dielectric layer.

[0026] In one embodiment, the pin layer includes a plurality of conductive protrusions arranged at intervals, and the conductive protrusions protrude from the dielectric layer; a conductive portion is provided in the through hole, and the pin layer is electrically connected to the redistribution layer through the conductive portion, and a recess is formed at a position corresponding to the conductive portion and the through hole; the semiconductor packaging structure also includes a solder layer, and the solder layer covers the surface of the conductive protrusion protruding from the dielectric layer, and the solder layer fills the recess.

[0027] In one embodiment, a ratio of the width to the depth of the through hole is greater than or equal to 1 / 3.

[0028] In one embodiment, the depth of the through hole is in the range of 60 μm to 100 μm; the thickness of the conductive portion located at the bottom wall of the through hole is in the range of 10 μm to 50 μm.

[0029] In one embodiment, the pin layer has a thickness greater than 30 μm.

[0030] In one embodiment, the rewiring layer includes a plurality of rewiring structures arranged at intervals, and the rewiring structures are provided with hollow portions.

[0031] The main technical effects achieved by the embodiments of the present application are:

[0032] In the semiconductor packaging method and semiconductor packaging structure provided by the embodiments of the present application, the dielectric layer covers the rewiring layer, the pin layer is located on the side of the dielectric layer away from the rewiring layer, and the pin layer is electrically connected to the rewiring layer through the through hole on the dielectric layer, that is, the pin layer is not in direct contact with the rewiring layer, so the size of the pin layer is not affected by the size of the rewiring layer, and the size of the rewiring layer can be set to be smaller, thereby reducing the contact area between the rewiring layer and the adjacent insulating layer, such as the dielectric layer, and reducing the stress difference between the rewiring layer and the adjacent insulating layer, thereby reducing the risk of delamination between the rewiring layer and the adjacent insulating layer or warping of the rewiring layer, which helps to improve the quality of the product; the pin layer is not in direct contact with the rewiring layer, so the thickness of the pin layer is less affected by the rewiring layer, and the thickness design of the pin layer is more free, which helps to increase the thickness of the formed pin layer, thereby increasing the breakdown voltage of the semiconductor packaging structure, helping the semiconductor packaging structure to be used in a high-voltage environment, and expanding the application range of the semiconductor packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

[0034] Figure 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application;

[0035] Figure 3 is a partial cross-sectional view of a first intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0036] Figure 4 is a partial cross-sectional view of a second intermediate structure of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0037] Figure 5 is a partial cross-sectional view of an encapsulation structure provided by an exemplary embodiment of the present application;

[0038] Figure 6 is a partial cross-sectional view of a third intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0039] Figure 7 is a partial cross-sectional view of a third intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0040] Figure 8 is a partial cross-sectional view of a fourth intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0041] Figure 9 is a partial cross-sectional view of a fifth intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0042] Figure 10 is a partial cross-sectional view of a sixth intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0043] Figure 11 is a schematic structural view of a sixth intermediate structure of a semiconductor packaging structure provided by another exemplary embodiment of the present application;

[0044] Figure 12 is a partial cross-sectional view of a semiconductor packaging structure provided by an exemplary embodiment of the present application;

[0045] Figure 13 is a partial cross-sectional view of a semiconductor packaging structure after being soldered to a circuit board provided by an exemplary embodiment of the present application;

[0046] Figure 14 A partial cross-sectional view of a semiconductor packaging structure provided by another exemplary embodiment of the present application. Specific Embodiments

[0047] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0048] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0049] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "upon" or "in response to determining".

[0050] The following describes in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0051] The embodiments of the present application provide a semiconductor packaging method. Refer to Figure 1 , the semiconductor packaging method includes the following steps 110 to step 140.

[0052] In step 110, a package structure is formed, the package structure includes a package layer and a chip, and a plurality of pads are provided on the front surface of the chip, and the package layer covers at least the side surface of the chip.

[0053] In step 120, a redistribution layer is formed on a side of the package structure close to the front surface of the chip, and the redistribution layer leads out the pads of the chip.

[0054] In step 130, a dielectric layer is formed, the dielectric layer covers the redistribution layer, and the dielectric layer is provided with vias exposing the redistribution layer.

[0055] In step 140, a pin layer is formed on a side of the dielectric layer facing away from the chip, and the pin layer is electrically connected to the redistribution layer through the through hole.

[0056] In the semiconductor packaging method provided by the embodiment of the present application, the dielectric layer covers the redistribution layer, the pin layer is located on a side of the dielectric layer facing away from the redistribution layer, and the pin layer is electrically connected to the redistribution layer through the through hole in the dielectric layer. That is, the pin layer and the redistribution layer do not directly contact each other. Then, the size of the pin layer is not affected by the size of the redistribution layer, and the size of the redistribution layer can be set to be smaller, reducing the contact area between the redistribution layer and the adjacent insulating layer, such as the dielectric layer, reducing the stress difference between the redistribution layer and the adjacent insulating layer, and further reducing the risk of delamination between the redistribution layer and the adjacent insulating layer or warping of the redistribution layer, which helps to improve the quality of the product; since the pin layer and the redistribution layer do not directly contact each other, the thickness of the pin layer is less affected by the redistribution layer, and the thickness design of the pin layer is more flexible, which helps to increase the thickness of the formed pin layer, and further increases the breakdown voltage of the semiconductor packaging structure, which helps the semiconductor packaging structure to be applied in a high-voltage environment and expands the application range of the semiconductor packaging structure.

[0057] Next, each step of the semiconductor packaging method provided by the embodiment of the present application will be introduced in detail.

[0058] In step 110, an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and a chip, and a plurality of pads are provided on a front surface of the chip, and the encapsulation layer covers at least a side surface of the chip.

[0059] In one embodiment, the encapsulation structure may include one or more chips, and concave cavities corresponding to the chips one by one are provided on the encapsulation layer, and the chips are located in the corresponding concave cavities.

[0060] In one embodiment, referring to Figure 2 , the step 110 of forming the encapsulation structure includes the following steps 111 to 113.

[0061] In step 111, the chip is mounted on a carrier board, and the front surface of the chip faces the surface of the carrier board.

[0062] Through step 111, the first intermediate structure as shown in Figure 3 can be obtained. Figure 3 In the embodiment shown in, a chip 20 is mounted on the carrier board 10. In other embodiments, the number of chips 20 mounted on the carrier board 10 may be multiple.

[0063] In one embodiment, the carrier board 10 includes a mounting area for mounting the chip 20. The shape of the mounting area is designed according to the layout of the chip 20 on the entire carrier board 10, and the shape of the mounting area may include a circle, a rectangle, or other shapes. The carrier board may include one or more mounting areas.

[0064] In one embodiment, the shape of the carrier board 10 may be a circle, a rectangle, or other shapes. The material of the carrier board 10 may be an iron-nickel constant expansion alloy, or the material of the carrier board 10 may also be stainless steel, polymer, etc.

[0065] In one embodiment, the chip 20 can be obtained by cutting a silicon wafer. The silicon wafer has an active surface, and bonding pads are provided on the active surface of the silicon wafer. The silicon wafer can be cut by a mechanical cutting method or a laser cutting method. Optionally, before cutting the silicon wafer, a grinding device can be used to grind the back surface of the silicon wafer opposite to the active surface so that the thickness of the silicon wafer is a specified thickness.

[0066] The bonding pads 21 of the chip 20 are composed of conductive electrodes led out from the internal circuit of the chip to the chip surface. A plurality of bonding pads 21 may be provided on the front surface of the chip 20. The bonding pads 21 are used to lead out the conductive electrodes of the chip 20.

[0067] In one embodiment, before the step 111 of mounting the chip on the carrier board, the semiconductor packaging method further includes: forming a protective layer 22 on the front surface of the chip 20, and an opening 23 exposing the bonding pads 21 is provided on the protective layer 22.

[0068] In some embodiments, the opening 23 can be formed on the protective layer 22 by a laser process. The size of the opening 23 may be smaller than the size of the bonding pads 21, and the opening 23 exposes a part of the surface of the bonding pads 21 facing away from the carrier board 10.

[0069] The material of the protective layer 22 may be a plastic film, PI (polyimide), PBO (polyphenylene benzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers may also be added to the protective layer 22.

[0070] In the subsequent step 112 of forming the encapsulation layer, since the encapsulation layer needs to be formed under high pressure during molding, the encapsulation material for forming the encapsulation layer is likely to penetrate between the carrier board 10 and the chip 20 during this process. By forming a protective layer 22 on the front surface of the chip 20, the protective layer 22 can prevent the encapsulation material from penetrating to the surface of the chip 20, and even if the encapsulation material penetrates into the protective layer 22 when forming the encapsulation layer, after the carrier board 10 and the chip 20 are peeled off, the surface of the protective layer 22 can be directly treated by a chemical method or a grinding method without directly contacting the front surface of the chip 20, thereby avoiding damaging the bonding pads on the front surface of the chip 20.

[0071] In one embodiment, the chip 20 can be mounted on the carrier board 10 through an adhesive layer, and the adhesive layer can be made of an easily peelable material so as to separate the chip 20 from the carrier board 10 subsequently. For example, the adhesive layer can be a thermal separation material whose adhesiveness can be lost by heating.

[0072] In step 112, an encapsulation layer is formed to cover the carrier board and encapsulate the chip.

[0073] Through step 112, the second intermediate structure as shown in Figure 4 can be obtained.

[0074] Refer to Figure 4 , where the encapsulation layer 30 is formed on the chip 20 and the exposed carrier board 10 to encapsulate the chip 20, so as to reconstruct a flat structure, so that after the carrier board 10 is peeled off, rewiring and encapsulation can continue on the reconstructed flat structure.

[0075] In one embodiment, before forming the encapsulation layer 30, some pre-treatment steps can be performed, such as chemical cleaning, plasma cleaning and other steps, to remove impurities on the surfaces of the chip 20 and the carrier board 10, so that the encapsulation layer 30 can be more closely connected to the chip 20 and the carrier board 10, and no delamination or cracking will occur.

[0076] In one embodiment, the encapsulation layer 30 can be formed by laminating an epoxy resin film, or can also be formed by injection molding, compression molding or transfer molding of an epoxy resin compound.

[0077] In one embodiment, step 120 of forming the encapsulation layer may include the following steps:

[0078] First, an encapsulation structure is formed to cover the carrier board and wrap the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20, so that the encapsulation structure completely wraps the chip 20.

[0079] After that, the side of the encapsulation structure facing away from the carrier board is thinned to obtain the encapsulation layer. In this step, the encapsulation structure can be thinned by a grinding process to reduce the thickness of the encapsulation structure to a specified thickness.

[0080] In step 113, the carrier board is removed to obtain the encapsulation structure.

[0081] Through step 113, the encapsulation structure as shown in Figure 5 can be obtained. In the embodiment shown in the accompanying drawings, the encapsulation layer 30 wraps the back and side surfaces of the chip 20. In other embodiments, the encapsulation layer may only wrap the side surface of the chip, etc.

[0082] In one embodiment, the carrier 10 can be directly mechanically peeled from the encapsulation layer 30 and the chip 20. In another embodiment, when the chip 20 and the carrier 10 are bonded through an adhesive layer and the material of the adhesive layer is a thermally separable material, the carrier 10 can also be peeled by heating, so that the viscosity of the adhesive layer decreases after heating, and then the carrier 10 is peeled off. After the carrier 10 is peeled off, the front sides of the respective chips 20 are exposed, that is, the pads of the chips 20 are exposed.

[0083] In step 120, a redistribution layer is formed on the side of the encapsulation structure close to the front side of the chip, and the redistribution layer leads out the pads of the chip.

[0084] Through step 120, the third intermediate structure as shown in Figure 6 can be obtained. The side of the encapsulation structure close to the front side of the chip refers to the side where the front side of the chip is located. Refer to Figure 6 , the redistribution layer 40 includes a plurality of redistribution structures 41. Each redistribution structure 41 can be electrically connected to one pad 21 or can be electrically connected to a plurality of pads 21.

[0085] In one embodiment, a conductive structure 24 is formed in the opening 23 of the protective layer 22, and the conductive structure 24 is in direct contact with the redistribution structure 41. The redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24. The conductive structure 24 and the redistribution structure 41 can be formed in the same process step, which helps to simplify the semiconductor packaging process.

[0086] In one embodiment, step 120 can be completed through the following steps:

[0087] First, a seed layer is formed on the side of the encapsulation structure close to the front side of the chip. The seed layer can cover the front side of the chip 20 and the inner wall of the opening 23.

[0088] Subsequently, a photoresist layer is formed on the side of the seed layer away from the chip. The photoresist layer is a patterned film layer.

[0089] Subsequently, the seed layer is connected to a power supply for electroplating to form a conductive layer in the area on the side of the first seed layer away from the chip and not covered by the photoresist layer.

[0090] Subsequently, the photoresist layer is removed.

[0091] Subsequently, the seed layer is patterned to etch away the area of the seed layer not covered by the conductive layer, and the remaining seed layer and the conductive layer form the redistribution layer.

[0092] In one embodiment, refer to Figure 7, the redistribution structure 41 is provided with a hollow portion 411. In this way, the size of the redistribution structure 41 can be reduced, thereby reducing the contact area between the redistribution structure 41 and the adjacent insulating layer, and further reducing the risk of peeling between the redistribution structure 41 and the adjacent insulating layer.

[0093] In step 130, a dielectric layer is formed, the dielectric layer covers the redistribution layer, and a through hole exposing the redistribution layer is provided on the dielectric layer.

[0094] In one embodiment, step 130 can be completed through the following process:

[0095] First, a dielectric layer is formed on the encapsulation structure, and the dielectric layer covers the redistribution layer 40 and the exposed encapsulation layer.

[0096] Through this step, the fourth intermediate structure as shown in Figure 8 can be obtained. Refer to Figure 8 , the dielectric layer 50 completely covers the redistribution layer 40.

[0097] Subsequently, through holes exposing the redistribution layer are formed on the dielectric layer.

[0098] Through this step, the fifth intermediate structure as shown in Figure 9 can be obtained. Refer to Figure 9 , a plurality of through holes 51 are provided on the dielectric layer 50. One or more through holes 51 can be provided in the portion of the dielectric layer 50 corresponding to a redistribution structure 41 in the longitudinal direction, that is, a redistribution structure 41 can correspond to one or more through holes 51. The size of the through hole 51 is smaller than the size of the redistribution structure 41, and the through hole 51 exposes a part of the surface of the redistribution structure 41.

[0099] In one embodiment, the material of the dielectric layer 50 can be a plastic encapsulation film, PI, PBO, an organic polymer film, an organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers can also be added to the dielectric layer 50.

[0100] In one embodiment, a laser process can be used to form the through holes 51 on the dielectric layer 50.

[0101] In step 140, a pin layer is formed on the side of the dielectric layer facing away from the chip, and the pin layer is electrically connected to the redistribution layer through the through hole.

[0102] Through step 140, the sixth intermediate structure as shown in Figure 10 can be obtained. Refer to Figure 10 , the pin layer 60 includes a plurality of spaced conductive posts 61, and the conductive posts 61 protrude from the dielectric layer 50.

[0103] Since the pin layer 60 is located on the side of the dielectric layer 50 away from the chip 20 and the conductive posts 61 protrude from the dielectric layer 50, it is not necessary to grind the dielectric layer 50. Compared with the solution of forming the dielectric layer after forming the pin layer and exposing the pin layer by grinding the dielectric layer, the time for grinding the dielectric layer can be saved, the packaging efficiency can be improved, and the production cost can be reduced. At the same time, the problem of poor thickness uniformity of the dielectric layer caused by the low precision of the grinding process can be avoided, and the problem of damaging the solder pads of the chip due to grinding the pin layer when grinding the dielectric layer can be avoided, which helps to improve the quality of the packaged product.

[0104] In one embodiment, a conductive portion 52 is formed in the through hole 51 of the dielectric layer 50. The conductive portions 52 are in direct contact with the redistribution structure 41 and the conductive posts 61 respectively, and the conductive posts 61 are electrically connected to the redistribution structure 41 through the conductive portions 52. The conductive posts 61 and the conductive portions 52 can be formed in the same process step, which helps to simplify the semiconductor packaging process.

[0105] In one embodiment, an electroplating process can be used to form the pin layer 60 on the side of the dielectric layer 50 away from the chip. Since the pin layer 60 is formed on the dielectric layer 50 and does not directly contact the redistribution layer 40, a conductive layer with a larger thickness can be formed on the side of the dielectric layer 50 away from the chip through the electroplating process, and thus the pin layer 60 obtained by etching the conductive layer has a larger thickness.

[0106] In one embodiment, the thickness d of the pin layer 60 is greater than 30 μm. With such a setting, the breakdown voltage of the semiconductor packaging structure can be effectively improved. In some embodiments, the conductive portion 52 and the pin layer 60 can be formed simultaneously. With such a setting, it can also be avoided that the portion of the conductive portion 52 located at the side wall of the through hole 51 breaks due to the small thickness of the conductive portion 52. In some embodiments, the thickness d of the pin layer 60 is, for example, 31 μm, 33 μm, 35 μm, 37 μm, 40 μm, etc.

[0107] In one embodiment, the semiconductor packaging method further includes: forming a heat dissipation layer on the side of the dielectric layer 50 away from the chip.

[0108] Participate Figure 11 , the heat dissipation layer 80 has a larger area, which can make the heat dissipation effect of the semiconductor packaging structure better. Each chip 20 can correspond to a heat dissipation layer 80, and the plurality of conductive posts 61 of the chip 20 can be located on the periphery of its corresponding heat dissipation layer 80.

[0109] In one embodiment, the heat dissipation layer 80 and the pin layer 60 can be formed in the same process step. This helps to simplify the semiconductor packaging process. At this time, the heat dissipation layer 80 can all protrude from the dielectric layer 50.

[0110] In one embodiment, after step 150 of forming a pin layer on a side of the dielectric layer facing away from the chip, the semiconductor packaging method further includes:

[0111] Forming a solder layer that covers the surface of the conductive posts protruding from the dielectric layer.

[0112] Through this step, a semiconductor packaging structure as shown in Figure 12 can be obtained.

[0113] Since the conductive posts 61 of the pin layer 60 are located on a side of the dielectric layer 50 facing away from the chip, that is, the conductive posts 61 are all exposed from the dielectric layer 50, the solder has good climbing ability when forming the solder layer, and the formed solder layer 70 can cover the entire surface of the conductive posts 61 protruding from the dielectric layer, that is, the solder layer 70 covers the side walls and the surface facing away from the chip 20 of the conductive posts 61. Thus, as shown in Figure 13 , when the semiconductor packaging structure is welded to the circuit board 90, the side walls of the conductive posts 61 and the solder layer 70 on the surface facing away from the chip 20 can be welded to the circuit board. Compared with the solution where only the surface of the conductive posts facing away from the chip is exposed from the dielectric layer and only the surface of the conductive posts facing away from the chip forms a solder layer, the conductive posts 61 of the semiconductor packaging structure obtained in the embodiment of the present application have higher welding reliability with the circuit board. At the same time, compared with the solution of forming solder balls through a reflow soldering process, the process of the embodiment of the present application is simpler.

[0114] In some embodiments, the material of the solder layer 70 can be a material that can achieve a welding function, such as metallic tin, a gold-tin alloy, or a nickel-based alloy.

[0115] In some embodiments, the solder layer 70 can be formed by processes such as electroplating, electroless plating, or stencil printing. Preferably, the electroplating process can be used to form the solder layer 70 on the surface of the conductive posts. This can make the overall thickness of the semiconductor packaging structure more controllable, and at the same time ensure the thickness uniformity of the semiconductor packaging structure. For board-level packaging, it can effectively improve the packaging efficiency and help reduce costs; at the same time, it can make the thickness of the formed solder layer 70 larger, and can improve the welding reliability of the semiconductor packaging structure with other components.

[0116] In one embodiment, since the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip, that is, the heat dissipation layer 80 is completely exposed from the dielectric layer 50, the solder has better climbing ability when forming the solder layer, and the solder layer 70 covers the surface of the part of the heat dissipation layer 80 protruding from the dielectric layer. When the semiconductor package structure is soldered to the circuit board, the solder layer 70 on the surface of the heat dissipation layer 80 can be evenly soldered to the circuit board. Compared with the solution where only the surface of the heat dissipation layer away from the chip is exposed from the dielectric layer and the solder layer is only formed on the surface of the heat dissipation layer away from the chip, the reliability of soldering between the heat dissipation layer of the semiconductor package structure obtained in the embodiment of the present application and the circuit board is higher.

[0117] In one embodiment, referring again to Figure 11 , when forming the solder layer, first form a tinned wire 71, the tinned wire 71 is electrically connected to each conductive bump 61 and the heat dissipation layer 80, and then the tinned wire 71 is electrically connected to an external power supply for electroplating to form a solder layer 70 on the side wall and the surface away from the chip of the conductive bump 61, and on the side wall and the surface away from the chip of the heat dissipation layer 80.

[0118] In one embodiment, referring to Figure 14 , the size of the through hole 51 is larger, which can prevent the part of the conductive part 52 located on the side wall of the through hole 51 of the dielectric layer 50 from breaking; the solder layer 70 fills the recess formed by the conductive part 52. In this way, the contact area between the solder layer 70 and the conductive bump 61 of the pin layer 60 is larger, the bonding force is better, and at the same time, it can provide enough filling space for the solder layer 70, and the solder layer 70 can be made thicker, which helps to improve the reliability of soldering between the semiconductor package structure and the circuit board.

[0119] In some embodiments, the ratio of the width to the depth of the through hole 51 is greater than or equal to 1 / 3. With such a setting, the formed conductive part 52 is more likely to form a recess at the through hole 51, which is more helpful to increase the contact area between the conductive bump 61 and the solder layer 70. The ratio of the width D to the depth H of the through hole 51 is, for example, 1 / 3, 1 / 2, 2 / 3, 3 / 4, 3 / 2, etc.

[0120] In one embodiment, the depth H of the through hole 51 ranges from 60 μm to 100 μm, and the thickness S of the portion of the conductive portion 52 located at the bottom wall of the through hole 51 ranges from 10 μm to 50 μm. Such a configuration is more conducive to providing sufficient filling space for the solder layer 70 in the through hole 51, thereby improving the reliability of welding the semiconductor package structure with other structures. In some embodiments, the depth H of the through hole 51 (hereinafter referred to as the depth H) is 100 μm, the thickness S of the portion of the conductive portion 52 located at the bottom wall of the through hole 51 (hereinafter referred to as the thickness S) is 40 μm, and the width D of the through hole 51 (hereinafter referred to as the width D) is 50 μm; or, the depth H is 80 μm, the thickness S is 35 μm, and the width D is 40 μm or 80 μm; or, the depth H is 60 μm, the thickness S is 25 μm, and the width D is 30 μm or 80 μm, etc.

[0121] The present application also provides a semiconductor packaging structure. Figure 12 and Figure 14 The semiconductor package structure includes an encapsulation structure, a redistribution layer 40 , a dielectric layer 50 and a pin layer 60 .

[0122] The encapsulation structure includes an encapsulation layer 30 and a chip 20. A plurality of pads 21 are provided on the front of the chip 20, and the encapsulation layer 30 at least covers the side of the chip 20. The rewiring layer 40 is located on the side of the encapsulation structure close to the front of the chip 20, and the rewiring layer 40 leads out the pads 21 of the chip 20. The side of the encapsulation structure close to the front of the chip 20 refers to the side where the front of the chip 20 is located. The dielectric layer 50 covers the rewiring layer 40, and a through hole 51 is provided on the dielectric layer 50 to expose a portion of the rewiring layer 40. The pin layer 60 is located on the side of the dielectric layer 50 away from the chip 20, and the pin layer 60 is electrically connected to the rewiring layer 40 through the through hole 51.

[0123] The semiconductor package structure provided by the embodiments of the present application has a dielectric layer covering the redistribution layer. The pin layer is located on the side of the dielectric layer away from the redistribution layer. The pin layer is electrically connected to the redistribution layer through vias in the dielectric layer, that is, the pin layer and the redistribution layer do not directly contact each other. Then, the size of the pin layer is not affected by the redistribution layer, and the area of the redistribution layer can be set smaller, reducing the contact area between the redistribution layer and adjacent insulating layers such as the dielectric layer, reducing the stress difference between the redistribution layer and the adjacent insulating layer, and further reducing the risk of delamination between the redistribution layer and the insulating layer or warping of the redistribution layer, which helps to improve the quality of the product. Since the pin layer and the redistribution layer do not directly contact each other, the thickness of the pin layer is not affected by the redistribution layer, and the thickness design of the pin layer is more flexible, which helps to increase the thickness of the formed pin layer, thereby increasing the breakdown voltage of the semiconductor package structure, facilitating the application of the semiconductor package structure in a high-voltage environment, and expanding the application range of the semiconductor package structure.

[0124] In one embodiment, a protective layer 22 is formed on the front surface of the chip 20, and an opening 23 exposing the pad 21 is provided on the protective layer 22. The size of the opening 23 can be smaller than the size of the pad 21, and the opening 23 exposes a part of the surface of the pad 21 that is opposite.

[0125] The material of the protective layer 22 can be a plastic film, PI, PBO, an organic polymer film, an organic polymer composite material, or other materials with similar properties. In some embodiments, organic or inorganic fillers can also be added to the protective layer 22.

[0126] When forming the encapsulation layer, high-pressure molding is required. During this process, the encapsulation material for forming the encapsulation layer easily penetrates between the carrier substrate 10 and the chip 20. By forming a protective layer 22 on the front surface of the chip 20, the protective layer 22 can prevent the encapsulation material from penetrating to the surface of the chip 20. Moreover, even if the encapsulation material penetrates into the protective layer 22 when forming the encapsulation layer 30, after the carrier substrate 10 and the chip 20 are peeled off, the surface of the protective layer 22 can be directly treated by chemical means or grinding means without directly contacting the front surface of the chip 20, thereby avoiding damaging the pads on the front surface of the chip 20.

[0127] In one embodiment, a conductive structure 24 is formed in the opening 23 of the protective layer 22. The conductive structure 24 is in direct contact with the redistribution structure 41, and the redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24. The material of the conductive structure 24 and the material of the redistribution structure 41 can be the same, so that the conductive structure 24 and the redistribution structure 41 can be formed in the same process step, which helps to simplify the packaging process for forming the semiconductor package structure.

[0128] In one embodiment, the rewiring layer 40 includes a plurality of rewiring structures 41 arranged at intervals. Each rewiring structure 41 may be electrically connected to one pad 21 or to a plurality of pads 21.

[0129] In one embodiment, see Figure 7 The rewiring structure 41 is provided with a hollow portion 411. In this way, the size of the rewiring structure 41 can be reduced, thereby reducing the contact area between the rewiring structure 41 and the adjacent insulating layer, and further reducing the risk of peeling between the rewiring structure 41 and the adjacent insulating layer.

[0130] In one embodiment, a plurality of through holes 51 are provided on the dielectric layer 50. A portion of the dielectric layer 50 corresponding to a rewiring structure 41 in the longitudinal direction may be provided with one through hole 51 or multiple through holes 51, that is, one rewiring structure 41 may correspond to one through hole 51 or multiple through holes 51. The size of the through hole 51 is smaller than the size of the rewiring structure 41, and the through hole 51 exposes a portion of the surface of the rewiring structure 41.

[0131] In one embodiment, the material of the dielectric layer 50 may be a plastic film, PI, PBO, an organic polymer film, an organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may also be added to the dielectric layer 50 .

[0132] In one embodiment, the pin layer 60 includes a plurality of conductive protrusions 61 arranged at intervals, and the conductive protrusions 61 protrude from the dielectric layer 50 .

[0133] Since the pin layer 60 is located on the side of the dielectric layer 50 away from the chip 20, and the conductive protrusion 61 protrudes from the dielectric layer 50, there is no need to grind the dielectric layer 50. Compared with the solution of forming the dielectric layer after forming the pin layer and exposing the pin layer by grinding the dielectric layer, the time for grinding the dielectric layer can be saved, the packaging efficiency can be improved, and the production cost can be reduced. At the same time, the problem of poor uniformity of the dielectric layer thickness due to the low precision of the grinding process can be avoided, and the pin layer can be avoided from being ground when grinding the dielectric layer, which will damage the chip's solder pad due to the stress on the pin layer, and help improve the quality of the packaged product.

[0134] In one embodiment, a conductive portion 52 is formed in the through hole 51 of the dielectric layer 50, and the conductive portion 52 is in direct contact with the rewiring structure 41 and the conductive protrusion 61 respectively, and the conductive protrusion 61 is electrically connected to the rewiring structure 41 through the conductive portion 52. The material of the conductive protrusion 61 and the material of the conductive portion 52 can be the same, so that the conductive protrusion 61 and the conductive portion 52 can be formed in the same process step, which helps to simplify the packaging process of the semiconductor packaging structure.

[0135] In one embodiment, the thickness d of the pin layer 60 is greater than 30 μm. With such a setting, the breakdown voltage of the semiconductor package structure can be effectively improved; in some embodiments, the conductive part 52 and the pin layer 60 are formed simultaneously, and this setting can also prevent the part of the conductive part 52 located on the side wall of the through hole 51 from breaking. In some embodiments, the thickness of the pin layer 60 is, for example, 31 μm, 33 μm, 35 μm, 37 μm, 40 μm, etc.

[0136] In one embodiment, referring to Figure 11 , the semiconductor package structure further includes a heat dissipation layer 80. The heat dissipation layer 80 has a relatively large area, which can make the heat dissipation effect of the semiconductor package structure better. Each chip 20 can correspond to a heat dissipation layer 80, and a plurality of conductive studs 61 of the chip 20 can be located on the periphery of its corresponding heat dissipation layer 80.

[0137] In one embodiment, the material of the heat dissipation layer 80 can be the same as that of the pin layer 60, so the heat dissipation layer 80 and the pin layer 60 can be formed in the same process step, which helps to simplify the packaging process of the semiconductor package structure. At this time, the heat dissipation layer 80 can protrude entirely from the dielectric layer 50.

[0138] In one embodiment, the semiconductor package structure further includes a solder layer 70, and the solder layer 70 covers the surface of the conductive stud 61 protruding from the dielectric layer 50.

[0139] Since the conductive stud 61 of the pin layer 60 is located on the side of the dielectric layer 50 away from the chip, and the conductive stud 61 protrudes from the dielectric layer 50, that is, the conductive stud 61 is entirely exposed from the dielectric layer 50, the climbing ability of the solder during the formation of the solder layer is better, and the formed solder layer 70 can cover the entire surface of the conductive stud 61 protruding from the dielectric layer, that is, the solder layer 70 covers the side wall and the surface away from the chip 20 of the conductive stud 61. Thus, as Figure 13 shown, when the semiconductor package structure is welded to the circuit board 90, the side wall of the conductive stud 61 and the solder layer 70 on the surface away from the chip 20 can both be welded to the circuit board. Compared with the solution where only the surface of the conductive stud away from the chip is exposed from the dielectric layer and only the surface of the conductive stud away from the chip forms a solder layer, the reliability of the welding of the conductive stud 61 of the semiconductor package structure provided by the embodiment of the present application to the circuit board is higher.

[0140] In one embodiment, since the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip, that is, the heat dissipation layer 80 is completely exposed from the dielectric layer 50, the solder has good climbing ability when forming the solder layer, and the solder layer 70 covers the surface of the portion of the heat dissipation layer 80 protruding from the dielectric layer. When the semiconductor package structure is soldered to the circuit board, the side wall of the heat dissipation layer 80 and the solder layer 70 on the surface away from the chip 20 can both be soldered to the circuit board. Compared with the solution where only the surface of the heat dissipation layer away from the chip is exposed from the dielectric layer and the solder layer is only formed on the surface of the heat dissipation layer away from the chip, the reliability of soldering the heat dissipation layer of the semiconductor package structure provided in the embodiment of the present application to the circuit board is higher.

[0141] In some embodiments, the material of the solder layer 70 can be a material that can achieve the soldering function, such as metallic tin, gold-tin alloy, or nickel-based alloy.

[0142] In some embodiments, the solder layer 70 can be formed by processes such as electroplating, electroless plating, or stencil printing. Preferably, the electroplating process can be used to form the solder layer 70 on the surface of the conductive posts. In this way, the overall thickness of the semiconductor package structure can be more controllable, and at the same time, the thickness uniformity of the semiconductor package structure can be ensured. For board-level packaging, the packaging efficiency can be effectively improved, which helps to reduce costs; at the same time, the thickness of the formed solder layer 70 can be made larger, which can improve the reliability of soldering the semiconductor package structure to other components.

[0143] In one embodiment, referring to Figure 14 , the size of the through hole 51 is relatively large, and a depression is formed at the position of the conductive part 52 corresponding to the through hole 51 of the dielectric layer 50; the solder layer 70 fills the depression. In this way, the contact area between the solder layer 70 and the conductive posts 61 of the pin layer 60 is larger, and the bonding force is better. At the same time, the solder layer 70 can also be made thicker, which helps to improve the reliability of soldering the semiconductor package structure to the circuit board.

[0144] In some embodiments, the ratio of the width to the depth of the through hole 51 is greater than or equal to 1 / 3. With such a setting, the formed conductive part 52 is more likely to form a depression at the through hole 51, which is more helpful to increase the contact area between the conductive posts 61 and the solder layer 70. The ratio of the width to the depth of the through hole 51 is, for example, 1 / 3, 1 / 2, 2 / 3, 3 / 4, 3 / 2, etc.

[0145] In one embodiment, the depth H of the through hole 51 ranges from 60 μm to 100 μm, and the thickness S of the portion of the conductive portion 52 located at the bottom wall of the through hole 51 ranges from 10 μm to 50 μm. With such a setting, it is more helpful to provide sufficient filling space for the solder layer 70 in the through hole 51, thereby improving the welding reliability between the semiconductor packaging structure and other structures. In some embodiments, the depth H (hereinafter referred to as depth H) of the through hole 51 is 100 μm, the thickness S (hereinafter referred to as thickness S) of the portion of the conductive portion 52 located at the bottom wall of the through hole 51 is 40 μm, and the width D (hereinafter referred to as width D) of the through hole 51 is 50 μm; or, the depth H is 80 μm, the thickness S is 35 μm, and the width D is 40 μm or 80 μm; or, the depth H is 60 μm, the thickness S is 25 μm, and the width D is 30 μm or 80 μm, etc.

[0146] The semiconductor packaging method and the semiconductor packaging structure provided by the embodiments of the present application belong to the same inventive concept. For the description of relevant details and beneficial effects, reference can be made to each other and will not be repeated here.

[0147] It should be noted that the drawings provided by the embodiments of the present application are only schematic and may have some differences from the actual structure. For example, the pads on the front side of the chip are not schematically shown in the drawings, and in practice, the pads on the front side of the chip are electrically connected to the redistribution structure.

[0148] It should be pointed out that in the drawings, the dimensions of layers and regions may be exaggerated for the sake of clarity of illustration. And it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Further, it can be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Like reference numerals throughout indicate like elements.

[0149] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are to be considered as exemplary only, and the true scope and spirit of the present application are pointed out by the following claims.

[0150] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A semiconductor packaging method, characterized in that, Comprising: Forming an encapsulation structure, the encapsulation structure including an encapsulation layer and a chip, the front side of the chip being provided with a plurality of pads, and the encapsulation layer covering at least the side surface of the chip; Forming a redistribution layer on one side of the encapsulation structure close to the front side of the chip, the redistribution layer leading out the pads of the chip; the redistribution layer including a plurality of spaced-apart redistribution structures, the redistribution structures being provided with hollow portions; Forming a dielectric layer, the dielectric layer covering the redistribution layer, and a through hole exposing the redistribution layer being provided on the dielectric layer; Forming a pin layer on one side of the dielectric layer facing away from the chip, the pin layer being electrically connected to the redistribution layer through the through hole.

2. The semiconductor packaging method according to claim 1, wherein, The pin layer includes a plurality of spaced-apart conductive bumps protruding from the dielectric layer; After forming the pin layer on one side of the dielectric layer facing away from the chip, the semiconductor packaging method further includes: Forming a solder layer, the solder layer covering the surface of the conductive bumps protruding from the dielectric layer.

3. The semiconductor packaging method according to claim 1, wherein, The pin layer includes a plurality of spaced-apart conductive bumps protruding from the dielectric layer; a conductive portion is provided in the through hole, the pin layer is electrically connected to the redistribution layer through the conductive portion, and a depression is formed at a position corresponding to the through hole of the conductive portion; After forming the pin layer on one side of the dielectric layer facing away from the chip, the semiconductor packaging method further includes: Forming a solder layer, the solder layer covering the surface of the conductive bumps protruding from the dielectric layer, and the solder layer filling the depression.

4. The semiconductor packaging method according to claim 3, wherein, The ratio of the width to the depth of the through hole is greater than or equal to 1 / 3.

5. The semiconductor packaging method according to claim 4, wherein The depth range of the through hole is 60 μm to 100 μm; the thickness range of the portion of the conductive portion located at the bottom wall of the through hole is 10 μm to 50 μm.

6. The semiconductor packaging method according to claim 1, wherein The thickness of the pin layer is greater than 30 μm.

7. The semiconductor packaging method according to claim 1, wherein The semiconductor packaging method further includes: forming a heat dissipation layer on one side of the dielectric layer facing away from the chip; After forming the heat dissipation layer on one side of the dielectric layer facing away from the chip, the semiconductor packaging method further includes: forming a solder layer, the solder layer covering the surface of the portion of the heat dissipation layer exposed from the dielectric layer.

8. A semiconductor package structure, characterized in that, The semiconductor packaging structure includes: An encapsulation structure, the encapsulation structure including an encapsulation layer and a chip, the front side of the chip being provided with a plurality of pads, and the encapsulation layer covering the back side and the side surface of the chip; A redistribution layer, located on one side of the encapsulation structure close to the front side of the chip, the redistribution layer leading out the pads of the chip; the redistribution layer includes a plurality of spaced-apart redistribution structures, and the redistribution structures are provided with hollow portions; A dielectric layer, covering the redistribution layer, and a through hole exposing the redistribution layer being provided on the dielectric layer; A pin layer, located on one side of the dielectric layer facing away from the chip, the pin layer being electrically connected to the redistribution layer through the through hole.

9. The semiconductor package structure according to claim 8, wherein, The pin layer includes a plurality of spaced-apart conductive bumps protruding from the dielectric layer; the semiconductor packaging structure further includes a solder layer, the solder layer covering the surface of the conductive bumps protruding from the dielectric layer.

10. The semiconductor package structure according to claim 8, wherein The pin layer includes a plurality of spaced-apart conductive posts protruding from the dielectric layer; a conductive portion is provided in the through hole, and the pin layer is electrically connected to the redistribution layer through the conductive portion, and a depression is formed at a position corresponding to the through hole of the conductive portion; The semiconductor package structure further includes a solder layer, the solder layer covers the surface of the conductive post protruding from the dielectric layer, and the solder layer fills the depression.

11. The semiconductor package structure according to claim 10, wherein The ratio of the width to the depth of the through hole is greater than or equal to 1 / 3.

12. The semiconductor package structure according to claim 11, wherein, The depth range of the through hole is 60 μm to 100 μm; the thickness range of the portion of the conductive portion located at the bottom wall of the through hole is 10 μm to 50 μm.

13. The semiconductor package structure according to claim 8, wherein The thickness of the pin layer is greater than 30 μm.

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