Method for testing diffusion depth of diffusion junction by voltage method

Abstract

The application discloses a method for testing diffusion depth by voltage method, which comprises the following steps: firstly, oxidizing the upper part of a silicon substrate; secondly, performing photoetching on the oxide layer according to a designed layout, wherein the shape of the photoetching pattern is square and the photoetching patterns are distributed in an array, the interval between two adjacent photoetching patterns in each row is increased in turn, and the interval between two adjacent rows is greater than the maximum value of the interval between any two adjacent photoetching patterns in the two rows; thirdly, removing the oxide layer in the photoetching area and photoresist used in the photoetching; fourthly, injecting or doping impurities into the photoetching area of the silicon substrate, and then removing the surface oxide layer; fifthly, connecting two probes with a graphic instrument, and testing the two adjacent photoetching patterns on the sample in the order of the interval from small to large; sixthly, continuing to test the next two adjacent photoetching patterns when the sample is broken down; and seventhly, recording the interval of the last two adjacent photoetching patterns when the sample cannot be broken down, and then obtaining the diffusion depth by combining the ratio of the lateral diffusion distance of the impurities to the diffusion depth, so that the method has low cost and wide application range.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of junction depth testing, and particularly relates to a method for testing diffusion junction depth by voltage method. BACKGROUND

[0002] In the process of semiconductor production and manufacturing, impurities are diffused into a certain area of a substrate silicon wafer by ion implantation annealing or high-temperature diffusion, and reach a certain depth, which is diffusion junction depth. Diffusion junction depths of various doped areas are key parameters for forming various semiconductor devices, and the parameters can be measured after each doping step.

[0003] By monitoring diffusion junction depth, on one hand, it can be monitored whether the process is stable, and on the other hand, it can be ensured that the process meets the requirements of device design, so as to ensure that the performance indicators of the finally formed device meet the requirements.

[0004] At present, methods for testing diffusion junction depth include C-V method, extended resistance method, grinding and dyeing method, dyeing and SEM method, etc. No matter which method is used, special testing equipment needs to be purchased, which not only causes trouble to the testing work, but also increases the cost. SUMMARY

[0005] In view of the problems in the prior art, the purpose of the present application is to provide a method for testing diffusion junction depth by voltage method, which uses commonly used graphic instruments and probes, and combines with layout design, so as to test diffusion junction depth by voltage method.

[0006] The present application is implemented by using the following technical solutions:

[0007] A method for testing diffusion junction depth by voltage method, comprising the following steps:

[0008] Step 1: The upper part of the silicon substrate wafer is first oxidized, and the upper part of the silicon substrate wafer forms an oxide layer. Then, the oxide layer is subjected to photolithography according to the designed layout. The shape of the pattern in the designed layout is a square and is distributed in an array. The distance between two adjacent patterns in each row increases successively. The distance between two adjacent rows is greater than the maximum value of the distance between any two adjacent patterns in the two rows. Finally, the oxide layer in the photolithography area and the photoresist in the photolithography are removed.

[0009] Step 2: Impurities are injected or doped into the photolithography area of the silicon substrate wafer obtained in step 1. The impurities are N-type or P-type. Then, the oxide layer on the surface of the silicon substrate wafer is removed to obtain a test wafer.

[0010] Step 3, connect two probes with the graphic instrument, and test the voltage of two adjacent photoetching patterns on the test sample in order of the distance from small to large, and continue to test the voltage of the next two adjacent photoetching patterns until the test sample is not broken down, then record the distance of the last two adjacent photoetching patterns, and combine the ratio of the lateral diffusion distance of the impurity and the diffusion depth to obtain the diffusion depth in the test sample.

[0011] Preferably, the side length of the pattern in step 1 is 5-200 μm, and the distance between two adjacent patterns in each row is 3-200 μm.

[0012] Preferably, the distance between two adjacent patterns in each row in step 1 increases by 0.1-5 μm successively.

[0013] Preferably, step 1 is carried out at 1000-1200 °C for 2-2.5 h on the upper part of the silicon substrate, wherein the hydrogen flow rate is 3-7 L / min, the oxygen flow rate is 5-9 L / min, and the thickness of the formed oxide layer is 800-1100 nm.

[0014] Preferably, step 1 uses a wet etching method to remove the oxide layer in the photoetching area.

[0015] Preferably, step 2 first uses a diffusion temperature of 900-1200 °C to dope the impurity, or implants the impurity under the conditions of an implantation dose of 10 13 ~10 17 cm -2 , an implantation energy of 20-160 keV, and an annealing temperature of 800-1200 °C, and then removes the oxide layer on the surface of the silicon substrate.

[0016] Preferably, step 2 uses HF acid to remove the oxide layer on the surface of the silicon substrate to obtain the test sample.

[0017] Preferably, step 3 places the test sample on the sample holder of the probe station, and the detection ends of the two probes are pressed on two adjacent photoetching patterns on the test sample to test the voltage.

[0018] Preferably, step 3 uses a scanning voltage of 0-10 V to test the voltage of the two adjacent photoetching patterns.

[0019] Preferably, step 3 uses the following formula to obtain the diffusion depth in the test sample:

[0020] wherein X j is the diffusion depth in the test sample, d is the distance between the two adjacent photoetching patterns recorded in step 3, and a is the ratio of the lateral diffusion distance of the impurity to the diffusion depth in the test sample.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] The method for testing diffusion junction depth by voltage method provided by the present application first performs oxidation on the upper part of the silicon substrate sheet, so that the upper part of the silicon substrate sheet forms an oxide layer; the shape of the pattern is square and the pattern is distributed in an array form during layout design, the distance between the two adjacent patterns in each row is increased in turn, and the distance between the two adjacent rows is greater than the maximum value of the distance between the patterns in the two rows, so that the oxide layer is subjected to photoetching according to the layout, which facilitates the subsequent injection or incorporation of N-type or P-type impurities in the photoetched area of the silicon substrate sheet, and the patterns will not be affected, the oxide layer can effectively mask the injected impurities or diffused impurities, and the required diffusion junction depth can be formed in the silicon substrate sheet. The oxide layer on the surface of the silicon substrate sheet is removed, and a test sheet is obtained. Two probes are connected to a plotter, so that the detection ends of the probes can perform voltage testing on the adjacent two photoetched patterns on the test sheet, and then a test curve is called out to determine whether the test sheet is broken down. When breakdown occurs, voltage testing is continuously performed on the next adjacent two photoetched patterns, until the test sheet cannot be broken down. The maximum distance between the patterns corresponding to the breakdown characteristics of the test curve is obtained by the method, and the distance is twice the lateral diffusion distance of the impurities. In combination with the ratio of the lateral diffusion distance of the impurities to the diffusion junction depth, the diffusion junction depth in the test sheet is obtained. The present application can be realized by using a commonly used plotter and probes, without the need to purchase special test equipment. Compared with other test equipment, the method has lower equipment cost, simple theory and easy understanding, different process technicians can design layouts with different distances according to different junction depth ranges, and the method can obtain test results with high repeatability, with an absolute deviation of about 1%, and is widely applicable. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The flowchart of the method for testing diffusion junction depth by voltage method shown in the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. The following embodiments are only a part of the embodiments of the present application, and are not used to limit the scope of the present application.

[0025] Referring to Figure 1 , the method for testing diffusion junction depth by voltage method provided by the present application comprises the following steps:

[0026] 1) performing layout design on a photoetching plate to obtain a series of patterns with the same size and distributed in an array form. The pattern design is specifically a square with a side length of 5 μm to 200 μm. Such pattern size can meet the normal testing of the probes later.

[0027] The interval between two adjacent patterns in each row is designed to be 3 μm-200 μm, and the interval between the patterns in the first row in the plane of the photoetching plate increases by 0.1 μm-5 μm from left to right, and the interval between the first two patterns in the second row is 0.1 μm-5 μm larger than that between the last two patterns in the first row; the interval between the patterns in each adjacent two rows is larger than the maximum of the interval between any two adjacent patterns in the two rows, and the interval between the patterns in the adjacent two rows is larger than that between the rightmost two patterns in the lower row according to the above rule;

[0028] 2) Prepare a silicon substrate sheet of the type opposite to the type of the injected impurities or diffused impurities, oxidize the upper part of the silicon substrate sheet, and adopt 1000°C-1200°C, hydrogen:oxygen volume ratio of 0.7-1.4 (safe ratio, or other), hydrogen flow rate (3-7) L / min, oxygen flow rate (5-9) L / min, 2h-2.5h, so that a part of the thickness of the silicon substrate sheet reacts with oxygen to form an 800 nm-1100 nm thick oxide layer, and the purpose of growing the oxide layer is to effectively mask the injected impurities or diffused impurities. Apply a photoresist (PR for short) on the oxide layer, and perform photoetching using the layout designed in step 1);

[0029] 3) Remove the oxide layer in the photoetched area by wet etching method, expose the underlying silicon substrate, and then remove the surface photoresist to obtain a treated silicon substrate sheet;

[0030] In this way, the size of the pattern obtained is consistent with the layout design;

[0031] 4) Inject N-type impurities or P-type impurities into the photoetched area of the silicon substrate sheet obtained in step 3) under the conditions of an injection dose of (10 13 -10 17 ) cm -2 , and an injection energy of 20 keV-160 keV, and obtain a 2 μm-100 μm diffused junction depth after high-temperature annealing at 800°C-1200°C;

[0032] Or, diffuse N-type impurities or P-type impurities under the condition of a diffusion temperature of 900°C-1200°C and an N-type or P-type impurity atmosphere to obtain a 2 μm-100 μm diffused junction depth;

[0033] 5) Remove the surface oxide layer by HF acid according to the wet etching process to obtain a test sample sheet;

[0034] 6) Set the current range of the plotter to 1 μA and the voltage range to 100 mV, i.e. one range corresponds to 1 μA and 100 mV; place the test sample on the sample holder of the probe station, adjust the positions of the two probes, and remove the oxide layer; because the silicon loss amounts of the masking area and the doped area are different, the lithographic patterns can still be seen, so align two adjacent lithographic patterns in order of the pattern spacing from small to large, press the two probes on the two adjacent lithographic patterns, connect the two probes with the high and low potentials of the plotter respectively, adjust the scanning voltage knob, and perform voltage testing on the two adjacent lithographic patterns, and adjust the test curve; the scanning voltage is generally selected as 0 V-10 V; when the test sample is broken down, continue to perform voltage testing on the next two adjacent lithographic patterns, until the test sample cannot be broken down, and the maximum pattern spacing corresponding to the breakdown characteristic of the test curve between the two adjacent lithographic patterns can be obtained by this method (e.g. the pattern spacing corresponding to the point of the middle breakdown), and the pattern spacing is twice the lateral diffusion distance of the impurities; and the diffusion depth can be calculated according to the ratio of the lateral diffusion distance of the impurities to the diffusion depth according to the following formula: Figure 1

[0035] d is the pattern spacing, d / 2 is the lateral diffusion distance of the impurities; a is the ratio of the lateral diffusion distance of the impurities to the diffusion depth, and the typical value corresponding to the silicon substrate sheet selected by the present application is 0.8, which generally has a slight change and can be measured by other methods; X j is the diffusion depth, and the unit is μm.

[0036] Example 1

[0037] 1) Perform layout design on the lithographic plate, and the pattern design is a square with a side length of 20 μm; the spacing between the two adjacent patterns in each row is designed to be 3 μm-30 μm; the pattern spacing in the first row in the plane of the lithographic plate increases by 0.1 μm in order from left to right; the spacing between the first two patterns in the second row is 0.1 μm larger than the spacing between the last two patterns in the first row; and the pattern spacing between each adjacent two rows is greater than the spacing between the two rightmost patterns in the lower row;

[0038] 2) Prepare a silicon substrate sheet with an opposite type of injected impurities, oxidize the upper part of the silicon substrate sheet, adopt 1000 ℃, hydrogen flow rate 3 L / min, oxygen flow rate 5 L / min, and 2 h, and the part of the thickness of the silicon substrate sheet reacts with oxygen to form an 800 nm thick oxide layer; coat PR on the oxide layer, and perform photolithography using the layout designed in step 1);

[0039] 3) Remove the oxide layer in the photolithographic area by wet etching method, expose the underlying silicon substrate, and then remove the surface PR to obtain the treated silicon substrate sheet;

[0040] ​4) The silicon substrate slice obtained in step 3) is subjected to photolithography, and N-type impurities are implanted at an implantation energy of 20 keV and an implantation dose of 10 13 cm -2 After high-temperature annealing at 800°C, a diffusion junction depth is obtained.

[0041] 5) The surface oxide layer is removed by using HF acid according to a wet etching process, and a test sample is obtained.

[0042] 6) The current range of the curve tracer is set to 1 μA, and the voltage range is set to 100 mV. The test sample is placed on the sample holder of the probe station. The positions of the two probes are adjusted. The two adjacent photolithography patterns are aligned in order of increasing distance. The two probes are pressed against the two adjacent photolithography patterns. The two probes are connected to the high and low potentials of the curve tracer, respectively. The scanning voltage knob is adjusted. The voltage test is performed on the two adjacent photolithography patterns. The scanning voltage is selected to be 0 V-10 V. The test is stopped when the two adjacent photolithography patterns cannot be broken down. The distance between the two adjacent photolithography patterns is 14.4 μm. The diffusion junction depth is calculated according to the following formula:

[0043] d is the distance between the two adjacent photolithography patterns. Therefore, the diffusion junction depth is 9 μm.

[0044] Example 2

[0045] 1) A layout is designed on a photolithography plate. The pattern is a square with a side length of 200 μm. The distance between the two adjacent patterns in each row is designed to be 5-200 μm. The distance between the two adjacent patterns in the first row on the plane of the photolithography plate is increased by 1 μm from left to right. The distance between the two patterns at the beginning of the second row is 1 μm greater than the distance between the two patterns at the end of the first row. The distance between the two adjacent patterns in each row is greater than the distance between the two patterns at the right end of the next row.

[0046] 2) A silicon substrate slice opposite to the implanted impurities is prepared. The upper part of the silicon substrate slice is oxidized at 1200°C, a hydrogen flow rate of 7 L / min, an oxygen flow rate of 9 L / min, and for 2.5 h. The thickness of the silicon substrate slice is reacted with oxygen to form an oxide layer with a thickness of 1100 nm. PR is coated on the oxide layer, and photolithography is performed using the layout designed in step 1).

[0047] 3) The oxide layer in the photolithography region is removed by a wet etching method, and the PR on the surface is removed, to obtain a treated silicon substrate slice.

[0048] 4) The silicon substrate slice obtained in step 3) is subjected to photolithography, and N-type impurities are implanted at an implantation energy of 20 keV and an implantation dose of 10 15 cm -2, and a diffusion junction depth is obtained after a high temperature annealing process at 1200°C;

[0049] 5) The surface oxide layer is removed by using HF acid according to a wet etching process, and a test sample is obtained;

[0050] 6) The current range of the plotter is set to 1 μA, and the voltage range is set to 100 mV. The test sample is placed on the sample holder of the probe table. The positions of the two probes are adjusted. The two adjacent photoetching patterns are aligned and pressed by the two probes. The two probes are connected to the high and low potentials of the plotter, respectively. The scanning voltage knob is adjusted. The voltage test is performed on the two adjacent photoetching patterns. The scanning voltage is selected as 0 V-10 V. The operation is stopped when the next two adjacent photoetching patterns cannot be broken down. The pattern spacing is 45 μm. The diffusion junction depth is calculated according to the formula in Embodiment 1:

[0051] X j = 28.1 μm.

[0052] Embodiment 3

[0053] 1) The layout design is performed on the photoetching plate. The pattern design is a square with a side length of 50 μm. The spacing between the two adjacent patterns in each row is designed as 3 μm-100 μm. The pattern spacing in the first row of the plane of the photoetching plate is sequentially increased by 1 μm from left to right. The spacing between the first two patterns in the second row is 1 μm larger than that between the last two patterns in the first row. The pattern spacing between each adjacent two rows is larger than that between the rightmost two patterns in the lower row.

[0054] 2) A silicon substrate sheet opposite to the diffusion impurity type is prepared. The upper part of the silicon substrate sheet is oxidized. The thickness of the silicon substrate sheet is reacted with oxygen at 1100°C, a hydrogen flow rate of 5 L / min, an oxygen flow rate of 7 L / min, and for 2.5 h to form a 1000 nm thick oxide layer. The PR is coated on the oxide layer, and the layout designed in step 1) is used for photoetching.

[0055] 3) The oxide layer in the photoetched area is removed by using a wet etching method, and the PR on the surface is removed to obtain a treated silicon substrate sheet.

[0056] 4) The silicon substrate sheet obtained in step 3) is doped with P-type impurities at a diffusion temperature of 1100°C and in a P-type impurity atmosphere to obtain a diffusion junction depth.

[0057] 5) The surface oxide layer is removed by using HF acid according to a wet etching process, and a test sample is obtained;

[0058] 6) Set the current range of the plotter to 1 μA and the voltage range to 100 mV, place the test sample on the sample holder of the probe station, adjust the positions of the two probes, align two adjacent photoetch patterns in order of their decreasing pitch, press the two probes on the two adjacent photoetch patterns, connect the two probes to the high and low voltage of the plotter, adjust the scanning voltage knob, and perform voltage test on the two adjacent photoetch patterns, and adjust the test curve, the scanning voltage is selected as 0 V-5 V, stop the operation when the next two adjacent photoetch patterns cannot be broken through, the pitch of the photoetch patterns is 56 μm, and the diffusion depth is calculated according to the formula in Embodiment 1:

[0059] X j = 35 μm.

[0060] The above is only used for illustrating the technical idea of the present application, and cannot limit the protection scope of the present application, any modification made according to the technical idea of the present application on the basis of the technical scheme falls within the protection scope of the present application.

Claims

1. A method of testing diffusion junction depth by voltage method, characterized by, The method comprises the following steps: Step 1: oxidizing the upper part of the silicon substrate sheet at 1000-1200 DEG C for 2-2.5 h, wherein the hydrogen flow rate is 3-7 L / min, the oxygen flow rate is 5-9 L / min, and the upper part of the silicon substrate sheet forms an oxide layer with a thickness of 800-1100 nm; then performing photoetching on the oxide layer according to a designed layout, wherein the shape of the pattern in the layout is a square with a side length of 5-200 μm, and the pattern is distributed in an array, the interval between two adjacent patterns in each row increases by 0.1-5 μm, the interval between two adjacent patterns in each row is 3-200 μm, and the interval between two adjacent rows is greater than the maximum value of the interval between two adjacent patterns in any row; and finally removing the oxide layer in the photoetched area and the photoresist used in the photoetching; Step 2: Impurities are implanted or doped into the photolithographic region of the silicon substrate obtained in Step 1. The impurities are N-type or P-type, and the doping is performed at a diffusion temperature of 900–1200°C. The implantation is carried out at a dose of 10 13 ~10 17 cm -2 The sample was annealed at 800–1200 °C under an energy of 20–160 keV, and then the oxide layer on the surface of the silicon substrate was removed to obtain the test sample. Step 3: connecting the two probes to the graphic tester, and performing voltage testing on two adjacent photoetched patterns on the test sheet with the detection ends of the two probes in the order of the interval of the photoetched patterns from small to large, the scanning voltage being 0-10 V; when the test sheet is broken down, continuing to perform voltage testing on the next two adjacent photoetched patterns, until the test sheet cannot be broken down, recording the interval d of the last two adjacent photoetched patterns, and obtaining the diffusion junction depth in the test sheet according to the following formula: X j = d / (2a), where X j is the diffusion junction depth in the test coupon, and a is the ratio of the lateral diffusion distance of the impurity described in step 2 to the diffusion junction depth in the test coupon.

2. The method of testing diffusion junction depth by voltage method according to claim 1, wherein, Step 1: removing the oxide layer in the photoetched area by using a wet etching method.

3. The method of testing diffusion junction depth by voltage method according to claim 1, wherein, Step 2: removing the oxide layer on the surface of the silicon substrate sheet by using HF acid to obtain a test sheet.

4. The method of testing diffusion junction depth by voltage method according to claim 1, wherein, Step 3: placing the test sheet on the sheet supporting table of the probe station, and pressing the detection ends of the two probes on two adjacent photoetched patterns on the test sheet to perform voltage testing. Step 4: obtaining the diffusion junction depth in the test sheet according to the following formula:

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