Double-sided wiring wafer sawing street structure and preparation method thereof

Abstract

The present invention provides a double-sided wiring wafer cutting road structure and a preparation method thereof, which can achieve firm adhesion of the cutting tape to the wafer cutting road structure, improve the wafer cutting quality, and increase the die yield. A double-sided wiring wafer cutting road structure includes multiple dies, and the thickness difference between the RDL wiring layer on the lower surface of the die and the cutting road area forms a U-shaped cutting road; a crossbeam is set in the middle of the U-shaped cutting road. A double-sided wiring wafer cutting road structure preparation method includes the following steps: temporarily bonding the upper surface of the wafer, and thinning the lower surface of the temporarily bonded wafer formed; sequentially preparing a dielectric layer, exposing TSV copper pillars, and preparing an RDL wiring layer on the lower surface of the thinned temporary bonded wafer; preparing an insulating layer on the surface of the RDL wiring layer, and preparing the crossbeam in the middle of the U-shaped cutting road, thereby completing the preparation of the wafer cutting road structure including the crossbeam.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design and manufacturing and advanced packaging technology, and in particular relates to a double-sided wiring wafer saw road structure and a preparation method thereof. Background Art

[0002] With the rise of 2.5D and 3D integration technologies, the market demand for TSV silicon transfer substrates has surged. Mass production of TSV silicon transfer substrates is required to meet market demand. In order to reduce the warpage of the TSV transfer substrate wafer during the process, the cutting lane area between dies is not covered with the RDL dielectric layer or metal layer. As the number of RDL wiring layers increases, the total thickness of the RDL layer can exceed 20μm, forming a deep U-shaped structure relative to the cutting road width of (60-80)μm. The existing technology cannot meet the film lamination and dicing processing problems of wafers with deep U-shaped cutting roads on the back side through traditional film lamination processes and cutting processes. In the traditional film lamination process, the cutting tape cannot tightly fill the deep U-shaped cutting road on the back side of the wafer, leaving it in a "suspended" state. During cutting, the large vibration amplitude of the wafer will cause the edge of the die (that is, the intact, stable, and sufficient capacity grain / bare die obtained after cutting and testing the entire wafer) to be prone to chipping (the bare die is diced and separated and then packaged to form a chip) with large size and hidden cracks, resulting in uncontrolled cutting quality of the silicon adapter board wafer and low die yield. Summary of the Invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a double-sided wiring wafer cutting street structure and a preparation method thereof, which can achieve firm adhesion of the cutting tape to the wafer cutting street structure, improve the wafer cutting quality, and increase the die yield.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A double-sided wiring wafer cutting path structure, comprising

[0006] Multiple dies, with RDL wiring layers covering the upper and lower surfaces of the die, and dicing areas between the dies. The dicing areas on the upper and lower surfaces of the wafer are completely aligned and overlapped, and the thickness difference between the RDL wiring layer on the lower surface of the die and the dicing area forms a U-shaped dicing area.

[0007] A crossbeam is arranged in the middle of the U-shaped cutting path.

[0008] Preferably, the width of the crossbeam is 2 / 3 of the width of the U-shaped cutting street, and the height is 3 / 4 of the depth of the U-shaped cutting street.

[0009] Preferably, the RDL wiring layer on the lower surface of the die is a single-layer RDL wiring layer or a multi-layer RDL wiring layer.

[0010] A method for preparing a double-sided wiring wafer saw path structure comprises the following steps:

[0011] Temporarily bonding the upper surface of the wafer and thinning the lower surface of the temporarily bonded wafer;

[0012] On the lower surface of the thinned temporary bonding wafer, dielectric layer preparation, TSV copper pillar copper exposure and RDL wiring layer preparation are carried out in sequence;

[0013] An insulating layer is prepared on the surface of the RDL wiring layer, and the crossbeam is prepared in the middle of the U-shaped cutting street, thereby completing the preparation of the wafer cutting street structure including the crossbeam.

[0014] Preferably, temporarily bonding the upper surface of the wafer comprises:

[0015] The upper surface of the wafer that has completed the wiring process is temporarily bonded to a temporary carrier sheet of the same size through a bonding material to form a temporary bonded wafer.

[0016] Preferably, preparing the dielectric layer comprises,

[0017] A silicon oxide dielectric layer is deposited on the lower surface of the thinned temporary bonding wafer by a PECVD process and a PI dielectric layer is prepared by a coating process.

[0018] Preferably, the TSV copper pillar exposed copper includes:

[0019] The lower surface of the temporary bonded wafer prepared with the dielectric layer is processed by wet polishing and dry etching until the top of the TSV copper column wrapped with the dielectric layer is exposed.

[0020] Preferably, preparing the RDL wiring layer includes,

[0021] A metal Ti barrier layer and a metal Cu seed layer are sequentially deposited on the surface of the dielectric layer by a PVD process;

[0022] RDL patterning is performed through coating and exposure and development processes;

[0023] Finally, the RDL wiring layer is prepared through electroplating, debonding and wet etching processes.

[0024] Preferably, preparing the crossbeam comprises,

[0025] An insulating layer is formed on the lower surface of the wafer on which the RDL wiring layer is formed by a glue coating process;

[0026] Expose the insulating layer exposed in the middle of the U-shaped cutting path through a set photomask;

[0027] The exposed insulating layer is developed through a development process, leaving the insulating layer in the masked area to form the crossbeam.

[0028] Preferably, after the preparation of the crossbeam is completed, the method further comprises:

[0029] Preparing a UBM on the RDL wiring layer on the lower surface of the temporary bonded wafer;

[0030] Attaching dicing tape to the lower surface of the temporarily bonded wafer;

[0031] Bonded wafer disassembly and separation;

[0032] Slice the wafer to separate the dies.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention provides a double-sided wiring wafer cutting street structure. By designing a crossbeam in the cutting street area between the dies on the back side of the wafer, that is, in the middle position of the U-shaped cutting street, the U-shaped cutting street is transformed into a W-shaped cutting street structure. While the total thickness of the RDL layer and the thickness difference between the RDL layer and the cutting street remain unchanged, the depth of the cutting street is shortened, ensuring that the cutting tape can be firmly attached to the crossbeam structure in the cutting street, and the wafer will not be in a suspended state. During subsequent cutting, the position of the crossbeam is used as the cutting position, thereby solving the problems of chipping oversize and hidden cracks at the edge of the die due to the suspended wafer and large vibration amplitude. At the same time, it can take into account the release of stress between the substrate die, reduce the warping of the wafer, and improve the die yield.

[0035] The present invention provides a method for preparing a double-sided wiring wafer cutting street structure. First, the upper surface of the wafer is temporarily bonded to a temporary glass carrier sheet by a temporary bonding material to form a temporarily bonded wafer, so that subsequent operations on the lower side can be performed without damaging the upper surface of the wafer; by arranging a dielectric layer and a first insulating layer, a total of two layers of insulating dielectric are prepared, so that the electrical insulation between the RDL layer on the lower surface of the wafer and the circuit on the upper surface of the wafer can be increased, and the risk of leakage can be reduced; the uniformity of the exposed TSV copper pillars on the lower surface of the above-mentioned temporary bonded wafer is modified and processed by a CMP flattening process, so as to facilitate the deposition of a metal layer in the next stage; by preparing an RDL wiring layer, the RDL lines thereof are connected and interconnected with the chip on the upper surface of the temporary bonded wafer through the TSV copper pillars, and a second insulating layer is coated on the RDL wiring layer to completely cover the RDL wiring layer; according to a set photomask exposure, the second insulating layer exposed outside the cutting street is exposed, and the central position corresponding to the U-shaped cutting street structure is retained to form the beam structure, thereby realizing the transformation of the U-shaped cutting street structure into a W-shaped cutting street structure.

[0036] Furthermore, the present invention also provides a film cutting method after the preparation of the double-sided wiring wafer cutting street structure is completed. Due to the presence of the beam structure, the problem of the cutting street portion of the wafer with a deep U-shaped cutting street on the back side being suspended after film lamination is effectively solved, thereby reducing the product's requirements for the thickness and viscosity of the cutting tape adhesive layer and other properties. The use of conventional cutting tape can meet the product cutting requirements, thereby greatly reducing the tape cost; and can reduce the product's special functional requirements for the film laminating equipment, which can be achieved through traditional film laminating technology, avoiding vacuum film laminating and high-temperature film laminating processing, and can significantly reduce the difficulty of the film laminating process and equipment cost; subsequently, cutting is performed with the center line position of the beam as the lower knife position, thereby solving the problems of large chipping size at the die edge and hidden cracks in the chip, and can significantly improve the die yield of products with a deep U-shaped cutting street structure such as TSV transfer substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a flow chart of a method for preparing a double-sided wiring wafer saw road structure according to the present invention;

[0038] Figure 2 Schematic diagram of the thinning process of the lower surface of the temporarily bonded wafer in Example 1 of the present invention;

[0039] Figure 3 Schematic diagram of depositing a dielectric layer and a first insulating layer on the lower surface of a temporarily bonded wafer in Example 1 of the present invention;

[0040] Figure 4 Schematic diagram of TSV copper pillar bump processing on the lower surface of a temporarily bonded wafer in Example 1 of the present invention;

[0041] Figure 5 Schematic diagram of preparing an RDL wiring layer on the lower surface of a temporarily bonded wafer in Example 1 of the present invention;

[0042] Figure 6 Schematic diagram of preparing a second insulating layer on the lower surface of a temporarily bonded wafer to form a beam in Example 1 of the present invention;

[0043] Figure 7 Schematic diagram of preparing UBM on the lower surface of a temporarily bonded wafer in Example 1 of the present invention;

[0044] Figure 8 Schematic diagram of attaching dicing tape to the lower surface of a temporarily bonded wafer in Example 1 of the present invention;

[0045] Figure 9 This is a schematic diagram of the wafer cutting position in Example 1 of the present invention.

[0046] In the figure, beam 1, dielectric layer 2, first insulating layer 3, Die 4, TSV copper pillar 5, RDL wiring layer 6, second insulating layer 7, UBM 8, dicing tape 9, TSV copper pillar bump 10, U-shaped cutting street 11. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; the following embodiments are only embodiments of a part of the present invention, not all embodiments, and are not intended to limit the scope of the present invention.

[0048] like Figure 6 As shown, the present invention provides a double-sided wiring wafer sawing structure, including multiple Die4,

[0049] The upper and lower surfaces of Die4 are both covered with RDL wiring layer 6. There is a scribe line area between Die4 and Die4. The scribe line areas on the upper and lower surfaces of the wafer are completely aligned and overlapped. The thickness difference between the RDL wiring layer 6 on the lower surface of Die4 and the scribe line area forms a U-shaped scribe line 11.

[0050] A crossbeam 1 is provided in the middle of the U-shaped cutting path 11 .

[0051] Since the cutting path area between Die4 does not cover the RDL wiring layer 6, as the number and thickness of the RDL wiring layer 6 increase, the total thickness of the RDL layer can exceed 20μm. Compared with the cutting path structure with a width of 60-80μm, a larger thickness difference will be generated, thereby forming a deep U-shaped cutting path structure. The present invention designs a beam 1 in the cutting path area between Die4 and Die4, that is, in the middle position of the U-shaped cutting path structure, so that the U-shaped cutting path is transformed into a W-shaped cutting path structure. While the total thickness of the RDL layer and the thickness difference between the cutting path remain unchanged, the depth of the cutting path is shortened to ensure that the cutting tape 9 can be firmly attached to the beam 1 in the cutting path, and the wafer will not be in a suspended state. During subsequent cutting, the position of the beam 1 is used as the cutting position, thereby solving the problems of chipping size being too large and hidden cracks at the edge of Die4 due to the suspended wafer and large vibration amplitude. At the same time, it can take into account the release of stress between the substrate Die4 and reduce the warping of the wafer.

[0052] The RDL wiring layer 6 on the lower surface of Die 4 is a single-layer RDL wiring layer or a multi-layer RDL wiring layer.

[0053] The width of the crossbeam is 2 / 3 of the width of the U-shaped cutting road, which corresponds to a single-layer RDL wiring process of usually 40-50 μm, and the height is 3 / 4 of the depth of the U-shaped cutting road 11, which corresponds to a single-layer RDL wiring process of usually 9-11 μm.

[0054] like Figure 1 As shown, the present invention provides a method for preparing a double-sided wiring wafer saw street structure, comprising the following steps:

[0055] Bonding the upper surface of the wafer and thinning the lower surface of the bonded wafer;

[0056] On the lower surface of the thinned bonded wafer, a dielectric layer 2, TSV copper pillar copper exposure, and an RDL wiring layer 6 are sequentially prepared;

[0057] An insulating layer is prepared on the surface of the RDL wiring layer 6 , and the above-mentioned beam 1 is prepared in the middle of the U-shaped cutting street 11 , thereby completing the preparation of the wafer cutting street structure including the beam 1 .

[0058] The temporary bonding of the upper surface of the wafer includes temporarily bonding the upper surface of the wafer that has completed the wiring process to a temporary carrier sheet of the same size through a temporary bonding material to form a temporary bonded wafer.

[0059] The preparation of the dielectric layer 2 includes depositing a silicon oxide dielectric layer on the lower surface of the thinned temporary bonding wafer by a PECVD process and preparing a PI dielectric layer by a coating process.

[0060] The TSV copper pillar copper exposure process includes wet polishing and dry etching the lower surface of the temporary bonded wafer on which the dielectric layer 2 is prepared, until the top of the TSV copper pillar wrapped with the dielectric layer is exposed.

[0061] Wherein, preparing the RDL wiring layer 6 includes:

[0062] A metal Ti barrier layer and a metal Cu seed layer are sequentially deposited on the surface of the dielectric layer 2 by a PVD process;

[0063] RDL patterning is performed through coating and exposure and development processes;

[0064] Finally, the RDL wiring layer 6 is prepared through electroplating, stripping, and wet etching processes.

[0065] Wherein, preparing the crossbeam 1 includes:

[0066] An insulating layer is prepared on the lower surface of the wafer on which the RDL wiring layer 6 is prepared by a glue coating process;

[0067] The insulating layer exposed in the middle of the U-shaped cutting path 11 is exposed through a set photomask;

[0068] The exposed insulating layer is developed through a development process, leaving the insulating layer in the masked area to form the crossbeam 1 .

[0069] The preparation method provided by the present invention is specifically implemented as follows:

[0070] Temporarily bonding the upper surface of the wafer on which the TSV preparation and RDL wiring layer 6 are completed to a temporary carrier sheet through a temporary bonding material to form a temporary bonded wafer;

[0071] Thinning the lower surface of the temporary bonded wafer to a thickness equal to the thickness of the TSV copper pillar bump 10;

[0072] Depositing a dielectric layer 2 on the lower surface of the thinned temporary bonded wafer by a PECVD process;

[0073] Coating a first insulating layer 3 on the dielectric layer 2 by a glue coating process;

[0074] Through the exposure and development process, the TSV patterning is completed on the lower surface of the temporary bonded wafer, exposing the dielectric layer 2 covering the TSV copper pillar bump 10; through the dry etching process, the dielectric layer 2 on the top of the TSV copper pillar bump 10 is removed; through the CMP planarization process, the TSV copper pillar 5 on the lower surface of the temporary bonded wafer is uniformly exposed;

[0075] Depositing a first metal barrier layer and a first metal seed layer on the first insulating layer 3 in sequence through a PVD process;

[0076] The RDL lines are patterned by spin-coating photoresist on the surface of the first metal seed layer and using exposure and development processes, and then the RDL wiring layer 6 is prepared by copper electroplating thickening process, wet stripping process and wet etching process;

[0077] Apply a second insulating layer 7 on the surface of the RDL wiring layer 6 by a glue coating machine to completely cover the RDL wiring layer 6;

[0078] Through exposure and development processes, the exposed second insulating layer 7 is developed according to the set photomask, leaving the insulating layer in the masking area to form the above-mentioned beam 1 structure, realize the patterning of the second insulating layer 7 of the W-shaped cutting street, and complete the preparation of a W-shaped wafer cutting street structure.

[0079] The present invention provides a method for preparing a double-sided wiring wafer cutting street structure, which comprises the following steps: first, temporarily bonding the upper surface of the wafer to a temporary glass carrier sheet by a temporary bonding material to form a temporarily bonded wafer, so as to facilitate subsequent operations on the lower surface without causing damage to the upper surface of the wafer; by arranging a dielectric layer 2 and a first insulating layer 3, a total of two layers of insulating dielectric are prepared, thereby increasing the electrical insulation between the RDL layer on the lower surface of the wafer and the circuit on the upper surface of the wafer, and reducing the risk of leakage; by a CMP planarization process, the uniformity of the exposed TSV copper pillars on the lower surface of the above-mentioned bonded wafer is modified and processed, so as to facilitate the deposition of the metal layer in the next stage; by preparing an RDL wiring layer 6, the RDL lines thereof are connected and interconnected with the chip on the upper surface of the temporary bonded wafer through the TSV copper pillars 5, and a second insulating layer 7 is coated on the RDL wiring layer 6 to completely cover the RDL wiring layer 6; according to a set photomask exposure, the second insulating layer 7 exposed outside the cutting street is exposed, and the crossbeam 1 structure is retained at the central position corresponding to the U-shaped cutting street structure, thereby realizing the transformation of the U-shaped cutting street structure into a W-shaped cutting street structure.

[0080] Furthermore, the precision of the thinning thickness is controlled within the range of ±2 μm of the thickness of the TSV copper pillar bump 10 .

[0081] Furthermore, the dielectric layer 2 is a silicon oxide dielectric layer with a thickness ranging from 2 to 3 μm.

[0082] Furthermore, both the first insulating layer 3 and the second insulating layer 7 are spin-coated with an insulating adhesive made of PI material, and the thickness of the insulating layer is in the range of 5-6 μm.

[0083] Furthermore, the temporary bonding material adopts a photosensitive temporary bonding adhesive or a heat-sensitive temporary bonding adhesive, and a laser temporary bonding debonding process is used for bonding.

[0084] Furthermore, the present invention also provides a film cutting method after the preparation of the double-sided wiring wafer saw street structure is completed, comprising the following steps:

[0085] Prepare UBM8 on the RDL wiring layer 6 on the lower surface of the temporary bonded wafer;

[0086] Attaching a dicing tape 9 to the lower surface of the temporary bonded wafer;

[0087] Temporarily bonded wafer disassembly and separation;

[0088] Slice the wafer to separate the dies.

[0089] Among them, before disassembling the bonded wafer, the temporary bonding material is processed by heat melting or laser irradiation.

[0090] The film cutting method provided by the present invention is specifically implemented as follows:

[0091] Depositing a second metal barrier layer and a second metal seed layer on the second insulating layer 7 of the temporary bonded wafer in sequence by a PVD process;

[0092] The UBM8 patterning on the back side of the wafer is achieved by spin-coating photoresist on the surface of the second metal seed layer and performing exposure and development processes. The UBM8 on the RDL wiring layer 6 is then prepared through electroplating copper thickening, wet stripping, wet etching, and chemical nickel-gold plating. At this point, the 2P1M wiring process on the bottom surface of the temporary bonded wafer is completed.

[0093] The lower surface of the temporary bonded wafer after the lower surface wiring process is attached to the dicing tape 9 by a conventional lamination process;

[0094] The bonding strength of the temporary bonding material is first reduced by heat melting or laser irradiation, and then mechanical disassembly is performed to separate the wafer from the temporary carrier.

[0095] The wafer is mechanically cut using a wafer cutting machine with the center line of the beam 1 as the cutting line, thereby completing the lamination and cutting of a single chip on the wafer cutting street structure.

[0096] Wafer film cutting is usually the last step in the wafer process. The film cutting process is crucial to the quality of wafer production. The present invention provides a film cutting method for a double-sided wiring wafer cutting street structure. Due to the existence of the beam 1 structure, the problem of the cutting street portion of the wafer with a deep U-shaped cutting street on the back side being suspended after film pasting is effectively solved, thereby reducing the product's requirements for the thickness and viscosity of the cutting tape 9. The use of conventional cutting tape 9 can meet the product cutting requirements, thereby greatly reducing the tape cost; and can reduce the product's special functional requirements for the film pasting equipment, which can be achieved through traditional film pasting technology, avoiding vacuum film pasting and high-temperature film pasting processing, and significantly reducing the difficulty of the film pasting process and equipment cost; subsequently, cutting is performed with the center line position of the beam 1 as the lower knife position, thereby solving the problems of Die4 edge chipping being too large and chip cracking, and can significantly improve the Die4 yield of products with a deep U-shaped cutting street structure such as TSV transfer substrates.

[0097] Furthermore, the first metal barrier layer and the second metal barrier layer are both made of Ti, and the first metal seed layer and the second metal seed layer are both made of Cu.

[0098] Furthermore, the dicing tape 9 is a UV dicing tape.

[0099] Furthermore, before separating the wafer from the temporary carrier, the temporary bonding material is treated by hot melting or laser irradiation, which can significantly reduce the adhesion of the temporary bonding glue, thereby facilitating the subsequent disassembly and separation of the wafer and the temporary carrier without damaging the wafer during the disassembly operation.

[0100] Example 1

[0101] In this embodiment 1, an 8-inch silicon transfer substrate with a TSV aspect ratio of 7:1 and a completed front-side wiring process is used as an example. The specific operation steps are as follows:

[0102] Step 1, such as Figure 2 As shown, an 8-inch silicon transfer substrate wafer that has completed the front wiring process is bonded to a glass carrier of the same size using a photosensitive temporary bonding adhesive to form a temporary bonded wafer. The lower surface of the temporary bonded wafer is automatically thinned, wet polished, and dry etched until the top of the TSV copper pillar 5 wrapped in the silicon oxide dielectric layer 2 protrudes 7μm from the lower surface of the wafer.

[0103] Step 2, such as Figure 3 As shown, a 2 μm thick silicon oxide dielectric layer is deposited on the entire lower surface of the temporary bonded wafer with the TSV bumps leaking out by the PECVD process, and a 5 μm thick PI dielectric layer is spin-coated on the silicon oxide dielectric layer to complete the preparation of the PI0 layer on the lower surface of the temporary bonded wafer;

[0104] Step 3, such as Figure 4 As shown, an exposure machine is used to expose the corresponding portion of the TSV copper pillar on the PI0 layer through a specific photomask, and a developer is further used to remove the PI on the top of the TSV bump to complete the TSV patterning on the back of the temporary bonded wafer. The silicon oxide dielectric layer wrapped around the TSV bump is removed by a plasma dry etching process to expose the copper on the top of the TSV copper pillar. The CMP planarization process is then used to modify the uniformity of the TSV copper pillar exposure on the lower surface of the temporary bonded wafer.

[0105] Step 4, such as Figure 5 As shown, a 0.1 μm thick metal Ti barrier layer and a 0.3 μm thick metal Cu seed layer are sequentially deposited on the surface of the above-mentioned PI0 layer by a PVD process, a layer of positive photoresist is spin-coated on the surface of the above-mentioned metal Cu seed layer by a coating process, and RDL patterning is completed by an exposure and development process. Then, through electroplating, debonding, wet etching and other processes, the preparation of the RDL lines on the lower surface of the temporary bonded wafer is completed;

[0106] Step 5, such as Figure 6As shown, a 9μm thick PI1 glue layer is spin-coated on the lower surface of the temporary bonded wafer on which the RDL line preparation is completed by a glue coater, and the PI1 glue layer at the UBM8 opening and the corresponding position in the cutting street on the RDL line is exposed by an exposure machine through a specific photomask. The exposed insulating layer is developed out through a development process, leaving the insulating layer in the masked area and exposing the RDL line at the UBM8 opening, thereby completing the preparation of the beam 1 in the U-shaped cutting street 11 on the lower surface of the temporary bonded wafer. The width of the beam is 40μm and the thickness is 9μm.

[0107] Step 6, such as Figure 7 As shown, referring to step 4, a 0.1 μm thick metal Ti barrier layer and a 0.3 μm thick metal Cu seed layer are sequentially deposited on the surface of the above-mentioned PI1 layer by a PVD process, a layer of positive photoresist is spin-coated on the surface of the above-mentioned metal Cu seed layer by a coating process, and UBM8 patterning on the RDL line is completed by an exposure and development process. Then, the preparation of UBM8 on the RDL line on the back of the bonded wafer is completed by a copper electroplating thickening process, a wet stripping process, a wet etching process and a chemical nickel-gold plating process. The 2P1M wiring process on the lower surface of the temporary bonded wafer is completed.

[0108] Step 7, such as Figure 8 As shown, the lower surface of the TSV silicon interposer wafer with the lower surface wiring process is attached to the UV dicing tape through the traditional film process. The UV dicing tape is tightly attached to the PI1 beam in the W-shaped dicing street.

[0109] Step 8, such as Figure 9 As shown, the bonded adapter plate wafer and the carrier glass after the film is attached are separated by laser irradiation, and the wafer is cut and separated from the front along the center line of the PI1 beam using a wafer cutting machine.

[0110] Example 2

[0111] In this embodiment 2, an 8-inch silicon transfer substrate with a TSV aspect ratio of 7:1 and a completed front-side wiring process is used as an example. The specific operation steps are as follows:

[0112] Step 1: Bond an 8-inch silicon transfer substrate wafer that has completed the front-side wiring process to a glass carrier of the same size using a heat-sensitive temporary bonding adhesive to form a temporary bonded wafer. The lower surface of the temporary bonded wafer is automatically thinned, wet polished, and dry etched until the top of the TSV copper pillar wrapped in the silicon oxide dielectric layer protrudes 9μm from the lower surface of the temporary bonded wafer.

[0113] Step 2: Deposit a 3 μm thick silicon oxide dielectric layer on the entire lower surface of the temporary bonded wafer with the TSV bumps leaking out by PECVD process, and spin-coat a 6 μm thick PI dielectric layer on the silicon oxide dielectric layer to complete the preparation of the PI0 layer on the lower surface of the temporary bonded wafer;

[0114] Step 3: Use an exposure machine to expose the corresponding part of the TSV copper pillar on the PI0 layer through a specific photomask, further use a developer to remove the PI on the top of the TSV bump, complete the TSV patterning on the back of the temporary bonded wafer, and use a plasma dry etching process to remove the silicon oxide dielectric layer wrapped around the TSV bump to expose the copper on the top of the TSV copper pillar. Then, use a CMP planarization process to modify the uniformity of the TSV copper pillar exposure on the lower surface of the temporary bonded wafer.

[0115] Step 4: A 0.1 μm thick metal Ti barrier layer and a 0.3 μm thick metal Cu seed layer are sequentially deposited on the surface of the above-mentioned PI0 layer by a PVD process, a layer of positive photoresist is spin-coated on the surface of the above-mentioned metal Cu seed layer by a coating process, and RDL patterning is completed by an exposure and development process. Then, the preparation of the RDL line on the lower surface of the temporary bonded wafer is completed by electroplating, degumming, wet etching and other processes;

[0116] Step 5: Spin-coat a layer of 11 μm thick PI1 glue on the lower surface of the temporary bonded wafer on which the RDL line preparation is completed by a glue coater, and use an exposure machine to expose the PI1 glue layer at the UBM opening on the RDL line and the corresponding position in the cutting street through a specific photomask. The exposed insulating layer is developed through a development process, leaving the insulating layer in the masked area, exposing the RDL line at the UBM opening and completing the preparation of the PI1 beam in the U-shaped cutting street on the lower surface of the temporary bonded wafer. The width of the beam is 50 μm and the thickness is 11 μm.

[0117] Step 6, referring to step 4, a 0.1 μm thick metal Ti barrier layer and a 0.3 μm thick metal Cu seed layer are sequentially deposited on the surface of the above-mentioned PI1 layer by a PVD process, a layer of positive photoresist is spin-coated on the surface of the above-mentioned metal Cu seed layer by a coating process, and the UBM patterning on the RDL line is completed by an exposure and development process. Then, the preparation of the UBM on the RDL line on the back of the temporary bonding wafer is completed by a copper electroplating thickening process, a wet stripping process, a wet etching process and a chemical nickel-gold plating process. The 2P1M wiring process on the lower surface of the temporary bonding wafer is completed;

[0118] Step 7: Using a conventional lamination process, the lower surface of the TSV silicon interposer wafer, which has completed the lower surface wiring process, is attached to the UV dicing tape. The UV dicing tape is tightly attached to the PI1 beam within the W-shaped dicing lane.

[0119] Step 8: Separate the bonded adapter plate wafer and the carrier glass after the film is attached by hot melting, and use a wafer cutting machine to cut and separate the wafer from the front along the center line of the PI1 beam.

Claims

1. A double-sided wiring wafer sawing street structure, characterized in that: include Multiple dies (4), upper and lower surfaces of the dies (4) are covered with RDL wiring layers (6), and there is a cutting path area between the dies (4), wherein the cutting path areas on the upper and lower surfaces of the wafer are completely aligned and overlapped, and the thickness difference between the RDL wiring layer (6) on the lower surface of the die (4) and the cutting path area forms a U-shaped cutting path (11); A crossbeam (1) is provided in the middle of the U-shaped cutting path (11); The width of the crossbeam (1) is 2 / 3 of the width of the U-shaped cutting path (11), and the height is 3 / 4 of the depth of the U-shaped cutting path (11); The RDL wiring layer (6) on the lower surface of the die (4) adopts a single-layer RDL wiring layer or a multi-layer RDL wiring layer; The preparation of the beam (1) comprises: An insulating layer is prepared on the lower surface of the wafer on which the RDL wiring layer (6) is prepared by a glue coating process; Exposing the insulating layer exposed at the middle position of the U-shaped cutting path (11) through a set photoresist; The exposed insulating layer is removed by a development process, leaving the insulating layer in the masked area, thereby forming the crossbeam (1); After the preparation of the beam (1) is completed, the following steps are also included: preparing a UBM (8) on the RDL wiring layer (6) on the lower surface of the temporary bonded wafer; Attaching a dicing tape (9) to the lower surface of the temporary bonded wafer; Bonded wafer disassembly and separation; Slice the wafer to separate the dies.

2. A method for preparing a double-sided wiring wafer saw road structure, characterized in that: The cutting street structure according to claim 1 comprises the following steps: Temporarily bonding the upper surface of the wafer and thinning the lower surface of the temporarily bonded wafer; On the lower surface of the thinned temporary bonding wafer, a dielectric layer (2), TSV copper pillar exposed copper, and an RDL wiring layer (6) are sequentially prepared; An insulating layer is prepared on the surface of the RDL wiring layer (6), and the crossbeam (1) is prepared in the middle of the U-shaped cutting road (11), thereby completing the preparation of the wafer cutting road structure including the crossbeam (1).

3. The method for preparing a double-sided wiring wafer saw street structure according to claim 2, wherein: Temporary bonding on the top surface of the wafer includes, The upper surface of the wafer that has completed the wiring process is temporarily bonded to a temporary carrier sheet of the same size through a bonding material to form a temporary bonded wafer.

4. The method for preparing a double-sided wiring wafer saw street structure according to claim 2, wherein: The preparation of the dielectric layer (2) includes, A silicon oxide dielectric layer is deposited on the lower surface of the thinned temporary bonding wafer by a PECVD process and a PI dielectric layer is prepared by a coating process.

5. The method for preparing a double-sided wiring wafer saw street structure according to claim 2, wherein: TSV copper pillar exposed copper includes: The lower surface of the temporary bonded wafer on which the dielectric layer (2) is prepared is processed by wet polishing and dry etching processes until the top of the TSV copper column wrapped with the dielectric layer is exposed.

6. The method for preparing a double-sided wiring wafer saw street structure according to claim 2, wherein: Preparing the RDL wiring layer (6) includes, Depositing a metal Ti barrier layer and a metal Cu seed layer in sequence on the surface of the dielectric layer (2) by a PVD process; RDL patterning is performed through coating and exposure and development processes; Finally, the RDL wiring layer (6) is prepared through electroplating, degumming, and wet etching processes.

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