Method for manufacturing a semiconductor device

Abstract

The present application relates to a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device includes the steps of: forming a stacked structure having a first material layer and a second material layer alternately stacked with each other; forming a first slit passing through the stacked structure; forming a second slit passing through the stacked structure; forming a contact hole passing through the stacked structure between the first slit and the second slit; forming a sealing layer sealing the first slit, the second slit, and the contact hole; forming a first opening passing through the sealing layer to form a first sealing region and partially expose the first slit to form a first exposed region; forming a first slit insulating layer by filling the first exposed region and the first sealing region; etching the sealing layer to open the contact hole; and forming a first contact plug in the contact hole.

Description

Technical Field

[0001] Various embodiments of the present invention relate generally to electronic devices, and more specifically to semiconductor devices and methods of manufacturing such semiconductor devices. Background Technology

[0002] The integration density of semiconductor devices is typically determined by the area of ​​a single memory cell. However, recent increases in the integration density of semiconductor devices with memory cells formed in a single layer on a substrate have been limited. Therefore, three-dimensional semiconductor devices with memory cells stacked on top of a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] According to one embodiment, a method of manufacturing a semiconductor device may include: forming a stacked structure having alternating layers of first and second materials; forming a first slit through the stacked structure; forming a second slit through the stacked structure; forming a contact hole through the stacked structure between the first and second slits; forming a sealing layer that seals the first slit, the second slit, and the contact hole; forming a first opening through the sealing layer and partially exposing the first slit; forming a first slit insulating layer in a first exposed region and a first sealed region included in the first slit, the first exposed region being the portion of the first slit exposed through the first opening, and the first sealed region being the portion of the first slit sealed by the sealing layer; etching the sealing layer to open the contact hole; and forming a first contact plug in the contact hole.

[0004] According to one embodiment, a method of manufacturing a semiconductor device may include: forming a stacked structure having cell regions and contact regions; forming a channel structure through the cell regions of the stacked structure; forming a first slit through the contact regions of the stacked structure; forming a contact hole through the contact regions of the stacked structure; forming a sealing layer that seals the first slit and the contact hole; forming a mask pattern on the sealing layer that partially exposes the first slit; etching the sealing layer using the mask pattern as an etch barrier layer to form a first opening that partially exposes the first slit; forming a first slit insulating layer in the exposed region and the sealed region included in the first slit, the exposed region being the portion of the first slit exposed through the first opening, and the sealed region being the portion of the first slit sealed by the sealing layer; etching the sealing layer to open the contact hole; and forming a first contact plug in the contact hole. Attached Figure Description

[0005] Figures 1A to 1C This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure;

[0006] Figures 2A to 2C , Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C ,as well as Figures 10A to 10C This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0007] Figure 11 This is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0008] Figure 12 This is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0009] Figure 13 This is a diagram illustrating a memory system according to an embodiment of the present disclosure;

[0010] Figure 14 A diagram illustrating a memory system according to an embodiment of the present disclosure; and

[0011] Figure 15 This is a diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0012] The specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are merely illustrative for the purpose of describing examples of embodiments of the concepts, and examples of embodiments of the concepts may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0013] It will be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0014] Furthermore, it will be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0015] Various implementations relate to semiconductor devices having stable structures and improved properties, as well as methods of manufacturing such semiconductor devices.

[0016] Figures 1A to 1CThis is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0017] Reference Figures 1A to 1C The semiconductor device may include a stacked structure ST, a first slit insulating layer SLI1, a second slit insulating layer SLI2, and a first contact plug CP1. The semiconductor device may further include a third slit insulating layer SLI3, a fourth slit structure SLS4, peripheral circuitry PC, a first interconnect structure IC1, a source structure 17, a channel structure CH, a second interconnect structure IC2, a first interlayer insulating layer 16, a second interlayer insulating layer 26, a third interconnect structure IC3, or a combination thereof.

[0018] The stacked structure ST may include unit regions CR and contact regions CT. The unit regions CR and contact regions CT may be adjacent to each other in a first direction I. According to one embodiment, the contact regions CT may be located between a pair of unit regions CR. Alternatively, the unit regions CR may be located between a pair of contact regions CT.

[0019] Memory cells can be stacked in the cell region CR. According to an embodiment, a string of memory cells, including at least one drain-select transistor, a plurality of memory cells, and at least one source-select transistor, can be located in the cell region CR.

[0020] The cell region CR may include conductive layers 23 and insulating layers 22 alternately stacked on top of each other. Each of the conductive layers 23 may be a memory cell or the gate of a select transistor. The conductive layers 23 may include polysilicon, a metal such as tungsten (W) or molybdenum (Mo), or a combination thereof. At least one bottommost conductive layer 23 may be a source select line, at least one topmost conductive layer 23 may be a drain select line, and the other conductive layers 23 may be word lines. The insulating layers 22 may insulate the conductive layers 23 from each other and may include insulating materials such as oxides or air gaps.

[0021] The contact area CT can refer to the area where the pads that apply bias to the conductive layers are located. The contact area CT can have a stepped shape and expose each conductive layer 23. The exposed portion of the conductive layer 23 can be used as a pad. The second contact plug CP2 can be electrically connected to the conductive layer 23.

[0022] The contact area CT may include a first portion P1 and a second portion P2. According to an embodiment, the first portion P1 may be located between adjacent second portions P2 in a second direction II. The second direction II may intersect with the first direction I. The second portion P2 may include conductive layers 23 and insulating layers 22 alternately stacked on top of each other. The conductive layers 23 in the unit region CR and the conductive layers 23 in the contact area CT may be interconnected. The insulating layers 22 in the unit region CR and the insulating layers 22 in the contact area CT may be interconnected.

[0023] The first part P1 may include a sacrificial layer 21 and an insulating layer 22 alternately stacked on top of each other. The sacrificial layer 21 may be a residual layer that was not replaced by the conductive layer 23 during the manufacturing process. The sacrificial layer 21 may include a material with high etch selectivity relative to the insulating layer 22. According to an embodiment, the sacrificial layer 21 may include a nitride, and the insulating layer 22 may include an oxide.

[0024] The first slit insulating layer SLI1 may be located in the contact area CT. The first slit insulating layer SLI1 may pass through the contact area CT of the laminated structure ST in a third direction III. The third direction III may intersect with the first direction I and the second direction II. According to an embodiment, the third direction III may protrude from the plane defined in the first direction I and the second direction II. The first slit insulating layer SLI1 may extend in the first direction I and may be located at the boundary between the first portion P1 and the second portion P2.

[0025] The second slit insulating layer SLI2 may be located within the contact region CT. The second slit insulating layer SLI2 may extend through the contact region CT of the stacked structure ST in the third direction III. The second slit insulating layer SLI2 may extend in the first direction I and may be located at the boundary between the first portion P1 and the second portion P2. The first slit insulating layer SLI1 and the second slit insulating layer SLI2 may be adjacent to each other in the second direction II.

[0026] The third slit insulating layer SLI3 may be located in the contact area CT. The third slit insulating layer SLI3 may pass through the contact area CT of the stacked structure ST in the third direction III. The third slit insulating layer SLI3 may be located in the second portion P2. In the plan view, the third slit insulating layer SLI3 may have a shape such as circular, elliptical, or polygonal, or it may have a T-shape. The third slit insulating layer SLI3 may be located in the second portion P2, and the third slit insulating layer SLI3 may be arranged in the first direction I.

[0027] The fourth slit structure SLS4 can be located within the contact area CT. The fourth slit structure SLS4 can pass through the contact area CT of the stacked structure ST in the third direction III. The fourth slit structure SLS4 can extend in the first direction I and can be located within the second portion P2. The third slit insulating layer SLI3 can be located between the first slit insulating layer SLI1 and the fourth slit structure SLS4, or between the second slit insulating layer SLI2 and the fourth slit structure SLS4.

[0028] The fourth slit structure SLS4 may include an insulating material and can be considered as a slit insulation layer. However, the fourth slit structure SLS4 may include a contact structure electrically connected to the source structure 17 and insulating spacers surrounding the sidewalls of the contact structure. The contact structure may include polysilicon, a metal such as tungsten (W) or molybdenum (Mo), or a combination thereof.

[0029] Each of the first slit insulating layer SLI1, the second slit insulating layer SLI2, or the fourth slit structure SLS4 may have a linear shape extending in the first direction I. The first slit insulating layer SLI1 may have a length in the first direction I and a width in the second direction II. The width of the first slit insulating layer SLI1 may vary based on its area. The first slit insulating layer SLI1 may have a relatively small width at the portion corresponding to the third slit insulating layer SLI3 or the first contact plug CP1. The first slit insulating layer SLI1 may have a relatively large width between the third slit insulating layers SLI3 or between the first contact plugs CP1. In the same manner as the first slit insulating layer SLI1, the width of the second slit insulating layer SLI2 may vary based on its area.

[0030] The first contact plug CP1 may be located in the contact area CT. The first contact plug CP1 may pass through the contact area CT of the stacked structure ST in the third direction III. The first contact plug CP1 may be located between the first slit insulation layer SLI1 and the second slit insulation layer SLI2. The first contact plug CP1 may be located in the first portion P1. The first contact plug CP1 may be located in the first portion P1 and may be arranged in the first direction I.

[0031] The channel structure CH can be located within the cell region CR. The channel structure CH can pass through the cell region CR of the stacked structure ST in the third direction III. The channel structure CH may include a channel layer 30, and may also include a memory layer 29 or a gap-filling insulating layer 31. The channel layer 30 may include a semiconductor material such as silicon or germanium. The memory layer 29 may be interposed between the channel layer 30 and the conductive layer 23. The memory layer 29 may include at least one of a tunnel insulating layer, a data storage layer, and a barrier layer. The data storage layer may include a charge trapping material, a floating gate, a nitride, a variable resistance material, a phase change material, or a ferroelectric material. The channel structure CH can be arranged in the first direction I and the second direction II.

[0032] Source structure 17 may be located below the stacked structure ST. Source structure 17 may be provided to apply a source voltage, and source structure 17 may have a single-layer or multi-layer structure. Source structure 17 may include polysilicon, a metal such as tungsten (W) or molybdenum (Mo), or combinations thereof. Channel structure CH may be connected to source structure 17. Channel structure CH may protrude into source structure 17 and may be directly connected to source structure 17. Alternatively, channel structure CH and source structure 17 may be interconnected through epitaxially grown semiconductor layers.

[0033] The peripheral circuitry PC can be located below the source structure 17. The peripheral circuitry PC may include circuitry driving the memory string and an X decoder. The peripheral circuitry PC may include a transistor TR, capacitors, resistors, etc. According to an embodiment, the transistor TR may include a gate 12 formed on the substrate 10 and a gate insulating layer 11 interposed between the substrate 10 and the gate 12. Although not shown, the transistor TR may also include a junction formed in the substrate 10, and an isolation layer may be formed in the substrate 10. The peripheral circuitry PC may be located below the contact region CT, below the cell region CR, or below both the contact region CT and the cell region CR.

[0034] The first interconnect structure IC1 can be electrically connected to the peripheral circuit PC. The first interconnect structure IC1 may include a first wiring 14 or a third contact plug 15. The first wiring 14 may be formed in a first interlayer insulating layer 16. The third contact plug 15 may pass through the source structure 17 and be electrically connected to the first wiring 14. An insulating pattern 18 may be inserted between the third contact plug 15 and the source structure 17. The first contact plug CP1 can be electrically connected to the third contact plug 15 and electrically connected to the peripheral circuit PC through the first interconnect structure IC1.

[0035] The second interconnect structure IC2 may be located above the stacked structure ST. The second interconnect structure IC2 may include a second wiring 24 or a fourth contact plug 25. The second wiring 24 or the fourth contact plug 25 may be formed in the second interlayer insulating layer 26. The fourth contact plug 25 may be electrically connected to the first contact plug CP1.

[0036] The third interconnect structure IC3 can be located above the stacked structure ST. The third interconnect structure IC3 may include a third wiring 27 or a fifth contact plug 28. The third wiring 27 or the fifth contact plug 28 may be formed in the second interlayer insulating layer 26. The third wiring 27 may be located at a different height from the second wiring 24 and may be electrically insulated from the second wiring 24. The second wiring 24 may be a bit line.

[0037] According to the above structure, the peripheral circuit PC can be located below the stacked structure ST, thereby increasing the integration density of the semiconductor device. The contact area CT can be divided into a first part P1 and a second part P2 by the first slit insulating layer SLI1 and the second slit insulating layer SLI2. In addition, the first contact plug CP1 can pass through the first part P1 and can be electrically connected to the peripheral circuit PC.

[0038] Figures 2A to 2C , Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6C , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C ,as well as Figures 10A to 10C This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2A to 10A It's a floor plan. Figures 2B to 10B This is a cross-sectional view of CC′. Figures 2C to 10C This is a cross-sectional view of DD′. For the sake of brevity, descriptions of some of the components discussed above have been omitted in the following description.

[0039] Reference Figures 2A to 2C A stacked structure ST can be formed on the lower structure. The lower structure may include peripheral circuitry PC. The peripheral circuitry PC may include a substrate 40, and the substrate 40 may include a semiconductor substrate. The peripheral circuitry PC may include a transistor TR. The transistor TR may include a gate insulating layer 41 and a gate 42. The lower structure may include a first interconnect structure IC1 electrically connected to the peripheral circuitry PC. The first interconnect structure IC1 may be formed in a first interlayer insulating layer 46 and may include wiring 44.

[0040] Before forming the stacked structure ST, a source structure 47 may be formed on the first interlayer insulating layer 46. The source structure 47 may include a single layer or multiple layers. The source structure 47 may include a sacrificial layer. Contact plugs 45 and insulating patterns 48 may be formed on the source structure 47. Contact plugs 45 may be part of the first interconnect structure IC1 and may be electrically connected to wiring 44.

[0041] The stacked structure ST may include alternating layers of a first material layer 51 and a second material layer 52. The first material layer 51 may include a material with high etch selectivity relative to the second material layer 52. For example, the first material layer 51 may include a sacrificial material such as a nitride, while the second material layer 52 may include an insulating material such as an oxide. For example, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, while the second material layer 52 may include an insulating material such as an oxide.

[0042] Figures 2A to 2C The diagram primarily illustrates the contact area of ​​the stacked structure ST. However, the stacked structure ST may also include cell regions. After forming the stacked structure ST, a channel structure can be formed through the cell regions of the stacked structure ST. When the source structure 47 includes a sacrificial layer, a process can be performed to replace the sacrificial layer with a source layer. Additionally, the contact area can be patterned to expose each first material layer 51. According to an embodiment, after the contact area is patterned into a stepped shape, an interlayer insulating layer can be formed.

[0043] A first mask pattern 53 can then be formed on the stacked structure ST. The first mask pattern 53 can be a hard mask pattern. The first mask pattern 53 can include nitrides, carbon-based materials, or combinations thereof.

[0044] Reference Figures 3A to 3C A first slit SL1 can be formed through the stacked structure ST. A second slit SL2 can also be formed through the stacked structure ST, a contact hole CTH can be formed through the stacked structure ST, or a third slit SL3 can be formed through the stacked structure ST. The second slit SL2, the contact hole CTH, or the third slit SL3 can be formed while forming the first slit SL1. According to an embodiment, the first slit SL1, the second slit SL2, the contact hole CTH, and the third slit SL3 can be formed by etching the stacked structure ST using a first mask pattern 53 as an etch barrier layer. The first slit SL1, the second slit SL2, or the third slit SL3 can be deep enough to expose the source structure 47. The contact hole CTH can be formed to a specific depth to expose the contact plug 45. The third slit SL3, the first slit SL1, the contact hole CTH, and the second slit SL2 can be adjacent to each other in the second direction II.

[0045] The laminated structure ST may include a first portion P1 defined between a first slit SL1 and a second slit SL2, and a second portion P2 located outside the region between the first slit SL1 and the second slit SL2. The first portion P1 may be located between adjacent second portions P2 that are opposite each other in a second direction II. The second portion P2 may be located outside the region between the first slit SL1 and the second slit SL2. The first portion P1 and the second portion P2 may be separated from each other by the first slit SL1 and the second slit SL2. Furthermore, the first portion P1 of the laminated structure ST may have a high aspect ratio.

[0046] Reference Figures 4A to 4C A sealing layer 54 can be formed. The sealing layer 54 can be formed to seal the first slit SL1, the contact hole CTH, and the second slit SL2. The sealing layer 54 can be formed using a material with a stepped coverage difference. The sealing layer 54 may include a silicon compound. According to an embodiment, the sealing layer 54 may include tetraethoxysilane (TEOS) or undoped silicate glass (USG).

[0047] The entrances to the first slit SL1, the contact hole CTH, and the second slit SL2 can be sealed by the sealing layer 54, and their interiors can remain empty. According to an embodiment, the upper portions of the first slit SL1, the contact hole CTH, and the second slit SL2 can be filled, while the remaining portions of the first slit SL1, the contact hole CTH, and the second slit SL2 can remain empty. Therefore, tilting or bending of the first portion P1 or the second portion P2 of the laminated structure ST in the second direction II can be minimized or prevented.

[0048] Reference Figures 5A to 5C A second mask pattern 55 may be formed on the sealing layer 54. The second mask pattern 55 may be a hard mask pattern. The second mask pattern 55 may include nitrides, carbon-based materials, or combinations thereof. The second mask pattern 55 may be formed to partially expose the first slit SL1 and may cover the contact hole CTH.

[0049] The second mask pattern 55 may include a first opening M_OP1 that partially exposes the first slit SL1. The first opening M_OP1 may expose a relatively large portion of the width of the first slit SL1.

[0050] The second mask pattern 55 may further include a second opening M_OP2, which partially exposes the second slit SL2. The second opening M_OP2 may expose a relatively large portion of the width of the second slit SL2. The second opening M_OP2 may be formed during the formation of the first opening M_OP1.

[0051] The second mask pattern 55 may further include a third opening M_OP3, which partially exposes a third slit SL3. The third opening M_OP3 may expose a third slit SL3 individually. However, one third opening M_OP3 may expose multiple third slits SL3. The third opening M_OP3 and the first opening M_OP1 may be arranged in an interleaved manner to avoid any overlap in the second direction II. The third opening M_OP3 may be formed when the first opening M_OP1 is formed.

[0052] Reference Figures 6A to 6C A first opening S_OP1 can be formed that penetrates the sealing layer 54 and partially exposes the first slit SL1. According to an embodiment, the sealing layer 54 can be etched using a second mask pattern 55 as an etching barrier layer to form a sealing layer 54A with the first opening S_OP1. A second opening S_OP2 can also be formed that penetrates the sealing layer 54 and partially exposes the second slit SL2. A third opening S_OP3 can also be formed that penetrates the sealing layer 54 and partially exposes the third slit SL3.

[0053] The first slit SL1 may include an exposed area SL1_E exposed through the first opening S_OP1 and a sealed area SL1_S sealed by the sealing layer 54A. The second slit SL2 may include an exposed area SL2_E exposed through the second opening S_OP2 and a sealed area SL2_S sealed by the sealing layer 54A. The third slit SL3 may be exposed through the third opening S_OP3.

[0054] Sealing layer 54A can partially expose the first slit SL1. Sealing layer 54A can seal the first slit SL1 between the first openings S_OP1 to continuously cover the first portion P1 and the second portion P2. Therefore, the first slit SL1 can be reopened while the first portion P1 and the second portion P2 of the laminated structure ST are supported by sealing layer 54A. As a result, tilting or bending of the first portion P1 or the second portion P2 of the laminated structure ST can be minimized or prevented.

[0055] Reference Figures 7A to 7CAn insulating layer 56 can be formed. The insulating layer 56 may include an insulating material such as an oxide. According to an embodiment, after forming an insulating material layer using a deposition process, the insulating material layer can be planarized to form the insulating layer 56. The insulating layer 56 can be formed in the first slit SL1 and the sealing region SL1_S, as well as the exposed region SL1_E. The insulating layer 56 can be formed in the sealing region SL1_S through the first opening S_OP1 and the exposed region SL1_E. Although the sealing region SL1_S is not directly exposed, insulating material can be introduced into the sealing region SL1_S and deposited through the exposed region SL1_E. Therefore, the insulating layer 56 can also be formed in the sealing region SL1_S.

[0056] An insulating layer 56 can be formed in the second slit SL2. An insulating layer 56 can be formed in the exposed area SL2_E and the sealed area SL2_S. An insulating layer 56 can be formed in the sealed area SL2_S through the second opening S_OP2 and the exposed area SL2_E. An insulating layer 56 can be formed in the third slit SL3. An insulating layer 56 can be formed in the third slit SL3 through the third opening S_OP3.

[0057] Reference Figures 8A to 8C This allows the contact hole CTH to be opened. The contact hole CTH can be reopened by etching the insulating layer 56 and the sealing layer 54A. The insulating layer 56 and the sealing layer 54A can be etched without a mask pattern. According to an embodiment, the insulating layer 56 and the sealing layer 54A can be etched using an etch-back process. As a result, the first slit insulating layer 56A can be formed in the first slit SL1. The second slit insulating layer 56B can be formed in the second slit SL2. The third slit insulating layer 56C can be formed in the third slit SL3. The second slit insulating layer 56B can be formed while the first slit insulating layer 56A is being formed. The third slit insulating layer 56C can be formed while the first slit insulating layer 56A is being formed.

[0058] When in reference Figures 3A to 3C If the contact hole CTH is not formed during the described manufacturing process, the contact hole CTH can be formed by etching the stacked structure ST at the current stage.

[0059] Reference Figures 9A to 9C A first contact plug 57 can be formed in the contact hole CTH. After depositing a conductive material to fill the contact hole CTH, the conductive material can be planarized until the top surface of the stacked structure ST is exposed, thereby forming the first contact plug 57. The first contact plug 57 may include polysilicon, a metal such as tungsten (W) or molybdenum (Mo), or a combination thereof.

[0060] Reference Figures 10A to 10CA fourth slit SL4 can be formed in the second portion P2. The fourth slit SL4 can have a specific depth to expose the first material layer 51. A third slit insulating layer 56C can be located between the fourth slit SL4 and the first slit insulating layer 56A. The third slit insulating layer 56C can also be located between the fourth slit SL4 and the second slit insulating layer 56B.

[0061] Subsequently, the opening OP can be formed by selectively etching the first material layer 51 via the fourth slit SL4. The first portion P1 and the second portion P2 can be separated from each other by the first slit insulating layer 56A and the second slit insulating layer 56B. Therefore, the first material layer 51 in the second portion P2 can be selectively etched. On the other hand, the first material layer 51 in the first portion P1 can be retained without being etched. The second material layer 52 retained in the second portion P2 can be supported by the first slit insulating layer 56A, the second slit insulating layer 56B, or the third slit insulating layer 56C.

[0062] A conductive layer 58 can be formed in the opening OP. According to an embodiment, after depositing a conductive material layer in the opening OP and the fourth slit SL4, the conductive material layer can be etched to form conductive layers 58 that are separated from each other. As a result, the first material layer 51 can be replaced by the conductive layer 58.

[0063] Although not shown, a second contact plug can be formed to connect to the conductive layer 58. A third interconnect structure can be formed to connect to the channel structure. A second interconnect structure can be formed to electrically connect to the first contact plug 57.

[0064] According to the manufacturing method described above, the contact area of ​​the laminated structure ST can be divided into a first part P1 and a second part P2 by using a first slit insulating layer 56A and a second slit insulating layer 56B. Furthermore, by using a sealing layer 54A to support the first part P1 and the second part P2 of the laminated structure ST, tilting or bending of the laminated structure ST can be minimized or prevented during the manufacturing process.

[0065] Figure 11 This is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0066] Reference Figure 11 The memory system 1000 may include a memory device 1200 configured to store data and a controller 1100 that performs communication between the memory device 1200 and the host 2000.

[0067] The host 2000 can be a device or system configured to store data in or retrieve data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for reading operations, and erase requests for erasing operations. The host 2000 can communicate with the memory system 1000 using at least one of the following interface protocols: PCIe (High-Speed ​​Peripheral Component Interconnect), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), NVMe (High-Speed ​​Non-Volatile Memory), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0068] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television set, wireless communication device, or cellular phone. However, the embodiments of the disclosed technology are not limited thereto.

[0069] Controller 1100 can control the overall operation of memory system 1000. Controller 1100 can control memory device 1200 in response to requests from host 2000. Controller 1100 can control memory device 1200 to perform programming, reading, and erasing operations upon request from host 2000. Alternatively, controller 1100 can perform background operations to improve the performance of memory system 1000 without requests from host 2000.

[0070] To control the operation of the memory device 1200, the controller 1100 can transmit control signals and data signals to the memory device 1200. Control signals and data signals can be transmitted to the memory device 1200 via different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to distinguish the time periods of input data signals.

[0071] The memory device 1200 can perform programming, reading, and erasing operations in response to control by the controller 1100. The memory device 1200 can be a volatile memory that loses data when power is cut off, or a non-volatile memory that retains data when there is no power supply. According to embodiments, the memory device 1200 can be the aforementioned semiconductor device or flash memory device.

[0072] Upon request for programming, reading, or erasing operations from the host 2000, the controller 1100 can command the device having the above-mentioned reference... Figures 1A to 1CThe described structure or by reference Figures 2A to 10C The memory device 1200 manufactured using the described method is used to perform programming, reading, or erasing operations. In this way, cell performance characteristics and retention characteristics can be improved.

[0073] Figure 12 This is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

[0074] Reference Figure 12 The memory system 30000 can be implemented in a cellular phone, smartphone, tablet computer, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 for controlling the operation of the memory device 2200.

[0075] The controller 2100 can control data access operations of the memory device 2200 in response to the control of the processor 3100, such as programming operations, erasing operations or reading operations of the memory device 2200.

[0076] In response to the control of the controller 2100, the data programmed into the memory device 2200 can be output through the display 3200.

[0077] The radio transceiver 3300 can exchange radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the controller 2100 or the display 3200. The controller 2100 can transmit the signals processed by the processor 3100 to the memory device 2200. In addition, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the radio signals to external devices via the antenna ANT. Control signals for controlling the operation of the host or data to be processed by the processor 3100 can be input via the input device 3400, and the input device 3400 may include pointing devices such as touchpads and computer mice, keypads, or keyboards. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0078] According to the implementation, the controller 2100 that can control the operation of the memory device 2200 can be implemented as part of the processor 3100 or as a chip separate from the processor 3100.

[0079] Figure 13 This is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0080] Reference Figure 13 The 40000 memory system can be implemented in personal computers (PCs), tablet PCs, netbooks, e-readers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, or MP4 players.

[0081] The memory system 40000 may include a memory device 2200 and a controller 2100 for controlling the data processing operations of the memory device 2200.

[0082] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input via the input device 4200. Examples of the input device 4200 may include a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0083] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to the embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a chip separate from the processor 4100.

[0084] Figure 14 This is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0085] Reference Figure 14 The memory system 50000 can be implemented in an image processor, for example, a digital camera, a cellular phone with a digital camera, a smartphone with a digital camera, or a tablet PC with a digital camera.

[0086] The memory system 50000 may include a memory device 2200 and a controller 2100, the controller 2100 controlling data processing operations of the memory device 2200, such as programming operations, erasing operations, or reading operations.

[0087] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be transmitted to the processor 5100 or the controller 2100. In response to the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. Therefore, data stored in the memory device 2200 can be output through the display 5300 in response to the control of the processor 5100 or the controller 2100.

[0088] According to the implementation, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be formed as part of the processor 5100 or as a chip separate from the processor 5100.

[0089] Figure 15 This is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

[0090] Reference Figure 15 The memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0091] The controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. According to the embodiment, the card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface.

[0092] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. Depending on the implementation, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Card interface 7100 can refer to hardware, software installed in the hardware, or signal transmission method capable of supporting the protocol used by host 60000.

[0093] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 in response to the control of the microprocessor 6100.

[0094] According to embodiments of the present invention, the integration density of a semiconductor device can be increased by three-dimensionally stacking memory cells. Furthermore, a semiconductor device with a stable structure and improved reliability can be provided.

[0095] Cross-references to related applications

[0096] This application claims priority to Korean Patent Application No. 10-2020-0093262, filed on July 27, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure having first material layers and second material layers stacked alternately with each other; forming a first slit through the stacked structure; forming a second slit through the stacked structure, the first slit and the second slit extending in a first direction on a plan view; forming a contact hole through the stacked structure between the first slit and the second slit; forming a sealing layer that seals entrances of the first slit, the second slit, and the contact hole above the first slit, the second slit, and the contact hole; forming a first opening through the sealing layer and partially exposing the first slit in the first direction; forming a first-slit insulating layer in a first exposed region and a first sealed region in the first slit, the first exposed region being a portion of the first slit exposed through the first opening, and the first sealed region being a portion of the first slit sealed by the sealing layer; etching the sealing layer to open the contact hole; and forming a first contact plug in the contact hole. The step of forming the first opening includes the steps of:

2. The method of claim 1, wherein, forming a mask pattern on the sealing layer to partially expose the first slit; and etching the sealing layer by using the mask pattern as an etching stopper. The step of forming the first-slit insulating layer includes the step of depositing an insulating material in the sealed region through the first opening and the first exposed region.

3. The method of claim 1, wherein, The step of etching the sealing layer includes etching the sealing layer without a mask pattern.

4. The method of claim 1, wherein, The etching of the sealing layer is performed by a back-etching process.

5. The method of claim 1, wherein, The step of forming the sealing layer includes the step of sealing the entrances of the first slit, the second slit, and the contact hole with a material having a step coverage difference.

6. The method of claim 1, wherein, 7. The method according to claim 1, further comprising the steps of: forming a second opening through the sealing layer and partially exposing the second slit; and forming a second-slit insulating layer in a second exposed region and a second sealed region included in the second slit, the second exposed region being a portion of the second slit exposed through the second opening, the second sealed region being a portion of the second slit sealed by the sealing layer. The second opening is formed when the first opening is formed, and 8. The method of claim 7, wherein, wherein the second-slit insulating layer is formed when the first-slit insulating layer is formed. The stacked structure includes a first portion between the first-slit insulating layer and the second-slit insulating layer, and a second portion in a region other than the region between the first-slit insulating layer and the second-slit insulating layer.

9. The method of claim 7, wherein, 10. The method according to claim 9, further comprising the steps of: forming a third slit on the second portion; sealing the third slit with the sealing layer; forming a third opening through the sealing layer and exposing the third slit, respectively; and forming a third-slit insulating layer in the third slit, respectively. ​ 11. The method of claim 10, wherein, the third opening is formed at the same time as the first opening, and the third slit insulating layer is formed at the same time as the first slit insulating layer.

12. The method of claim 10, further comprising the step of: the first material layer of the second portion is replaced with a third material layer by using the third slit insulating layer as a support.

13. The method of claim 12, wherein, the step of replacing the first material layer with the third material layer includes the steps of: forming a fourth slit on the second portion; forming a fourth opening by selectively etching the first material layer of the second portion through the fourth slit; and forming a conductive layer in the fourth opening.

14. The method of claim 13, further comprising the step of: second contact plugs respectively coupled to the conductive layer are formed in the second portion.

15. The method of claim 1, further comprising the step of: before the layer stack is formed: a peripheral circuit is formed; a source structure is formed on the peripheral circuit; and an interconnection structure coupled to the peripheral circuit is formed through the source structure.

16. The method of claim 15, wherein, the first contact plugs are electrically coupled to the interconnection structure.

17. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a layer stack having a cell region and a contact region; forming a trench structure through the cell region of the layer stack; forming a first slit through the contact region of the layer stack, the first slit extending in a first direction in a plan view; forming a contact hole through the contact region of the layer stack; forming a sealing layer that seals entrances of the first slit and the contact hole over the first slit and the contact hole; forming a mask pattern that partially exposes the first slit in the first direction on the sealing layer; forming a first opening that partially exposes the first slit by etching the sealing layer using the mask pattern as an etching stopper; forming a first slit insulating layer in an exposed region and a sealed region in the first direction included in the first slit, the exposed region being a portion of the first slit exposed through the first opening, and the sealed region being a portion of the first slit sealed by the sealing layer; etching the sealing layer to open the contact hole; and forming a first contact plug in the contact hole. the step of etching the sealing layer includes the step of etching the sealing layer without a mask pattern.

18. The method of claim 17, wherein, the etching of the sealing layer is performed by a back-etching process.

19. The method of claim 17, wherein, 20. The method according to claim 17, further comprising the steps of: replacing a first material layer of the layer stack with a conductive layer, the first material layer and a second material layer being alternately stacked with each other in the layer stack; and forming second contact plugs respectively coupled to the conductive layer in the contact region. ​

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