Driving substrate, manufacturing method thereof, and display device

Abstract

The present disclosure provides a driving substrate, comprising: a flexible substrate, a plurality of thin-film transistors (TFTs) located on the flexible substrate, and a first conductive patterned layer located on a side of the TFTs away from the flexible substrate. The flexible substrate comprises a display area, a bendable area, and a binding area, the bendable area being located between the display area and the binding area, and the TFTs being located within the display area. The first conductive patterned layer comprises: a plurality of first connecting terminals and a plurality of signal supply leads, the first connecting terminals being located within the display area, some of the first connecting terminals being electrically connected to first electrodes of the TFTs, the signal supply leads being located within the bendable area, and both ends of the signal supply leads extending into the display area and the binding area, respectively. At least one inorganic insulating layer is disposed between the first conductive patterned layer and the flexible substrate, the inorganic insulating layer having a hollow structure within the bendable area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving substrate and a manufacturing method thereof, and a display device. Background Art

[0002] As a new generation of display technology, micro / mini-LED (Micro / Mini-LED) display technology has the advantages of high brightness, good luminous efficiency, and low power consumption. Micro / Mini-LED chips are usually transferred to the display substrate through transfer technology. Due to the limitations of transfer technology, it is impossible to directly prepare large-sized LED display substrates. Therefore, in the existing technology, multiple small-sized LED display substrates are spliced ​​together to form a large-sized LED display substrate. During the splicing process, in order to reduce the gap between the small-sized LED display substrates, it is often necessary to first bend the periphery of the LED display substrate so that the binding area of ​​the small-sized LED display substrate is located on the back, and then the splicing and fixing are carried out.

[0003] At present, in order to achieve high-definition display, active matrix drive is an inevitable choice. In current technology, in order to achieve active matrix drive, two methods are generally used: driver chip (uIC) direct drive and thin film transistor (TFT) drive. Since the uIC direct drive method is costly and has a low yield, it is difficult to actually apply it to actual products. Therefore, major manufacturers have used TFT drive as the main research method. However, in actual applications, it was found that since the TFT process will inevitably bring many inorganic layers, the Young's modulus of the inorganic layer is large, which is not conducive to the bending of the LED display substrate. In other words, the thin film transistor process and the substrate bending requirement cannot coexist. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a driving substrate and a preparation method thereof, and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a driving substrate, comprising: a flexible substrate, a plurality of thin film transistors located on the flexible substrate, and a first conductive pattern layer located on a side of the thin film transistors away from the flexible substrate;

[0006] The flexible substrate comprises: a display area, a bendable area and a binding area, the bendable area is located between the display area and the binding area, and the thin film transistor is located in the display area;

[0007] The first conductive pattern layer includes: a plurality of first connection terminals and a plurality of signal supply leads, the first connection terminals are located in the display area, some of the first connection terminals are electrically connected to the first electrode of the thin film transistor, the signal supply leads are located in the bendable area, and two ends of the signal supply leads extend into the display area and the binding area respectively;

[0008] At least one inorganic insulating layer is provided between the first conductive pattern layer and the flexible substrate, and the inorganic insulating layer is a hollow structure in the bendable region.

[0009] In some embodiments, the driving substrate further includes: an isolation barrier layer located between the flexible substrate and the thin film transistor, wherein a thickness of a portion of the isolation barrier layer located in the display area is greater than a thickness of a portion located in the bendable area.

[0010] In some embodiments, the thickness of the portion of the isolation barrier layer located in the display area includes:

[0011] The thickness of the portion of the isolation barrier layer located in the bendable region includes:

[0012] In some embodiments, the first conductive pattern layer further includes: a second connection terminal located in the binding area, the second connection terminal being electrically connected to the signal supply lead.

[0013] In some embodiments, the driving substrate further comprises: a first planarization layer located on a side of the first conductive pattern layer away from the flexible substrate;

[0014] A first via hole connected to the first connecting terminal is formed on the first planarization layer in the area where the first connecting terminal is located;

[0015] A second via hole connected to the second connecting terminal is formed on the first planarization layer in the area where the second connecting terminal is located.

[0016] In some embodiments, the thin film transistor includes: an active layer pattern, a first gate, a first electrode, and a second electrode;

[0017] A gate insulating layer is formed between the active layer pattern and the first gate electrode, an interlayer dielectric layer is formed between the first electrode and the second electrode and the active layer pattern, and the first electrode and the second electrode are connected to the active layer pattern through via holes in the interlayer dielectric layer;

[0018] The inorganic insulating layer includes the gate insulating layer and the interlayer dielectric layer.

[0019] In some embodiments, the thin film transistor further includes: a second gate;

[0020] The second gate is located on a side of the active layer pattern close to the flexible substrate, and a buffer layer is formed between the second gate and the active layer pattern;

[0021] The first gate is located on a side of the active layer pattern away from the flexible substrate, the first electrode and the second electrode are located on a side of the first gate away from the flexible substrate, and the first gate is electrically connected to the second gate;

[0022] The inorganic insulating layer further includes the buffer layer.

[0023] In some embodiments, the driving substrate further includes: a second conductive pattern layer located between the first conductive pattern layer and the flexible substrate;

[0024] The second conductive pattern layer includes: a plurality of signal transmission lines, and each of the first connection terminals that is not electrically connected to the first electrode of the thin film transistor is electrically connected to the corresponding signal supply lead through the corresponding signal transmission line.

[0025] In some embodiments, the second conductive pattern layer is provided on the same layer as the first electrode and the second electrode.

[0026] In some embodiments, a second planarization layer is formed on a side of the first electrode and the second electrode away from the flexible substrate, a first passivation layer is formed on a side of the second planarization layer away from the flexible substrate, and the second planarization layer has a hollow structure in the bendable area;

[0027] The first conductive pattern layer is located on a side of the first passivation layer away from the flexible substrate;

[0028] The inorganic insulating layer includes the first passivation layer.

[0029] In some embodiments, an expansion area is provided on a side of the binding area away from the display area;

[0030] The bendable area, the binding area and the outward expansion area are arranged along a preset direction;

[0031] The width of the bendable area in the preset direction includes: 15mm to 25mm;

[0032] The width of the binding area in the preset direction includes: 3.5mm to 4.5mm;

[0033] The width of the outward expansion area in the preset direction includes: 4.5mm to 5.5mm.

[0034] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising: a light-emitting element and a driving substrate as provided in the first aspect, wherein the light-emitting element is located on a side of the first conductive pattern layer away from the flexible substrate;

[0035] The light emitting element has a first pin and a second pin, and the first pin and the second pin are electrically connected to the corresponding first connection terminal respectively.

[0036] In a third aspect, the present disclosure further provides a method for preparing a drive substrate, which can be used to prepare the drive substrate in the first aspect, comprising:

[0037] Providing a flexible substrate, the flexible substrate comprising: a display area, a bendable area and a binding area, wherein the bendable area is located between the display area and the binding area;

[0038] forming a plurality of thin film transistors and at least one inorganic insulating layer on the flexible substrate, wherein the inorganic insulating layer has a hollow structure in the bendable region;

[0039] A first conductive graphic layer is formed on a side of the thin film transistor away from the flexible substrate, the first conductive graphic layer including: a plurality of first connecting terminals and a plurality of signal supply leads, the first connecting terminals being located in the display area, some of the first connecting terminals being electrically connected to the first electrode of the thin film transistor, the signal supply leads being located in the bendable area, and both ends of the signal supply leads extending into the display area and the binding area, respectively.

[0040] In some embodiments, the preparation method further comprises: forming a first planarization layer on a side of the first conductive pattern layer away from the flexible substrate;

[0041] The step of forming a first planarization layer includes:

[0042] forming a first planarization material film on a side of the first conductive pattern layer away from the flexible substrate, wherein the thickness of the signal supply lead is H1, and the maximum thickness of the first planarization material film is H2, where H2 is less than H1;

[0043] forming a second planarizing material film on a side of the first planarizing material film away from the flexible substrate, wherein the maximum thickness of the second planarizing material film is H3, and H3+H2>H1;

[0044] A first via hole connected to the first connection terminal and a second via hole connected to the second connection terminal are formed in an area where the second connection terminal is located on the second planarization material film through a patterning process.

[0045] In some embodiments, the step of forming a plurality of thin film transistors and at least one inorganic insulating layer on the flexible substrate includes:

[0046] forming a first gate, a gate insulating layer, an active layer pattern and an interlayer dielectric layer on the flexible substrate respectively;

[0047] A first electrode, a second electrode and a second conductive pattern layer are formed on a side of the interlayer dielectric layer away from the flexible substrate, wherein the second conductive pattern layer includes: a plurality of signal transmission lines;

[0048] A second planarization layer is formed on a side of the first electrode and the second electrode away from the flexible substrate, wherein a third via hole connected to the first connection terminal not electrically connected to the first electrode of the thin film transistor and a fourth via hole connected to the signal transmission line are formed on the second planarization layer, and the planarization layer has a hollow structure in the bendable area;

[0049] forming a first passivation layer on the second planarization layer;

[0050] Removing the first passivation layer, the interlayer dielectric layer, and the gate insulation layer in the bendable area through an etching process;

[0051] The portion of the first passivation layer located at the bottom of the third via hole and the portion of the first passivation layer located at the bottom of the fourth via hole are removed by an etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A top view of a driving substrate provided in an embodiment of the present disclosure;

[0053] Figure 2 for Figure 1 A schematic cross-sectional view in the A-A' direction;

[0054] Figure 3 for Figure 1 Another cross-sectional schematic diagram along the A-A' direction;

[0055] Figure 4 This is a schematic structural diagram of the embodiment of the present disclosure after the driving substrate is bent and assembled with the spliced ​​box;

[0056] Figure 5 A flowchart of a method for preparing a drive substrate provided in an embodiment of the present disclosure;

[0057] Figure 6 A flow chart of another method for preparing a drive substrate provided in an embodiment of the present disclosure;

[0058] Figures 7a to 7j To adopt Figure 6 Schematic diagram of the intermediate structure of the driving substrate prepared by the method shown;

[0059] Figure 8 Schematic diagram of the structure of a material film for forming a first planarization layer on a second passivation layer through a one-time coating process in an embodiment of the present disclosure;

[0060] Figure 9a and 9b Schematic diagram of the structure of a material film for forming a first planarization layer on a second passivation layer through two coating processes in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the technical solution of the present invention, a driving substrate, a preparation method thereof, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0062] Figure 1 A top view of a driving substrate provided in an embodiment of the present disclosure is shown. Figure 2 for Figure 1 A cross-sectional diagram in the A-A' direction, as shown in Figure 1 and Figure 2 As shown, the driving substrate includes: a flexible substrate 1, a plurality of thin film transistors 5 and a first conductive pattern layer 3.

[0063] The flexible substrate 1 includes: a display area 1a, a bendable area 1b, and a binding area 1c. The display area 1a is used for display; the bendable area 1b is used to bend when splicing, so that the binding area 1c is placed on the back of the flexible substrate 1. When splicing, the spacing between the display areas 1a in adjacent small-size LED display substrates can be greatly reduced, thereby reducing the splicing gap; the binding area 1c is used to bind to a flexible printed circuit (FPC) so that external signals can be written to the driver substrate through the flexible printed circuit board.

[0064] In some embodiments, the material of the flexible substrate 1 includes polyimide. In some embodiments, the thickness of the flexible substrate 1 ranges from 3 μm to 10 μm.

[0065] The thin film transistor 5 is located on the flexible substrate 1 and can be manufactured using an existing thin film transistor 5 manufacturing process, which will be described in detail later with reference to specific examples. During the manufacturing process of the thin film transistor 5 using the thin film transistor 5 manufacturing process, at least one inorganic insulating layer is inevitably formed. This inorganic insulating layer has a hollow structure in the bendable region 1b.

[0066] It should be noted that during the process of manufacturing the thin film transistor 5 through the thin film transistor 5 process, a gate insulating layer 11 is inevitably formed between the gate electrode and the active layer. The material of the gate insulating layer 11 is an inorganic insulating material (generally silicon oxide and / or silicon nitride). Therefore, in the embodiment of the present disclosure, at least one gate insulating layer 11 is present between the first conductive pattern and the flexible substrate 1 as an inorganic insulating layer.

[0067] In the embodiment of the present disclosure, each LED chip is configured with a corresponding pixel driving circuit 2, which is used to provide a driving current to the corresponding LED chip to drive the corresponding LED chip to emit light. Each pixel driving circuit 2 includes a plurality of thin film transistors 5. It should be noted that the technical solution of the present disclosure does not limit the specific circuit structure of the pixel driving circuit 2. Figure 2 In the figure, only one transistor connected to the LED in the pixel circuit is shown as an example.

[0068] The first conductive pattern layer 3 is located on the side of the thin film transistor 5 away from the flexible substrate 1. The first conductive pattern layer 3 includes: multiple first connection terminals 3a (also called pads) and multiple signal supply leads 3b. The first connection terminals 3a are located in the display area 1a, and some of the first connection terminals 3a are electrically connected to the first electrode 8 of the thin film transistor 5. The signal supply leads 3b are located in the bendable area 1b, and the two ends of the signal supply leads 3b extend into the display area 1a and the binding area 1c respectively, so that the external signal provided by the FPC can be written to the display area 1a through the signal supply leads 3b.

[0069] In the embodiment of the present disclosure, since the inorganic insulating layer is a hollow structure in the bendable area 1b, the setting of the inorganic insulating layer will not cause the Young's modulus of the bendable area 1b to increase, and the bendable area 1b can be bent normally, thereby realizing the coexistence of the thin film transistor 5 process and the substrate bending requirements.

[0070] See also Figure 2 As shown, in some embodiments, the thin film transistor 5 is a top-gate thin film transistor, that is, the gate electrode 7 is located on the side of the active layer pattern 6 away from the flexible substrate 1, the first electrode 8 and the second electrode 9 are located on the side of the gate electrode 7 away from the flexible substrate 1, a gate insulating layer 11 is formed between the active layer pattern 6 and the gate electrode 7, and an interlayer dielectric layer 12 (generally made of silicon oxide and / or silicon nitride) is formed between the first electrode 8 and the second electrode 9 and the active layer pattern 6. The first electrode 8 and the second electrode 9 are connected to the active layer pattern 6 through vias in the interlayer dielectric layer 12. In this case, the inorganic insulating layer includes the interlayer dielectric layer 12 and the gate insulating layer 11.

[0071] In the embodiment of the present disclosure, one of the first electrode 8 and the second electrode 9 in the thin film transistor 5 is a source electrode, and the other is a drain electrode; in some cases, the source electrode and the drain electrode can be interchanged.

[0072] It should be noted that Figure 2 The thin film transistor 5 shown in the figure is a top-gate thin film transistor for illustrative purposes only and does not limit the technical solution of the present disclosure. In the embodiment of the present disclosure, the thin film transistor 5 may also adopt other structures, such as a bottom-gate thin film transistor or a dual-gate thin film transistor.

[0073] When thin film transistor 5 is a bottom-gate thin film transistor, gate 7 is located on the side of active layer pattern 6 close to flexible substrate 1, first electrode 8 and second electrode 9 are located on the side of active layer pattern 6 away from flexible substrate 1, a gate insulating layer 11 is formed between active layer pattern 6 and gate, and an interlayer dielectric layer 12 is formed between first electrode 8 and second electrode 9 and active layer pattern 6. In this case, the inorganic insulating layer includes interlayer dielectric layer 12 and gate insulating layer 11.

[0074] Figure 3 for Figure 1 Another cross-sectional diagram along the A-A' direction is shown in FIG. Figure 3 As shown, in Figure 3 In the illustrated case, the thin film transistor 5 is a dual-gate thin film transistor. Specifically, the thin film transistor 5 includes a first gate 7a, a second gate 7b, a first electrode 8, and a second electrode 9 ( Figure 3 (not shown); wherein, the second gate 7b is located on the side of the active layer pattern 6 close to the flexible substrate 1, the first gate 7a is located on the side of the active layer pattern 6 away from the flexible substrate 1, the first electrode 8 and the second electrode 9 are located on the side of the first gate 7a away from the flexible substrate 1, a buffer layer 19 is formed between the second gate 7b and the active layer pattern 6, a gate insulating layer 11 is formed between the first gate 7a and the active layer pattern 6, and an interlayer dielectric layer 12 is formed between the first electrode 8 and the second electrode 9 and the first gate 7a. The first gate 7a and the second gate 7b are electrically connected by a connecting wire (not shown, provided on the same layer as the first electrode 8 and the second electrode 9, with both ends connected to the first gate 7a and the second gate 7b via holes). In this case, the inorganic insulating layer includes the buffer layer 19, the gate insulating layer 11, and the interlayer dielectric layer 12.

[0075] Continue to see Figure 2 and Figure 3 As shown, in some embodiments, the driving substrate further includes: an isolation barrier layer 10, which is located between the flexible substrate 1 and the thin film transistor 5 and is used to prevent impurities such as particles, water vapor, and oxygen in the flexible substrate 1 from diffusing to the functional film layers above, so as to avoid abnormalities in the functional film layers located on the flexible substrate 1.

[0076] In some embodiments, the thickness of the portion of the isolation barrier layer 10 located in the display area 1a is greater than the thickness of the portion located in the bendable area 1b. In the display area 1a, since the electrical characteristics of the thin film transistor 5 are relatively sensitive, when impurities such as particles, water vapor, and oxygen diffuse into the active layer pattern 6 of the thin film transistor 5, the electrical characteristics of the thin film transistor 5 will change significantly. Therefore, the isolation barrier layer 10 in the display area 1a has a higher isolation barrier requirement. In the bendable area 1b, since there is only one conductive structure, namely the signal supply lead 3b, impurities such as particles, water vapor, and oxygen have a relatively small effect on the electrical characteristics of the signal supply lead 3b (the signal supply lead 3b is generally made of a metal material. When oxidizing particles diffuse into the signal supply lead 3b, they easily cause oxidation on the metal material surface, slightly increasing the resistance of the signal supply lead 3b). Therefore, the isolation barrier layer 10 in the display area 1a has a relatively lower isolation barrier requirement.

[0077] The thickness of the isolation barrier layer 10 directly determines the isolation barrier performance. Generally speaking, the thicker the isolation barrier layer 10, the higher the isolation barrier performance. Therefore, in this application, the thickness of the portion of the isolation barrier layer 10 located in the display area 1a can be set to be the same as the thickness of the portion located in the bendable area 1b. Since the thickness of the isolation barrier layer 10 in the bendable area 1b is thinner, the overall Young's modulus of the bendable area can be effectively reduced, facilitating the bending of the drive substrate.

[0078] In some embodiments, the thickness of the portion of the isolation barrier layer 10 located in the display area 1a includes: The thickness of the portion of the isolation barrier layer 10 located in the bendable region 1b includes: The large-thickness isolation barrier layer 10 located in the display area can effectively prevent impurities such as particles, water vapor, oxygen, etc. in the flexible substrate 1 from diffusing to the thin film transistor 5; the small-thickness isolation barrier layer 10 located in the bendable area 1b can not only improve the isolation and barrier performance of the bendable area 1b, but also effectively reduce the overall Young's modulus of the bendable area, which is conducive to driving the bending of the substrate.

[0079] In some embodiments, the portion of the isolation barrier layer 10 located in the display area 1a includes SiO (with a thickness of about ), SiN (thickness is about ) and SiO (thickness in The portion of the isolation barrier layer 10 located in the display area 1a includes SiO (thickness of about ) and SiN (thickness approx. ), in some embodiments, SiO (with a thickness of about ).

[0080] Continue to see Figure 2 and Figure 3 As shown, in some embodiments, the first conductive pattern layer 3 further includes: a second connection terminal 3c located in the binding area 1c, and the second connection terminal 3c is electrically connected to the signal supply lead 3b.

[0081] In some embodiments, a first planarization layer 16 is provided on a side of the first conductive pattern layer 3 away from the flexible substrate 1; a first via 17 connected to the first connection terminal 3a is formed on the first planarization layer 16 in the area where the first connection terminal 3a is located; and a second via 18 connected to the second connection terminal 3c is formed on the first planarization layer 16 in the area where the second connection terminal 3c is located.

[0082] In practical applications, a die-bonding process can be used to electrically connect the LED chip pins to the first connection terminals 3a through the first vias 17 on the first planarizing layer 16. A bonding process can be used to bond the connection pins on the FPC to the second connection terminals 3c through the second vias 18 on the first planarizing layer 16. The LED chip die-bonding process and the FPC bonding process can be based on existing methods in the art, and the specific process is not described here in detail.

[0083] In some embodiments, a second passivation layer 15 is disposed between the first planarization layer 16 and the first conductive pattern layer 3. Connection holes are formed in the second passivation layer 15 at the bottom of the first via 17 and the bottom of the second via 18, exposing the first and second connection terminals 3a and 3c. The second passivation layer 15 effectively prevents impurities such as particles, water vapor, and oxygen from the first planarization layer 16 from invading the first conductive pattern layer 3, thereby extending the service life of the driver substrate.

[0084] In some embodiments, the second passivation layer 15 and the isolation barrier layer 10 are hollow structures in the bendable region 1b and not covering the second conductive pattern layer 4. Further reducing the inorganic material in the bendable region 1b can further reduce the overall Young's modulus of the bendable region.

[0085] In some embodiments, the driving substrate further includes: a second conductive pattern layer 4; a second conductive pattern layer 4 located between the first conductive pattern layer 3 and the flexible substrate 1; the second conductive pattern layer 4 includes: a plurality of signal transmission traces 4a, and each first connection terminal 3a that is not electrically connected to the first electrode 8 of the thin film transistor 5 is electrically connected to the corresponding signal supply lead 3b through the corresponding signal transmission trace 4a.

[0086] In the embodiment of the present disclosure, the signal transmission traces 4a in the second conductive pattern layer 4 are used for electrical connection between the conductive structures in the display area 1a to realize signal transmission in the display area 1a. For example, the signal transmission traces 4a can be data lines, wires connecting different thin film transistors 5 in the pixel driving circuit 2, Figure 3 The technical solution disclosed in the present invention does not limit the type and quantity of the signal transmission lines 4a included in the second conductive pattern layer 4, such as the connecting lines connecting the first gate 7a and the second gate 7b.

[0087] In some embodiments, the second conductive pattern layer 4 further includes: a plurality of conductive electrodes 4b, which are located in the binding area 1c and connected in parallel with the second connection terminal 3c, thereby effectively reducing the equivalent resistance at the second connection terminal 3c.

[0088] In some embodiments, the second conductive pattern layer 4 is provided in the same layer as the first electrode 8 and the second electrode 9. In this case, the first electrode 8, the second electrode 9 and the second conductive pattern layer 4 can be prepared simultaneously through a source-drain process.

[0089] In some embodiments, a second planarization layer 13 is formed on the side of the first electrode 8 and the second electrode 9 away from the flexible substrate 1, and a first passivation layer 14 is formed on the side of the second planarization layer 13 away from the flexible substrate 1. The second planarization layer 13 has a hollow structure in the bendable area 1b; the first conductive pattern layer 3 is located on the side of the first passivation layer 14 away from the flexible substrate 1; in this case, the inorganic insulating layer also includes the first passivation layer 14.

[0090] Figure 4 FIG. 1 is a schematic diagram of the structure of the drive substrate after being bent and assembled with the splicing box in the embodiment of the present disclosure. Figures 1 to 4 As shown, an expansion area 1e is provided on a side of the binding area 1c away from the display area 1a, and the bendable area 1b, the binding area 1c and the expansion area 1e are arranged along a preset direction.

[0091] In some embodiments, the width W2 of the bendable area 1b in the preset direction includes: 15mm~25mm; the width W3 of the binding area 1c in the preset direction includes: 3.5mm~4.5mm; the width W4 of the outward expansion area 1e in the preset direction includes: 4.5mm~5.5mm.

[0092] In some embodiments, a reserved bending area 1d with a width W1 of about 1 mm is provided between the display area 1a and the bendable area 1b to prevent the portion of the display area 1a close to the bendable area 1b from bending when the bendable area 1b is bent.

[0093] See also Figure 4As shown, in some embodiments, the left and right sides of the driving substrate 20 are both provided with a bendable area 1b, a binding area 1c and an expansion area 1e, that is, both the left and right sides of the driving substrate 20 can be bent.

[0094] During the splicing process of the driver substrate 20, the bendable region 1b of the driver substrate 20 must first be bent, then the driver substrate 20 and the glass substrate 21 must be assembled and fixed together. Finally, the glass substrate 21 carrying the driver substrate 20 must be assembled and fixed together with the splicing box 22. The bendable region 1b, the binding region 1c, and the expansion region 1e of the driver substrate 20 are ultimately bent into a stepped shape. The back of the glass substrate 21 and the splicing box 22 hold the binding region 1c and the expansion region 1e of the driver substrate.

[0095] The embodiment of the present disclosure further provides a method for preparing a driving substrate, which is used to prepare the driving substrate provided in the previous embodiment, and will be described in detail below with reference to the accompanying drawings.

[0096] Figure 5 A flowchart of a method for preparing a drive substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the preparation method comprises:

[0097] Step S101: providing a flexible substrate.

[0098] The flexible substrate includes a display area, a bendable area and a binding area, and the bendable area is located between the display area and the binding area.

[0099] Step S102 : forming a plurality of thin film transistors and at least one inorganic insulating layer on the flexible substrate, wherein the inorganic insulating layer has a hollow structure in the bendable region.

[0100] Step S103: forming a first conductive pattern layer on a side of the thin film transistor away from the flexible substrate.

[0101] Among them, the first conductive graphic layer includes: multiple first connecting terminals and multiple signal supply leads, the first connecting terminals are located in the display area, some of the first connecting terminals are electrically connected to the first pole of the thin film transistor, the signal supply leads are located in the bendable area, and the two ends of the signal supply leads extend to the display area and the binding area respectively.

[0102] Figure 6 A flowchart of another method for preparing a drive substrate provided in an embodiment of the present disclosure is provided. Figures 7a to 7j To adopt Figure 6 The intermediate structure diagram of the driving substrate prepared by the method shown in FIG. Figures 6-7j As shown, to prepare Figure 2 and Figure 3 The driving substrate shown in FIG is taken as an example for exemplary description, and the preparation method includes:

[0103] Step S201: providing a flexible substrate.

[0104] See also Figure 7a As shown, the flexible substrate 1 includes a display area 1a, a bendable area 1b, and a binding area 1c. The bendable area 1b is located between the display area 1a and the binding area 1c. In some embodiments, a reserved bending area 1d is provided between the display area 1a and the bendable area 1b, and an expansion area 1e is provided on the side of the binding area 1c away from the display area 1a.

[0105] Step S202: forming an initial structure of an isolation barrier layer on a flexible substrate.

[0106] See also Figure 7b As shown, in some embodiments, the isolation barrier layer 10 includes SiO films (with a thickness of about 100 nm) sequentially arranged in a direction away from the flexible substrate 1. ), SiN film (thickness is about ) and SiO thin films (thickness ). SiO film and SiN film can be prepared by sputtering process. The overall thickness of the three-layer film stack structure is

[0107] Step S203 : forming a thin film transistor 5 and a second conductive pattern layer 4 on the side of the initial pattern of the isolation barrier layer 10 away from the flexible substrate 1 through a thin film transistor 5 process.

[0108] To prepare Figure 2 Taking the thin film transistor 5 shown in FIG as an example, step S103 specifically includes: first, forming an active layer pattern 6 on the side of the isolation barrier layer 10 away from the flexible substrate 1 through a patterning process; then, forming a gate insulating layer 11 on the side of the active layer pattern 6 away from the flexible substrate 1 through a sputtering process; then, forming a first gate electrode 7a on the side of the gate insulating layer 11 away from the flexible substrate 1 through a patterning process; then, forming an interlayer dielectric layer 12 on the side of the first gate electrode 7a away from the flexible substrate 1 through a sputtering process; finally, forming a first electrode 8, a second electrode 9, and various conductive structure patterns in the second conductive pattern layer 4 (for example, a signal transmission line in the display area 1a, a conductive electrode 4b in the binding area 1c) on the side of the interlayer dielectric layer 12 away from the flexible substrate 1 through a patterning process. The corresponding figures for this case are not provided.

[0109] In the embodiments of the present disclosure, the "patterning process" may also be referred to as a composition process, which refers to the step of forming a structure with a specific pattern, which may be a photolithography process. The photolithography process includes one or more steps of photoresist coating, exposure, development, etching, photoresist stripping, etc. performed after the material is formed into a film; of course, the "composition process" may also be other processes such as an imprinting process and an inkjet printing process.

[0110] See also Figure 7c As shown, to prepare Figure 3 Taking the thin film transistor 5 shown in FIG as an example, step S103 specifically includes: first, forming a second gate 7b on the side of the isolation barrier layer 10 away from the flexible substrate 1 through a patterning process; then, forming a buffer layer 19 (made of SiO and / or SiN) on the side of the second gate 7b away from the flexible substrate 1 through a sputtering process; then, forming an active layer pattern 6 on the side of the isolation barrier layer 10 away from the flexible substrate 1 through a patterning process; then, forming a gate insulating layer 11 on the side of the buffer layer 19 away from the flexible substrate 1 through a sputtering process; then, forming a first gate 7a on the side of the gate insulating layer 11 away from the flexible substrate 1 through a patterning process; then, forming an interlayer dielectric layer 12 on the side of the first gate 7a away from the flexible substrate 1 through a sputtering process; finally, forming a first electrode 8, a second electrode 9, and various conductive structure patterns in the second conductive pattern layer 4 (for example, a signal transmission line located in the display area 1a, a conductive electrode 4b located in the binding area 1c) on the side of the interlayer dielectric layer 12 away from the flexible substrate 1 through a patterning process.

[0111] In some embodiments, the materials of the first electrode 8 , the second electrode 9 and the second conductive pattern layer 4 are metal materials.

[0112] Step S204 : forming a second planarization layer on a side of the first electrode and the second electrode away from the flexible substrate.

[0113] See also Figure 7d As shown, a third via 13a connected to the first pole 8 of the thin film transistor 5, a fourth via 13b connected to the signal transmission line 4a, and a fifth via 13c connected to the conductive electrode 4b are formed on the second planarization layer 13. The second planarization layer 13 is a hollow structure in the bendable area 1b.

[0114] Step S205 , forming an initial structure of a first passivation layer 14 on the second planarization layer 13 .

[0115] See also Figure 7e As shown, a passivation material film is formed by a sputtering process to obtain the initial structure of the first passivation layer 14.

[0116] Step S206 , removing the first passivation layer, the interlayer dielectric layer, the gate insulation layer, and the buffer layer located in the bendable region through an etching process.

[0117] See also Figure 7fAs shown, the first passivation layer 14, the interlayer dielectric layer 12, the gate insulating layer 11, and the buffer layer 19 are removed from the bendable region 1b by a dry etching process, and the isolation barrier layer 10 is thinned from the bendable region 1b to make the thickness of the isolation barrier layer 10 from the bendable region 1b to be within 1 / 4 of the thickness.

[0118] Step S207 , removing the portion of the first passivation layer located at the bottom of the third via hole, the portion located at the bottom of the fourth via hole, and the portion located at the bottom of the fifth via hole by an etching process.

[0119] See also Figure 7g As shown, the portion of the first passivation layer 14 located at the bottom of the third via hole 13a, the portion located at the bottom of the fourth via hole 13b, and the portion located at the bottom of the fifth via hole 13c are removed by a dry etching process, so that the conductive structure located under the third via hole 13a, the fourth via hole 13b, and the fifth via hole 13c is exposed.

[0120] Since the material of the second planarization layer 13 is an organic material, the organic material itself contains a certain amount of water and oxygen, which will cause the gas in the organic material to overflow under the high-temperature process. If this part of the gas cannot be discharged in time, it will easily cause bulging on the first passivation layer 14; for this reason, in the embodiment of the present disclosure, in the process of re-etching the first passivation layer 14 through S207, an exhaust hole (not shown) is also formed on the first passivation layer 14 to obtain the final pattern of the first passivation layer 14.

[0121] Step S208 : forming a first conductive pattern layer on a side of the first passivation layer facing away from the flexible substrate.

[0122] See also Figure 7h As shown, the first conductive graphic layer 3 includes: multiple first connecting terminals 3a, multiple second connecting terminals 3c and multiple signal supply leads 3b, the first connecting terminals 3a are located in the display area 1a, the second connecting terminals 3c are located in the binding area 1c, part of the first connecting terminals 3a are electrically connected to the first electrode 8 of the thin film transistor 5, the signal supply lead 3b is located in the bendable area 1b, and both ends of the signal supply lead 3b extend to the display area 1a and the binding area 1c respectively.

[0123] The first connecting terminal 3a is connected to the corresponding first pole 8 and the signal transmission line 4a through the third via 13a and the fourth via 13b respectively. The signal supply lead 3b extends to one end of the display area 1a and is connected to the corresponding signal transmission line 4a through the fourth via. The signal supply lead 3b extends to one end of the binding area 1c and is connected to the second connecting terminal 3c. The second connecting terminal 3c is connected to the conductive electrode 4b through the fifth via 13c.

[0124] In some embodiments, the material of the first conductive pattern layer 3 includes copper.

[0125] In order to minimize the voltage drop caused by the resistance of the conductive structure in the first conductive pattern layer 3, the thickness of the conductive structure in the first conductive pattern layer 3 is generally designed to be thicker. For example, if the material of the first conductive pattern layer 3 includes copper, the thickness of copper is generally greater than 2 μm.

[0126] Step S209 : forming an initial pattern of a second passivation layer on a side of the first conductive pattern layer away from the flexible substrate.

[0127] See also Figure 7i As shown, a passivation material film is first formed by a sputtering process, and then a patterning process is used to form an exhaust hole on the second passivation layer 15 that is connected to the exhaust hole on the first passivation layer 14, and the second passivation layer 15 and the isolation barrier layer 10 that are located in the bendable area 1b and not covering the second conductive pattern layer 4 are removed to obtain the initial pattern of the second passivation layer 15 and the final pattern of the isolation barrier layer 10.

[0128] Step S210 : forming a first planarization layer 16 on a side of the second passivation layer 15 away from the flexible substrate 1 .

[0129] See also Figure 7j As shown, a first via 17 connected to the first connection terminal 3a is formed on the first planarization layer 16 in the area where the first connection terminal 3a is located; a second via 18 connected to the second connection terminal 3c is formed on the first planarization layer 16 in the area where the second connection terminal 3c is located.

[0130] Figure 8 FIG. 1 is a schematic structural diagram of a material film for forming a first planarization layer on a second passivation layer through a one-time coating process in an embodiment of the present disclosure. Figure 8 As shown, in actual production, it has been found that due to the high viscosity of existing planarization materials, when the planarization material is evenly coated on the surface of the second passivation layer 15 through a coating process, the surface morphology of the planarization material film formed is substantially the same as the surface morphology of the second passivation layer 15. In this case, the thickness H0' of the planarization material film above the signal supply lead 3b in the bendable area 1b is substantially equal to the thickness H0 of the planarization material film in the display area 1a.

[0131] Since the die bonding process requires that the thickness of the first planarization layer 16 be 2um to 3um greater than the first connecting terminal 3a, when the thickness of the conductive structure in the first conductive pattern layer 3 is large, the thickness of the planarization material film to be applied is thicker. The thickness H0' of the planarization material film located above the signal supply lead 3b in the bendable area 1b is large. At this time, the overall thickness of the position where the signal supply lead 3b is set in the bending area is large, which will generate large stress during the bending process, and the first planarization layer 16 is prone to tensile fracture.

[0132] Based on the above considerations, in the disclosed embodiment, when the thickness of the first conductive pattern layer 3 (signal supply lead 3b) is relatively small (for example, when the thickness of the first conductive pattern layer 3 is less than or equal to 4 μm), the required thickness of the planarization material film is relatively small, and the thickness H0' of the planarization material film located above the signal supply lead 3b is relatively small, resulting in a relatively low risk of tensile fracture of the first planarization layer 16. In this case, a single coating method can be used to form the material film of the first planarization layer 16.

[0133] Figure 9a and 9b FIG. 1 is a schematic diagram of a structure in which a material film of a first planarization layer is formed on a second passivation layer through two coating processes in an embodiment of the present disclosure. Figure 9a and 9b As shown, when the thickness of the first conductive pattern layer 3 (signal supply lead 3b) is relatively large (for example, when the thickness of the first conductive pattern layer 3 is greater than 4um), it is necessary to adopt a two-time coating method to form the material film of the first planarization layer 16. In this case, step S210 includes: first, referring to Figure 9a As shown, a first planarization material film 16a is formed on the side of the first conductive pattern layer 3 away from the flexible substrate 1, the thickness of the signal supply lead 3b is H1, the maximum thickness of the first planarization material film 16a is H2, H2 Figure 9b As shown, a second planarizing material film 16b is formed on the side of the first planarizing material film 16a away from the flexible substrate 1. The maximum thickness of the second planarizing material film 16b is H3, and H3+H2>H1. The first planarizing material film 16a and the second planarizing material film 16b constitute the material film of the first planarizing layer 16. It should be noted that when the material film of the first planarizing layer 16 is formed by a double coating process and H3+H2 is equal to Figure 8 When H0, the thickness H3 of the planarization material film above the signal supply lead 3b is significantly smaller than Figure 8 Middle H0'.

[0134] See also Figure 7j As shown, Figure 8 or Figure 9b ​The material film of the first planarization layer 16 is patterned to form a first via hole 17 and a second via hole 18 at positions corresponding to the first connection terminal 3 a and the second connection terminal 3 c , respectively.

[0135] Step S211 , removing the portion of the second passivation layer located at the bottom of the first via hole and the portion of the second passivation layer located at the bottom of the second via hole.

[0136] See also Figure 2 and Figure 3 As shown, the portion of the second passivation layer 15 located at the bottom of the first via hole 17 and the portion located at the bottom of the second via hole 18 are removed by a dry etching process, so that the first connection terminal 3a and the second connection terminal 3c are exposed.

[0137] Based on the above steps S201 to S211, Figure 2 and Figure 3 The driving substrate shown in FIG. Because the inorganic insulating layer formed by the thin-film transistor process has a hollow structure within the bendable region, the provision of the inorganic insulating layer does not increase the Young's modulus of the bendable region, allowing the bendable region to bend normally. This allows the coexistence of the thin-film transistor process and the substrate bending requirements.

[0138] An embodiment of the present disclosure also provides a display device comprising: a light-emitting element and a driving substrate, the light-emitting element being located on a side of a first planarization layer away from a flexible substrate, the light-emitting element having a first pin and a second pin, the first pin and the second pin being connected to corresponding first connection terminals in the first conductive layer through a first via hole on the first planarization layer.

[0139] When the first pin / the second pin is connected to the first connection terminal, an auxiliary structure (such as solder, conductive adhesive, etc.) may be used to achieve a more reliable electrical connection.

[0140] In some embodiments, the light-emitting element includes: a Micro-LED or a Mini-LED, and the first pin and the second pin of the light-emitting element refer to the cathode and anode of the Micro-LED / Mini-LED, respectively.

[0141] In this embodiment, the light-emitting element and the drive substrate can form a light source with other optical structures (such as a light guide plate, a diffuser, etc.) to provide light for the display panel in the display device. Alternatively, the light-emitting element and the drive substrate can be part of the display panel in the display device and directly display the image.

[0142] In some embodiments, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0143] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a driving substrate, wherein: include: Providing a flexible substrate, the flexible substrate comprising: a display area, a bendable area and a binding area, wherein the bendable area is located between the display area and the binding area; forming a plurality of thin film transistors and at least one inorganic insulating layer on the flexible substrate, wherein the inorganic insulating layer has a hollow structure in the bendable region; A first conductive pattern layer is formed on a side of the thin film transistor away from the flexible substrate, the first conductive pattern layer comprising: a plurality of first connection terminals, a plurality of signal supply leads, and a plurality of second connection terminals, the first connection terminals being located in the display area, some of the first connection terminals being electrically connected to the first electrode of the thin film transistor, the signal supply leads being located in the bendable area, two ends of the signal supply leads extending into the display area and the binding area, respectively; the second connection terminals being located in the binding area, and electrically connected to the signal supply leads; forming a first planarization layer on a side of the first conductive pattern layer away from the flexible substrate; The step of forming a first planarization layer includes: forming a first planarization material film on a side of the first conductive pattern layer away from the flexible substrate, wherein the thickness of the signal supply lead is H1, and the maximum thickness of the first planarization material film is H2, where H2 is less than H1; forming a second planarizing material film on a side of the first planarizing material film away from the flexible substrate, wherein the maximum thickness of the second planarizing material film is H3, and H3+H2>H1; A first via hole connected to the first connection terminal and a second via hole connected to the second connection terminal are formed on the second planarization material film through a patterning process.

2. The preparation method according to claim 1, wherein The step of forming a plurality of thin film transistors and at least one inorganic insulating layer on the flexible substrate comprises: forming a first gate, a gate insulating layer, an active layer pattern and an interlayer dielectric layer on the flexible substrate respectively; A first electrode, a second electrode and a second conductive pattern layer are formed on a side of the interlayer dielectric layer away from the flexible substrate, wherein the second conductive pattern layer includes: a plurality of signal transmission lines; A second planarization layer is formed on a side of the first electrode and the second electrode away from the flexible substrate, wherein a third via hole connected to the first connection terminal not electrically connected to the first electrode of the thin film transistor and a fourth via hole connected to the signal transmission line are formed on the second planarization layer, and the planarization layer has a hollow structure in the bendable area; forming a first passivation layer on the second planarization layer; Removing the first passivation layer, the interlayer dielectric layer, and the gate insulation layer in the bendable area through an etching process; The portion of the first passivation layer located at the bottom of the third via hole and the portion of the first passivation layer located at the bottom of the fourth via hole are removed by an etching process.

3. A driving substrate, prepared by the preparation method according to claim 1 or 2; wherein: The driving substrate comprises: a flexible substrate, a plurality of thin film transistors located on the flexible substrate, and a first conductive pattern layer located on a side of the thin film transistors away from the flexible substrate; The flexible substrate comprises: a display area, a bendable area, and a binding area, the bendable area being located between the display area and the binding area, and the thin film transistor being located within the display area; the thin film transistor comprising: an active layer pattern, a first gate, a first electrode, and a second electrode; a second planarization layer is formed on a side of the first electrode and the second electrode away from the flexible substrate, a first passivation layer is formed on a side of the second planarization layer away from the flexible substrate, and the second planarization layer and the first passivation layer are hollow structures in the bendable area; The first conductive pattern layer includes: a plurality of first connection terminals and a plurality of signal supply leads, the first connection terminals are located in the display area, some of the first connection terminals are electrically connected to the first electrode of the thin film transistor, the signal supply leads are located in the bendable area, and two ends of the signal supply leads extend into the display area and the binding area respectively; At least one inorganic insulating layer is provided between the first conductive pattern layer and the flexible substrate, and the inorganic insulating layer is a hollow structure in the bendable region.

4. The driving substrate according to claim 3, wherein: Also includes: An isolation barrier layer is located between the flexible substrate and the thin film transistor, wherein a thickness of a portion of the isolation barrier layer located in the display area is greater than a thickness of a portion located in the bendable area.

5. The driving substrate according to claim 4, wherein: The thickness of the portion of the isolation barrier layer located in the display area includes: 6500Å to 9500Å; The thickness of the portion of the isolation barrier layer located in the bendable area ranges from 1000Å to 2000Å. The drive substrate according to claim 3 , wherein: Also includes: a first planarization layer located on a side of the first conductive pattern layer away from the flexible substrate; A first via hole connected to the first connecting terminal is formed on the first planarization layer in the area where the first connecting terminal is located; A second via hole connected to the second connecting terminal is formed on the first planarization layer in the area where the second connecting terminal is located.

7. The driving substrate according to any one of claims 3 to 6, wherein: The thin film transistor comprises: an active layer pattern, a first gate, a first electrode and a second electrode; A gate insulating layer is formed between the active layer pattern and the first gate electrode, an interlayer dielectric layer is formed between the first electrode and the second electrode and the active layer pattern, and the first electrode and the second electrode are connected to the active layer pattern through via holes in the interlayer dielectric layer; The inorganic insulating layer includes the gate insulating layer and the interlayer dielectric layer.

8. The driving substrate according to claim 7, wherein: The thin film transistor further includes: a second gate; The second gate is located on a side of the active layer pattern close to the flexible substrate, and a buffer layer is formed between the second gate and the active layer pattern; The first gate is located on a side of the active layer pattern away from the flexible substrate, the first electrode and the second electrode are located on a side of the first gate away from the flexible substrate, and the first gate is electrically connected to the second gate; The inorganic insulating layer further includes the buffer layer.

9. The driving substrate according to claim 7, wherein: The driving substrate further includes: a second conductive pattern layer located between the first conductive pattern layer and the flexible substrate; The second conductive pattern layer includes: a plurality of signal transmission lines, and each of the first connection terminals that is not electrically connected to the first electrode of the thin film transistor is electrically connected to the corresponding signal supply lead through the corresponding signal transmission line.

10. The driving substrate according to claim 9, wherein: The second conductive pattern layer is provided on the same layer as the first electrode and the second electrode. The driving substrate according to claim 10 , wherein: A second planarization layer is formed on a side of the first electrode and the second electrode away from the flexible substrate, a first passivation layer is formed on a side of the second planarization layer away from the flexible substrate, and the second planarization layer has a hollow structure in the bendable area; The first conductive pattern layer is located on a side of the first passivation layer away from the flexible substrate; The inorganic insulating layer includes the first passivation layer.

12. The driving substrate according to claim 3, wherein: An outward expansion area is provided on a side of the binding area away from the display area; The bendable area, the binding area and the outward expansion area are arranged along a preset direction; The width of the bendable area in the preset direction includes: 15mm to 25mm; The width of the binding area in the preset direction includes: 3.5mm to 4.5mm; The width of the outward expansion area in the preset direction includes: 4.5mm to 5.5mm.

13. A display device, wherein: include: A light-emitting element and a driving substrate as claimed in any one of claims 3 to 12, wherein the light-emitting element is located on a side of the first conductive pattern layer away from the flexible substrate; The light emitting element has a first pin and a second pin, and the first pin and the second pin are electrically connected to the corresponding first connection terminal respectively.

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