A nitride power semiconductor device with a core-shell structure and a method for preparing the same

Abstract

The present invention provides a vertical III-type nitride power semiconductor device with a core-shell structure and a preparation method thereof. The device of the present invention comprises: an N-type gallium nitride substrate layer; an N-type gallium nitride drift layer, located above the N-type gallium nitride substrate layer; a groove is arranged on the N-type gallium nitride drift layer; an N-type gallium nitride ring is arranged on the bottom surface and sidewall of the groove, a P-type gallium nitride region is arranged above the N-type gallium nitride ring, and the N-type gallium nitride ring and the P-type gallium nitride region form a core-shell structure; an oxide layer, an oxide layer is arranged on the outer surface of the P-type gallium nitride region, an exposed surface of the N-type gallium nitride ring, and an exposed surface of the inner wall of the groove; and a metal electrode layer. The structural design of the present invention can essentially solve the problem of electric field concentration near the heterojunction, thereby improving the reverse withstand voltage capability of the device. At the same time, there is no obvious decay phenomenon in the forward on-resistance of the device, which further demonstrates the great prospect of commercial application of vertical power devices in the field of high-frequency and high-power devices.

Description

Technical Field

[0001] The invention relates to a vertical group III nitride power semiconductor device with a core-shell structure and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] At present, the gallium nitride devices that have been successfully commercialized are mainly lateral devices prepared by heteroepitaxial growth on substrates such as silicon, silicon carbide and sapphire. The high electron mobility field effect transistor (HEMT) device prepared by using the two-dimensional electron gas layer (2DEG) at the heterojunction interface formed between gallium nitride and aluminum gallium nitride materials as a conductive channel has successfully realized the functions of high-frequency transmission and bidirectional switching elements and is widely used in 5G high-frequency communications and consumer electronics. However, lateral devices based on heteroepitaxial substrates have problems such as high defect density of epitaxial materials and channel performance being easily affected by trap effects, which causes dynamic on-resistance degradation, which greatly limits their application in high-voltage and high-power power electronic systems. On the other hand, lateral devices are also affected by trap states and strong surface electric fields, which leads to current collapse and other reliability problems; the main disadvantage of lateral devices is that the breakdown voltage of the device is proportional to the spacing between the electrodes, resulting in a larger device area in high-voltage working scenarios. Therefore, in order to increase the breakdown voltage of the device in a lateral device, in addition to separating different electrodes, the reverse blocking performance of the device can also be improved by increasing the thickness of the device and improving the quality of the epitaxial growth material. This also increases the overall complexity and process preparation cost of the commercial production of high-voltage, high-power devices.

[0003] These problems of lateral devices can be fundamentally solved in vertical GaN power devices grown homoepitaxially on single-crystal GaN substrates. Because the electric field peak of vertical GaN power devices is far away from the device surface, the breakdown voltage depends on the thickness and concentration of the drift layer rather than the size of the device. Therefore, the preparation of high-voltage devices can be done by increasing the thickness of the material without increasing the size of a single device. At the same time, vertical GaN power devices are less sensitive to surface trap states, which can reduce dynamic on-resistance and alleviate current collapse effects. However, vertical GaN power devices usually also experience premature breakdown of the device due to electric field accumulation near the heterojunction, and the forward conduction channel region also has a large forward conduction resistance due to the depletion effect of carriers inside the device.

[0004] Schottky diodes have become an important part of modern power electronic systems due to their advantages such as low voltage drop and fast switching speed. In order to meet the application of consumer electronics, high-frequency communications and other fields, higher requirements are put forward for traditional Schottky diodes in high-voltage and high-power application scenarios, and the performance limitations of the devices are becoming more and more prominent.

[0005] When traditional GaN Schottky diodes operate under high reverse bias, the high resistivity and high Schottky barrier of the material are the main limiting factors that significantly increase the on-state voltage drop and reduce the switching speed of the device. At the same time, the high surface electric field in the Schottky contact area causes a tunneling effect at the device contact interface, which significantly increases the reverse leakage current of the device. The introduction of GaN vertical trench Schottky barrier (TMBS) diodes can greatly improve the significant problems of traditional GaN Schottky diodes, such as large reverse leakage and premature breakdown of the device caused by local electric field concentration. Using a metal oxide semiconductor (MOS) structure to shield part of the Schottky surface high electric field can better alleviate the problem of reduced Schottky barrier height caused by image force, thereby reducing the reverse leakage current of the device. Although the performance of GaN vertical trench Schottky barrier (TMBS) diodes is greatly improved compared to traditional planar Schottky barrier diodes, due to the introduction of the trench structure on the surface of the Schottky contact area, there will be a strong local electric field concentration effect at the corner of the bottom of the trench (the corner of the bottom of the trench where the oxide layer contacts the GaN), which will limit and reduce the reverse voltage withstand capability of the vertical trench Schottky barrier diode.

[0006] The present invention is proposed to solve the above-mentioned problems. Summary of the invention

[0007] In view of the shortcomings of the prior art, the present invention provides a vertical III-nitride power semiconductor device with a core-shell structure and a method for preparing the same. The present invention adds a core-shell structure at the bottom of the groove of the device to maximize the device's forward on-resistance while significantly improving the breakdown characteristics. The structural design of the present invention can essentially solve the problem of electric field concentration near the heterojunction, thereby improving the reverse withstand voltage capability of the device. At the same time, there is no obvious decay in the forward on-resistance of the device, further demonstrating the great prospect of commercial application of vertical power devices in the field of high-frequency and high-power devices.

[0008] The technical solution of the present invention is as follows:

[0009] A vertical III-group nitride power semiconductor device with a core-shell structure, comprising:

[0010] N-type gallium nitride substrate layer;

[0011] An N-type GaN drift layer located above the N-type GaN substrate layer;

[0012] A groove is provided on the N-type gallium nitride drift layer; an N-type gallium nitride ring is provided on the bottom surface and sidewall of the groove, a P-type gallium nitride region is provided above the N-type gallium nitride ring, and the N-type gallium nitride ring and the P-type gallium nitride region form a core-shell structure;

[0013] An oxide layer is provided on the outer surface of the P-type gallium nitride region, the exposed surface of the N-type gallium nitride ring, and the exposed surface of the inner wall of the groove;

[0014] Metal electrode layer.

[0015] Preferably, according to the present invention, the N-type gallium nitride ring is composed of a bottom layer and a side wall, the bottom layer and the side wall are vertically connected, the bottom layer covers the bottom surface of the groove and has the same area as the bottom surface of the groove, and the side wall is arranged on the side wall of the groove; the thickness of the bottom layer is 0.02-2 μm; the thickness of the side wall is 0.02-1 μm, preferably 0.1-0.3 μm; the height of the side wall is 0.05-2 μm, preferably 1.5-2 μm; the doping element of the N-type gallium nitride ring is silicon, and the doping concentration is 1e14-5e20 cm -3 , the preferred doping concentration is 1e16-2e17cm -3 , and the doping concentration is preferably 1e17-2e17 cm -3 The height of the N-type GaN ring sidewall is the sum of the thickness of the N-type GaN ring bottom layer and the height of the N-type GaN ring sidewall covering the trench sidewall.

[0016] Preferably, according to the present invention, the P-type gallium nitride region is arranged above the N-type gallium nitride ring bottom layer and covers the bottom layer; the thickness of the P-type gallium nitride region is 0.02-2 μm; the doping element of the P-type gallium nitride region is magnesium ion, and the doping concentration is 1e15-1e20 cm -3 The preferred doping concentration range is 7e17-3e18 cm -3 .

[0017] Preferably according to the present invention, the semiconductor device may further include a P-type gallium nitride layer, an N-type gallium nitride layer, and an N-type gallium nitride highly doped layer; an oxide layer is further provided on the upper surface of the N-type gallium nitride highly doped layer.

[0018] Preferably according to the present invention, the depth and height of the groove may be in accordance with the prior art.

[0019] According to the preferred embodiment of the present invention, the oxide layer is selected from silicon oxide (SiO X ), Silicon Nitride (SiN x ), hafnium oxide (HfO2), aluminum oxide (Al2O3) or high-K dielectric layer; silicon oxide (SiO X ) is preferably SiO2, silicon nitride (SiN x ) is preferably Si3N4.

[0020] Preferably according to the present invention, the metal electrode layer is selected from one or a combination of two or more metal materials of chromium (Cr), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium (Ti), gold (Au), nickel (Ni), platinum (Pt), vanadium (V), copper (Cu), ruthenium (Ru), cobalt (Co) or hafnium (Hf).

[0021] Preferably according to the present invention, the semiconductor device is a vertical trench Schottky barrier diode (TMBS), which is provided with a metal electrode layer, an N-type gallium nitride substrate layer, and an N-type gallium nitride drift layer in sequence from bottom to top, a groove is provided on the N-type gallium nitride drift layer and does not pass through the N-type gallium nitride drift layer, an N-type gallium nitride ring is provided on the bottom surface and sidewall of the groove, a P-type gallium nitride region is provided above the N-type gallium nitride ring, and the N-type gallium nitride ring and the P-type gallium nitride region form a shell-core structure; a silicon dioxide layer (oxide layer) is provided on the outer surface of the P-type gallium nitride region, an exposed surface of the N-type gallium nitride ring, and an exposed surface of the inner wall of the groove, and a metal electrode layer is provided on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer.

[0022] Preferably, the N-type gallium nitride substrate layer is a heavily doped N-type gallium nitride substrate layer with a thickness of 1-3 μm, a doping element of silicon, and a doping concentration of 4e18-6e18 cm -3 The N-type GaN drift layer is a lightly doped N-type GaN drift layer with a thickness of 8-10 μm, a doping element of silicon, and a doping concentration of 5e14-3e16 cm -3 ; The thickness of the silicon dioxide layer is 180-220nm; the metal electrode layer arranged on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer is a metal combination of Pt and Au, with a thickness of 120-160nm, and forms a Schottky contact with the N-type gallium nitride drift layer; the metal electrode layer arranged on the lower surface of the N-type gallium nitride substrate layer is selected from one or a combination of two or more materials selected from chromium (Cr), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium (Ti) or gold (Au), with a thickness of 280-320nm, and forms an ohmic contact with the N-type gallium nitride substrate layer.

[0023] Preferably, according to the present invention, the semiconductor device is a vertical trench metal oxide semiconductor field effect transistor (T-MOSFET), which is provided with a metal electrode layer (drain), an N-type gallium nitride substrate layer, an N-type gallium nitride drift layer, a P-type gallium nitride layer, an N-type gallium nitride layer, and an N-type gallium nitride high-doping layer in sequence from bottom to top; a trench is provided on the N-type gallium nitride high-doping layer, the bottom of the trench is sunken to the N-type gallium nitride drift layer and does not pass through the N-type gallium nitride drift layer; an N-type gallium nitride ring is provided on the bottom surface and sidewall of the trench, and a N-type gallium nitride ring is provided above the N-type gallium nitride ring. There is a P-type gallium nitride region, and the N-type gallium nitride ring and the P-type gallium nitride region form a core-shell structure; a silicon dioxide layer (oxide layer) is provided on the outer surface of the P-type gallium nitride region, the exposed surface of the N-type gallium nitride ring, and the exposed surface of the inner wall of the groove; a metal electrode layer (gate) is provided on the surface of the silicon dioxide layer, and the metal electrode (gate) is in contact with the N-type gallium nitride high-doping layer; a silicon dioxide layer (oxide layer) is provided on the upper surface of the N-type gallium nitride high-doping layer, and the metal electrode layer (source) passes through the silicon dioxide layer on the N-type gallium nitride high-doping layer and is in contact with the N-type gallium nitride high-doping layer.

[0024] Preferably, the metal electrode layer (drain) is a Cr / Au mixed metal with a thickness of 50 / 250nm respectively; the N-type gallium nitride substrate layer is a heavily doped N-type gallium nitride substrate layer with a thickness of 1-3μm, the doping element is silicon, and the doping concentration is 4e18-6e18cm -3 ; The N-type GaN drift layer is a lightly doped N-type GaN drift layer with a thickness of 2-10 μm, the doping element is silicon, and the doping concentration is 1e16-3e16 cm -3 The thickness of the P-type GaN layer is 330-370nm, the doping ions are magnesium ions, and the doping concentration is 2e19-6e19 cm -3 The thickness of the N-type GaN layer is 180-220nm, the doping element is silicon, and the doping concentration is 3e18-7e18 cm -3 ; N-type GaN highly doped layer, thickness is 18-22nm, doped element is silicon, doping concentration is 1e19-5e19 cm -3 ; The thickness of the silicon dioxide layer set on the outer surface of the P-type gallium nitride region, the exposed surface of the N-type gallium nitride ring and the exposed surface of the inner wall of the groove is 180-220nm; the metal electrode layer (gate) is a mixed metal of Cr / Au, with a thickness of 50 / 250nm respectively; the metal electrode layer (source) is a mixed metal of Cr / Au, with a thickness of 50 / 250nm respectively; the thickness of the silicon dioxide layer on the upper surface of the N-type gallium nitride high-doped layer is the same as the thickness of the metal electrode layer (gate) on the upper surface of the N-type gallium nitride high-doped layer.

[0025] The method for preparing the vertical III-type group III nitride power semiconductor device having a core-shell structure comprises the following steps:

[0026] (1) Preparing an N-type gallium nitride substrate layer using a MOCVD method;

[0027] (2) homoepitaxially growing an N-type GaN drift layer on an N-type GaN substrate layer using a MOCVD method;

[0028] (3) etching the groove area using a dry etching process; then performing damage treatment on the etched surface;

[0029] (4) using an ion implanter to perform Si ion implantation on the N-type GaN drift layer at the bottom of the groove area and in the direction of the sidewall to form an N-type GaN ring with a higher N-type doping concentration than the N-type GaN drift layer; then using an ion implanter to perform Mg ion implantation on the N-type GaN drift layer at the bottom of the groove area and above the N-type GaN ring to form a P-type GaN region; or, using an ion implanter to perform Si ion implantation on the N-type GaN drift layer at the bottom of the groove area and in the direction of the sidewall to form an N-type GaN ring with a higher N-type doping concentration than the N-type GaN drift layer; then using an MOCVD method to deposit a P-type GaN region at the bottom of the groove area and above the N-type GaN ring;

[0030] Then a rapid thermal annealing (PIA) process is performed;

[0031] (5) Preparing the oxide layer using plasma enhanced chemical vapor deposition (PECVD);

[0032] (6) The metal electrode layer is prepared using an electron beam evaporator.

[0033] Preferably, according to the present invention, between step (2) and step (3), the method further includes: using a MOCVD method to sequentially prepare a P-type gallium nitride layer, an N-type gallium nitride layer, and an N-type gallium nitride highly doped layer on the surface of the N-type gallium nitride drift layer from bottom to top.

[0034] Preferably, according to the present invention, in step (4), the rapid thermal annealing treatment is carried out in an atmosphere of a mixed gas of one or more of nitrogen, ammonia, argon or hydrogen in any ratio, the temperature range of the thermal annealing treatment is 400 to 1500° C., and the annealing time is 10 to 90 minutes, so as to increase the activation rate of Mg ions in gallium nitride.

[0035] The technical features and beneficial effects of the present invention are as follows:

[0036] 1. The present invention preferably utilizes ion implantation to dope silicon to form an N-type gallium nitride ring and utilizes Mg ion implantation to form a P-type gallium nitride region. The ion implantation process of the present invention achieves no obvious interface effect between the implanted layer and the substrate, has high bonding strength and good adhesion, and does not change the device's dimensions and surface finish. In addition, the method of the present invention is applicable to gallium nitride systems and has a simple process.

[0037] 2. The core-shell structure design of the present invention effectively solves the problem of electric field concentration at the corner of the oxide layer of the vertical structure electronic devices of group III nitride (including optoelectronic devices, radio frequency devices, power devices, etc.), thereby improving the reverse withstand voltage capability of the device, and at the same time, it can also maintain excellent performance of the forward on-resistance of the device. Among them, the P-type gallium nitride region can alleviate the electric field concentration effect at the bottom of the trench and improve the reverse withstand voltage capability of the device; the N-type gallium nitride ring can successfully reduce the resistance of the junction field effect transistor (JFET) formed between the P-type gallium nitride region and the lightly doped N-type gallium nitride drift layer, and provide an additional current path for the device in the forward conduction state, thereby reducing the forward on-resistance of the device; the combination of the two structures enables the device to achieve a significant improvement in the reverse withstand voltage characteristics of the device without significantly reducing the forward conduction characteristics.

[0038] 3. Use TCAD simulation to assist in analyzing and optimizing the relevant parameters of the N-type gallium nitride ring in the core-shell structure to achieve device performance optimization. With the help of TCAD simulation to assist in analyzing the device structure parameters, a lot of time and cost can be saved, and the preparation of subsequent process experiments can be better guided.

[0039] 4. By optimizing the relevant parameters of the N-type GaN ring in the core-shell structure (including the doping concentration of the N-type GaN ring, the width of the Figure 2 , 3 W in, height as Figure 2 , 3 H) in order to achieve the optimal electrical performance of III-nitride vertical trench Schottky barrier (TMBS) diodes or vertical trench metal oxide semiconductor field effect (T-MOSFET) transistors with embedded core-shell structures. Through a large number of numerical simulation analyses, a novel core-shell structure design is embedded in the gallium nitride vertical trench Schottky barrier (TMBS) diode, while maintaining the good forward conduction characteristics of the device, so that the reverse withstand voltage capability of the device is greatly improved, and the reverse leakage is further reduced, thereby improving the reliability of the device and achieving the purpose of reducing power consumption, further reducing the device size and process preparation cost. In the traditional semiconductor manufacturing process, it is feasible to carry out a double-layer ion implantation process in the core-shell structure region, and the difficulty and complexity of the process experiment are within a controllable range. Therefore, this embedded core-shell structure in the traditional gallium nitride vertical trench Schottky barrier (TMBS) diode and vertical trench metal oxide semiconductor field effect (T-MOSFET) transistor will be very promising for the application of gallium nitride vertical power electronic devices in high-frequency, high-voltage and high-power industrial electronic systems and power integrated modules in the future. It demonstrates the great potential of gallium nitride vertical electronic devices to break through the physical limits of traditional electronic devices and become an ideal new generation alternative product. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the process flow of using ion implantation to combine a P-type GaN region with an N-type GaN ring to form a core-shell GaN vertical trench Schottky barrier (TMBS) diode;

[0041] Figure 2 Schematic diagram of the structure of a vertical trench Schottky barrier (TMBS) diode with a core-shell structure in Example 1;

[0042] Figure 3 Schematic diagram of the structure of a vertical trench metal oxide semiconductor field effect transistor (T-MOSFET) with a core-shell structure in Example 2;

[0043] Figure 4 A schematic diagram of the structure of a conventional gallium nitride vertical trench Schottky barrier diode in Comparative Example 1;

[0044] Figure 5 A schematic diagram of the structure of a conventional gallium nitride vertical trench metal oxide semiconductor field effect transistor in comparative example 2;

[0045] 1 is a metal electrode layer a, 2 is an N-type gallium nitride substrate layer, 3 is an N-type gallium nitride drift layer, 4 is an N-type gallium nitride ring, 5 is a P-type gallium nitride region, 6 is a silicon dioxide layer, 7 is a metal electrode layer b, 8 is a P-type gallium nitride layer, 9 is an N-type gallium nitride layer, 10 is an N-type gallium nitride highly doped layer, 11 is a source electrode, and 12 is a gate electrode;

[0046] Figure 6 Graphs showing forward characteristics of the conventional gallium nitride vertical trench Schottky barrier diode in comparative example 1 and the gallium nitride vertical trench Schottky barrier diode with a core-shell structure in embodiment 1;

[0047] Figure 7 Graph showing reverse characteristic of the conventional gallium nitride vertical trench Schottky barrier diode in comparative example 1 and the gallium nitride vertical trench Schottky barrier diode with a core-shell structure in embodiment 1;

[0048] Figure 8 is a graph showing the relationship between the breakdown voltage and forward resistance of a GaN vertical trench Schottky barrier diode with a core-shell structure and the doping concentration of the N-type GaN ring;

[0049] Fig. 9 The relationship between the breakdown voltage and forward resistance of the GaN vertical trench Schottky barrier diode with a core-shell structure and the width (W) of the N-type GaN ring;

[0050] Fig.10Graph showing the relationship between the breakdown voltage and forward resistance of a GaN vertical trench Schottky barrier diode with a core-shell structure and the height (H) of the N-type GaN ring. DETAILED DESCRIPTION

[0051] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] The methods involved in the examples are all existing methods unless otherwise specified; the reagents and materials used are all commercially available unless otherwise specified.

[0053] Example 1

[0054] A vertical III-type nitride power semiconductor device with a core-shell structure, wherein the semiconductor device is a vertical trench Schottky barrier diode (TMBS), such as Figure 2 As shown, from bottom to top, an anode metal electrode layer a1, an N-type gallium nitride substrate layer 2, and an N-type gallium nitride drift layer 3 are sequentially arranged, and a groove (a rectangular parallelepiped groove with a depth of 2 μm and a width of 3 μm) is arranged on the N-type gallium nitride drift layer 3 and does not pass through the N-type gallium nitride drift layer 3. An N-type gallium nitride ring 4 is arranged on the bottom surface and sidewall of the groove, and the N-type gallium nitride ring 4 is composed of a bottom layer and a sidewall, and the bottom layer and the sidewall are vertically connected, the bottom layer covers the bottom surface of the groove and has the same area as the bottom surface of the groove, and the sidewall is arranged on the sidewall of the groove; the thickness of the bottom layer is 0.1 μm, and the thickness of the sidewall (as shown in FIG. Figure 2 , W) is 0.3μm, and the height of the side wall (as shown Figure 2 , H) is 0.3μm. The doping element is silicon, and the doping concentration is 1e17 cm -3 The P-type gallium nitride region 5 is disposed above the bottom layer of the N-type gallium nitride ring 4 and covers the bottom layer; the thickness of the P-type gallium nitride region 5 is 0.2 μm, the doping element is magnesium, and the doping concentration is 8e17 cm -3 The N-type gallium nitride ring 4 and the P-type gallium nitride region 5 form a core-shell structure. The outer surface of the P-type gallium nitride region 5 and the exposed surface of the inner wall of the groove are provided with a silicon dioxide layer 6, and the surface of the silicon dioxide layer 6 and the upper surface of the N-type gallium nitride drift layer 3 are provided with a cathode metal electrode layer b7.

[0055] The N-type GaN substrate layer is a heavily doped N-type GaN substrate layer with a thickness of 2 μm, a doping element of silicon, and a doping concentration of 5e18 cm -3 ; The N-type GaN drift layer is a lightly doped N-type GaN drift layer with a thickness of 9 μm, a doping element of silicon, and a doping concentration of 2e16 cm -3The thickness of the silicon dioxide layer is 200nm; the anode metal electrode layer arranged on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer is a metal combination of Pt and Au, with a thickness of 150nm, which forms a Schottky contact with the N-type gallium nitride drift layer; the cathode metal electrode layer arranged on the lower surface of the N-type gallium nitride substrate layer is a metal combination of Cr and Au, with a thickness of 300nm, which forms an ohmic contact with the N-type gallium nitride substrate layer.

[0056] The width of the recessed terraces on both sides of the vertical trench Schottky barrier diode (TMBS) is half of the width of the complete trench, and the width of the recessed terraces is 1.5 μm.

[0057] The method for preparing the vertical III-type group III nitride power semiconductor device having a core-shell structure is as follows: Figure 1 As shown, the steps include:

[0058] (1) Using trimethylammonium (TMGa) and ammonia (NH3) as Ga and N sources, SiH3CH3 as N-type impurity source, and H2 as carrier gas, a heavily doped N-type GaN substrate layer was achieved in MOCVD;

[0059] (2) Using trimethylammonium (TMGa) and ammonia (NH3) as Ga source and N source, SiH3CH3 as N-type impurity source, and H2 as carrier gas, a lightly doped N-type GaN drift layer is homoepitaxially grown on the surface of the heavily doped N-type GaN substrate layer.

[0060] (3) Using SiO2 as a hard mask on the epitaxial wafer, ICP dry etching was performed to form a groove area. The etching atmosphere was a mixed gas composed of Cl2 / BCl3 / Ar. The etching depth was 2 μm and the width was 3 μm. The surface was etched with TMAH solution for damage treatment.

[0061] (4) using an ion implanter to implant Si ions into the N-type GaN drift layer at the bottom of the groove area and in the direction of the sidewall, to form an N-type GaN ring having a higher N-type doping concentration than the N-type GaN drift layer; then using the ion implanter to implant Mg ions into the N-type GaN drift layer at the bottom of the groove area and above the N-type GaN ring to form a P-type GaN region; and then performing a rapid thermal annealing (PIA) process; the rapid thermal annealing process is performed in a nitrogen atmosphere, the temperature range of the thermal annealing process is 450° C., and the annealing time is 20 minutes, so as to increase the activation rate of Mg ions in GaN, that is, to obtain a P-type GaN region, and the N-type GaN ring is combined with the P-type GaN region to form a core-shell structure region at the bottom of the groove.

[0062] (6) Plasma enhanced chemical vapor deposition (PECVD) was used to deposit hydrogen-diluted silane (S iH4) and oxygen (O2) are used as chamber reaction gases to deposit a silicon dioxide film on the outer surface of the P-type gallium nitride region and the exposed surface of the inner wall of the trench.

[0063] (7) Finally, an electron beam evaporator is used to deposit an anode metal electrode layer on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer to form a Schottky contact with the N-type gallium nitride drift layer; and a cathode metal electrode layer is deposited on the lower surface of the substrate to form an ohmic contact with the heavily doped N-type gallium nitride substrate layer.

[0064] Example 2

[0065] A vertical III-nitride power semiconductor device with a core-shell structure, wherein the semiconductor device is a vertical trench metal oxide semiconductor field effect transistor (T-MOSFET), such as Figure 3 As shown, from bottom to top, a metal electrode layer (drain) 1, an N-type gallium nitride substrate layer 2, an N-type gallium nitride drift layer 3, a P-type gallium nitride layer 8, an N-type gallium nitride layer 9, and an N-type gallium nitride high-doping layer 10 are sequentially arranged; a groove (a rectangular parallelepiped groove with a depth of 2 μm and a width of 4 μm) is arranged on the N-type gallium nitride high-doping layer 10, and the bottom of the groove is sunken to the N-type gallium nitride drift layer 3 and does not pass through the N-type gallium nitride drift layer 3. An N-type gallium nitride ring 4 is arranged on the bottom surface and sidewalls of the groove, and the N-type gallium nitride ring 4 consists of a bottom layer and a sidewall, the bottom layer and the sidewall are vertically connected, the bottom layer covers the bottom surface of the groove and has the same area as the bottom surface of the groove, and the sidewall is arranged on the sidewall of the groove; the thickness of the bottom layer is 0.1 μm, and the thickness of the sidewall (such as Figure 3 , W) is 0.3μm, and the height of the side wall (as shown Figure 3 , H) is 0.3μm. The doping element is silicon, and the doping concentration is 1e17 cm -3 The P-type gallium nitride region 5 is disposed above the bottom layer of the N-type gallium nitride ring 4 and covers the bottom layer; the thickness of the P-type gallium nitride region 5 is 0.2 μm, the doping element is magnesium, and the doping concentration is 8e17 cm -3 The N-type gallium nitride ring 4 and the P-type gallium nitride region 5 form a core-shell structure. A silicon dioxide layer 6 (oxide layer) is provided on the outer surface of the P-type gallium nitride region 5 and the exposed surface of the inner wall of the groove, and a metal electrode layer 12 (gate) is provided on the surface of the silicon dioxide layer 6. The metal electrode 12 (gate) is in contact with the N-type gallium nitride high-doped layer 10; a silicon dioxide layer 6 (oxide layer) is provided on the upper surface of the N-type gallium nitride high-doped layer 10, and the metal electrode layer 11 (source) passes through the silicon dioxide layer 6 on the N-type gallium nitride high-doped layer 10 and contacts with the N-type gallium nitride high-doped layer 10.

[0066] The metal electrode layer (drain) is a Cr / Au mixed metal with a thickness of 50 / 250nm respectively; the N-type gallium nitride substrate layer is a heavily doped N-type gallium nitride substrate layer with a thickness of 2μm, the doping element is silicon, and the doping concentration is 5e18 cm-3 ; The N-type GaN drift layer is a lightly doped N-type GaN drift layer with a thickness of 5 μm, a doping element of silicon, and a doping concentration of 2e16 cm -3 The thickness of the P-type GaN layer is 350nm, the doping ions are magnesium ions, and the doping concentration is 2e19cm -3 The thickness of the N-type GaN layer is 200nm, the doping element is silicon, and the doping concentration is 5e18cm -3 ; N-type GaN high-doped layer, thickness 20nm, doped element is silicon, doping concentration is 1e19 cm -3 ; The thickness of the silicon dioxide layer set on the outer surface of the P-type gallium nitride area and the exposed surface of the inner wall of the groove is 200nm; the metal electrode layer (gate) is a mixed metal of Cr / Au, with a thickness of 50 / 250nm respectively; the metal electrode layer (source) is a mixed metal of Cr / Au, with a thickness of 50 / 250nm respectively; the thickness of the silicon dioxide layer on the upper surface of the N-type gallium nitride high-doped layer is the same as the thickness of the metal electrode layer (gate) on the upper surface of the N-type gallium nitride high-doped layer.

[0067] The method for preparing the vertical III-type group III nitride power semiconductor device having a core-shell structure comprises the following steps:

[0068] (1) Using trimethylammonium (TMGa) and ammonia (NH3) as Ga and N sources, SiH3CH3 as N-type impurity source, and H2 as carrier gas, an N-type GaN substrate layer is realized in MOCVD;

[0069] (2) Using trimethylammonium (TMGa) and ammonia (NH3) as Ga source and N source, SiH3CH3 as N-type impurity source, and H2 as carrier gas, an N-type GaN drift layer is homoepitaxially grown on the surface of the N-type heavily doped GaN substrate layer.

[0070] (3) using trimethylammonium (TMGa) and ammonia (NH3) as Ga source and N source, SiH3CH3 as N-type impurity source, and H2 as carrier gas, a P-type GaN layer is homoepitaxially grown on the surface of the N-type GaN drift layer;

[0071] (4) using trimethylammonium (TMGa) and ammonia (NH3) as Ga source and N source, SiH3CH3 as N-type impurity source, and H2 as carrier gas, to homoepitaxially grow an N-type GaN layer on the surface of the P-type GaN layer;

[0072] (5) using trimethylammonium (TMGa) and ammonia (NH3) as Ga source and N source, SiH3CH3 as N-type impurity source, and H2 as carrier gas, to homoepitaxially grow an N-type GaN high-doped layer on the surface of the N-type GaN layer;

[0073] (6) Using SiO2 as a hard mask on the epitaxial wafer, ICP dry etching is performed to form a groove area. The etching atmosphere is Cl2 / BCl 3 / A mixed gas composed of Ar was used to etch a rectangular groove with a depth of 2 μm and a width of 4 μm, and then TMAH solution was used to perform surface etching damage treatment;

[0074] (7) using an ion implanter to implant Si ions into the N-type GaN drift layer at the bottom of the groove area and in the direction of the sidewall, to form an N-type GaN ring having a higher N-type doping concentration than the N-type GaN drift layer; then using the ion implanter to implant Mg ions into the N-type GaN drift layer at the bottom of the groove area and above the N-type GaN ring to form a P-type GaN region; and then performing a rapid thermal annealing (PIA) process; the rapid thermal annealing process is performed in a nitrogen atmosphere, the temperature range of the thermal annealing process is 450° C., and the annealing time is 20 minutes, so as to increase the activation rate of Mg ions in GaN, that is, to obtain a P-type GaN region, and the N-type GaN ring is combined with the P-type GaN region to form a core-shell structure region at the bottom of the groove.

[0075] (8) Plasma enhanced chemical vapor deposition (PECVD) is used to deposit a silicon dioxide film on the outer surface of the P-type gallium nitride region, the exposed surface of the inner wall of the trench, and the upper surface of the N-type gallium nitride highly doped layer using hydrogen-diluted silane (SiH4) and oxygen (O2) as chamber reaction gases.

[0076] (9) Using an electron beam evaporator, a gate electrode is deposited on the surface of the silicon dioxide layer in the groove area. Through holes are dry-etched on the silicon dioxide on the N-type gallium nitride highly doped layer, and a source electrode is evaporated using an electron beam evaporator. A drain electrode is evaporated at the bottom of the N-type gallium nitride substrate layer.

[0077] Comparative Example 1

[0078] A conventional vertical trench Schottky barrier diode (TMBS) having a structure such as Figure 4 As shown, as described in Example 1, the difference is that the N-type gallium nitride ring 4 and the P-type gallium nitride region 5 and the formed core-shell structure are omitted, and the other structures are consistent with Example 1.

[0079] The preparation method is the same as that of Example 1, except that step (4) is omitted, that is, ion implantation is not performed, and a layer of silicon dioxide film is directly deposited on the bottom surface of the groove and the inner side wall of the groove; the other steps and conditions are the same as those of Example 1.

[0080] Comparative Example 2

[0081] A vertical trench metal oxide semiconductor field effect transistor (T-MOSFET) having a structure as Figure 5As shown, as described in Example 2, the difference is that the N-type gallium nitride ring 4 and the P-type gallium nitride region 5 and the formed core-shell structure are omitted, and the other structures are consistent with Example 2.

[0082] The preparation method is the same as that of Example 2, except that step (7) is omitted, that is, ion implantation is not performed, and a layer of silicon dioxide film is directly deposited on the bottom surface of the groove and the inner side wall of the groove; the other steps and conditions are the same as those of Example 2.

[0083] Test Example 1

[0084] The forward and reverse characteristics of the gallium nitride vertical trench Schottky barrier diodes prepared in Example 1 and Comparative Example 1 were tested, and the test results are as follows: Figure 6 and 7 As shown, the TMBS marked in the figure is the traditional vertical trench Schottky barrier diode described in Comparative Example 1, and the C / S-TMBS is the vertical Schottky barrier diode with a core-shell structure described in Example 1.

[0085] As can be seen from the figure, the forward characteristics of the device with a core-shell structure of the present invention do not have an obvious decay phenomenon, and the reverse withstand voltage characteristics are greatly improved.

[0086] Test Example 2

[0087] The doping concentration of the N-type GaN ring in the vertical trench Schottky barrier diode (TMBS) in the modified embodiment 1 (varying in the range of 1e16-7e17 cm -3 ), other structures, parameters and preparation methods remain unchanged; the relationship between the reverse breakdown voltage and forward on-resistance of the device and the doping concentration of the N-type GaN ring is obtained by numerical simulation, such as Figure 8 shown.

[0088] From the analysis of the figure, we can see that when the doping concentration of N-type GaN ring is 1e16-2e17 cm -3 The device breakdown voltage is maintained at a high level, and the preferred concentration is 1e17-2e17 cm -3 range (optimal concentration is 2e17 cm -3 ) has a high breakdown voltage and a lower forward resistance.

[0089] Test Example 3

[0090] The width of the N-type GaN ring in the vertical trench Schottky barrier diode (TMBS) in the variation example 1 (i.e. Figure 2 The W in the figure varies from 0.1 to 1 μm, and the other structures, parameters and preparation methods remain unchanged. The relationship between the reverse breakdown voltage and forward on-resistance of the device and the width of the N-type GaN ring is obtained by numerical simulation, as shown in Fig. 9 as shown.

[0091] From the analysis of the figure, it can be seen that when the width of the N-type gallium nitride ring is 0.1-0.3μm, the device breakdown voltage is maintained at a high level. When the width is preferably 0.2μm, the device breakdown voltage is high and the forward on-resistance is lower.

[0092] Test Example 4

[0093] The height of the N-type GaN ring in the vertical trench Schottky barrier diode (TMBS) in the variation example 1 (i.e. Figure 2 The H in the figure varies from 0.05 to 2 μm), and the other structures, parameters and preparation methods remain unchanged. The relationship between the reverse breakdown voltage and forward on-resistance of the device and the height of the N-type gallium nitride ring is obtained by numerical simulation, as shown in FIG. Fig.10 as shown.

[0094] From the analysis of the figure, it can be seen that the device breakdown voltage is maintained at a high level when the height of the N-type gallium nitride ring is 0.05-2μm. When the width is preferably in the range of 1.5-2μm (the optimal height is 2μm), the device breakdown voltage is high and the forward on-resistance is lower.

Claims

1. A vertical III-nitride power semiconductor device with a core-shell structure, comprising: N-type gallium nitride substrate layer; An N-type GaN drift layer located above the N-type GaN substrate layer; A groove is provided on the N-type gallium nitride drift layer; An N-type gallium nitride ring is disposed on the bottom surface and sidewall of the groove, a P-type gallium nitride region is disposed above the N-type gallium nitride ring, and the N-type gallium nitride ring and the P-type gallium nitride region form a core-shell structure; The N-type GaN ring consists of a bottom layer and a side wall. The bottom layer and the side wall are vertically connected. The bottom layer covers the bottom surface of the groove and has the same area as the bottom surface of the groove. The side wall is set on the side wall of the groove. The thickness of the bottom layer is 0.02-2 μm; the thickness of the side wall is 0.1-0.3 μm; the height of the side wall is 1.5-2 μm; the doping element of the N-type GaN ring is silicon, and the doping concentration is 1e17-2e17 cm -3 ; The P-type GaN region is arranged above the N-type GaN ring bottom layer and covers the bottom layer; the thickness of the P-type GaN region is 0.02-2 μm; the doping element of the P-type GaN region is magnesium ion, and the doping concentration range is 8e17 cm -3 ; An oxide layer is provided on the outer surface of the P-type gallium nitride region, the exposed surface of the N-type gallium nitride ring, and the exposed surface of the inner wall of the groove; Metal electrode layer.

2. The vertical III-nitride power semiconductor device with a core-shell structure according to claim 1, characterized in that: The semiconductor device further comprises a P-type gallium nitride layer, an N-type gallium nitride layer, and an N-type gallium nitride highly doped layer; an oxide layer is also arranged on the upper surface of the N-type gallium nitride highly doped layer.

3. The vertical III-nitride power semiconductor device with a core-shell structure according to claim 1, characterized in that: The oxide layer is selected from silicon oxide (SiO X ), hafnium oxide (HfO2), aluminum oxide (Al2O3) or high-K dielectric layer.

4. The vertical III-nitride power semiconductor device with a core-shell structure according to claim 1, characterized in that: The metal electrode layer is selected from one or a combination of two or more metal materials of chromium (Cr), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium (Ti), gold (Au), nickel (Ni), platinum (Pt), vanadium (V), copper (Cu), ruthenium (Ru), cobalt (Co) or hafnium (Hf).

5. The vertical III-nitride power semiconductor device with a core-shell structure according to claim 1, characterized in that: The semiconductor device is a vertical trench Schottky barrier diode (TMBS), which is provided with an anode metal electrode layer, an N-type gallium nitride substrate layer, and an N-type gallium nitride drift layer in sequence from bottom to top, a groove is provided on the N-type gallium nitride drift layer and does not pass through the N-type gallium nitride drift layer, an N-type gallium nitride ring is provided on the bottom surface and sidewall of the groove, a P-type gallium nitride region is provided above the N-type gallium nitride ring, and the N-type gallium nitride ring and the P-type gallium nitride region form a shell-core structure; a silicon dioxide layer (oxide layer) is provided on the outer surface of the P-type gallium nitride region, the exposed surface of the N-type gallium nitride ring, and the exposed surface of the inner wall of the groove, and a cathode metal electrode layer is provided on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer.

6. The vertical III-nitride power semiconductor device with a core-shell structure according to claim 5, characterized in that: The N-type gallium nitride substrate layer is a heavily doped N-type gallium nitride substrate layer with a thickness of 1-3μm, a doping element of silicon, and a doping concentration of 4e18-6e18cm -3 The N-type GaN drift layer is a lightly doped N-type GaN drift layer with a thickness of 8-10 μm, a doping element of silicon, and a doping concentration of 5e14-3e16 cm -3 The thickness of the silicon dioxide layer is 180-220nm; the cathode metal electrode layer arranged on the surface of the silicon dioxide layer and the upper surface of the N-type gallium nitride drift layer is a metal combination of Pt and Au, with a thickness of 120-160nm, and forms a Schottky contact with the N-type gallium nitride drift layer; the anode metal electrode layer arranged on the lower surface of the N-type gallium nitride substrate layer is selected from one or a combination of two or more materials selected from chromium (Cr), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium (Ti) or gold (Au), with a thickness of 280-320nm, and forms an ohmic contact with the N-type gallium nitride substrate layer.

7. A method for preparing a vertical III-nitride power semiconductor device having a core-shell structure according to any one of claims 1 to 6, comprising the steps of: (1) Prepare N-type gallium nitride substrate layer using MOCVD method; (2) Homoepitaxially growing an N-type GaN drift layer on an N-type GaN substrate layer using a MOCVD method; (3) Etching the groove area using a dry etching process; then performing damage treatment on the etched surface; (4) using an ion implanter to perform Si ion implantation on the N-type GaN drift layer at the bottom of the trench area and in the direction of the sidewall to form an N-type GaN ring with a higher N-type doping concentration than the N-type GaN drift layer; then using an ion implanter to perform Mg ion implantation on the N-type GaN drift layer at the bottom of the trench area and above the N-type GaN ring to form a P-type GaN region; or, using an ion implanter to perform Si ion implantation on the N-type GaN drift layer at the bottom of the trench area and in the direction of the sidewall to form an N-type GaN ring with a higher N-type doping concentration than the N-type GaN drift layer; then using an MOCVD method to deposit a P-type GaN region at the bottom of the trench area and above the N-type GaN ring; Then rapid thermal annealing (PIA) is performed; (5) Preparation of oxide layer by plasma enhanced chemical vapor deposition (PECVD); (6) Prepare the metal electrode layer using an electron beam evaporator.

8. The method for preparing a vertical III-nitride power semiconductor device having a core-shell structure according to claim 7, characterized in that: Includes one or more of the following conditions: i. Between step (2) and step (3), the method further includes: using an MOCVD method to sequentially prepare a P-type gallium nitride layer, an N-type gallium nitride layer, and an N-type gallium nitride highly doped layer on the surface of the N-type gallium nitride drift layer from bottom to top; ii. In step (4), the rapid thermal annealing treatment is carried out in an atmosphere of one or a mixed gas of any ratio of nitrogen, ammonia, argon or hydrogen, the temperature range of the thermal annealing treatment is 400-1500° C., and the annealing time is 10-90 minutes.

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