Display device

Abstract

A display device includes a first display area, a second display area, and a non-display area disposed between the first display area and the second display area and extending in a first direction. The first display area extends in a horizontal direction, and the second display area extends in a vertical direction. At least a part of the non-display area forms a curved area that connects the first display area and the second display area to each other and is curved to have a curvature. The display device includes: light-emitting elements disposed on a base substrate in the first display area and the second display area; a first encapsulation layer covering the light-emitting elements disposed in the first display area; a second encapsulation layer covering the light-emitting elements disposed in the second display area; signal wirings intersecting the non-display area and extending in a second direction; and an upper compensation layer disposed in the non-display area and filling a gap between the first encapsulation layer and the second encapsulation layer.

Description

Technical Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device including a display area at a side surface of the display device. Background Art

[0002] Generally, a display device has a display area on a substrate. Recently, a display device having a display area extended to a side surface by bending a substrate is being developed.

[0003] However, stress applied to the bent area may cause damage to the display device and reduce durability. Summary of the Invention

[0004] Technical Problem to be Solved

[0005] An object of the present invention is to provide a display device having an extended display area and improved reliability.

[0006] However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0007] Technical Solution

[0008] To achieve the object of the present invention, a display device according to an embodiment of the present invention includes a first display area, a second display area, and a non-display area disposed between the first display area and the second display area and extending in a first direction. The first display area extends in a horizontal direction, and the second display area extends in a vertical direction. At least a part of the non-display area forms a bent area connecting the first display area and the second display area to each other and bent to have a curvature. The display device includes: a light-emitting element disposed on a base substrate in the first display area and the second display area; a first encapsulation layer covering the light-emitting element disposed in the first display area; a second encapsulation layer covering the light-emitting element disposed in the second display area; a signal wiring crossing the non-display area and extending in a second direction; and an upper compensation layer disposed in the non-display area and filling a gap between the first encapsulation layer and the second encapsulation layer.

[0009] In an embodiment, the display device further includes an organic protection pattern disposed under the upper compensation layer.

[0010] In an embodiment, the non-display area includes: a first non-display area where the organic protection pattern is disposed; and a second non-display area where the first encapsulation layer and the second encapsulation layer extending from the first display area and the second display area are in direct contact with an inorganic insulating layer disposed under the first encapsulation layer and the second encapsulation layer.

[0011] In an embodiment, the signal wiring includes: a first signal wiring pattern disposed under an inorganic insulating layer; a second signal wiring pattern spaced apart from the first signal wiring pattern in a second direction; and a bridging pattern disposed in a first non-display area and in electrical contact with the first signal wiring pattern and the second signal wiring pattern.

[0012] In an embodiment, the organic protection pattern includes a first organic pattern and a second organic pattern disposed on the first organic pattern. The bridging pattern is disposed between the first organic pattern and the second organic pattern.

[0013] In an embodiment, the display device further includes a power bus wiring disposed in a non-display area and extending in a first direction. The bridging pattern is disposed on the power bus wiring.

[0014] In an embodiment, the display device further includes a power bus wiring disposed in a non-display area and extending in a first direction. The bridging pattern is disposed under the power bus wiring.

[0015] In an embodiment, the bridging pattern is disposed under the organic protection pattern.

[0016] In an embodiment, the display device further includes a power bus wiring disposed in a non-display area and extending in a first direction.

[0017] In an embodiment, the power bus wiring is disposed under the organic protection pattern.

[0018] In an embodiment, the display device further includes a lower compensation layer disposed between a substrate and the organic protection pattern and including an organic material.

[0019] In an embodiment, the signal wiring extends over the lower compensation layer.

[0020] In an embodiment, the display device further includes: a touch sensing line extending in a first direction in a non-display area and disposed on an upper compensation layer; and a shielding pattern disposed between the upper compensation layer and the signal wiring.

[0021] In an embodiment, the shielding pattern and a lower electrode of a light-emitting element are disposed in the same layer.

[0022] In an embodiment, the display device further includes a power bus wiring disposed under the shielding pattern and extending in a first direction.

[0023] In an embodiment, the display device further includes a support film bonded to a lower surface of the substrate and having an opening overlapping a non-display area.

[0024] In an embodiment, the display device further includes a support film bonded to the lower surface of the base substrate. The support film includes a support portion overlapping the first display region and the second display region, and a bending portion overlapping the non-display region and including a material different from that of the support portion.

[0025] In an embodiment, the display device further includes a power wiring that intersects the non-display region and extends in a second direction.

[0026] In an embodiment, the power wiring includes: a first power wiring pattern extending in the second direction; a second power wiring pattern spaced apart from the first power wiring pattern; and a bridging pattern disposed in the non-display region and in electrical contact with the first power wiring pattern and the second power wiring pattern.

[0027] In an embodiment, the display device further includes a driving circuit disposed in the non-display region.

[0028] Advantageous Effects

[0029] According to an embodiment of the present invention, the bending region of the display device does not include a light-emitting element and a packaging layer. Therefore, the curvature of the display device can be reduced, especially the curvature of the inorganic layer that is weak in stress. Therefore, the reliability of the display device having a bending region can be improved.

[0030] In addition, a power bus wiring, a touch wiring, or a driving circuit can be formed in the non-display region. Therefore, the peripheral region where the power bus wiring, the touch wiring, or the driving circuit is disposed in a conventional display device can be reduced. Therefore, the bezel of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0032] Figure 2 is a side view showing a display device according to an embodiment of the present invention.

[0033] Figure 3 is a circuit diagram showing a pixel unit of a display device according to an embodiment of the present invention.

[0034] Figure 4 is a cross-sectional view showing a pixel unit disposed in a display region of a display device according to an embodiment of the present invention.

[0035] Figure 5 is Figure 1 an enlarged plan view of region “A” of

[0036] Figure 6 is Figure 5 a cross-sectional view taken along line I-I' of

[0037] Figures 7 to 10 is a cross-sectional view showing a display device according to an embodiment of the present invention.

[0038] Figure 11 is an enlarged plan view showing a bent region of a display device according to an embodiment of the present invention.

[0039] Figure 12 is along Figure 11 sectional view taken along line II-II'.

[0040] Figure 13 is an enlarged plan view showing a bent region of a display device according to an embodiment of the present invention.

[0041] Figure 14 is along Figure 13 sectional view taken along line III-III'.

[0042] Figure 15 is an enlarged plan view showing a bent region of a display device according to an embodiment of the present invention.

[0043] Figure 16 is along Figure 15 sectional view taken along line IV-IV'.

[0044] Figure 17 is along Figure 15 sectional view taken along line V-V'.

[0045] Figure 18 is a plan view showing a display device according to an embodiment of the present invention. Detailed Description

[0046] Hereinafter, a display device according to an embodiment will be described more fully with reference to the accompanying drawings in which some embodiments are shown. In the drawings, the same or similar reference numerals may be used for the same or similar elements.

[0047] Figure 1 is a plan view showing a display device according to an embodiment of the present invention. Figure 2 is a side view showing a display device according to an embodiment of the present invention.

[0048] Referring to Figure 1 and Figure 2 , a display device 10 according to an embodiment includes a first display area DA1 and a second display area DA2. In an embodiment, the display device 10 may be partially bent to have a side display area. For example, the first display area DA1 may correspond to a front display area, and the second display area DA2 may correspond to a side display area. For ease of explanation, Figure 1The display device 10 having a flat shape that is not bent is shown.

[0049] An array of pixel units PX including light-emitting elements is provided in each of the display regions DA1 and DA2 to generate light in response to a driving signal.

[0050] In an embodiment, in a side view, the first display region DA1 may extend in a direction parallel to the horizontal direction, and the second display region DA2 may extend in a direction parallel to the vertical direction.

[0051] In an embodiment, the display device 10 includes a non-display region NDA provided between the first display region DA1 and the second display region DA2. In an embodiment, at least a part of the non-display region NDA may be bent to have a curvature. Thus, the non-display region NDA may correspond to a bent region connecting the front display region and the side display region. Thus, the non-display region NDA may have a shape extending in a first direction D1 along the boundary between the first display region DA1 and the second display region DA2.

[0052] The non-display region NDA does not include a light-emitting element and a packaging layer. In addition, the inorganic insulating layer may be removed in the non-display region NDA. Thus, the curvature of the display device, particularly the curvature of the inorganic layer that is weak in stress, can be reduced. Thus, the reliability of the display device having a bent region can be improved.

[0053] In addition, signal wirings, power wirings, or driving circuits may be formed in the non-display region NDA. Thus, the peripheral region PA where signal wirings, power wirings, or driving circuits are provided in a conventional display device can be reduced. Thus, the bezel of the display device can be reduced.

[0054] The detailed configuration of the non-display region NDA will be described below.

[0055] Figure 3 It is a circuit diagram showing a pixel unit of a display device according to an embodiment of the present invention.

[0056] In an embodiment, the pixel unit of the display device may include a pixel circuit and a light-emitting element. For example, the pixel circuit may include an organic light-emitting diode OLED, first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, a wiring for a high power supply voltage ELVDD, a wiring for a low power supply voltage ELVSS, a wiring for an initialization voltage VINT, a wiring for a data signal DATA, a wiring for a gate signal GW, a wiring for a gate initialization signal GI, a wiring for a light emission control signal EM, a wiring for a diode initialization signal GB, etc.

[0057] An organic light emitting diode (OLED) can output light based on a driving current ID. The organic light emitting diode (OLED) can include a first terminal and a second terminal. In an embodiment, the second terminal of the organic light emitting diode (OLED) can receive a low power supply voltage ELVSS. For example, the first terminal of the organic light emitting diode (OLED) can be an anode terminal, and the second terminal of the organic light emitting diode (OLED) can be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode (OLED) can be a cathode terminal, and the second terminal of the organic light emitting diode (OLED) can be an anode terminal.

[0058] The first transistor TR1 can include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor TR1 can be a source terminal, and the second terminal of the first transistor TR1 can be a drain terminal. Alternatively, the first terminal of the first transistor TR1 can be a drain terminal, and the second terminal of the first transistor TR1 can be a source terminal.

[0059] The first transistor TR1 can generate the driving current ID. In an embodiment, the first transistor TR1 can operate in the saturation region. In this case, the first transistor TR1 can generate the driving current ID based on the voltage difference between the gate terminal and the source terminal. Additionally, the gray scale can be represented based on the magnitude of the driving current ID provided to the organic light emitting diode (OLED). Alternatively, the first transistor TR1 can operate in the linear region. In this case, the gray scale can be represented based on the sum of the times during which the driving current is provided to the organic light emitting diode (OLED) within one frame.

[0060] The second transistor TR2 can include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 can receive a gate signal GW. The first terminal of the second transistor TR2 can receive a data signal DATA. The second terminal of the second transistor TR2 can be connected to the first terminal of the first transistor TR1. For example, the gate signal GW can be provided from a gate driver, and the gate signal GW can be applied to the gate terminal of the second transistor TR2 through a gate signal wiring. In an embodiment, the first terminal of the second transistor TR2 can be a source terminal, and the second terminal of the second transistor TR2 can be a drain terminal. Alternatively, the first terminal of the second transistor TR2 can be a drain terminal, and the second terminal of the second transistor TR2 can be a source terminal.

[0061] The second transistor TR2 can provide the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 can operate in the linear region.

[0062] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 through a gate signal wiring. In an embodiment, the first terminal of the third transistor TR3 may be a source terminal, and the second terminal of the third transistor TR3 may be a drain terminal. Alternatively, the first terminal of the third transistor TR3 may be a drain terminal, and the second terminal of the third transistor TR3 may be a source terminal.

[0063] During an activation period of the gate signal GW, the third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1. In this case, the third transistor TR3 may operate in the linear region. That is, the third transistor TR3 may diode-connect the first transistor TR1 during the activation period of the gate signal GW. Since the first transistor TR1 is diode-connected, a voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 may be formed to be as large as the threshold voltage of the first transistor TR1. As a result, during the activation period of the gate signal GW, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA provided to the first terminal of the first transistor TR1 may be provided to the gate terminal of the first transistor TR1. That is, the data signal DATA may be compensated by the threshold voltage of the first transistor TR1, and the compensated data signal DATA may be provided to the gate terminal of the first transistor TR1. Since the threshold voltage compensation is performed, the problem of non-uniform drive current caused by the threshold voltage deviation of the first transistor TR1 may be solved.

[0064] An input terminal of a wiring for receiving an initialization voltage VINT may be connected to the first terminals of a fourth transistor TR4 and a seventh transistor TR7, and an output terminal of the wiring for the initialization voltage VINT may be connected to the second terminal of the fourth transistor TR4 and the first terminal of a storage capacitor CST.

[0065] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may receive a gate initialization signal GI. The first terminal of the fourth transistor TR4 may receive an initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an embodiment, the first terminal of the fourth transistor TR4 may be a source terminal, and the second terminal of the fourth transistor TR4 may be a drain terminal. Alternatively, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0066] During an activation period of the gate initialization signal GI, the fourth transistor TR4 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1. In this case, the fourth transistor TR4 may operate in the linear region. That is, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 which is a PMOS (P-channel metal oxide semiconductor) transistor.

[0067] In other embodiments, the initialization voltage may have a voltage level sufficiently higher than the voltage level of the data signal held by the storage capacitor in the previous frame, and the initialization voltage may be supplied to the gate terminal of the first transistor TR1 which is an NMOS (N-channel metal oxide semiconductor) transistor.

[0068] In an embodiment, the gate initialization signal GI may be a signal substantially the same as the gate signal GW transmitted one horizontal time before. For example, the gate initialization signal GI supplied to the pixel circuit in the nth row (where n is an integer greater than or equal to 2) among a plurality of pixel circuits included in the display device may be substantially the same as the gate signal GW supplied to the pixel circuit in the (n - 1)th row among the pixel circuits. That is, by supplying the activated gate signal GW to the first pixel circuit in the (n - 1)th row among the pixel circuits, the activated gate initialization signal GI may be supplied to the first pixel circuit in the nth row among the pixel circuits. As a result, while the gate terminal of the first transistor TR1 included in the pixel circuit in the nth row among the pixel circuits is initialized to the initialization voltage VINT, the data signal DATA may be supplied to the pixel circuit in the (n - 1)th row among the pixel circuits.

[0069] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a light emission control signal EM. The first terminal may be connected to a wiring for a high power supply voltage ELVDD. The second terminal may be connected to the first terminal of the first transistor TR1. For example, the light emission control signal EM may be provided from a light emission control driver, and the light emission control signal EM may be applied to the gate terminal of the fifth transistor TR5 through a wiring for the light emission control signal EM. In an embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. Alternatively, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0070] The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during an activation period of the light emission control signal EM. Conversely, the fifth transistor TR5 may turn off the supply of the high power supply voltage ELVDD during a deactivation period of the light emission control signal EM. In this case, the fifth transistor TR5 may operate in the linear region. The fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emission control signal EM so that the first transistor TR1 can generate a drive current ID. Additionally, the fifth transistor TR5 turns off the supply of the high power supply voltage ELVDD during the deactivation period of the light emission control signal EM so that a data signal DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0071] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a light emission control signal EM. The first terminal may be connected to the second terminal of the first transistor TR1. The second terminal may be connected to the first terminal of the organic light emitting diode OLED. For example, the light emission control signal EM may be provided from a light emission control driver, and the light emission control signal EM may be applied to the gate terminal of the sixth transistor TR6 through a wiring for the light emission control signal EM. In an embodiment, the first terminal of the sixth transistor TR6 may be a source terminal, and the second terminal of the sixth transistor TR6 may be a drain terminal. Alternatively, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0072] The sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emission control signal EM. In this case, the sixth transistor TR6 can operate in the linear region. That is, the sixth transistor TR6 supplies the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emission control signal EM so that the organic light emitting diode OLED can output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 from the organic light emitting diode OLED during the deactivation period of the light emission control signal EM so that the data signal DATA supplied to the second terminal of the first transistor TR1 (more precisely, the data signal compensated by the threshold voltage compensation) can be supplied to the gate terminal of the first transistor TR1.

[0073] The seventh transistor TR7 can include a gate terminal, a first terminal, and a second terminal. The gate terminal can receive a diode initialization signal GB. The first terminal can receive an initialization voltage VINT. The second terminal can be connected to the first terminal of the organic light emitting diode OLED. In an embodiment, the first terminal of the seventh transistor TR7 can be a source terminal, and the second terminal of the seventh transistor TR7 can be a drain terminal. Alternatively, the first terminal of the seventh transistor TR7 can be a drain terminal, and the second terminal of the seventh transistor TR7 can be a source terminal.

[0074] The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 can operate in the linear region. That is, the seventh transistor TR7 can initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0075] Alternatively, the gate initialization signal GI and the diode initialization signal GB can be substantially the same signal. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED can not affect each other. That is, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED can be independent of each other.

[0076] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between a wiring for a high power supply voltage ELVDD and a gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the wiring for the high power supply voltage ELVDD. The storage capacitor CST may hold the voltage level of the gate terminal of the first transistor TR1 during a deactivation period of the gate signal GW. The deactivation period of the gate signal GW may include an activation period of the light emission control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED during the activation period of the light emission control signal EM. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED based on the voltage level held by the storage capacitor CST.

[0077] However, embodiments of the present invention are not limited thereto. For example, the pixel circuit may have a configuration including at least one transistor and at least one storage capacitor.

[0078] Figure 4 is a cross-sectional view showing a pixel unit disposed in a display area of a display device according to an embodiment of the present invention.

[0079] Reference Figure 4 , the pixel unit PX disposed in the display area DA1 or DA2 may include a driving transistor disposed on a substrate 110, an organic light emitting diode 260 electrically connected to the driving transistor, and a package layer 210 covering the organic light emitting diode 260. A support film SF may be disposed on a lower surface of the substrate 110 to support the substrate 110.

[0080] A buffer layer 120 may be disposed on the substrate 110. A first active pattern AP1 may be disposed on the buffer layer 120.

[0081] For example, the substrate 110 may include glass, quartz, silicon, polymeric materials, etc. For example, the polymeric materials may include polyethylene terephthalate, polyethylene naphthalate, polyether ketone, polycarbonate, polyarylate, polyethersulfone, polyimide, etc.

[0082] The buffer layer 120 may prevent or reduce the penetration of impurities, moisture, or external gas from below the substrate 110, and may planarize the upper surface of the substrate 110. For example, the buffer layer 120 may include an inorganic material such as an oxide, a nitride, etc.

[0083] The first gate electrode GE1 may be disposed on the first active pattern AP1. The first insulating layer 130 may be disposed between the first active pattern AP1 and the first gate electrode GE1.

[0084] The gate wiring pattern GP may be disposed on the first gate electrode GE1. The gate wiring pattern GP may include a capacitor electrode for forming a capacitor, wirings for transmitting various signals, and the like.

[0085] The second insulating layer 140 may be disposed between the first gate electrode GE1 and the gate wiring pattern GP. The third insulating layer 150 may be disposed on the gate wiring pattern GP.

[0086] For example, the first active pattern AP1 may include silicon or a metal oxide semiconductor. In an embodiment, the first active pattern AP1 may include polysilicon that may be doped with n-type impurities or p-type impurities.

[0087] In another embodiment or another transistor not shown, the active pattern may include a metal oxide semiconductor. For example, the active pattern may include a binary compound (AB x ) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc., a ternary compound (AB x C y ) or a quaternary compound (AB x C y D z ). For example, the active pattern may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), etc.

[0088] The first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. In addition, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. For example, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may each have a single-layer structure or a multi-layer structure including silicon nitride and / or silicon oxide, or may have different structures from each other.

[0089] The first gate electrode GE1 and the gate wiring pattern GP may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the first gate electrode GE1 and the gate wiring pattern GP may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. In an embodiment, the first gate electrode GE1 and the gate wiring pattern GP may have a multi-layer structure including at least molybdenum.

[0090] The first source metal pattern may be disposed on the third insulating layer 150. The first source metal pattern may include a first source electrode SE1 and a first drain electrode DE1 that are in contact with the first active pattern AP1. The first source electrode SE1 and the first drain electrode DE1 may each pass through the insulating layer disposed thereunder to contact the first active pattern AP1.

[0091] The fourth insulating layer 160 may be disposed on the first source metal pattern. The second source metal pattern may be disposed on the fourth insulating layer 160. The second source metal pattern may include a connection electrode CE for electrically connecting the first drain electrode DE1 to the organic light-emitting diode 260 disposed thereon. In an embodiment, the second source metal pattern may further include a mesh power line for preventing a voltage drop of the power applied to the organic light-emitting diode 260. The fifth insulating layer 170 may be disposed on the second source metal pattern.

[0092] The first source metal pattern and the second source metal pattern may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, etc. For example, the first source metal pattern and the second source metal pattern may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. In an embodiment, the first source metal pattern and the second source metal pattern may have a multi-layer structure including at least aluminum. For example, the first source metal pattern and the second source metal pattern may have a stacked structure of an aluminum layer and a titanium layer.

[0093] The fourth insulating layer 160 and the fifth insulating layer 170 may include an organic material. For example, the fourth insulating layer 160 and the fifth insulating layer 170 may include an organic insulating material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, epoxy resin, etc.

[0094] The organic light-emitting diode 260 may be disposed on the fifth insulating layer 170. The organic light-emitting diode 260 may include a first electrode 262 in contact with the connection electrode CE, a light-emitting layer 264 disposed on the first electrode 262, and a second electrode 266 disposed on the light-emitting layer 264. The first electrode 262 may be the lower electrode of the organic light-emitting diode 260, and the second electrode 266 may be the upper electrode of the organic light-emitting diode 260.

[0095] The first electrode 262 may be used as an anode. For example, depending on the emission type of the display device, the first electrode 262 may be formed as a transmissive electrode or a reflective electrode. When the first electrode 262 is a transmissive electrode, the first electrode 262 may include indium tin oxide, indium zinc oxide, zinc oxide tin, indium oxide, zinc oxide, tin oxide, etc. When the first electrode 262 is a reflective electrode, the first electrode 262 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or a combination thereof, and may have a stacked structure further including a material that can be used for a transmissive electrode.

[0096] The pixel defining layer 180 has an opening exposing at least a portion of the first electrode 262. For example, the pixel defining layer 180 may include an organic insulating material.

[0097] The light-emitting layer 264 may have a single-layer structure or a multi-layer structure including at least one of a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. For example, the light-emitting layer 264 may include a low molecular weight organic compound or a high molecular weight organic compound.

[0098] In an embodiment, the light-emitting layer 264 may emit red, green, or blue light. In another embodiment, the light-emitting layer 264 may emit white light. The light-emitting layer 264 that emits white light may have a multi-layer structure including a red emission layer, a green emission layer, and a blue emission layer or a single-layer structure including a mixture of a red emission material, a green emission material, and a blue emission material.

[0099] Depending on the emission type of the display device, the second electrode 266 may be formed as a transmissive electrode or a reflective electrode. For example, the second electrode 266 may include a metal, a metal alloy, a metal nitride, a metal fluoride, a conductive metal oxide, or a combination thereof.

[0100] For example, the second electrode 266 may continuously extend across multiple pixel units in the display area. In an embodiment, a capping layer and a barrier layer may be further formed on the second electrode 266.

[0101] The encapsulation layer 210 is entirely disposed in the display areas DA1 and DA2 to cover the organic light-emitting diode 260.

[0102] For example, the encapsulation layer 210 may have a stacked structure of an inorganic thin film and an organic thin film. For example, as Figure 4 shown, the encapsulation layer 210 may include a first inorganic thin film 212, an organic thin film 214 disposed on the first inorganic thin film 212, and a second inorganic thin film 216 disposed on the organic thin film 214. However, the embodiments of the present invention are not limited thereto. For example, the encapsulation layer 210 may have a structure including at least two organic thin films and at least three inorganic thin films.

[0103] For example, the organic thin film 214 may include a cured polymer, such as polyacrylate or the like. For example, the cured polymer may be formed by a crosslinking reaction of monomers. For example, the inorganic thin films 212 and 216 may include inorganic materials, such as silicon oxide, silicon nitride, silicon carbide, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0104] The touch screen may be disposed on the encapsulation layer 210. For example, a touch sensing electrode TSE and a touch insulating layer 230 covering the touch sensing electrode TSE may be disposed on the encapsulation layer 210. For example, the touch sensing electrode TSE may include a transparent conductive material, such as indium tin oxide, indium zinc oxide, etc.

[0105] The polarization layer 240 and the protection window 250 may be disposed on the touch screen. An adhesive or a transparent adhesive film may be provided between the polarization layer 240 and the touch screen and between the polarization layer 240 and the protection window 250.

[0106] For ease of illustration, Figure 4 a transistor for transmitting power to the organic light-emitting diode is shown. As described above with reference to Figure 3 the pixel unit may include multiple transistors, and the transistors may include different channel materials or may be formed in different layers.

[0107] Figure 5 is an enlarged plan view showing Figure 1 the area “A”. Figure 6 is a cross-sectional view taken along the line I-I’ of Figure 5 the same.

[0108] Refer to Figure 5 and Figure 6, the non-display area includes a first non-display area NDA1 and a second non-display area NDA2. The second non-display area NDA2 is disposed between the first non-display area NDA1 and the display areas DA1 and DA2. For example, the first non-display area NDA1 may be defined by an area where the encapsulation layer 210 is not provided. The second non-display area NDA2 may be defined by an area where the organic insulating layer is removed between the first non-display area NDA1 and the display areas DA1 and DA2. Accordingly, the encapsulation layer 210 may be in direct contact with the inorganic insulating layer (e.g., the third insulating layer 150) under the encapsulation layer 210 in the second non-display area NDA2.

[0109] In the process of forming the encapsulation layer 210, the area where the organic insulating layer is removed can prevent monomers from overflowing into the first non-display area NDA1.

[0110] In an embodiment, the second non-display area NDA2 may be disposed in a flat area without curvature, such as the display areas DA1 and DA2. However, embodiments of the present invention are not limited thereto. The second non-display area NDA2 may be disposed in a curved area with curvature, such as the first non-display area NDA1.

[0111] In an embodiment, the non-display area may extend in a first direction D1 and may be adjacent to the display areas DA1 and DA2 in a second direction D2 perpendicular to the first direction D1.

[0112] Signal wirings and power wirings may be disposed in the display areas DA1 and DA2 and the non-display area. In an embodiment, the signal wirings may cross the non-display area and extend in the second direction D2 in the display areas DA1 and DA2.

[0113] The signal wirings may transmit various driving signals or driving voltages to pixel units in the display areas DA1 and DA2. For example, the signal wirings may include a plurality of signal wirings that respectively transmit different signals.

[0114] For example, the first signal wiring may include a first signal wiring pattern SL1 disposed in the first display area DA1 and extending in the second direction D2, a second signal wiring pattern SL1' disposed in the second display area DA2 and extending in the second direction D2, and a first bridging pattern BP1 that electrically connects the first signal wiring pattern SL1 to the second signal wiring pattern SL1'.

[0115] The second signal wiring may include a first signal wiring pattern SL2 disposed in the first display area DA1 and extending along a second direction D2, a second signal wiring pattern SL2' disposed in the second display area DA2 and extending along the second direction D2, and a second bridging pattern BP2 that electrically connects the first signal wiring pattern SL2 to the second signal wiring pattern SL2'.

[0116] The third signal wiring may include a first signal wiring pattern SL3 disposed in the first display area DA1 and extending along the second direction D2, a second signal wiring pattern SL3' disposed in the second display area DA2 and extending along the second direction D2, and a third bridging pattern BP3 that electrically connects the first signal wiring pattern SL3 to the second signal wiring pattern SL3'.

[0117] The first to third signal wirings may transmit Figure 3 the initialization voltage VINT, gate signal GW, gate initialization signal GI, emission control signal EM, diode initialization signal GB, etc. shown in. For example, the first signal wiring may transmit the gate signal GW, the second signal wiring may transmit the emission control signal EM, and the third signal wiring may transmit the initialization voltage VINT. However, the above combination is an exemplary embodiment. Embodiments of the present invention are not limited thereto, and various combinations may be possible.

[0118] In an embodiment, the display device includes a power bus wiring extending along a first direction D1 in a non-display area and a power wiring PL extending along a second direction D2 in the display areas DA1 and DA2 and the non-display area.

[0119] In an embodiment, the power bus wiring includes a first power bus wiring PBL1 and a second power bus wiring PBL2. The first power bus wiring PBL1 is electrically connected to the power wiring PL to supply a first power voltage to the power wiring PL. The first power voltage may be supplied to a driving transistor. The second power bus wiring PBL2 may transmit a second power voltage supplied to the cathode of the organic light emitting diode.

[0120] The power bus wiring and the power wiring PL may be disposed in different layers from each other. For example, the power bus wiring may be included in a first source metal pattern, and the power wiring PL may be included in a second source metal pattern.

[0121] In an embodiment, the encapsulation layer 210 and the inorganic layer are removed in a first non-display area NDA1 corresponding to the bending area. In addition, as the inorganic layer is removed, the gate metal pattern having low ductility is removed. Further, since light is not generated in the non-display area, the light-emitting element is not provided in the non-display area. Accordingly, since the inorganic layer, the common layer for the light-emitting element, and the gate metal pattern, which are weak against bending stress, are removed, it is possible to achieve the effect of substantially reducing the curvature of the bending area of the display device.

[0122] Reference Figure 6 , in at least a part of the first non-display area NDA1, the buffer layer 120, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150, which extend from the display area and include an inorganic material, are removed. The area from which the inorganic layer is removed may extend as the first non-display area NDA1 in a first direction D1.

[0123] The lower compensation layer 155 may be provided in the area from which the inorganic layer is removed. The lower compensation layer 155 may compensate for the height difference and may reduce the stress caused by bending. The lower compensation layer 155 may be in contact with the upper surface of the base substrate 110. For example, the lower compensation layer 155 may include an organic insulating material similar to the material for the fourth insulating layer 160 or the like.

[0124] In an embodiment, the lower compensation layer 155 may have a pattern shape that fills the area from which the inorganic layer is removed. However, embodiments of the present invention are not limited thereto. The lower compensation layer 155 may continuously extend in a horizontal direction to cover the upper surface of the third insulating layer 150.

[0125] The power bus wirings PBL1 and PBL2 may be provided on the lower compensation layer 155. The power bus wirings PBL1 and PBL2 may be included in the first source metal pattern and may be provided in the same layer as the first source electrode SE1 and the first drain electrode DE1 in the display area.

[0126] The first signal wiring pattern SL1 and the second signal wiring pattern SL1' of the first signal wiring may be formed of the same layer as the first gate electrode GE1. Accordingly, the first signal wiring pattern SL1 and the second signal wiring pattern SL1' of the first signal wiring may be provided between the first insulating layer 130 and the second insulating layer 140. However, embodiments of the present invention are not limited thereto. For example, the first signal wiring pattern SL1 and the second signal wiring pattern SL1' of the first signal wiring may be formed of the same layer as the gate wiring pattern GP.

[0127] The organic protection pattern is disposed in the first non-display area NDA1. The organic protection pattern can protect signal wirings, power wirings, power bus wirings, etc. Further, when forming the organic film 214 of the encapsulation layer, the organic protection pattern can be used as a dam to prevent monomers from overflowing into the first non-display area NDA1. The organic protection pattern can extend along the first direction D1 like the first non-display area NDA1.

[0128] For example, the organic protection pattern can include a first organic pattern 162, a second organic pattern 172 disposed on the first organic pattern 162, and a third organic pattern 182 disposed on the second organic pattern 172. The first organic pattern 162 can be formed of the same layer as the fourth insulating layer 160 in the display area, the second organic pattern 172 can be formed of the same layer as the fifth insulating layer 170 in the display area, and the third organic pattern 182 can be formed of the same layer as the pixel defining layer 180 in the display area. However, embodiments of the present invention are not limited to the above combinations. For example, the organic protection pattern can have a bilayer structure or a multilayer structure including at least four layers.

[0129] Reference Figure 6 , the first organic pattern 162 is disposed on the third insulating layer 150 and the lower compensation layer 155, and covers the power bus wirings PBL1 and PBL2.

[0130] The first bridging pattern BP1 is disposed on the first organic pattern 162. The first bridging pattern BP1 can be included in the second source metal pattern to be disposed in the same layer as the connection electrode CE in the display area. The first bridging pattern BP1 can pass through the first organic pattern 162 and the underlying inorganic layer to form electrical contact with the first signal wiring pattern SL1 and the second signal wiring pattern SL1' of the first signal wiring. The first signal wiring can cross the non-display area to extend from the first display area DA1 to the second display area DA2.

[0131] The upper compensation layer 220 can be disposed on the organic protection pattern. Since the encapsulation layer 210 is removed in the first non-display area NDA1, a height difference may be generated. The upper compensation layer 220 can compensate for the height difference and can reduce the stress caused by bending. Thus, the upper compensation layer 220 can fill the gap between the first encapsulation layer disposed in the first display area DA1 and the second encapsulation layer disposed in the second display area DA2. The first encapsulation layer is the portion of the encapsulation layer 210 disposed in the first display area, and the second encapsulation layer is the portion of the encapsulation layer 210 disposed in the second display area.

[0132] For example, the upper compensation layer 220 can be formed by coating or selectively dropping an organic material such as an adhesive resin or a curable monomer. For example, the upper compensation layer 220 can include a phenolic resin, an acrylic resin, a silicone resin, an epoxy resin, etc.

[0133] The touch insulation layer 230, the polarization layer 240, and the protection window 250 can be disposed on the upper compensation layer 220.

[0134] In an embodiment, the support film SF attached to the lower surface of the base substrate 110 can have an opening OP overlapping with the first non-display area NDA1. The opening OP can be defined by an area where the support film SF is removed. Thus, the stress caused by the support film SF can be reduced.

[0135] In addition, since the bridging pattern, the power bus wiring, the power wiring, etc. disposed in the non-display area are formed of a source metal pattern including aluminum having relatively high ductility, the reliability of the wiring can be improved.

[0136] Figures 7 to 10 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0137] Reference Figure 7 , a touch sensing line TL and a shielding pattern SP can be further disposed in the first non-display area NDA1 of the display device.

[0138] In an embodiment, the touch sensing line TL can be disposed on the upper compensation layer 220 and can extend in the first direction D1 in the first non-display area NDA1. The touch sensing line TL can be electrically connected to the touch sensing electrode TSE in the display area to provide the voltage required for sensing and transfer the capacitance change. For example, the touch sensing line TL can be formed of the same layer as the touch sensing electrode TSE.

[0139] The shielding pattern SP can be disposed between the touch sensing line TL and the signal wiring to prevent sensing noise caused by interference of the signal wiring.

[0140] In an embodiment, the shielding pattern SP can be disposed between the second organic pattern 172 and the third organic pattern 182. For example, the shielding pattern SP can be formed of the same layer as the first electrode 262 of the organic light emitting diode 260.

[0141] The touch sensing line TL and the shielding pattern SP can extend in the first direction D1 like the first non-display area NDA1.

[0142] Reference Figure 8, the power bus wirings PBL1 and PBL2 can be directly disposed on the upper surface of the substrate 110 in a region where the buffer layer 120, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 including inorganic materials are removed.

[0143] The first organic pattern 162 of the organic protection pattern can fill the region where the inorganic layer is removed and can cover the power bus wirings PBL1 and PBL2.

[0144] According to the above configuration, the lower compensation layer 155 shown in Figure 6 can be omitted, and the first organic pattern 162 can form a filling portion. Therefore, the process for manufacturing a display device can be simplified.

[0145] Referring to Figure 9 , the upper compensation layer 222 disposed on the organic protection pattern can extend in the horizontal direction to cover the upper surface of the encapsulation layer 210.

[0146] Referring to Figure 10 , the support film SF attached to the lower surface of the substrate 110 can include a support portion SA overlapping with the display region and a bending portion BA overlapping with the first non-display region NDA1. In an embodiment, the bending portion BA includes a material different from that of the support portion SA. The bending portion BA can include a material having greater flexibility or ductility than that of the support portion SA. For example, the support portion SA can include polyimide, polycarbonate, polyethylene terephthalate, polymethyl methacrylate, etc., and the bending portion BA can include polyurethane, etc.

[0147] Therefore, the stress in the bending region can be reduced.

[0148] Figure 11 is an enlarged plan view showing a bending region of a display device according to an embodiment of the present invention. Figure 12 is a cross-sectional view taken along line II-II' of Figure 11 .

[0149] Referring to Figure 11 and Figure 12 , the bridging patterns BP1, BP2, and BP3 for continuing the signal wiring can be disposed in the first non-display region NDA1. In addition, the power bus wirings PBL1 and PBL2 extending along the first direction D1 can be disposed in the first non-display region NDA1.

[0150] In an embodiment, the power wiring disposed in the display area and the power bus wirings PBL1 and PBL2 disposed in the first non-display area NDA1 may be disposed in the same layer. Accordingly, a bridging pattern BP4 may be disposed in the first non-display area NDA1 to connect a first power bus wiring pattern PL1 and a second power bus wiring pattern PL2 separated from each other through the first non-display area NDA1.

[0151] In an embodiment, the bridging patterns BP1, BP2, BP3, and BP4 may be disposed under the power bus wirings PBL1 and PBL2. For example, the bridging patterns BP1, BP2, BP3, and BP4 may be included in a first source metal pattern to be disposed in the same layer as the first source electrode SE1 and the first drain electrode DE1 in the display area. The power bus wirings PBL1 and PBL2 may be included in a second source metal pattern to be disposed in the same layer as the connection electrode CE in the display area.

[0152] For example, the bridging patterns BP1, BP2, BP3, and BP4 may be disposed between the organic protection pattern and the substrate 110. The lower compensation layer 155 may be disposed under the bridging patterns BP1, BP2, BP3, and BP4.

[0153] For example, the power bus wirings PBL1 and PBL2 may be disposed between a first organic pattern 162 and a second organic pattern 172 of the organic protection pattern.

[0154] Figure 13 is an enlarged plan view showing a bent area of a display device according to an embodiment of the present invention. Figure 14 is along Figure 13 a cross-sectional view taken along line III-III' of.

[0155] Referring to Figure 13 and Figure 14 for continuing the signal wiring, the bridging patterns BP1, BP2, and BP3 may be disposed in the first non-display area NDA1. In addition, a bridging pattern BP4 may be disposed in the first non-display area NDA1 to connect a power bus wiring pattern PL1 and a power bus wiring pattern PL2 separated from each other through the first non-display area NDA1.

[0156] A touch sensing line TL extending in a first direction D1 and a shielding pattern SP are disposed in the first non-display area NDA1.

[0157] The shielding pattern SP may be disposed between the touch sensing line TL and the signal wiring to prevent sensing noise caused by interference of the signal wiring.

[0158] In an embodiment, the bridging patterns BP1, BP2, BP3, and BP4 may be included in the first source metal pattern to be disposed in the same layer as the first source electrode SE1 and the first drain electrode DE1 in the display region. The shielding pattern SP may be included in the second source metal pattern to be disposed in the same layer as the connection electrode CE in the display region. Accordingly, the shielding pattern SP may be disposed between the second organic pattern 172 and the first organic pattern 162.

[0159] Figure 15 is an enlarged plan view showing a bent region of a display device according to an embodiment of the present invention. Figure 16 is along Figure 15 sectional view taken along line IV-IV'. Figure 17 is along Figure 15 sectional view taken along line V-V'.

[0160] Refer to Figure 15 and Figure 16 The driving circuit DC is disposed in the first non-display area NDA1. The driving circuit DC may generate driving signals. For example, the driving signals may include a gate signal, a light emission control signal, etc. For example, the driving circuit DC may supply the gate signal to the first signal wirings SL1 and SL1' and may supply the light emission control signal to the second signal wirings SL2 and SL2'.

[0161] The driving circuit DC may include transistors for generating driving signals. The transistors of the driving circuit DC may be formed together with the transistors in the display region. For example, as Figure 17 shown, the transistors of the driving circuit DC may include a second active pattern AP2 disposed on the buffer layer 120, a second gate electrode GE2 disposed on the first insulating layer 130 and overlapping with the second active pattern AP2, a second source electrode SE2 and a second drain electrode DE2 in contact with the second active pattern AP2.

[0162] The organic protection pattern and the upper compensation layer 220 may be disposed on the transistors of the driving circuit DC. In addition, the touch sensing line TL may be disposed on the upper compensation layer 220, and the shielding pattern SP may be disposed under the touch sensing line TL.

[0163] In an embodiment, the inorganic layers 120, 130, 140, and 150 are not removed but retained in the first non-display area NDA1 to form the driving circuit DC in the first non-display area NDA1. Accordingly, as Figure 16 shown, the wiring SL3 that does not receive driving signals from the driving circuit DC may pass through the first non-display area NDA1 without a bridging pattern.

[0164] In an embodiment, the driving circuit DC that generates a driving signal may be disposed in a non-display area of the bent area. Accordingly, the size of the peripheral area can be reduced. In addition, since the encapsulation layer is removed in the non-display area and the compensation layer is disposed in the non-display area, stress in the bent area can be reduced.

[0165] Figure 18 is a plan view showing a display device according to an embodiment of the present invention.

[0166] Reference Figure 18 , the display device 20 according to an embodiment of the present invention includes a first display area DA1 and a second display area DA2. In an embodiment, the display device 20 may be partially bent to have a side display area. For example, the first display area DA1 may correspond to a front display area, and the second display area DA2 may correspond to a side display area.

[0167] An array of pixel units PX including light-emitting elements is disposed in each of the display areas DA1 and DA2 to generate light in response to a driving signal.

[0168] In an embodiment, the display device 20 includes a non-display area NDA disposed between the first display area DA1 and the second display area DA2. In an embodiment, at least a portion of the non-display area NDA may be bent to have a curvature. Accordingly, the non-display area NDA may correspond to a bent area connecting the front display area and the side display area.

[0169] In an embodiment, the display device 20 may include four second display areas DA2 respectively corresponding to each side of the first display area DA1 having a rectangular shape. Accordingly, the display device 20 may include four non-display areas NDA.

[0170] Accordingly, the display device 20 may display an image on a front surface and four side surfaces.

[0171] The foregoing is an illustration of embodiments and should not be construed as a limitation thereof. Although some embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

[0172] Industrial Applicability

[0173] The present invention can be applied to various display devices. For example, the present invention can be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, and the like.

Claims

1. A display device, comprising a first display area, a second display area, and a non-display area disposed between the first display area and the second display area and extending in a first direction, wherein the first display area extends in a horizontal direction, the second display area extends in a vertical direction, at least a part of the non-display area forms a curved area that connects the first display area and the second display area to each other and is curved to have a curvature, and the display device includes: Light-emitting elements disposed on a base substrate in the first display area and the second display area; A first encapsulation layer covering the light-emitting elements disposed in the first display area; A second encapsulation layer covering the light-emitting elements disposed in the second display area; Signal wirings intersecting the non-display area and extending in a second direction; An upper compensation layer disposed in the non-display area and filling a gap between the first encapsulation layer and the second encapsulation layer; Touch sensing lines extending in the first direction in the non-display area and disposed on the upper compensation layer; And A shielding pattern disposed between the upper compensation layer and the signal wirings.

2. The display device according to claim 1, further comprising an organic protection pattern disposed under the upper compensation layer.

3. The display device according to claim 2, wherein, The non-display area includes: A first non-display area where the organic protection pattern is disposed; and A second non-display area where the first encapsulation layer and the second encapsulation layer extending from the first display area and the second display area are in direct contact with an inorganic insulating layer disposed under the first encapsulation layer and the second encapsulation layer.

4. The display device according to claim 3, wherein, The signal wirings include: A first signal wiring pattern disposed under the inorganic insulating layer; A second signal wiring pattern spaced apart from the first signal wiring pattern in the second direction; and A bridging pattern disposed in the first non-display area and in electrical contact with the first signal wiring pattern and the second signal wiring pattern.

5. The display device according to claim 4, wherein, The organic protection pattern includes a first organic pattern and a second organic pattern disposed on the first organic pattern, wherein the bridging pattern is disposed between the first organic pattern and the second organic pattern.

6. The display device according to claim 5, further comprising a power bus wiring disposed in the non-display area and extending in the first direction, wherein, The bridging pattern is disposed on the power bus wiring.

7. The display device according to claim 4, further comprising a power bus wiring disposed in the non-display area and extending in the first direction, wherein, The bridging pattern is disposed under the power bus wiring.

8. The display device according to claim 4, wherein, The bridging pattern is disposed under the organic protection pattern.

9. The display device according to claim 2, further comprising a power bus wiring disposed in the non-display area and extending in the first direction.

10. The display device according to claim 9, wherein, The power bus wiring is disposed under the organic protection pattern.

11. The display device according to claim 2, further comprising a lower compensation layer disposed between the base substrate and the organic protection pattern and including an organic material.

12. The display device according to claim 11, wherein, The signal wirings extend above the lower compensation layer.

13. The display device according to claim 1, wherein, The shielding pattern and the lower electrode of the light-emitting element are disposed in the same layer.

14. The display device according to claim 1, further comprising a power bus wiring disposed under the shielding pattern and extending in the first direction.

15. The display device according to claim 1, further comprising a support film bonded to a lower surface of the base substrate and having an opening overlapping the non-display area.

16. The display device according to claim 1, further comprising a support film bonded to a lower surface of the base substrate, wherein, The support film includes a support portion overlapping the first display area and the second display area, and a bending portion overlapping the non-display area and including a material different from that of the support portion.

17. The display device according to claim 1, further comprising a power wiring crossing the non-display area and extending in the second direction.

18. The display device according to claim 17, wherein, The power wiring includes: a first power wiring pattern extending in the second direction; a second power wiring pattern spaced apart from the first power wiring pattern; and a bridging pattern disposed in the non-display area and in electrical contact with the first power wiring pattern and the second power wiring pattern.

19. The display device according to any one of claims 1-2 and 13, further comprising a driving circuit disposed in the non-display area.

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