Neural network circuit

Abstract

The application provides a neural network circuit, comprising: a first computing circuit comprising at least two memory-computing unit cross arrays and at least one group of switch circuits; and a controller configured to control the at least one group of switch circuits, so that the first computing circuit implements at least two different circuit functions. The neural network circuit in the application implements at least two different circuit functions.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of neural networks, and more particularly, to a neural network circuit. BACKGROUND

[0002] Artificial intelligence (AI) is the theory, method, technology and application system that use digital computers or digital computer controlled machines to simulate, extend and expand human intelligence, perceive environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is the design principle and implementation method of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making. The research in the field of artificial intelligence includes robots, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, AI basic theory, etc.

[0003] Non-volatile memory crossbar (NVM crossbar) can be used as an accelerator of neural network due to its structure suitable for accelerating vector-matrix multiplication and low power consumption and area, and has wide prospects. NVM crossbar is actually an analog calculation, and other operations (storage, activation) in actual application need to be implemented by digital circuits. Therefore, some peripheral auxiliary circuits are needed as the interface between VMM and other digital circuits. The peripheral auxiliary circuits can include but are not limited to shift and add (S+A), intra-layer shift and add (intra-layer S+A), digital-to-analog converter (DAC), analog-to-digital converter (ADC).

[0004] In related technical solutions, on the one hand, due to the scale and structure of neural networks are different, the demand for computing resources is also different. If the hardware circuit needs to adapt to all the neural networks to be supported, it needs to be designed according to the largest scale, which will cause a great waste of design. On the other hand, the peripheral circuits in the traditional architecture are generally implemented by complementary metal oxide semiconductor (CMOS) circuits, and the power consumption ratio is large. SUMMARY

[0005] The neural network circuit can be configured according to different requirements, so that the neural network circuit implements at least two different circuit functions.

[0006] In a first aspect, a neural network circuit is provided, comprising: a first computing circuit comprising at least two memory-computing unit cross arrays and at least one group of switch circuits; and a controller configured to control the at least one group of switch circuits, so that the first computing circuit implements at least two different circuit functions.

[0007] In the above technical solution, the neural network circuit can be configured according to different requirements, so that the neural network circuit implements the functions of at least two different circuit modules. In this way, on the one hand, the waste of circuit design caused by the use of various special-purpose circuits can be avoided. On the other hand, some peripheral auxiliary circuits are implemented by the cross array, and since the cross array itself has the advantages of low power consumption and small area, the power consumption of the chip can also be reduced.

[0008] In a possible implementation manner of the first aspect, the first computing circuit implements at least two of the following circuit functions: a shift-adder, an analog-to-digital converter ADC, a digital-to-analog converter DAC, and a vector-matrix multiplier VMM.

[0009] In another possible implementation manner of the first aspect, the first computing circuit comprises: a first memory-computing unit cross array comprising N rows and M columns of first memory-computing units; a second memory-computing unit cross array comprising P rows and Q columns of second memory-computing units; and a first group of switch circuits comprising a plurality of first switches for connecting bit lines of the first memory-computing unit cross array and the second memory-computing unit cross array, the first group of switch circuits being configured to control the communication between the first memory-computing unit cross array and the second memory-computing unit cross array.

[0010] In another possible implementation manner of the first aspect, the first computing circuit is configured to implement the function of a shift-adder, wherein: the controller is configured to control the first group of switch circuits to be in an open state, the first group of switch circuits in the open state indicating that the first memory-computing unit cross array and the second memory-computing unit cross array are not connected; and the first memory-computing unit cross array is configured to receive a first group of data through word lines of the first row to the (N-1)th row, obtain a first calculation result according to first weights stored in memory-computing units of the first row to the (N-1)th row and the first group of data, wherein a word line of the Nth row in the first memory-computing unit cross array is configured to output the first calculation result, the first weights are configured to indicate the number of bits to be shifted of the first group of data, and the first calculation result is configured to indicate a calculation result obtained after the first group of data is shifted and accumulated.

[0011] In one case, the first memory and computing unit cross array can implement the function of a cyclic shift adder in actual application. The first memory and computing unit cross array is configured to receive a first group of data through word lines of the first row to the (N-1)th row, the first group of data being output on a plurality of bit lines of a previous memory and computing unit cross array connected to the first memory and computing unit cross array. The first memory and computing unit cross array is configured to shift each data in the first group of data based on a first weight stored in a memory and computing unit of the first memory and computing unit cross array, and accumulate a result of the shift of each data in the first group of data to obtain an output result of the cyclic shift adder.

[0012] In another case, the first memory and computing unit cross array can implement the function of an inter-cycle shift adder. The first memory and computing unit cross array is configured to receive a first group of data through word lines of the first row to the (N-1)th row, the first group of data being output results of a plurality of cyclic shift adders of a previous memory and computing unit cross array connected to the first memory and computing unit cross array. The first memory and computing unit cross array is configured to shift each data in the first group of data, and accumulate a result of the shift of each data in the first group of data to obtain an output result of the inter-cycle shift adder.

[0013] In another possible implementation of the first aspect, the second memory and computing unit cross array is configured to receive a second group of data through word lines of the first row to the (P-1)th row, and obtain a second calculation result based on a second weight stored in a memory and computing unit of the first row to the (P-1)th row and the second group of data, wherein a word line of the Pth row in the second memory and computing unit cross array is configured to output the second calculation result, the second weight is configured to indicate a number of bits to be shifted of the second group of data, and the second calculation result is configured to indicate a calculation result of accumulation after the shift of the second group of data.

[0014] In another possible implementation of the first aspect, the first calculation circuit is configured to implement a function of a VMM, and the controller is configured to control the first group of switch circuits to be in a closed state, the first group of switch circuits in the closed state being configured to indicate that the first memory and computing unit cross array and the second memory and computing unit cross array are in communication. The first calculation circuit is configured to receive a third group of data through the word lines of the first memory and computing unit cross array and the second memory and computing unit cross array, and perform a matrix multiplication operation on the third group of data based on a third weight stored in the first memory and computing unit cross array and the second memory and computing unit cross array to obtain a third calculation result, and the bit lines of the first memory and computing unit cross array and the second memory and computing unit cross array are configured to output the third calculation result.

[0015] In a possible implementation form of the first aspect, the first computing circuit further comprises: a plurality of current-voltage conversion circuits, a second group of switch circuits, wherein the plurality of current-voltage conversion circuits comprises a current-voltage conversion circuit connected to an output end of each bit line in the second memory-computing unit cross array; the second group of switch circuits comprises a plurality of second switches for connecting the plurality of current-voltage conversion circuits and the bit lines of the second memory-computing unit cross array, and the second group of switch circuits is configured to control the communication between the plurality of current-voltage conversion circuits and the second memory-computing unit cross array; the controller is further configured to control the second group of switch circuits to be in a closed state, and the second group of switch circuits in the closed state indicates that the second memory-computing unit cross array and the plurality of current-voltage conversion circuits are in communication; and the plurality of current-voltage conversion circuits are configured to convert the third computing result into a voltage signal for output.

[0016] In a possible implementation form of the first aspect, the first computing circuit further comprises: a plurality of inverters, a third group of switch circuits, wherein the plurality of inverters comprises an inverter connected to each bit line in the first memory-computing unit cross array and the second memory-computing unit cross array; the third group of switch circuits comprises a plurality of third switches for connecting the plurality of inverters and the first memory-computing unit cross array and the second memory-computing unit cross array, and the third group of switch circuits is configured to control the communication between the plurality of inverters and the first memory-computing unit cross array and the second memory-computing unit cross array.

[0017] In a possible implementation form of the first aspect, the first computing circuit is configured to implement an ADC, the controller is configured to control the first group of switch circuits and the third group of switch circuits to be in a closed state, the first group of switch circuits in the closed state is configured to indicate that the first memory-computing unit cross array and the second memory-computing unit cross array are in communication, and the third group of switch circuits in the closed state is configured to indicate that the first memory-computing unit cross array, the second memory-computing unit cross array and the plurality of inverters are in communication; the first computing circuit is configured to receive a fourth group of data through the word lines of the first memory-computing unit cross array and the second memory-computing unit cross array, obtain a fourth computing result according to the fourth group of data and fourth weights stored in the first memory-computing unit cross array and the second memory-computing unit cross array, wherein the fourth weights are configured to indicate the number of bits to be shifted in the process of converting the fourth group of data into a digital signal, and the plurality of inverters are configured to perform nonlinear processing on the fourth computing result to obtain a conversion result of converting the fourth group of data into a digital signal.

[0018] In a further possible implementation form of the first aspect, the first computing circuit is configured to implement a function of a DAC, and the controller is configured to control the first set of switch circuits to be in an open state, the first set of switch circuits in the open state indicating that the first crossbar of memory and compute cells and the second crossbar of memory and compute cells are not connected; the first crossbar of memory and compute cells is configured to receive a fifth set of data via word lines of the 1st to N-1st rows, and obtain a first computation result based on fifth weights stored in the 1st to N-1st rows of memory and compute cells and the fifth set of data, wherein a Nth row of word lines in the first crossbar of memory and compute cells is configured to output the fifth computation result, the fifth weights indicating a number of bits to be shifted in a process of converting the fifth set of data into an analog signal, and the fifth computation result indicating a processing result after the fifth set of data is converted into the analog signal. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A structure schematic diagram of a neural network system 100 provided by the present application.

[0020] Figure 2 A schematic block diagram of a computing node in a neural network chip provided by the present application.

[0021] Figure 3 A schematic diagram of a mapping relationship between a neural network and a neural network array.

[0022] Figure 4 A possible weight matrix schematic diagram provided by the present application.

[0023] Figure 5 A schematic diagram of a neural network circuit provided by the present application.

[0024] Figure 6 A functional block diagram of S+A provided by the present application.

[0025] Figure 7 A schematic diagram of a first crossbar of memory and compute cells provided by the present application.

[0026] Figure 8 A functional block diagram of inter-layer S+A provided by the present application.

[0027] Figure 9 A functional block diagram of DAC provided by the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the present application will be described below with reference to the drawings.

[0029] Artificial intelligence (AI) is a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a branch of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is the design principle and implementation method of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making. The research in the field of artificial intelligence includes robots, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, AI basic theory, etc.

[0030] In the field of AI, deep learning is a learning technology based on deep artificial neural network (ANN) algorithm. Artificial neural network (ANN), also known as neural network (NN) or neural network, is a mathematical model or computational model that simulates the structure and function of biological neural network (animal central nervous system, especially brain) in the field of machine learning and cognitive science, which is used to estimate or approximate functions. Artificial neural network can include convolutional neural network (CNN), multilayer perceptron (MLP), recurrent neural network (RNN), deep neural network (DNN) and other neural networks.

[0031] The training process of neural network is a data-centered task, which requires high-performance and low-power processing capability of computing hardware. Due to the separation of storage unit and computing unit based on traditional von Neumann architecture, a large amount of data needs to be moved, which cannot realize high energy efficiency processing.

[0032] The following will be combined Figure 1 The system architecture of the present application is described.

[0033] Figure 1 A structure diagram of a neural network system 100 provided by an embodiment of the present application is shown. As shown in the figure, the neural network system 100 can include a host 105 and a neural network circuit 110. Figure 1

[0034] ​The neural network circuit 110 is connected with the host 105 through a host interface. The host interface can include a standard host interface and a network interface. For example, the host interface can include a peripheral component interconnect express (PCIE) interface.

[0035] As an example, as shown in FIG. 1, the neural network circuit 110 can be connected with the host 105 through a PCIE bus. Thus, data is input into the neural network circuit 110 through the PCIE bus, and data processed by the neural network circuit 110 is received through the PCIE bus. In addition, the host 105 can also monitor the working state of the neural network circuit 110 through the host interface. Figure 1

[0036] The host 105 can include a processor 1052 and a memory 1054. It should be noted that, in addition to the devices shown in FIG. 1, the host 105 can also include a communication interface and other devices such as a disk as an external memory, which are not limited herein. Figure 1

[0037] The processor 1052 is the operation core and control core of the host 105. The processor 1052 can include multiple processor cores. The processor 1052 can be a very large scale integrated circuit. The processor 1052 is installed with an operating system and other software programs, so that the processor 1052 can realize access to the memory 1054, cache, disk and peripheral devices (such as the neural network circuit in FIG. 1). Figure 1 It can be understood that, in the embodiments of the present application, the core in the processor 1052 can be a central processing unit (CPU), and can also be an application specific integrated circuit (ASIC).

[0038] ​​It is to be understood that the processor 1052 in the embodiments of this application can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0039] The memory 1054 is the main memory of the host 105. The memory 1054 is connected to the processor 1052 through a double data rate (DDR) bus. The memory 1054 is usually used to store various running software in the operating system, input and output data, and information exchanged with the external storage, etc. In order to improve the access speed of the processor 1052, the memory 1054 needs to have the advantage of fast access speed. In the traditional computer system architecture, dynamic random access memory (DRAM) is usually used as the memory 1054. The processor 1052 can access the memory 1054 at a high speed through a memory controller (not shown in the figure) and perform read and write operations on any storage unit in the memory 1054. Figure 1

[0040] ​It should also be appreciated that the memory 1054 in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0041] Figure 1 The neural network circuit 110 shown can include a plurality of PCIE cards, and each PCIE card can include a plurality of neural network chips (chips). There are various implementation manners for data transmission and information interaction between the plurality of chips, which are not limited in the present application. In one possible implementation manner, the plurality of chips can be connected through a router, and the data transmission and information interaction between the plurality of chips can be realized through the network topology composed of the router. In another possible implementation manner, the plurality of chips can also be hung on the PCIE bus, and the data transmission and information interaction between the plurality of chips in the neural network circuit 110 can be realized through the PCIE bus.

[0042] Optionally, Figure 1 The architecture of the neural network system in the above embodiment is only an example, and those skilled in the art can understand that in practice, the neural network system can include more than Figure 1More or fewer units can be included. Alternatively, the modules, units or circuits in the neural network system can also be replaced by other modules, units or circuits with similar functions, and the embodiments of the present application do not limit this. For example, in other examples, the above neural network system can also be implemented by a graphics processing unit (GPU) or a field programmable gate array (FPGA) based on digital calculation.

[0043] Figure 1 One of the neural network chips can include a plurality of computing nodes for performing neural network calculations. The internal structure of the computing node will be described in detail below Figure 2 , and the internal structure of the computing node will be described in detail below

[0044] Figure 2 is a schematic block diagram of a computing node in a neural network chip. As Figure 2 indicated, the computing node 200 can include a plurality of CUs 210, an intra-layer shift and add (intra-layer S+A) 220, and an activation function 230.

[0045] Each CU 210 internally includes a plurality of vector-matrix multipliers (VMMs) 211. The VMM 211 can also be referred to as a crossbar of compute-in-memory. The VMM 211 is a large NVM crossbar array for computing vector-matrix multiplication, which is the core of the entire accelerator. The weights of the DNN are written on the crossbar array of the VMM 211.

[0046] The storage and calculation unit is not specifically limited in the embodiments of the present application, and can include but is not limited to a non-violate memory (NVM), a memristor, a static RAM (SRAM), a NOR Flash, a magnetism RAM (MRAM), a ferroelectric gate field-effect transistor (FeFET), and an electrochemistry RAM (ECRAM). The memristor can include but is not limited to a resistive random-access memory (ReRAM), a conductive-bridging RAM (CBRAM), and a phase-change memory (PCM).

[0047] For the convenience of understanding hereinafter, the VMM 211 is described in detail as follows. Figure 3 and Figure 4 .

[0048] Figure 3 The VMM 211 shown in FIG. 1 is an m x n cross array, and can include a plurality of NVMs (for example, G 1,1 , G 1,2 , and the like) in the VMM 211. The bit lines (BLs) of the NVMs in each column are connected together, and the source lines (SLs) of the NVMs in each row are connected together.

[0049] In the embodiments of the present application, the weight of a neuron in a neural network can be represented by the conductance value of an NVM. Specifically, as an example, each element in the weight matrix shown in FIG. 2 can be represented by the conductance value of the NVM located at the intersection of the BL and the SL. For example, the G 1,1 of the NVM in the element W 0,0 in FIG. 2 represents the weight element W 1,2 in FIG. 3 represents the weight element W 0,1 , and the like. Figure 4 Figure 3 Figure 4 Figure 3 Figure 4

[0050] The different conductance values of the NVMs can represent different weights of neurons in a neural network stored by the memristor units.

[0051] ​​​​​In the process of performing neural network calculation, n input data V1, V2, V3, …Vn can be represented by voltage values loaded to BL, for example Figure 3 The input data can be represented by voltage, so that the input data loaded to the memristor and the weight values stored in the NVM realize point multiplication operation, and m output data as shown in Figure 3 The m output data can be represented by current of SL, for example Figure 3 I1, I2, …Im.

[0052] It should be understood that there are many ways to implement the voltage values loaded to the VMM 211, and the embodiments of the present application do not make specific limitations thereon. For example, the voltage can be represented by pulse amplitude, for example, the voltage can also be represented by pulse width, for example, the voltage can also be represented by pulse number, for example, the voltage can also be represented by the combination of pulse number and pulse amplitude of voltage.

[0053] It should be noted that in the above, a neural network array is taken as an example, and the process of completing the corresponding multiply-accumulate calculation in the neural network by the neural network array is described in detail. In actual application, a plurality of neural network arrays jointly complete the multiply-accumulate calculation required by the complete neural network.

[0054] One of the plurality of neural network arrays can correspond to one neural network layer, and the neural network array is used to implement the calculation of the one neural network layer. Alternatively, a plurality of neural network arrays can correspond to one neural network layer, and are used to implement the calculation of the one neural network layer. Alternatively, one of the plurality of neural network arrays can correspond to a plurality of neural network layers, and is used to implement the calculation of the plurality of neural network layers.

[0055] Since the VMM 211 is actually an analog calculation, other operations (storage, activation) in actual application need to be implemented by digital circuits. Therefore, some peripheral auxiliary circuits are needed as the interface between the VMM 211 and other digital circuits. The peripheral auxiliary circuits can include but are not limited to: shift and add (S+A), intra-layer shift and add (intra-layer S+A), digital-to-analog converter (DAC), analog-to-digital converter (ADC).

[0056] Referring to Figure 2DAC 212, ADC 213, S+A 214. As an example, the excitation value of the DNN is read from the buffer and enters the CU 210, converted into an analog signal by the DAC 212 and input into the VMM 211. After the calculation is completed in the VMM 211, the calculation result is quantized into a digital signal by the ADC 213. Then, the S+A 214 circuit is used for shift-add operation, and the calculation in the CU 210 is completed at this time. The calculation result in the CU 210 is then stored in the buffer after being calculated by the intra-layer S+A 220 and the activation function 230 in the calculation node 200, for the VMM calculation of the next layer.

[0057] The functions of the above-mentioned circuits (for example, DAC 212, ADC 213, S+A 214, intra-layer S+A 220) will be described in detail below.

[0058] 1. DAC 212

[0059] The DAC 212 is logically connected to the VMM 211 and connected to the input of the VMM 211, and is used to convert a digital signal into an analog signal and input it into the VMM 211. For example, a 4-bit digital signal 0010 is converted into an analog level.

[0060] 2. ADC 213

[0061] The ADC 213 is logically connected to the VMM 211 and connected to the output of the VMM 211, and is used to convert the analog signal output by the VMM 211 into a digital signal for processing by other digital calculation circuits. For example, an analog level is converted into a digital signal.

[0062] 3. S+A 214

[0063] The S+A 214 performs calculation after the ADC 213, and according to the function of the S+A 213 circuit, it can be divided into intra-period S+A and inter-period S+A.

[0064] Intra-period S+A, since the number of bits that can be written by each unit of the VMM 211 is limited, each weight is quantized and written in several adjacent storage units (for example, NVM units) on the same word line. Therefore, the results output on several adjacent bit lines of the VMM 211 need to be shifted and added, which can be referred to as intra-period S+A. Specifically, taking an 8-bit quantized weight as an example, assuming that each NVM unit can write 2 bits, then a weight is written in 4 NVM units, and intra-period S+A needs to shift and add the results output on these 4 word lines.

[0065] In the inter-cycle S+A, the resolution of the DAC used in the traditional accelerator is less than the quantization bit number of the DNN, and the excitation value is also quantized and input into the VMM 211 in multiple calculation cycles. Therefore, the results of the intra-cycle S+A in these cycles also need to be shifted and added, and this process can be referred to as inter-cycle S+A. Specifically, taking 8-bit quantized weights as an example, assuming that the DAC resolution is 1 bit, then a group of excitation needs to be input for 8 cycles, and the inter-cycle S+A needs to shift the result of the last cycle by 1 bit and add it to the result of the intra-cycle S+A in the current cycle. After 8 cycles, the inter-cycle S+A outputs the result after the complete S+A.

[0066] 4、intra-layer S+A 220

[0067] The weight matrix of one layer of the DNN is much larger than the cross array size of the VMM 211, so the weight matrix of one layer of the DNN is divided and written on multiple VMMs 211, and the results calculated by these VMMs 211 need to be added to obtain the complete vector-matrix multiplication result. This addition operation is completed by the intra-layer S+A circuit. Specifically, taking four VMMs as an example, the results of two VMMs in the same column need to be added respectively to obtain the complete vector-matrix multiplication result.

[0068] In the related technical solutions, on the one hand, due to the different scales and structures of the neural networks, the demand for computing resources is also different. If the hardware circuit needs to adapt to all the neural networks to be supported, the design needs to be performed according to the largest scale, which will cause a great waste in design. For example, the proportion of the three modules in the calculation node of the Conv1-1 layer is VMM:S+A:ADC = 1:1:1. The proportion of the three modules in the calculation node of the Conv5-3 layer is VMM:S+A:ADC = 36:1:1. If the maximum case (Conv1-1) is completely matched, then the S+A and the ADC will be wasted. On the other hand, the peripheral circuit in the traditional architecture is generally implemented by a complementary metal oxide semiconductor (CMOS) circuit, and the power consumption ratio is large.

[0069] Embodiments of the present application provide a neural network circuit, which can be configured according to different needs, so that the neural network circuit realizes at least two different circuit functions. In this way, on the one hand, the waste of circuit design caused by the use of various special circuits can be avoided. On the other hand, some peripheral auxiliary circuits are implemented by the cross array, and since the cross array of the storage and calculation unit itself has the advantages of low power consumption and small area, the power consumption of the chip can also be reduced.

[0070] As an example, the at least two different circuit functions can include, but are not limited to, at least two of the following: a DAC, a S+A, an intra-layer S+A, a VMM, and an ADC.

[0071] The following describes in detail Figure 5 The neural network circuit 500 provided by the embodiments of the present application is described in detail.

[0072] The neural network circuit 500 includes a first computing unit and a controller. The first computing unit includes at least two cross arrays of storage and computing units and at least one group of switch circuits. The controller is configured to control the at least one group of switch circuits, so that the computing circuit realizes at least two different circuit functions.

[0073] As an example, the first computing circuit can realize at least two of the following circuit functions: a shift adder, an analog-to-digital converter ADC, a digital-to-analog converter DAC, and a vector-matrix multiplier VMM.

[0074] The following describes in detail Figure 5 The following describes in detail the specific process of the first computing circuit realizing at least two of the above-mentioned circuit functions, taking the neural network circuit 500 shown in FIG. 1 as an example.

[0075] It should be understood that the following examples are only to help those skilled in the art to understand the embodiments of the present application, and are not intended to limit the embodiments of the present application to specific values or specific scenarios. Those skilled in the art can obviously make various equivalent modifications or changes based on the examples given, and such modifications and changes also fall within the scope of the embodiments of the present application.

[0076] (1) The following describes in detail the specific process of the first computing circuit realizing the function of the shift adder.

[0077] It should be understood that it can be assumed that in the neural network architecture, the quantization bits of the weights in the neural network are Q bits, the size of the first cross array of storage and computing units and the second cross array of storage and computing units is n x n, and the size of the storage and computing unit (for example, an NVM unit) in each cross array of storage and computing units is Q c bits, and the resolution of the DAC connected to the input of the cross array of storage and computing units is Q d bits.

[0078] 1. Neural network circuit configuration

[0079] The first computing circuit in the neural network circuit can include: a first cross array of storage and computing units, a second cross array of storage and computing units, a first group of switch circuits,

[0080] a first memory and compute cell cross array including N rows of M columns of first memory and compute cells;

[0081] a second memory and compute cell cross array including P rows of Q columns of second memory and compute cells;

[0082] a first group of switch circuits including a plurality of first switches for connecting bit lines of the first memory and compute cell cross array and the second memory and compute cell cross array, the first group of switch circuits being configured to control communication between the first memory and compute cell cross array and the second memory and compute cell cross array.

[0083] a controller in the neural network circuit is configured to control the first group of switch circuits to be in an open state, wherein the first group of switch circuits being in the open state indicates that the first memory and compute cell cross array and the second memory and compute cell cross array are not in communication.

[0084] That is, the controller controls the first group of switch circuits to be in the open state, the first memory and compute cell cross array in the first compute circuit and the second memory and compute cell cross array are two independent memory and compute cell cross arrays, and each memory and compute cell cross array can realize the function of a shift-adder.

[0085] Taking the function of the shift-adder realized by the first memory and compute cell cross array as an example, the first memory and compute cell cross array is configured to receive a first group of data through word lines of the 1st row to the (N-1)th row, obtain a first calculation result according to first weights stored in memory and compute cells of the 1st row to the (N-1)th row and the first group of data, wherein a word line of the Nth row in the first memory and compute cell cross array is configured to output the first calculation result, the first weights are configured to indicate a number of bits to be shifted of the first group of data, and the first calculation result is configured to indicate a calculation result of the first group of data after being shifted and accumulated.

[0086] Taking the function of the shift-adder realized by the second memory and compute cell cross array as an example, the second memory and compute cell cross array is configured to receive a second group of data through word lines of the 1st row to the (P-1)th row, obtain a second calculation result according to second weights stored in memory and compute cells of the 1st row to the (P-1)th row and the second group of data, wherein a word line of the Pth row in the second memory and compute cell cross array is configured to output the second calculation result, the second weights are configured to indicate a number of bits to be shifted of the second group of data, and the second calculation result is configured to indicate a calculation result of the second group of data after being shifted and accumulated.

[0087] 2. Configuration of weights stored in memory and compute cells (e.g., NVM) of a crossbar

[0088] For ease of description, taking the function of the shift-adder realized by the first memory and compute cell cross array as an example for description below.

[0089] It should be understood that the functions implemented by the shift-adder S+A can include, but are not limited to, intra-cycle S+A, inter-cycle S+A, and inter-layer S+A. Specifically, different S+A functions can be implemented according to different sources of received data and different weight values stored in the storage and computing units of the storage and computing unit cross array.

[0090] As an example, the first storage and computing unit cross array implements the function of intra-cycle S+A. The first storage and computing unit cross array is configured to receive a first group of data through the word lines of the first row to the N-1th row, the first group of data being output on a plurality of bit lines of a previous storage and computing unit cross array connected to the first storage and computing unit cross array. The first storage and computing unit cross array shifts each data in the first group of data based on a first weight stored in the storage and computing units thereof, and adds the shifted data to obtain an output result of intra-cycle S+A.

[0091] Specifically, the first storage and computing unit cross array implements the function of intra-cycle S+A by the input a of the i-th bit line i multiplied by the corresponding weight and then added to obtain the voltage b output by the first storage and computing unit cross array. Therefore, the first weight stored in the storage and computing units in the first storage and computing unit cross array is determined according to the number Q of bits that can be stored on each storage and computing unit (e.g., NVM cell) in each storage and computing unit cross array c .

[0092] The specific implementation of determining the first weight stored in the storage and computing units in the first storage and computing unit cross array is described below.

[0093] One possible objective function for implementing the function of intra-cycle S+A is shown in equation (1).

[0094]

[0095] wherein b represents the voltage output by the first storage and computing unit cross array;

[0096] a i represents the output of the i-th bit line belonging to the same weight in the first storage and computing unit cross array,

[0097] For example, Q=8, Q c =2, and Q d =4, the objective function for implementing the function of intra-cycle S+A is shown in equation (2), and the function block diagram for implementing the function of intra-cycle S+A is shown in Figure 6 .

[0098]

[0099] Referring toFigure 6 a0, a1, a2, a3 are respectively taken as the input of the 4 bit lines in the first storage and computing unit cross array, and the input of the 4 bit lines is moved Q c bits, and the input of the 4 bit lines is moved Q

[0100] In the embodiment of the application, the first storage and computing unit cross array can be regarded as two connected NVM cross arrays XB1 and XB2. As shown in Figure 7 , wherein the last row of the first storage and computing unit cross array can be regarded as XB2, and the remaining rows can be regarded as XB1.

[0101] Figure 7 The corresponding relationship between the input voltage and the output voltage of the first storage and computing unit cross array shown in

[0102]

[0103] wherein V out represents the output voltage of the first storage and computing unit cross array, for example, the output voltage on the last row word line of the first storage and computing unit cross array;

[0104] V in,i represents the i-th input voltage of the first storage and computing unit cross array, for example, the input voltage on the i-th word line of the first storage and computing unit cross array except the last row word line;

[0105] represents the conductance value of the storage and computing unit (for example, NVM) in the i-th row and the k-th column of the first storage and computing unit cross array XB1;

[0106] represents the conductance value of the storage and computing unit (for example, NVM) in the k-th column of the first storage and computing unit cross array XB2;

[0107] m represents the number of word lines of the first storage and computing unit cross array XB1.

[0108] In order to deploy the first storage and computing unit cross array shown in Figure 7 to achieve the function of S+A in the cycle, according to the target function of S+A in the cycle shown in formula (1), the and in formula (3) can be configured, so that the first storage and computing unit cross array can achieve the function of S+A in the cycle.

[0109] As an example, the construction and The problem is converted into a quadratic mixed integer constrained programming (MIQCP) feasible solution problem. All the conductance solutions (e.g., and ) are obtained by a solver, and the conductance solutions are written into the corresponding individual storage and computing units (e.g., NVM) in the first storage and computing unit cross array.

[0110] The specific implementation process of obtaining all the conductance solutions (e.g., and ) is described in detail below.

[0111] Since the writable conductance of each storage and computing unit (e.g., NVM) is a discrete value, the solution of the conductance (e.g., and ) can actually be the conductance level of each storage and computing unit (e.g., NVM). The variable of the above problem is the conductance level of each storage and computing unit (e.g., NVM) and wherein, represents the conductance level of the storage and computing unit (e.g., NVM) in the i-th row and the k-th column of the cross matrix XB1, represents the conductance level of the storage and computing unit (e.g., NVM) in the k-th column of the cross matrix XB2.

[0112] The constraint conditions of the above problem include:

[0113] (1) Since the conductance state of each storage and computing unit (e.g., NVM) is limited, the conductance level of each storage and computing unit (e.g., NVM) can be limited to Q c = 2 as an example, l can take 3, that is, the 2-bit NVM unit can write 0-3 conductance levels.

[0114] (2) The output of the circuit needs to be consistent with the objective function: wherein, numer i is the numerator of the weight in the objective function. For example, for the S+A in the period shown in formula (2), numer 3,2,1,0 = 64, 16, 4, 1.

[0115] (3) Add a restriction condition to formula (3): All k are equal.

[0116] In the embodiments of the present application, according to the above constraint conditions, all the conductance (e.g., and ) and write the solution of the above conductance into each corresponding storage and computing unit (e.g. NVM) in the first storage and computing unit cross array. In this way, the first storage and computing unit cross array can realize the function of S+A in a period.

[0117] Another example, the first storage and computing unit cross array realizes the function of S+A between periods. The first storage and computing unit cross array is configured to receive a first group of data through word lines of the 1st to N-1st rows, the first group of data being output results of S+A in a plurality of periods of a previous storage and computing unit cross array connected to the first storage and computing unit cross array, and the first storage and computing unit cross array is configured to shift each data in the first group of data and add the shifted data to obtain an output result of S+A between periods.

[0118] Specifically, the first storage and computing unit cross array needs to add the output voltage b of S+A in the current period and the output voltage R i-1 of S+A in the previous period after being shifted by Q d bits to obtain the output result R i of S+A in the current period. Therefore, the first weight stored in the storage and computing unit in the first storage and computing unit cross array is determined according to the resolution Q d of the DAC connected to the input of the storage and computing unit cross array.

[0119] The specific implementation of determining the first weight stored in the storage and computing unit in the first storage and computing unit cross array is described below.

[0120] One possible objective function for realizing the function of S+A between periods is shown in equation (4).

[0121]

[0122] wherein R i represents the output voltage of S+A in the current period;

[0123] R i-1 represents the output voltage of S+A in the previous period.

[0124] Taking Q=8, Q c =2, and Q d =4 as an example, the objective function for realizing the function of S+A between periods is shown in equation (5), and the function block diagram for realizing the function of S+A between periods is shown in Figure 6 .

[0125]

[0126] Referring to Figure 6 , b is the output voltage of S+A in the current period, and R i-1As the output voltage of S+A in the previous cycle, R i-1 Moving bits and adding b, the output result R i of S+A in the current cycle is obtained. i-1 Moving 0.0625 bits and adding b, the output result R i of S+A in the current cycle is obtained.

[0127] In order to deploy the first storage and calculation unit cross array shown in Figure 7 to realize the function of S+A in the above cycle, the and in formula (3) can be configured according to the target function of S+A in the cycle shown in formula (4), so that the first storage and calculation unit cross array can realize the function of S+A in the cycle. For specific implementation, please refer to the description in the foregoing, which will not be repeated here.

[0128] As another example, the first storage and calculation unit cross array realizes the function of interlayer S+A. The first storage and calculation unit cross array is used to receive a first group of data through the word lines of the 1st to N-1st rows, and the first group of data is the output of a plurality of storage and calculation unit cross arrays connected to the first storage and calculation unit cross array. The first storage and calculation unit cross array shifts each data in the first group of data, and the result of accumulating each data in the first group of data after shifting is taken as the output result of interlayer S+A.

[0129] Specifically, interlayer S+A is used to add the calculation results of a plurality of VMMs, and the function block diagram is as shown in Figure 8 V in,1 represents the calculation result of the first VMM, V in,2 represents the calculation result of the second VMM, and so on. After adding the calculation results of a plurality of VMMs, the output voltage V out is obtained.

[0130] The specific implementation of determining the first weight stored in the storage and calculation unit in the first storage and calculation unit cross array is described below.

[0131] A possible target function for realizing the interlayer S+A function is shown in formula (6).

[0132]

[0133] Among them, V out represents the output voltage of the first storage and calculation unit cross array, for example, the output voltage on the last row of word lines of the first storage and calculation unit cross array;

[0134] V in,irepresents the i-th input voltage of the first memory and computing unit cross array, for example, the input voltage of the i-th word line in the first memory and computing unit cross array except the last row of word lines;

[0135] In order to realize the function of inter-layer S+A, the first memory and computing unit cross array can be deployed as follows: Figure 7 The first memory and computing unit cross array can be deployed as follows: And So that the first memory and computing unit cross array can realize the function of inter-layer S+A. For specific implementation, please refer to the description in the foregoing, which will not be repeated here.

[0136] (2), the following detailed description of the specific process of the first computing circuit to realize the function of DAC.

[0137] 1, configuration of neural network circuit

[0138] The first computing circuit in the neural network circuit can include: a first memory and computing unit cross array, a second memory and computing unit cross array, a first group of switch circuits,

[0139] The first memory and computing unit cross array includes N rows and M columns of first memory and computing units;

[0140] The second memory and computing unit cross array includes P rows and Q columns of second memory and computing units;

[0141] The first group of switch circuits includes a plurality of first switches for connecting the bit lines of the first memory and computing unit cross array and the second memory and computing unit cross array;

[0142] The controller in the neural network circuit is used to control the first group of switch circuits to be in an open state. The controller controls the first group of switch circuits to be in an open state. The first memory and computing unit cross array and the second memory and computing unit cross array in the first computing circuit are two independent memory and computing unit cross arrays. Each memory and computing unit cross array can realize the function of DAC.

[0143] Specifically, the first memory and computing unit cross array receives the fifth group of data through the first row to the N-1 row of word lines, and obtains a first calculation result according to the fifth weight stored in the first row to the N-1 row of memory and computing units and the fifth group of data, wherein the Nth row of word lines in the first memory and computing unit cross array is used to output the fifth calculation result, the fifth weight is used to indicate the number of bits to be shifted in the process of converting the fifth group of data into an analog signal, and the fifth calculation result is used to indicate the processing result after the fifth group of data is converted into an analog signal.

[0144] 2, configuration of weight stored in memory and computing unit (for example, NVM) in cross matrix

[0145] As an example, the DAC is used to convert a digital signal into an analog signal input into the VMM. The target function for implementing the function of the DAC is shown in equation (7).

[0146]

[0147] Wherein, k·GND is used to adjust the range of the DAC output analog signal, for adjusting the input voltage of the VMM to a suitable magnitude.

[0148] Taking Q=8, Q c =2, Q d =4, i=4 as an example, the target function for implementing the function of the DAC is shown in equation (8).

[0149]

[0150] The function block diagram of the DAC is shown in Figure 9 In order to deploy the first memory and calculation unit cross array shown in Figure 7 into a form that can implement the above-mentioned function of the DAC, on the one hand, in Figure 8 , the inputs of the first memory and calculation unit cross array are V in,1 , V in,2 , V in,3 , V in,4 on the word line of XB1, respectively, and after passing through the bit line of XB1, V out is output from the word line of XB2. On the other hand, it is also necessary to configure and in equation (3) according to the target function of the DAC shown in equation (7), so that the first memory and calculation unit cross array can implement the function of the DAC. As an example, it is possible to configure and in equation (3) according to the target function of the DAC shown in equation (7), so that the first memory and calculation unit cross array can implement the function of the DAC. For specific implementation, please refer to the description in the foregoing, which will not be repeated here.

[0151] (3), the specific implementation of the first calculation circuit to implement the VMM is described below.

[0152] 1. Neural network circuit configuration

[0153] The first calculation circuit in the neural network circuit can include: a first memory and calculation unit cross array, a second memory and calculation unit cross array, a first group of switch circuits,

[0154] The first memory and calculation unit cross array includes N rows and M columns of first memory and calculation units.

[0155] The second storage and calculation unit cross array includes P rows and Q columns of second storage and calculation units.

[0156] The first group of switch circuits includes a plurality of first switches for connecting bit lines of the first storage and calculation unit cross array and the second storage and calculation unit cross array.

[0157] The controller in the neural network circuit is configured to control the first group of switch circuits to be in a closed state, and the first group of switch circuits in the closed state indicates that the first storage and calculation unit cross array and the second storage and calculation unit cross array are in communication. The first storage and calculation unit cross array and the second storage and calculation unit cross array implement the function of the VMM.

[0158] Specifically, the first calculation circuit receives a third group of data through word lines of the first storage and calculation unit cross array and the second storage unit cross array, performs a matrix multiplication operation on the third group of data based on third weights stored in the first storage and calculation unit cross array and the second storage unit cross array, and obtains a third calculation result. Bit lines of the first storage and calculation unit cross array and the second storage unit cross array are used to output the third calculation result.

[0159] 2. Configuration of weights stored in the storage and calculation units (e.g., NVM) in the cross matrix

[0160] In a conventional manner, the weights corresponding to the storage and calculation units (e.g., NVM) in the neural network can be written into the storage and calculation units (e.g., NVM), so that the larger cross array can implement the function of the VMM. For specific implementation process, please refer to the description of the VMM in the foregoing, which will not be described here.

[0161] Optionally, in some embodiments, the third group of data received by the first calculation circuit through the word lines of the first storage and calculation unit cross array and the second storage unit cross array is a voltage signal, and the third calculation result obtained after the matrix multiplication operation of the voltage signal and the third weights stored in the first storage and calculation unit cross array and the second storage unit cross array is a current signal. The current signal can also be converted into a voltage signal.

[0162] In this implementation, the first calculation circuit further includes a plurality of current-voltage conversion circuits and a second group of switch circuits, wherein,

[0163] The plurality of current-voltage conversion circuits includes a current-voltage conversion circuit connected to an output end of each bit line in the second storage and calculation unit cross array.

[0164] The second group of switch circuits includes a plurality of second switches for connecting the plurality of current-voltage conversion circuits and the bit lines of the second cross-point array of memory and computation units, and is configured to control the connection between the plurality of current-voltage conversion circuits and the second cross-point array of memory and computation units.

[0165] The controller is further configured to control the second group of switch circuits to be in a closed state, and the second group of switch circuits in the closed state indicates that the second cross-point array of memory and computation units and the plurality of current-voltage conversion circuits are connected.

[0166] The plurality of current-voltage conversion circuits is configured to convert the third calculation result into a voltage signal and output the voltage signal.

[0167] (4) The specific implementation of the first calculation circuit for realizing the ADC is described below.

[0168] 1. Configuration of a neural network circuit

[0169] The first calculation circuit in the neural network circuit can include a first cross-point array of memory and computation units, a second cross-point array of memory and computation units, a first group of switch circuits, a third group of switch circuits, and a plurality of inverters, wherein

[0170] The first cross-point array of memory and computation units includes N rows and M columns of first memory and computation units.

[0171] The second cross-point array of memory and computation units includes P rows and Q columns of second memory and computation units.

[0172] The first group of switch circuits includes a plurality of first switches for connecting the first cross-point array of memory and computation units and the bit lines of the second cross-point array of memory and computation units.

[0173] The plurality of inverters includes an inverter connected to each bit line in the first cross-point array of memory and computation units and the second cross-point array of memory and computation units.

[0174] The third group of switch circuits includes a plurality of third switches for connecting the plurality of inverters and the first cross-point array of memory and computation units and the second cross-point array of memory and computation units, and is configured to control the connection between the plurality of inverters and the first cross-point array of memory and computation units and the second cross-point array of memory and computation units.

[0175] The controller is configured to control the first group of switch circuits and the third group of switch circuits to be in a closed state, the first group of switch circuits in the closed state indicates that the first cross-point array of memory and computation units and the second cross-point array of memory and computation units are connected, and the third group of switch circuits in the closed state indicates that the first cross-point array of memory and computation units, the second cross-point array of memory and computation units, and the plurality of inverters are connected.

[0176] Specifically, the first computing circuit is configured to receive a fourth group of data through word lines of the first storage-computing unit cross array and the second storage unit cross array, and obtain a fourth computing result according to the fourth group of data and a fourth weight stored in the first storage-computing unit cross array and the second storage unit cross array, wherein the fourth weight is used to indicate a number of bits to be shifted in a process of converting the fourth group of data into a digital signal, and the plurality of inverters are configured to perform nonlinear processing on the fourth computing result to obtain a conversion result of converting the fourth group of data into a digital signal.

[0177] 2. Configuration of weights stored in storage-computing units (e.g., NVM) in a cross matrix

[0178] In order to convert the first group of data into the digital signal, the first storage-computing unit cross array is deployed to have a function of an ADC. Figure 7 The first storage-computing unit cross array is deployed to have a function of an ADC. The first storage-computing unit cross array is deployed to have a function of an ADC. Thus, the first computing circuit can have a function of an ADC. The implementation of the configuration of the in formula (3) will be described above, and will not be described here again. The first storage-computing unit cross array is deployed to have a function of an ADC. The implementation of the configuration of the in formula (3) will be described above, and will not be described here again.

[0179] In the above technical solution, the neural network circuit can be configured to have different circuit functions according to actual needs of each layer, and the resource utilization rate is further increased.

[0180] It should be understood that the size of the sequence number of each process described above in various embodiments of the present application does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0181] Those skilled in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0182] In several embodiments provided in the present application, it should be understood that the pulse neural network embodiments described above are merely illustrative, for example, the division of the units is only a logical functional division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be through some interfaces.

[0183] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0184] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0185] If the function is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0186] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A neural network circuit, characterized by, The first computing circuit comprises: a first memory-computing unit cross array comprising N rows and M columns of first memory-computing units; a second memory-computing unit cross array comprising P rows and Q columns of second memory-computing units; and a first group of switch circuits comprising a plurality of first switches for connecting bit lines of the first memory-computing unit cross array and the second memory-computing unit cross array, the first group of switch circuits being configured to control communication between the first memory-computing unit cross array and the second memory-computing unit cross array, the controller being configured to control the first group of switch circuits to be in an open state or a closed state, wherein the first group of switch circuits in the open state indicates that the first memory-computing unit cross array and the second memory-computing unit cross array are not in communication, and the first group of switch circuits in the closed state indicates that the first memory-computing unit cross array and the second memory-computing unit cross array are in communication; in the case that the first group of switch circuits is in the open state, each memory-computing unit cross array in the first computing circuit respectively implements a function of a shift adder, or each memory-computing unit cross array in the first computing circuit respectively implements a function of a digital-to-analog converter (DAC); in the case that the first group of switch circuits is in the closed state, the first memory-computing unit cross array and the second memory-computing unit cross array implement a function of a vector-matrix multiplier (VMM). Each memory-computing unit cross array in the first computing circuit respectively implements a function of a shift adder, comprising the first memory-computing unit cross array is configured to receive a first group of data through word lines of the 1st to N-1th rows, obtain a first calculation result according to first weights stored in memory-computing units of the 1st to N-1th rows and the first group of data, wherein an Nth row of word lines in the first memory-computing unit cross array is configured to output the first calculation result, the first weights are configured to indicate a number of bits to be shifted of the first group of data, and the first calculation result is configured to indicate a calculation result of the first group of data after being shifted and accumulated.

3. The neural network circuit according to claim 2, wherein 2. The neural network circuit of claim 1, wherein, the second memory-computing unit cross array is configured to receive a second group of data through word lines of the 1st to P-1th rows, obtain a second calculation result according to second weights stored in memory-computing units of the 1st to P-1th rows and the second group of data, wherein a Pth row of word lines in the second memory-computing unit cross array is configured to output the second calculation result, the second weights are configured to indicate a number of bits to be shifted of the second group of data, and the second calculation result is configured to indicate a calculation result of the second group of data after being shifted and accumulated. the first memory-computing unit cross array and the second memory-computing unit cross array implement a function of a vector-matrix multiplier (VMM), comprising: ​ ​ 4. The neural network circuit of claim 1, wherein, ​ The first computing circuit is configured to receive a third group of data through word lines of the first storage and computing unit cross array and the second storage unit cross array, perform a matrix multiplication operation on the third group of data based on third weights stored in the first storage and computing unit cross array and the second storage unit cross array, and obtain a third computing result, and bit lines of the first storage and computing unit cross array and the second storage unit cross array are configured to output the third computing result.

5. The neural network circuit of claim 4, wherein, The first computing circuit further includes a plurality of current-voltage conversion circuits and a second group of switch circuits. The plurality of current-voltage conversion circuits include a current-voltage conversion circuit connected to an output end of each bit line in the second storage unit cross array. The second group of switch circuits include a plurality of second switches for connecting the plurality of current-voltage conversion circuits and the bit lines of the second storage unit cross array, and are configured to control communication between the plurality of current-voltage conversion circuits and the second storage unit cross array. The controller is further configured to control the second group of switch circuits to be in a closed state, and the second group of switch circuits in the closed state indicates that the second storage unit cross array and the plurality of current-voltage conversion circuits are in communication. The plurality of current-voltage conversion circuits are configured to convert the third computing result into a voltage signal for output.

6. The neural network circuit of claim 1, wherein, The first computing circuit further includes: The plurality of current-voltage conversion circuits include a current-voltage conversion circuit connected to an output end of each bit line in the second storage unit cross array. The third group of switch circuits include a plurality of third switches for connecting the plurality of current-voltage conversion circuits and the first storage and computing unit cross array and the second storage unit cross array, and are configured to control communication between the plurality of current-voltage conversion circuits and the first storage and computing unit cross array and the second storage unit cross array.

7. The neural network circuit of claim 6, wherein, The first computing circuit is further configured to implement a function of an analog-to-digital converter (ADC). The controller is configured to control the first group of switch circuits and the third group of switch circuits to be in a closed state, the first group of switch circuits in the closed state indicates that the first storage and computing unit cross array and the second storage unit cross array are in communication, and the third group of switch circuits in the closed state indicates that the first storage and computing unit cross array, the second storage unit cross array, and the plurality of current-voltage conversion circuits are in communication. The first computing circuit is configured to receive a fourth group of data through word lines of the first storage and computing unit cross array and the second storage unit cross array, obtain a fourth computing result according to the fourth group of data and fourth weights stored in the first storage and computing unit cross array and the second storage unit cross array, and the fourth weights are configured to indicate a number of bits to be shifted in a process of converting the fourth group of data into a digital signal, and the plurality of current-voltage conversion circuits are configured to perform nonlinear processing on the fourth computing result to obtain a conversion result of converting the fourth group of data into a digital signal.

8. The neural network circuit of claim 1, wherein, Each memory-computing unit in the first computing circuit cross array respectively implements the function of a digital-to-analog converter (DAC), including: The first memory-computing unit cross array is configured to receive a fifth group of data through word lines of the 1st to N-1th rows, and obtain a first calculation result according to fifth weights stored in the memory-computing units of the 1st to N-1th rows and the fifth group of data, wherein a word line of the Nth row in the first memory-computing unit cross array is configured to output a fifth calculation result, the fifth weights are configured to indicate a number of bits to be shifted in a process of converting the fifth group of data into an analog signal, and the fifth calculation result is configured to indicate a processing result after the fifth group of data is converted into the analog signal.

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