Display panel, display panel motherboard and display device

Abstract

The embodiment of the present application provides a display panel, a display panel motherboard and a display device, wherein the display panel comprises: a substrate; a plurality of first pads, the first pads being located on one side of the substrate; a plurality of second pads, the second pads being located on the same side of the substrate as the first pads; the maximum vertical distance between the first surface of the second pads and the target surface of the substrate being greater than the maximum vertical distance between the first surface of the first pads and the target surface of the substrate, the first surface of the first pads being the surface of the first pads away from the substrate, the first surface of the second pads being the surface of the second pads away from the substrate, and the target surface comprising the surface of the substrate away from or close to the first pads. The embodiment of the present application can ensure the normal display of the display panel and improve the yield rate of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a display panel, a display panel motherboard and a display device. Background Art

[0002] With the continuous development of display technology, the application scope of display panels is becoming more and more extensive, and people's requirements for display panels are also getting higher and higher. In particular, the display quality of display panels has always been one of the important indicators for consumers and panel manufacturers to measure the quality of display panels. However, the display panels in related technologies are prone to abnormal screen display under electrostatic interference, which affects the display quality and performance of the display panels. Summary of the invention

[0003] The embodiments of the present application provide a display panel, a display panel motherboard and a display device, which can solve the problem of abnormal screen display of the display panel and improve the yield rate of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a substrate; a plurality of first solder pads, the first solder pads being located on one side of the substrate; a plurality of second solder pads, the second solder pads and the first solder pads being located on the same side of the substrate; the maximum vertical distance between the first surface of the second solder pad and a target surface of the substrate is greater than the maximum vertical distance between the first surface of the first solder pad and the target surface of the substrate, the first surface of the first solder pad is a surface of the first solder pad away from the substrate, the first surface of the second solder pad is a surface of the second solder pad away from the substrate, and the target surface includes a surface of the substrate away from or close to the first solder pad.

[0005] According to an implementation of the first aspect of the present application, the second pad is electrically connected to an electrostatic release element for releasing the charge on the second pad.

[0006] In this way, by releasing the charge stored on the second pad in time, the hidden danger of the charge stored on the second pad damaging the electronic components in the display panel can be eliminated, the anti-static ability of the display panel is improved, and the stability of the circuit in the display panel is improved.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the electrostatic release element includes an electrostatic metal ring, and the electrostatic metal ring is arranged around the display panel.

[0008] In this way, since the electrostatic metal ring is arranged around the display panel, the electrostatic metal ring can isolate different display panels to achieve electrostatic shielding effect; on the other hand, the two ends of the electrostatic metal ring are electrically connected to form a loop, which is conducive to the flow and release of charges and can improve the electrostatic release ability of the electrostatic metal ring.

[0009] According to any of the aforementioned implementations of the first aspect of the present application, the display panel may further include a binding area, in which a third pad is provided; the second pad is electrically connected to the electrostatic release element via the third pad.

[0010] In this way, since the second pad is electrically connected to the third pad in the binding area, during the subsequent use of the display panel, the second pad can receive a stable voltage signal through the third pad bound to the flexible circuit board or the driving chip, so that the second pad maintains a stable potential, avoiding coupling between the second pad and other pads or signal lines to generate interference signals, thereby improving the stability of the circuit in the display panel.

[0011] According to any of the aforementioned implementations of the first aspect of the present application, the plurality of second pads are electrically connected to the same routing line, and the routing line is electrically connected to the third pad.

[0012] In this way, on the one hand, since the plurality of second pads are electrically connected to the same routing line, the charges on the plurality of second pads can flow between each other through the routing line, and the second pads storing less charge can share the charge on the second pads storing more charge, thereby ensuring the stability of the circuit in the display panel. On the other hand, compared to the method in which each second pad is connected to the third pad via an independent routing line, since the plurality of second pads are electrically connected to the same routing line, the number and length of the routing lines can be reduced, thus saving the wiring space of the display panel and reducing the production cost.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the plurality of first pads are arranged sequentially along the first direction, the plurality of first pads include M first pad groups, each first pad group includes at least one first pad, and M is a positive integer;

[0014] The second pad is located at least one of the following positions: between different first pad groups, on a side of a first first pad group away from a second first pad group, and on a side of a last first pad group away from a last second first pad group.

[0015] In this way, since the second pad is arranged between the first pads and / or on both sides of the first pad, even if the mask is bent toward the side close to the first pad, the mask will not contact the first pad, but will contact the second pad that is adjacent to the first pad and has a higher height, thereby preventing the charge from entering the circuit in the display panel through the first pad and damaging the electronic devices in the circuit, ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0016] According to any of the aforementioned implementations of the first aspect of the present application, the second pads and the first pad groups are alternately arranged in sequence along the first direction.

[0017] In this way, since second pads are provided on both sides of each first pad group, it can be ensured that the mask will not contact any first pad, thereby preventing charge from entering the circuit in the display panel through any first pad and damaging the electronic components in the circuit, thereby ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0018] According to any of the aforementioned embodiments of the first aspect of the present application, the display panel includes N metal layers stacked in sequence on one side of a substrate, and an insulating layer is arranged between adjacent metal layers, and the outer metal layer is the farthest from the substrate among the N metal layers; the first soldering pad includes i stacked and interconnected first sub-conductive film layers, the second soldering pad includes j stacked and interconnected second sub-conductive film layers, the i first sub-conductive film layers are respectively located in i metal layers among the N metal layers, the j second sub-conductive film layers are respectively located in j metal layers among the N metal layers, and one of the first sub-conductive film layers and one of the second sub-film layers are located in the outer metal layer; 1≤i≤N, 1≤j≤N, and i≤j, i, j, and N are all positive integers; the total thickness of the i first sub-conductive film layers perpendicular to the target plane is less than the total thickness of the j second sub-conductive film layers perpendicular to the target plane.

[0019] According to any of the aforementioned embodiments of the first aspect of the present application, i<j; N=4, the four metal layers are respectively a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, and the second metal layer is located on a side of the first metal layer away from the substrate, the third metal layer is located on a side of the second metal layer away from the substrate, and the fourth metal layer is located on a side of the third metal layer away from the substrate; i=2, the two first sub-conductive film layers are respectively located in the third metal layer and the fourth metal layer; j=3, or, j=4, two of the j second sub-conductive film layers are respectively located in the third metal layer and the fourth metal layer.

[0020] In this way, the first pad and the second pad can be prepared together when preparing the first metal layer, the second metal layer, the third metal layer and the fourth metal layer in the display area of ​​the display panel, so that no additional preparation process is added, which is conducive to the simplification of the display panel preparation process.

[0021] According to any of the aforementioned implementations of the first aspect of the present application, the display panel further includes a display area, and the display area includes a plurality of light-emitting elements;

[0022] The maximum vertical distance between the first surface of the second pad and the target surface of the substrate is smaller than the maximum vertical distance between the first surface of the light-emitting element and the target surface of the substrate. The first surface of the light-emitting element is the surface of the light-emitting element away from the substrate.

[0023] In this way, since the maximum vertical distance between the first surface of the second soldering pad and the target surface of the substrate is smaller than the maximum vertical distance between the first surface of the light-emitting element and the target surface of the substrate, that is, the height of the second soldering pad is smaller than the height of the light-emitting element, it is possible to avoid the distance between the mask and the display panel being too large, which is beneficial to ensuring the alignment accuracy between the opening on the mask and the position to be evaporated on the display panel, thereby ensuring the position accuracy of the device formed on the display panel based on the mask, and improving the yield rate of the display panel.

[0024] According to any of the aforementioned embodiments of the first aspect of the present application, the first pad is electrically connected to the electronic device in the display panel, and the second pad is not electrically connected to the electronic device in the display panel, and the electronic device includes at least one of the following items: a transistor, a capacitor, and a light-emitting element.

[0025] According to any of the aforementioned implementations of the first aspect of the present application, the first pad is electrically connected to the array substrate test circuit in the display panel.

[0026] In a second aspect, an embodiment of the present application provides a display panel motherboard, which includes: at least one display panel provided in the first aspect of the present application; an electrostatic release element, which is electrically connected to a second pad in the display panel and is used to release the charge on the second pad.

[0027] In a third aspect, an embodiment of the present application provides a display device, and the display device includes the display panel provided in the first aspect of the present application.

[0028] The display panel, display panel motherboard and display device of the embodiment of the present application, the display panel includes: a substrate; a plurality of first pads, the first pads are located on one side of the substrate; a plurality of second pads, the second pads and the first pads are located on the same side of the substrate; the maximum vertical distance between the first surface of the second pad and the target surface of the substrate is greater than the maximum vertical distance between the first surface of the first pad and the target surface of the substrate, the first surface of the first pad is the surface of the first pad away from the substrate, the first surface of the second pad is the surface of the second pad away from the substrate, and the target surface includes the surface of the substrate away from or close to the first pad. The inventor of the present application found that in the production process of the display panel, the electrostatic charge on the display panel is mainly generated by the contact friction between the display panel and the mask. Since the maximum vertical distance between the first surface of the second pad and the target surface of the substrate is greater than the maximum vertical distance between the first surface of the first pad and the target surface of the substrate, that is, the height of the second pad is higher than the height of the first pad, the mask will only contact the second pad with a higher height, but not the first pad, thereby avoiding the generation of charge due to contact between the mask and the first pad, and further avoiding the charge from entering the circuit in the display panel through the first pad and damaging the electronic devices in the circuit, thereby ensuring that the display panel can display normally and improving the yield rate of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application;

[0031] Figure 2 for Figure 1 A schematic cross-sectional view of the display panel along the AA' direction is shown;

[0032] Figure 3 Another schematic top view of a display panel provided in an embodiment of the present application;

[0033] Figure 4 A schematic top view of another display panel provided in an embodiment of the present application;

[0034] Figure 5 A schematic top view of another display panel provided in an embodiment of the present application;

[0035] Figure 6 A schematic top view of another display panel provided in an embodiment of the present application;

[0036] Figure 7 A schematic top view of another display panel provided in an embodiment of the present application;

[0037] Figure 8 A schematic top view of another display panel provided in an embodiment of the present application;

[0038] Fig. 9 A partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0039] Fig.10 Another partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of another partial cross-section of a display panel provided in an embodiment of the present application;

[0041] Fig.12 A schematic diagram of another partial cross-section of a display panel provided in an embodiment of the present application;

[0042] Fig.13 A schematic top view of another display panel provided in an embodiment of the present application;

[0043] Fig.14 for Fig.13 A schematic cross-sectional view of the display panel along the BB' direction is shown;

[0044] Fig.15 A schematic diagram of the structure of a display panel motherboard provided in an embodiment of the present application;

[0045] Fig.16 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0047] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0048] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0049] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0050] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0051] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the prior art:

[0052] As mentioned above, the inventors of the present application have discovered that the display panel in the related art is prone to abnormal screen display under electrostatic interference, which affects the display quality and performance of the display panel.

[0053] In order to solve the problem that the display panel is prone to screen display abnormality, the inventor of the present application first studied and analyzed the root causes of the above technical problems. The specific research and analysis process is as follows:

[0054] The inventors of the present application have discovered that a large amount of static electricity is generated during the production process of the display panel. The ways in which static electricity is generated may include, for example: static electricity generated by the transmission of the display panel during the production line flow, and / or static electricity generated by repeated alignment and contact between the mask and the display panel during the evaporation process. Since a high vacuum environment must be maintained during the evaporation process, it is usually impossible to eliminate the static electricity on the display panel by external force. As a result, due to the high height of some pads on the display panel (such as array substrate test pads, AT pads for short), static electricity will preferentially enter the circuit in the display panel through these pads, causing the electronic devices in the circuit to be damaged by static electricity burns, and then causing some interference signals to enter the data lines of the display panel through the damaged electronic devices, causing the display panel to have display abnormalities such as bright lines or dark lines.

[0055] In view of the above research findings of the inventors, the embodiments of the present application provide a display panel, a display panel motherboard and a display device, which can solve the technical problem in the related art that the display panel is prone to display abnormalities such as bright lines or dark lines.

[0056] The technical concept of the embodiment of the present application is that a second pad is set on the display panel. Since the maximum vertical distance between the first surface of the second pad and the target surface of the substrate is greater than the maximum vertical distance between the first surface of the first pad and the target surface of the substrate, that is, the height of the second pad is higher than the height of the first pad, the mask plate will contact the second pad with a higher height instead of the first pad, thereby avoiding the generation of charges due to the contact between the mask plate and the first pad, and further avoiding the charges from entering the circuit in the display panel through the first pad and damaging the electronic devices in the circuit, thereby ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0057] The following first introduces the display panel provided in the embodiment of the present application.

[0058] Figure 1 A schematic top view of a display panel provided in an embodiment of the present application. Figure 2 for Figure 1 The cross-sectional view of the display panel along the AA' direction is shown in FIG. Figure 1 and Figure 2 As shown, the display panel 10 provided in the embodiment of the present application includes: a substrate 100, a plurality of first pads 101 and a plurality of second pads 102. The second pads 102 and the first pads 101 are located on the same side of the substrate 100. The maximum vertical distance between the first surface of the second pad 102 and the target surface of the substrate 100 is greater than the maximum vertical distance between the first surface of the first pad 101 and the target surface of the substrate 100. The first surface of the first pad 101 is the surface of the first pad 101 away from the substrate 100 ( Figure 2 The first surface of the second pad 102 is the surface of the second pad 102 away from the substrate 100 ( Figure 2 The target surface includes the surface of the substrate 100 away from the first pad 101 ( Figure 2 The surface 100a shown in FIG. 1 or the surface of the substrate 100 close to the first pad 101 ( Figure 2 Surface 100b shown).

[0059] In the embodiment of the present application, since the maximum vertical distance between the first surface of the second pad 102 and the target surface of the substrate 100 is greater than the maximum vertical distance between the first surface of the first pad 101 and the target surface of the substrate 100, that is, the height of the second pad 102 is higher than the height of the first pad 101, the mask plate will contact the second pad 102 with a higher height instead of the first pad 101, thereby avoiding the generation of charges due to the contact between the mask plate and the first pad 101, and further avoiding the charges from entering the circuit in the display panel 10 through the first pad 101 and damaging the electronic devices in the circuit, thereby ensuring that the display panel 10 can display normally and improving the yield rate of the display panel 10.

[0060] According to some embodiments of the present application, optionally, the electronic device may include at least one of the following items: a transistor, a capacitor, and a light-emitting element.

[0061] It is easy to understand that the first pad 101 can be electrically connected to the electronic device in the display panel 10, and the second pad 102 can be not electrically connected to the electronic device in the display panel 10, so as to avoid the charge from entering the circuit in the display panel 10 through the second pad 102 and damaging the electronic device in the circuit, and ensure that the display panel 10 can display normally. Exemplarily, the first pad 101 can be electrically connected to the array substrate test circuit (AT test circuit) in the display panel 10, that is, the first pad 101 can be an AT test pad. The main function of the AT test pad is to receive a test signal from an external device (such as a lighting machine PG) during the array substrate test process, and then pass the test signal to the AT test circuit to implement the array substrate test. Of course, it should be noted that the first pad 101 can also be other types of pads, such as the first pad 101 can be a pad bound to the flexible circuit board on the display panel 10, and the first pad 101 can be a pad bound to the driver chip on the display panel 10, and the embodiment of the present application is not limited to this.

[0062] like Figure 3 As shown, according to some embodiments of the present application, optionally, the second pad 102 may be electrically connected to an electrostatic release element 20 , and the electrostatic release element 20 is used to release the charge on the second pad 102 .

[0063] In this way, the charge stored on the second pad 102 is released in time through the electrostatic release element 20, which can eliminate the hidden danger of the charge stored on the second pad 102 damaging the electronic components in the display panel 10, improve the anti-static ability of the display panel 10, and improve the stability of the circuit in the display panel 10.

[0064] like Figure 4As shown, according to some embodiments of the present application, optionally, the electrostatic release element 20 includes an electrostatic metal ring 200, and the electrostatic metal ring 200 is arranged around the display panel 10. Specifically, an electrostatic metal ring 200 can be arranged on the outside of the display panel 10, and the electrostatic metal ring 200 forms a loop around one or more circles of the display panel 10. Optionally, after the display panel 10 is tested, that is, before the display panel 10 leaves the factory, the electrostatic metal ring 200 can be cut off along the thickness direction of the display panel 10, which is conducive to the narrow frame design. Of course, in other examples, the electrostatic metal ring 200 may not be cut off, but the electrostatic metal ring 200 may be retained on the display panel 10, and the embodiments of the present application are not limited to this.

[0065] In this way, since the electrostatic metal ring 200 is arranged around the display panel 10, the electrostatic metal ring 200 can isolate different display panels 10 to achieve an electrostatic shielding effect; on the other hand, the two ends of the electrostatic metal ring 200 are electrically connected to form a loop, which is conducive to the flow and release of charges, and can improve the electrostatic release ability of the electrostatic metal ring 200.

[0066] Optionally, the electrostatic metal ring 200 may include a layer of metal or multiple layers of metal. When the electrostatic metal ring 200 includes multiple layers of metal, the multiple layers of metal are electrically connected to each other (eg, electrically connected to each other through vias) to form the electrostatic metal ring 200, thereby improving the electrostatic discharge capability of the electrostatic metal ring 200.

[0067] like Figure 5 As shown, according to some embodiments of the present application, optionally, the display panel 10 may further include a binding area NA1, and the binding area NA1 is provided with a third pad 103, and the second pad 102 may be electrically connected to the electrostatic release element 20 through the third pad 103. The third pad 103 may be understood as a pad bound to a flexible circuit board or a driver chip. During the use of the display panel, the third pad 103 may receive a fixed voltage signal from the driver chip.

[0068] In this way, since the second pad 102 is electrically connected to the third pad 103 of the binding area NA1, during the subsequent use of the display panel 10, the second pad 102 can receive a stable voltage signal through the third pad 103 bound to the flexible circuit board or the driving chip, so that the second pad 102 maintains a stable potential, avoiding the coupling between the second pad 102 and other pads or signal lines to generate interference signals, thereby improving the stability of the circuit in the display panel 10.

[0069] For example, due to the small spacing, a capacitor may be formed between the second pad 102 and other pads (such as the first pad 101) or the signal line. When the potential on other pads or signal lines jumps (such as a high level jumps to a low level, or a low level jumps to a high level), the second pad 102, which is the other plate of the capacitor, will also change its potential, which is not conducive to the stability of the display panel 10. By applying a stable potential to the second pad 102, the second pad 102 can be at a stable potential regardless of whether the potential on other pads or signal lines jumps, thereby improving the stability of the circuit in the display panel 10.

[0070] Continue to see Figure 5 According to some embodiments of the present application, optionally, multiple second pads 102 can be electrically connected to the same routing line s, and routing line s can be electrically connected to the third pad 103. That is, multiple second pads 102 can be electrically connected to each other through the same routing line s, and electrically connected to the third pad 103 through the routing line s. Here, it should be noted that routing line s can be electrically connected to one third pad 103, and routing line s can also be electrically connected to multiple third pads 103. The number of third pads 103 can be flexibly set according to actual conditions, and the embodiments of the present application do not limit this. In addition, the third pad 103 can be an additional pad on the basis of the original pad in the binding area, or it can be an idle pad in the binding area, and the embodiments of the present application do not limit this.

[0071] In this way, on the one hand, since the plurality of second pads 102 are electrically connected to the same routing line s, the charges on the plurality of second pads 102 can flow between each other through the routing line s, and the second pads 102 storing less charge can share the charges on the second pads 102 storing more charge, thereby ensuring the stability of the display panel 10. On the other hand, compared with the manner in which each second pad 102 is connected to the third pad 103 through an independent routing line, since the plurality of second pads 102 are electrically connected to the same routing line s, the number and length of the routing lines can be reduced, thereby saving the wiring space of the display panel 10 and reducing the production cost.

[0072] like Figure 6 As shown, according to some embodiments of the present application, optionally, the plurality of first pads 101 may be arranged along a first direction (eg Figure 6The plurality of first pads 101 may include M first pad groups h1 to hn, each first pad group hx may include at least one first pad 101, x, n and M are positive integers, and hx is any one of h1 to hn. The second pad 102 is located at least one of the following positions: between different first pad groups hx, the first first pad group h1 is away from the side of the second first pad group h2, and the last first pad group hn is away from the side of the last second first pad group hn-1. The spacing between the second pad 102 and the first pad 101, the size and number of the second pad 102 can be flexibly set according to actual conditions, and the embodiments of the present application are not limited to this. However, it should be noted that the spacing between the second pad 102 and the first pad 101 should be kept small to avoid the mask from contacting the first pad 101 when it bends toward the side close to the first pad 101.

[0073] In this way, since the second pad 102 is arranged between the first pad 101 and / or on both sides of the first pad 101, even if the mask is bent toward the side close to the first pad 101, the mask will not contact the first pad 101, but will contact the second pad 102 which is adjacent to the first pad 101 and has a higher height, thereby preventing the charge from entering the circuit in the display panel 10 through the first pad 101 and damaging the electronic devices in the circuit, ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0074] like Figure 7 As shown, in some specific examples, each first pad group hx may include a plurality of first pads 101, for example, three first pads 101. The second pad 102 may be connected to the first pad group hx along a first direction (eg, Figure 7 That is, the plurality of first pads 101 may form a first pad group hx, and the second pads 102 are disposed on both sides of each first pad group hx.

[0075] In this way, since second pads 102 are provided on both sides of each first pad group hx, it can be ensured that the mask will not contact any first pad 101, thereby preventing charges from entering the circuit in the display panel through any first pad 101 and damaging the electronic components in the circuit, thereby ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0076] like Figure 8 As shown, in some other specific examples, Figure 7 Different from the example shown, each first pad group hx may include only one first pad 101. The second pad 102 may be aligned with the first pad 101 along a first direction (eg, Figure 8The first pads 101 are arranged alternately in the X direction as shown in the figure, and the second pads 102 are arranged on both sides of each first pad 101. In this way, since the second pads 102 are arranged on both sides of each first pad 101, it can be ensured that the mask will not contact any of the first pads 101, thereby preventing the electric charge from entering the circuit in the display panel through any of the first pads 101 and damaging the electronic devices in the circuit, ensuring that the display panel can display normally and improving the yield rate of the display panel.

[0077] As mentioned above, the height of the second pad 102 is higher than the height of the first pad 101. For ease of understanding, some specific implementations of achieving the height of the second pad 102 being higher than the height of the first pad 101 are described below.

[0078] like Fig. 9 As shown, according to some embodiments of the present application, optionally, the display panel 10 may include N metal layers m1-mN stacked on one side of the substrate 100, and insulating layers fm1-fmM are arranged between adjacent metal layers, where N and M are both positive integers. The outer metal layer mN is the farthest from the substrate 100 among the N metal layers m1-mN.

[0079] The first pad 101 may include i stacked and interconnected first sub-conductive film layers 1011, and the second pad 102 may include j stacked and interconnected second sub-conductive film layers 1021, i first sub-conductive film layers 1011 are respectively located at i metal layers among N metal layers m1 to mN, and j second sub-conductive film layers 1021 are respectively located at j metal layers among N metal layers m1 to mN. That is, the first pad 101 may be formed by stacking i metal layers among N metal layers m1 to mN and insulating layers between the i metal layers, and the second pad 102 may be formed by stacking j metal layers among N metal layers m1 to mN and insulating layers between the j metal layers. Wherein, 1≤i≤N, 1≤j≤N, and i≤j. It is easy to understand that one of the i first sub-conductive film layers 1011 is located in the outer metal layer mN, and one of the j second sub-conductive film layers 1021 is also located in the outer metal layer mN to ensure that the exposed surfaces of the first pad 101 and the second pad 102 are conductive metals.

[0080] like Fig.10As shown, in some specific examples, optionally, i=j. That is, the first pad 101 may include i first sub-conductive film layers 1011, and the second pad 102 may include i second sub-conductive film layers 1021. Further, the i metal layers where the i first sub-conductive film layers 1011 are located may be the same as the i metal layers where the i second sub-conductive film layers 1021 are located. In other words, the first pad 101 and the second pad 102 may be stacked with the same metal layers, but it is necessary to ensure that the thickness of at least one metal layer in the second pad 102 is greater than the thickness of the corresponding metal layer in the first pad 101, so as to ensure that the total thickness of the i first sub-conductive film layers on the target plane perpendicular to the substrate 100 is less than the total thickness of the i second sub-conductive film layers on the target plane perpendicular to the substrate 100.

[0081] For example, the first pad 101 includes two first sub-conductive film layers 1011, and the second pad 102 includes two second sub-conductive film layers 1021. The first first sub-conductive film layer 1011 and the first second sub-conductive film layer 1021 are located in the same metal layer. The second first sub-conductive film layer 1011 and the second second sub-conductive film layer 1021 are located in the same metal layer. In order to ensure that the height of the second pad 102 is higher than the height of the first pad 101, the thickness of the first first sub-conductive film layer 1011 can be the same as the thickness of the first second sub-conductive film layer 1021, and the thickness of the second first sub-conductive film layer 1011 can be less than the thickness of the second second sub-conductive film layer 1021. Of course, the thickness of the second first sub-conductive film layer 1011 can also be the same as the thickness of the second second sub-conductive film layer 1021, and the thickness of the first first sub-conductive film layer 1011 can be less than the thickness of the first second sub-conductive film layer 1021. Of course, other methods may be used to ensure that the height of the second pad 102 is higher than the height of the first pad 101 .

[0082] like Fig.11 As shown, Fig.10Different from the example shown, in some other specific examples, i<j. That is, the number of the first sub-conductive film layer 1011 in the first pad 101 is less than the number of the second sub-conductive film layer 1021 in the second pad 102. Specifically, the display panel 10 may include three metal layers m1-m3 stacked on one side of the substrate 100, which are the first metal layer m1, the second metal layer m2 and the third metal layer m3. Among them, the second metal layer m2 is located on the side of the first metal layer m1 away from the substrate 100, the third metal layer m3 is located on the side of the second metal layer m2 away from the substrate 100, and the fourth metal layer m4 is located on the side of the third metal layer m3 away from the substrate 100. The display panel 10 may also include insulating layers fm1 and fm2 arranged between adjacent metal layers, which are the first insulating layer fm1 arranged between the first metal layer m1 and the second metal layer m2, and the second insulating layer fm2 arranged between the second metal layer m2 and the third metal layer m3. The first pad 101 may include one first sub-conductive film layer 1011, and the first sub-conductive film layer 1011 may be located on the third metal layer m3. The second pad 102 may include two second sub-conductive film layers 1021 or three second sub-conductive film layers 1021. In the case where the second pad 102 includes two second sub-conductive film layers 1021, one of the second sub-conductive film layers 1021 may be located on the third metal layer m3, and the other second sub-conductive film layer 1021 may be located on the first metal layer m1 or the second metal layer m2. In the case where the second pad 102 includes three second sub-conductive film layers 1021, the three second sub-conductive film layers 1021 are respectively located on the first metal layer m1, the second metal layer m2 and the third metal layer m3, and the three second sub-conductive film layers 1021 are electrically connected through vias.

[0083] In this way, since the number of first sub-conductive film layers 1011 in the first soldering pad 101 is smaller than the number of second sub-conductive film layers 1021 in the second soldering pad 102, it can be ensured that the total thickness of i first sub-conductive film layers on the target plane perpendicular to the substrate 100 is smaller than the total thickness of j second sub-conductive film layers on the target plane perpendicular to the substrate 100.

[0084] like Fig.12 As shown, Fig.11Different from the example shown, in some specific examples, the display panel 10 may include four metal layers m1 to m4 stacked on one side of the substrate 100, namely, a first metal layer m1, a second metal layer m2, a third metal layer m3 and a fourth metal layer m4. Among them, the second metal layer m2 is located on the side of the first metal layer m1 away from the substrate 100, the third metal layer m3 is located on the side of the second metal layer m2 away from the substrate 100, and the fourth metal layer m4 is located on the side of the third metal layer m3 away from the substrate 100. The display panel 10 may also include insulating layers fm1 to fm3 disposed between adjacent metal layers, namely, a first insulating layer fm1 disposed between the first metal layer m1 and the second metal layer m2, a second insulating layer fm2 disposed between the second metal layer m2 and the third metal layer m3, and a third insulating layer fm3 disposed between the third metal layer m3 and the fourth metal layer m4. The first pad 101 may include two first sub-conductive film layers 1011, one of which may be located on the third metal layer m3, the other first sub-conductive film layer 1011 may be located on the fourth metal layer m4, and the two first sub-conductive film layers 1011 are electrically connected through vias. The second pad 102 may include three second sub-conductive film layers 1021 or four second sub-conductive film layers 1021. In the case where the second pad 102 includes three second sub-conductive film layers 1021, the first second sub-conductive film layer 1021 may be located on the fourth metal layer m4, the second second sub-conductive film layer 1021 may be located on the third metal layer m3, the third second sub-conductive film layer 1021 may be located on the first metal layer m1 or the second metal layer m2, and the three second sub-conductive film layers 1021 are electrically connected through vias. When the second pad 102 includes four second sub-conductive film layers 1021, the four second sub-conductive film layers 1021 are respectively located on the first metal layer m1, the second metal layer m2, the third metal layer m3 and the fourth metal layer m4, and the four second sub-conductive film layers 1021 are electrically connected through vias.

[0085] In this way, since the number of first sub-conductive film layers 1011 in the first soldering pad 101 is smaller than the number of second sub-conductive film layers 1021 in the second soldering pad 102, it can be ensured that the total thickness of i first sub-conductive film layers on the target plane perpendicular to the substrate 100 is smaller than the total thickness of j second sub-conductive film layers on the target plane perpendicular to the substrate 100.

[0086] In some specific examples, optionally, the first metal layer m1 may be a gate metal layer, in which a gate of a transistor in the display panel 10 may be prepared. The second metal layer m2 may be a capacitor plate metal layer, in which one of the plates of a capacitor in the display panel 10 may be prepared. The third metal layer m3 may be a source-drain metal layer, in which a source metal and / or a drain metal of a transistor in the display panel 10 may be prepared. The fourth metal layer m4 may be a routing metal layer, in which a signal routing in the display panel 10, such as a positive polarity power signal routing, may be prepared.

[0087] In this way, the first pad 101 and the second pad 102 can be prepared together when preparing the first metal layer m1, the second metal layer m2, the third metal layer m3 and the fourth metal layer m4 in the display area of ​​the display panel 10, so that no additional preparation process is added, which is conducive to the simplification of the display panel preparation process.

[0088] Continue to see Fig.12 According to some embodiments of the present application, optionally, the edges of the second sub-conductive film layer 1021 located on the first metal layer m1, the second sub-conductive film layer 1021 located on the second metal layer m2, the first sub-conductive film layer 1011 located on the third metal layer m3, and the second sub-conductive film layer 1021 located on the third metal layer m3 are all covered by corresponding insulating layers to prevent the edges of the first sub-conductive film layer 1011 and the second sub-conductive film layer 1021 from being exposed. Specifically, the edge of the second sub-conductive film layer 1021 located on the first metal layer m1 is covered by the first insulating layer fm1, the edge of the second sub-conductive film layer 1021 located on the second metal layer m2 is covered by the second insulating layer fm2, and the edge of the first sub-conductive film layer 1011 located on the third metal layer m3 and the edge of the second sub-conductive film layer 1021 located on the third metal layer m3 are covered by the third insulating layer fm3.

[0089] Fig.13 This is another schematic top view of a display panel provided in an embodiment of the present application. Fig.14 for Fig.13 The cross-sectional view of the display panel along the BB' direction is shown. Fig.13 and Fig.14 As shown, according to some embodiments of the present application, optionally, the display panel 10 may further include a display area AA, and the display area AA may include a plurality of light-emitting elements 104. The maximum vertical distance between the first surface of the second pad 102 and the target surface of the substrate 100 is less than the maximum vertical distance between the first surface of the light-emitting element 104 and the target surface of the substrate 100. The first surface of the light-emitting element 104 is the surface of the light-emitting element 104 away from the substrate 100 ( Fig.14The target surface of the substrate 100 includes the surface of the substrate 100 away from the light emitting element 104 ( Fig.14 The surface 100a shown in FIG. 100a) or the surface of the substrate 100 close to the light emitting element 104 ( Fig.14 Surface 100b shown).

[0090] In this way, since the maximum vertical distance between the first surface of the second soldering pad 102 and the target surface of the substrate 100 is smaller than the maximum vertical distance between the first surface of the light-emitting element 104 and the target surface of the substrate 100, that is, the height of the second soldering pad 102 is smaller than the height of the light-emitting element 104, it is possible to avoid the distance between the mask and the display panel 10 being too large, which is beneficial to ensuring the alignment accuracy between the opening on the mask and the position to be evaporated on the display panel, thereby ensuring the position accuracy of the device formed on the display panel based on the mask, thereby improving the yield rate of the display panel.

[0091] Based on the display panel 10 provided in the above embodiment, the present application also provides a display panel motherboard. Fig.15 As shown, the display panel motherboard 1 provided in the embodiment of the present application includes at least one display panel 10 provided in the above embodiment and an electrostatic release element 20, and the electrostatic release element 20 is electrically connected to the second pad 102 in the display panel 10 for releasing the charge on the second pad 102.

[0092] The electrostatic discharge element 20 is mainly used to release static electricity on the display panel 10 during the production process of the display panel 10. Therefore, according to some embodiments of the present application, optionally, after the display panel 10 is tested, that is, before the display panel 10 is shipped, the electrostatic discharge element 20 is removed along the thickness direction of the display panel 10, thereby facilitating a narrow frame design.

[0093] Based on the display panel provided in the above embodiment, the present application also provides a display device accordingly. Fig.16 As shown, the display device 1000 may include a device body 20' and the display panel 10 in the above embodiment, and the display panel 10 covers the device body 20'. The device body 20' may be provided with various devices, such as sensor devices, processing devices, etc., which are not limited here. The display device 1000 may specifically be a device with a display function, such as a mobile phone, a computer, a tablet computer, a digital camera, a television, an electronic paper, etc., which are not limited here.

[0094] It should be clear that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For the display panel embodiment and the display device embodiment, the relevant parts can refer to the description part of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the specific structure described above and shown in the figures. Those skilled in the art can make various changes, modifications and additions after understanding the spirit of the present application. In addition, for the sake of brevity, a detailed description of the known technology is omitted here.

[0095] Those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on the study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to indicate names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that: include: substrate; a plurality of first pads, wherein the first pads are located on one side of the substrate; a plurality of second pads, wherein the second pads and the first pads are located on the same side of the substrate; The maximum vertical distance between the first surface of the second pad and the target surface of the substrate is greater than the maximum vertical distance between the first surface of the first pad and the target surface of the substrate, the first surface of the first pad is the surface of the first pad away from the substrate, the first surface of the second pad is the surface of the second pad away from the substrate, and the target surface includes the surface of the substrate away from or close to the first pad; The second pad is electrically connected to an electrostatic discharge element for releasing the charge on the second pad.

2. The display panel according to claim 1, wherein: The electrostatic discharge element includes an electrostatic metal ring, and the electrostatic metal ring is arranged around the display panel.

3. The display panel according to claim 1, wherein: The display panel further includes a binding area, wherein the binding area is provided with a third pad; The second pad is electrically connected to the electrostatic discharge element through the third pad.

4. The display panel according to claim 3, wherein: The plurality of second pads are electrically connected to a same trace, and the trace is electrically connected to the third pad.

5. The display panel according to claim 1, wherein: The plurality of first pads are arranged along a first direction, the plurality of first pads include M first pad groups, each first pad group includes at least one first pad, and M is a positive integer; The second pad is located at least one of the following positions: between different first pad groups, on a side of a first first pad group away from a second first pad group, and on a side of a last first pad group away from a last second first pad group.

6. The display panel according to claim 5, wherein: The second pads and the first pad groups are alternately arranged in sequence along the first direction.

7. The display panel according to claim 1, wherein: The display panel includes N metal layers stacked on one side of the substrate, with an insulating layer provided between adjacent metal layers, and the outer metal layer is the one farthest from the substrate among the N metal layers; The first pad includes i stacked and interconnected first sub-conductive film layers, the second pad includes j stacked and interconnected second sub-conductive film layers, the i first sub-conductive film layers are respectively located in i metal layers among the N metal layers, the j second sub-conductive film layers are respectively located in j metal layers among the N metal layers, and one of the first sub-conductive film layers and one of the second sub-conductive film layers are located in the outer metal layer; 1≤i≤N, 1≤j≤N, and i≤j, i, j, and N are all positive integers; The total thickness of the i first sub-conductive film layers perpendicular to the target plane is less than the total thickness of the j second sub-conductive film layers perpendicular to the target plane.

8. The display panel according to claim 7, wherein: i<j.

9. The display panel according to claim 8, wherein: N=4, the four metal layers are respectively a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, and the second metal layer is located on the side of the first metal layer away from the substrate, the third metal layer is located on the side of the second metal layer away from the substrate, and the fourth metal layer is located on the side of the third metal layer away from the substrate.

10. The display panel according to claim 9, wherein: i=2, and the two first sub-conductive film layers are respectively located in the third metal layer and the fourth metal layer.

11. The display panel according to claim 9 or 10, characterized in that: j=3, or j=4, and two of the j second sub-conductive film layers are located in the third metal layer and the fourth metal layer respectively.

12. The display panel according to claim 1, wherein The display panel further includes a display area, wherein the display area includes a plurality of light-emitting elements; The maximum vertical distance between the first surface of the second pad and the target surface of the substrate is smaller than the maximum vertical distance between the first surface of the light-emitting element and the target surface of the substrate. The first surface of the light-emitting element is the surface of the light-emitting element away from the substrate.

13. The display panel according to claim 1, wherein The first pad is electrically connected to an electronic device in the display panel, and the second pad is not electrically connected to an electronic device in the display panel. The electronic device includes at least one of the following items: a transistor, a capacitor, and a light-emitting element.

14. The display panel according to claim 1, wherein The first pad is electrically connected to an array substrate test circuit in the display panel.

15. A display panel motherboard, characterized in that: include: At least one display panel according to any one of claims 1 to 14; An electrostatic release element is electrically connected to the second pad in the display panel and is used to release the charge on the second pad.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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