A fan-out packaging structure and construction method thereof

Abstract

The present invention relates to the field of advanced semiconductor packaging technology and proposes a fan-out packaging structure and its construction method. The structure comprises: a wiring layer; a chip having first to sixth sides, the first side being connected to the wiring layer; a metal shielding layer covering and contacting the second to sixth sides of the chip; and a metal heat dissipation layer connected to the metal shielding layer.

Description

Technical Field

[0001] The present invention generally relates to the field of advanced semiconductor packaging technology. Specifically, the present invention relates to a fan-out packaging structure and a construction method thereof. Background Art

[0002] With the advent of the 5G era, the application of high-frequency, high-power electronic devices is becoming increasingly common. However, for traditional packaging structures, the high frequency and high power characteristics of these high-frequency, high-power electronic devices will lead to increasingly prominent electronic device anomalies such as electromagnetic interference and heat generation. This will not only affect product performance but also severely shorten its service life, thereby affecting its reliability. Summary of the Invention

[0003] To at least partially solve the above-mentioned problems in the prior art, the present invention proposes a fan-out packaging structure that is well suited for high-frequency and high-power electronic devices. The structure includes:

[0004] Wiring layer;

[0005] A chip comprising a first surface to a sixth surface, wherein the first surface is connected to the wiring layer;

[0006] a metal shielding layer, which is in contact with the second to sixth surfaces of the chip; and

[0007] A metal heat dissipation layer is connected to the metal shielding layer.

[0008] In one embodiment of the present invention, the wiring layer includes a multi-layer wiring layer, and the multi-layer wiring layer includes:

[0009] an upper wiring layer, comprising a passivation layer, the passivation layer being in contact with the first surface of the chip and having a passivation layer opening;

[0010] a middle wiring layer, comprising a metal wiring layer, wherein the metal wiring layer is connected to the chip through the passivation layer opening; and

[0011] The lower wiring layer includes a metal pad, which is arranged on the outside of the metal wiring layer and is electrically connected to the chip through the metal wiring layer.

[0012] In one embodiment of the present invention, the fan-out packaging structure further includes solder balls, and the solder balls are arranged on the metal pads.

[0013] In one embodiment of the present invention, it is provided that the substrate material of the chip includes gallium arsenide or gallium nitride.

[0014] In one embodiment of the present invention, it is provided that the thickness of the chip is less than 100 μm.

[0015] In one embodiment of the present invention, the fan-out packaging structure further includes:

[0016] heat sink; and

[0017] Thermally conductive adhesive connects the heat sink and the metal heat dissipation layer.

[0018] In one embodiment of the present invention, it is stipulated that the fan-out packaging structure also includes a plastic encapsulation material, which is filled between the chip and the metal heat dissipation layer, the plastic encapsulation material covers the chip, a plastic encapsulation layer opening is formed on the plastic encapsulation material, and the metal heat dissipation layer and the thermal conductive adhesive are formed in the plastic encapsulation layer opening.

[0019] The present invention also provides a method for constructing the fan-out packaging structure, characterized by comprising the following steps:

[0020] Providing a first carrier, covering the upper surface of the first carrier with a temporary adhesive layer, and arranging a substrate on the temporary adhesive layer;

[0021] constructing a substrate opening on the substrate so as to expose the upper surface of the temporary adhesive layer;

[0022] arranging the chip on the temporary adhesive layer;

[0023] constructing the metal shielding layer;

[0024] Filling the opening of the substrate with a molding compound to form a molding layer, wherein the upper surface of the molding layer is flush with the upper surface of the substrate;

[0025] Constructing the plastic sealing layer opening on the plastic sealing layer so as to expose the back side of the chip from the plastic sealing layer;

[0026] constructing the metal heat dissipation layer, wherein the metal heat dissipation layer contacts and communicates with the metal shielding layer on the back side of the chip;

[0027] Arranging a temporary bonding layer and a second carrier;

[0028] Removing the first carrier and the temporary adhesive layer, and constructing the multi-layer wiring layer and solder balls below the chip, wherein the uppermost layer of the multi-layer wiring layer is a passivation layer, and the passivation layer is constructed with a passivation layer opening, and the solder balls are arranged on the metal pads of the lowermost layer of the multi-layer wiring layer;

[0029] removing the temporary bonding layer and the second carrier; and

[0030] Slicing is performed, the thermal conductive adhesive is filled and the heat sink is covered.

[0031] In one embodiment of the present invention, the material of the substrate includes:

[0032] semiconductor materials, including silicon, germanium, gallium arsenide, and indium phosphide; and

[0033] Electrically non-conductive materials, including glass, plastic, and sapphire wafers.

[0034] The present invention has at least the following beneficial effects: By connecting the electromagnetic shielding layer and the metal heat dissipation layer, the present invention can achieve electromagnetic shielding on all five sides of the chip and highly efficient heat conduction on all five sides of the chip, effectively shielding electrical interference between device chips while also significantly improving the heat dissipation efficiency of the overall structure. Furthermore, the present invention can implement multi-chip system-level fan-out packaging, utilizing substrate grooves to reduce chip offset during surface mount packaging, thereby improving routing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To further illustrate the advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings depict only typical embodiments of the present invention and are not to be considered as limiting the scope of the present invention. In the drawings, for clarity, identical or corresponding components will be represented by the same or similar reference numerals.

[0036] Figure 1 A schematic structural diagram of a fan-out packaging structure in one embodiment of the present invention is shown.

[0037] Figure 2 A schematic flow chart of a method for constructing a fan-out packaging structure in one embodiment of the present invention is shown.

[0038] Figure 3-14 A schematic structural diagram of the process of constructing a fan-out packaging structure in one embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] It should be noted that the components in the drawings may be shown exaggeratedly for the sake of illustration and are not necessarily correct to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.

[0040] In the present invention, unless otherwise specified, the phrases "disposed on," "disposed above," and "disposed above" do not exclude the presence of intermediate components. Furthermore, "disposed on or above" merely indicates the relative positional relationship between two components and, in certain circumstances, such as after reversing the product orientation, can be converted to "disposed below or below," and vice versa.

[0041] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0042] In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the presence of multiple elements.

[0043] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added according to the needs of the specific scenario. In addition, unless otherwise stated, the features of different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or description of this application.

[0044] It should also be noted that, within the scope of the present invention, terms such as "same," "equal," and "equal to" do not imply absolute equality of values, but rather allow for a certain reasonable error. In other words, such terms also encompass "substantially the same," "substantially equal," and "substantially equal." Similarly, in the present invention, terms such as "perpendicular to" and "parallel to" indicating direction also encompass the meaning of "substantially perpendicular to" and "substantially parallel to."

[0045] In addition, the numbering of the steps of the methods of the present invention does not limit the order in which the steps are to be performed. Unless otherwise specified, the steps of the methods may be performed in different orders.

[0046] The present invention will be further described below with reference to the accompanying drawings in conjunction with specific embodiments.

[0047] Figure 1 FIG. 1 shows a schematic diagram of a fan-out packaging structure in one embodiment of the present invention. Figure 1 As shown, the structure may include: solder balls 101 , multi-layer wiring layers 102 , chips 103 , metal shielding layers 104 , metal heat dissipation layers 105 , thermal conductive adhesive 106 , heat sinks 107 and molding compound 108 .

[0048] The solder balls 101 may be arranged on the metal pads of the lowest layer of the multi-layer wiring layer 102 to achieve electrical connection with the metal wiring layers within the multi-layer wiring layer 102 .

[0049] The multilayer wiring layer 102 may include a passivation layer, a metal wiring layer, and a metal pad. The passivation layer is located at the topmost layer of the multilayer wiring layer and is configured with a passivation layer opening. The metal wiring layer is located in the middle layer of the multilayer wiring layer and includes one or more layers of metal conductors and an insulating medium disposed between the metal conductors. The conductors in the metal wiring layer can be electrically connected to the chip pad on the lower surface of the chip 103 and the metal shielding layer 104 through the passivation layer opening. The metal pad is located at the bottommost layer of the multilayer wiring layer and can be arranged on the solder ball 101.

[0050] The number of chips 103 can be one or more, and the types of chips 103 can be one or more. The substrate material of chip 103 can be gallium arsenide (GaAs) or gallium nitride (GaN). The thickness of chip 103 can be less than 100 μm. Chip 103 includes first to sixth sides, wherein the first side has a chip pad and is connected to the multilayer wiring layer 102, and the second to sixth sides are covered by a metal shielding layer 104. Herein, the term "first to sixth sides" refers to the six faces of the cube formed by the chip.

[0051] The metal shielding layer 104 is arranged above the chip 103 and covers and contacts the second to sixth surfaces of the chip.

[0052] The metal heat dissipation layer 105 is arranged above the metal shielding layer 104 and is in contact with and connected to the metal shielding layer 104 .

[0053] The thermal conductive adhesive 106 and the heat sink 107 are arranged above the metal heat dissipation layer 105. When the high-frequency and high-power electronic device is working, the heat generated by the chip 103 is conducted out through the metal shielding layer 104 and the metal heat dissipation layer 105, and further dissipated through the thermal conductive adhesive 106 and the heat sink 107.

[0054] The molding compound 108 is filled in the gaps between the chips 103 and the metal heat dissipation layer 105 .

[0055] When high-frequency, high-power electronic devices are working, this technical solution can achieve electromagnetic shielding of the chip 103 on five sides by connecting the metal shielding layer 104 and the metal heat dissipation layer 105. The electromagnetic signal emitted by the chip 103 is only transmitted to the multi-layer wiring layer 102 through the first side, which can effectively avoid electromagnetic interference between multiple chips 103 and can also achieve high-efficiency heat conduction on the five sides of the chip 103, thereby improving heat dissipation efficiency.

[0056] Figure 2 FIG. 1 is a flow chart showing a method for constructing a fan-out packaging structure according to an embodiment of the present invention. Figure 2 As shown, the method may include the following steps:

[0057] Step 100: Figure 3 As shown, in this step, a first carrier 301 can be provided, a temporary adhesive layer 302 is covered on the upper surface of the first carrier 301, and a substrate 303 is arranged on the temporary adhesive layer 302. In an embodiment of the present invention, the substrate 303 can be a silicon wafer or any other material, for example, including a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc.; alternatively, the substrate can also be made of electrically non-conductive materials such as glass, plastic, or sapphire wafers. The temporary adhesive layer 302 can be a thermoplastic or thermosetting organic material, or an inorganic material containing components such as Cu, Ni, Cr, Co, etc. The temporary adhesive layer 302 can be removed by heating, mechanical, chemical, laser, freezing, etc.

[0058] Step 200: Figure 4 As shown, in this step, a substrate opening 401 may be formed on the substrate 303 so as to expose the upper surface of the temporary adhesive layer 302 .

[0059] Step 300: Figure 5 As shown, in this step, one or more chips 103 can be arranged on the upper surface of the temporary adhesive layer 302. The chips 103 can be of one or more types, and the substrate material of the chips 103 can be gallium arsenide (GaAs) or gallium nitride (GaN). The thickness of the chips 103 can be less than 100 μm. The technical solution of the present invention can achieve fan-out packaging at the multi-chip system level, and substrate grooves can be used to reduce chip offset during surface mount packaging, thereby improving routing accuracy.

[0060] Step 400: Figure 6 As shown, in this step, Figure 5 The illustrated structural surface further comprises a metal shielding layer 104 , wherein electromagnetic shielding can be achieved on five sides of the chip 103 through the metal shielding layer 104 .

[0061] Step 500: Figure 7 As shown, in this step, the molding compound 108 may be filled in the substrate opening to form a molding layer 701 , wherein the upper surface of the molding layer 701 is flush with the upper surface of the substrate 303 .

[0062] Step 600: Figure 8 As shown, in this step, a molding layer opening 801 may be constructed on the molding layer 701 so as to expose the back side of the chip 103 from the molding layer 701 .

[0063] Step 700: Figure 9 As shown, in this step, a patterned metal heat dissipation layer 105 can be constructed, wherein the metal heat dissipation layer 105 is in contact with and connected to the metal shielding layer 104 on the back side of the chip 103 .

[0064] Step 800: Figure 10 As shown, in this step, Figure 9 A temporary bonding layer 1001 and a second carrier sheet 1002 are further arranged on the upper surface of the structure shown, and the structure is bonded to the second carrier sheet 1002 via the temporary bonding layer 1001. The temporary bonding layer 1001 can be a thermoplastic or thermosetting organic material, or an inorganic material containing components such as Cu, Ni, Cr, and Co. The temporary bonding layer 1001 can be removed by heating, mechanical means, chemical means, laser means, freezing, and the like.

[0065] Step 900: Figure 11 As shown, in this step you can remove Figure 10 The first carrier 301 and temporary adhesive layer 302 in the structure shown are then constructed below the chip, with a multi-layer wiring layer 102 and solder balls 101. The top layer of the multi-layer wiring layer 102 is a passivation layer, and the passivation layer is configured with passivation layer openings, so that the metal wiring layer in the middle of the multi-layer wiring layer 102 can be electrically connected to the pads on the lower surface of the chip 103 and the metal shielding layer 104. The solder balls 101 are arranged on the metal pads in the bottom layer of the multi-layer wiring layer 102 to achieve electrical connection with the metal wiring layer within the multi-layer wiring layer 102.

[0066] Step 1000: Figure 12 As shown, in this step you can remove Figure 11 The temporary bonding layer 1001 and the second carrier 1002 in the structure shown.

[0067] Step 1100: Figure 13 As shown, in this step, Figure 12 The structure shown is diced to obtain Figure 13 The package 1300 is shown.

[0068] Step 1200: In this step, the groove in the upper surface of the package body 1300 may be filled with thermal conductive adhesive 106 and further covered with heat sink 107 to obtain the following: Figure 1 The fan-out package structure shown.

[0069] Although various embodiments of the present invention have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations may be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely in accordance with the appended claims and their equivalents.

Claims

1. A fan-out packaging structure, characterized in that: include: Wiring layer; A chip comprising a first surface to a sixth surface, wherein the first surface is connected to the wiring layer; The wiring layer includes a multi-layer wiring layer, and the multi-layer wiring layer includes: a passivation layer, the passivation layer being in contact with the first surface of the chip and having a passivation layer opening; a metal wiring layer, the metal wiring layer being connected to the chip through the passivation layer opening; and a metal pad, the metal pad being arranged outside the metal wiring layer and electrically connected to the chip through the metal wiring layer; a metal shielding layer, which covers and contacts the second to sixth surfaces of the chip; a metal heat dissipation layer connected to the metal shielding layer, the metal heat dissipation layer being arranged above the metal shielding layer, contacting with the metal shielding layer and communicating with the metal shielding layer; heat sink; Thermally conductive adhesive connecting the heat sink and the metal heat dissipation layer, wherein the heat sink and the thermally conductive adhesive are arranged above the metal heat dissipation layer; and A molding compound is filled between the chip and the metal heat dissipation layer, the molding compound covers the chip, a molding layer opening is formed on the molding compound, and the metal heat dissipation layer and the thermal conductive adhesive are formed in the molding layer opening.

2. The fan-out packaging structure according to claim 1, wherein: Also included is a solder ball, which is arranged on the metal pad.

3. The fan-out packaging structure according to claim 1, wherein: The substrate material of the chip includes gallium arsenide or gallium nitride.

4. The fan-out packaging structure according to claim 1, wherein: The thickness of the chip is less than 100 μm.

5. A method for constructing the fan-out packaging structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a first carrier, covering the upper surface of the first carrier with a temporary adhesive layer, and arranging a substrate on the temporary adhesive layer; constructing a substrate opening on the substrate so as to expose the upper surface of the temporary adhesive layer; arranging the chip on the temporary adhesive layer; constructing the metal shielding layer; Filling the molding compound at the substrate opening to form a molding layer, wherein the upper surface of the molding layer is flush with the upper surface of the substrate; Constructing the plastic sealing layer opening on the plastic sealing layer so as to expose the back side of the chip from the plastic sealing layer; constructing the metal heat dissipation layer, wherein the metal heat dissipation layer contacts and communicates with the metal shielding layer on the back side of the chip; Arranging a temporary bonding layer and a second carrier; Removing the first carrier and the temporary adhesive layer, and constructing the multi-layer wiring layer and solder balls below the chip, wherein the uppermost layer of the multi-layer wiring layer is a passivation layer, and the passivation layer is constructed with the passivation layer opening, and the solder balls are arranged on the metal pads of the lowermost layer of the multi-layer wiring layer; removing the temporary bonding layer and the second carrier; as well as Slicing is performed, the thermal conductive adhesive is filled and the heat sink is covered.

6. The method according to claim 5, characterized in that The materials of the substrate include: semiconductor materials, including silicon, germanium, gallium arsenide, and indium phosphide; and Electrically non-conductive materials, including glass, plastic, and sapphire wafers.

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