Integrated circuit device and method of manufacturing the same

Abstract

An integrated circuit device includes a substrate, first and second fin active regions extending on the substrate in a first direction, first and second gate lines on the substrate extending in a second direction that intersects the first direction, and first and second contact structures. The first and second gate lines intersect the first and second fin active regions, respectively. The first contact structure is on the first fin active region to one side of the first gate line and contacts the first gate line. The second contact structure is on the second fin active region to one side of the second gate line. The first contact structure includes a first lower contact portion including a metal silicide and a first upper contact portion on the first lower contact portion. The second contact structure includes a second lower contact portion including a metal silicide and a second upper contact portion on the second lower contact portion.

Description

[0001] This application is a divisional application of the invention application filed on March 25, 2016, with application number 201610177256.9 and title "Integrated Circuit Device and Manufacturing Method Thereof".

[0002] Cross-references to related applications

[0003] This application claims priority to Korean Patent Application No. 10-2015-0041644, filed on March 25, 2015, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] This disclosure relates to an integrated circuit device and / or a method of manufacturing thereof, and more specifically, to an integrated circuit device including a FinFET and / or a method of manufacturing thereof. Background Technology

[0005] For high-speed electronic devices, miniaturization of semiconductor devices has been achieved. FinFET is proposed as an example of semiconductor miniaturization technology. In FinFET, the gate can be formed on a fin protruding from the substrate, so that the fin can be used as a three-dimensional channel. Summary of the Invention

[0006] This disclosure relates to an integrated circuit device with improved integration density and performance.

[0007] This disclosure relates to a method for manufacturing integrated circuit devices.

[0008] According to an example embodiment, an integrated circuit device includes a substrate, a first finned active region and a second finned active region spaced apart from each other on the substrate, a first gate line and a second gate line on the substrate, a first contact structure on the first finned active region, and a second contact structure on the second finned active region. The first finned active region and the second finned active region extend in a first direction. The first gate line and the second gate line extend in a second direction intersecting the first direction. The first gate line and the second gate line intersect the first finned active region and the second finned active region, respectively. The first contact structure is located on one side of the first gate line. The first contact structure contacts the first gate line. The second contact structure is located on one side of the second gate line. The first contact structure includes a first lower contact portion and a first upper contact portion located on the first lower contact portion. The first lower contact portion includes a metal silicide. The second contact structure includes a second lower contact portion and a second upper contact portion located on the second lower contact portion. The second lower contact portion includes a metal silicide.

[0009] In an example embodiment, the first upper contact portion may contact the upper surface of the first gate line.

[0010] In an example embodiment, the first lower contact portion may extend in the second direction.

[0011] In an example embodiment, the first finned active region and the second finned active region may protrude from the substrate in a direction perpendicular to the main surface of the substrate. A first lower contact portion may extend to cover the sidewalls and top surface of the first finned active region. The first lower contact portion may extend to cover the sidewalls and top surface of the second finned active region.

[0012] In an example embodiment, the width of the first upper contact portion in the first direction may be greater than the width of the second upper contact portion in the first direction.

[0013] In an example embodiment, the portion of the first gate line that contacts the first upper contact portion may be a dummy gate.

[0014] In an example embodiment, the portion of the first gate line that contacts the first upper contact portion may vertically overlap with the sidewall of the first fin-type active region.

[0015] In an example embodiment, the first upper contact portion may include a first portion and a second portion. The first portion of the first upper contact portion may contact the first lower contact portion. The second portion of the first upper contact portion may protrude downward from one side of the first portion and may contact the first gate line.

[0016] In an example embodiment, the bottom surface of the second portion of the first upper contact portion may be lower than the upper surface of the first lower contact portion.

[0017] In an example embodiment, the upper surface of the first lower contact portion may be higher than the upper surface of the first gate line.

[0018] In an example embodiment, the first contact structure may further include a first lower barrier layer surrounding the sidewalls and bottom surface of the first lower contact portion. The second contact structure may further include a second lower barrier layer surrounding the sidewalls and bottom surface of the second lower contact portion.

[0019] In an example embodiment, the first finned active region may include a pair of PMOS active regions arranged separately from each other. The second finned active region may include a pair of NMOS active regions. The pair of PMOS active regions may be located between the pair of NMOS active regions.

[0020] In an example embodiment, the first distance between the pair of PMOS active regions may be substantially equal to the second distance between one of the pair of PMOS active regions and one of the pair of NMOS active regions adjacent to one of the pair of PMOS active regions.

[0021] In an example embodiment, the first finned active region may include a pair of PMOS active regions. The second finned active region may include two pairs of NMOS active regions. Each pair of the two pairs of NMOS active regions is arranged on each side of the pair of PMOS active regions.

[0022] In an example embodiment, the first distance between the pair of PMOS active regions may be substantially equal to the second distance between one of the pair of PMOS active regions and one of the two pairs of NMOS active regions adjacent to one of the pair of PMOS active regions.

[0023] In an example embodiment, the first distance between the pair of PMOS active regions may be greater than the third distance between the pair of NMOS active regions.

[0024] According to an example embodiment, an integrated circuit device includes a substrate and a static random access memory (SRAM) array located on the substrate. The SRAM array includes a plurality of SRAM cells. The SRAM array includes: a plurality of first fin active regions and a plurality of second fin active regions extending on the substrate in a first direction; a first gate line and a second gate line extending on the substrate in a second direction intersecting the first direction; and a first contact structure located on one side of the first gate line on one of the plurality of first fin active regions and a second contact structure located on one side of the second gate line on one of the plurality of second fin active regions. The first gate line and the second gate line intersect the plurality of first fin active regions and the plurality of second fin active regions, respectively. The first contact structure includes: a first lower contact portion located on the plurality of first fin active regions; and a first upper contact portion located on the first lower contact portion; and a first lower barrier layer surrounding a sidewall of the first lower contact portion. The first upper contact portion contacts a portion of the first gate line.

[0025] In an example embodiment, the first lower contact portion may include a metal silicide.

[0026] In an example embodiment, the second contact structure may include a second lower contact portion located on the plurality of second finned active regions, and a second upper contact portion located on the second lower contact portion. The second upper contact portion may be formed such that it does not contact the first gate line or the second gate line. The height of the upper surface of the first lower contact portion may be substantially equal to the height of the upper surface of the second lower contact portion.

[0027] In an example embodiment, the second lower contact portion may extend in a second direction. The second lower contact portion may contact the plurality of second finned active regions.

[0028] In an example embodiment, multiple portions of the first gate line may intersect with the plurality of first fin active regions. These multiple portions of the first gate line may be located on the sidewalls of the plurality of first fin active regions and may form a pseudo-transistor.

[0029] In an example embodiment, the static random access memory array may include a plurality of inverters. Each of the inverters may include a pull-up transistor and a pull-down transistor, and a plurality of transfer transistors are respectively connected to the output nodes of the plurality of inverters. A first gate line is shared by the pull-up transistor and the pull-down transistor, and a second gate line is shared by two transfer transistors selected from the plurality of transfer transistors.

[0030] In an example embodiment, the static random access memory array may include multiple NMOS transistors and multiple PMOS transistors. The second gate line may be shared by two of the multiple NMOS transistors.

[0031] In an example embodiment, the static random access memory array may include a plurality of NMOS transistors and a plurality of PMOS transistors. A first gate line may be shared by two transistors with channels having different conductivity types. The two transistors may be a subset of the plurality of NMOS transistors and the plurality of PMOS transistors.

[0032] According to an example embodiment, a method of manufacturing an integrated circuit device includes: forming a first finned active region and a second finned active region on a substrate, the first finned active region and the second finned active region extending in a first direction parallel to a main surface of the substrate; forming a first gate line and a second gate line on the first finned active region and the second finned active region, respectively, the first gate line and the second gate line extending in a second direction intersecting the first direction, the first gate line intersecting the first finned active region, and the second gate line intersecting the second finned active region; and forming a first contact structure on one side of the first gate line on the first finned active region and forming a second contact structure on one side of the second gate line on the second finned active region. The first contact structure and the second contact structure each include a metal silicide.

[0033] In an example embodiment, the steps of forming the first contact structure and forming the second contact structure may include: forming a first lower barrier layer and a second lower barrier layer on the inner walls and bottom of the first opening and the second opening; and forming a first lower contact portion and a second lower contact portion that fill the first opening and the second opening on the first lower barrier layer and the second lower barrier layer.

[0034] In an example embodiment, the method may further include: forming an etch stop layer and a second insulating interlayer on the insulating interlayer, and forming a third opening through the etch stop layer and the second insulating interlayer. The insulating interlayer may be a first insulating interlayer. The third opening may expose a portion of the upper surface of the first gate line and the upper surface of the first lower contact portion.

[0035] According to an example embodiment, an integrated circuit device includes: a plurality of fins extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the plurality of fins including a first fin and a second fin; a first lower contact portion extending in the second direction above the first and second fins; a second lower contact portion on the second fin and spaced apart from the first lower contact portion, the first and second lower contact portions being formed of metal silicide; a first gate line on the first fin and extending in the second direction; a second gate line on the second fin and extending in the second direction, the first and second gate lines being spaced apart from each other; a first upper contact portion on the first gate line and the first lower contact portion, the first upper contact portion extending in the first direction; and a second upper contact portion located on the second lower contact portion.

[0036] In an example embodiment, the integrated circuit device may further include a substrate and a plurality of first gate lines and second gate lines located on the substrate. A first fin may be one of a plurality of first fins extending in a first direction formed in the substrate. The plurality of first fins may include two first fins spaced apart from each other in a second direction. A second fin may be one of a plurality of second fins formed in the substrate. The plurality of second fins may include two second fins spaced apart from each other in a second direction and located on the substrate. The two first fins may be disposed between the two second fins. A first gate line may extend in a second direction above the two first fins and a first of the two second fins. A second gate line may extend in a second direction above the two first fins and a second of the two second fins. A first second gate line may be connected to a first of the two second fins. A second second gate line may be connected to a second of the two second fins.

[0037] In an example embodiment, the integrated circuit device may further include a gate insulating layer between the first gate line and the first fin. The first gate line may include a first portion and a second portion. The first portion may be located on the upper surface of the first fin. The second portion may be adjacent to the sidewall of the first fin. The gate insulating layer may be located between the first fin and the first and second portions of the first gate line.

[0038] In an example embodiment, the upper surface of the first lower contact portion may be higher than the upper surface of the first gate line.

[0039] In an example embodiment, the integrated circuit may further include a substrate. A first fin and a second fin may be formed in the substrate. The first fin may include a channel region of a PMOS transistor. The second fin may include a channel region of an NMOS transistor. Attached Figure Description

[0040] From the following description of non-limiting embodiments of the inventive concept as illustrated in the accompanying drawings, exemplary embodiments of which will become clearer, wherein the same reference numerals refer to the same parts throughout the different illustrations. The drawings are not necessarily to scale, but rather emphasize the principles of the inventive concept. In the drawings:

[0041] Figures 1A-1F Perspective views, plan views, and sectional views of an integrated circuit device according to an example embodiment are shown;

[0042] Figure 2 It is a circuit diagram used to describe an integrated circuit device according to an example embodiment;

[0043] Figures 3A-3G Plan view, layout view and cross-sectional view of an integrated circuit device according to an example embodiment are shown;

[0044] Figures 4A-4D Plan view, layout view and cross-sectional view of an integrated circuit device according to an example embodiment are shown;

[0045] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 , Figure 8A , Figure 8B and Figures 9-11 It is a cross-sectional view used to describe the process sequence of manufacturing an integrated circuit device according to an example embodiment;

[0046] Figure 12 This is a block diagram of a non-volatile memory device according to an example embodiment;

[0047] Figure 13 It is a block diagram of an electronic system including integrated circuit devices according to an example embodiment;

[0048] as well as

[0049] Figure 14 It is a block diagram of a memory system including an integrated circuit device according to an example embodiment. Detailed Implementation

[0050] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which elements of exemplary embodiments are illustrated. However, the inventive concept can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to one skilled in the art. In the drawings, the thickness of layers and regions is exaggerated for clarity. The same reference numerals and / or numbers in the drawings refer to the same elements, and therefore their description will not be repeated.

[0051] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When an expression such as “at least one of…” appears after a list of elements, the entire list of elements is changed without changing any individual element in the list.

[0052] It should be understood that when an element, such as a layer, region, or substrate, is referred to as being "located" "on," "connected to," or "bonded to" another element, it may be directly located on, directly connected to, or directly bonded to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly located" "on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or layers present. Other terms used to describe relationships between elements or layers (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.) should be interpreted in the same manner.

[0053] It should be understood that although the terms first, second, etc., may be used herein to describe multiple elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments.

[0054] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature shown in the accompanying drawings and another element or feature. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures were flipped, an element described as “below other elements” or “below other elements” would therefore be oriented “above other elements or features.” Thus, the term “below” can encompass both the orientations of “above” and “below”. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0055] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “comprising,” “including,” “containing,” and / or “comprising…” are used in this specification, they indicate the presence of the listed features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0056] This document describes exemplary embodiments with reference to schematic cross-sectional views of ideal embodiments (and intermediate structures) as example examples. Thus, variations in the shapes shown in the figures are foreseeable as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape, for example, due to manufacturing processes. For example, etched or implanted regions shown as rectangular may have circular or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense.

[0058] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0059] Figures 1A-1F Perspective views, plan views, and sectional views of an integrated circuit device according to an example embodiment are shown. Figure 1A This is a perspective view of the main components of the integrated circuit device 100. Figure 1B yes Figure 1A A plan view of the integrated circuit device 100. Figure 1C It is along Figure 1B The sectional view taken from line 1A-1A'. Figure 1D It is along Figure 1B The sectional view taken from line 1B-1B'. Figure 1E It is along Figure 1B The sectional view taken from line 1C-1C'. Figure 1F It is along Figure 1B A sectional view taken from line 1D-1D'. For convenience, in Figure 1AThe first upper barrier layer 142U and the second upper barrier layer 144U, as well as the first lower barrier layer 142L and the second lower barrier layer 144L, are omitted.

[0060] Reference Figures 1A-1F The integrated circuit device 100 may include a substrate 110 on which a first finned active region FA1 and a second finned active region FA2 are formed. In an example embodiment, the substrate 110 may be a semiconductor substrate comprising a semiconductor material such as silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. In an example embodiment, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. The substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0061] The first finned active region FA1 and the second finned active region FA2 may protrude from the substrate 110 in a direction Z perpendicular to the main surface of the substrate 110, and may respectively have a channel region CH1 of a first conductivity type and a channel region CH2 of a second conductivity type. According to an example embodiment, the channel region CH1 of the first conductivity type may be a channel region of a p-type metal-oxide-semiconductor (PMOS) transistor, and the channel region CH2 of the second conductivity type may be a channel region of an n-type metal-oxide-semiconductor (NMOS) transistor. The first channel region CH1 may be n-type. The second channel region CH2 may be p-type. However, the example embodiment is not limited thereto.

[0062] The first finned active region FA1 and the second finned active region FA2 may extend in a first direction (direction X) parallel to the main surface of the substrate 110. For example, the first finned active region FA1 may have a long side along direction X (which is the direction in which the first finned active region FA1 extends) and a short side along direction Y perpendicular to direction X.

[0063] A first trench (not shown) extending in direction X may be formed between the first finned active region FA1 and the second finned active region FA2, and an isolation layer 112 may be formed on the first trench. On the substrate 110, a first gate line GL1 and a second gate line GL2 may extend in a straight line in a second direction (direction Y), which intersects the direction in which the first finned active region FA1 and the second finned active region FA2 extend. The first gate line GL1 may extend on the isolation layer 112 to intersect with the first finned active region FA1 and simultaneously cover the upper surface and two side surfaces of the first finned active region FA1, and the second gate line GL2 may extend on the isolation layer 112 to intersect with the second finned active region FA2 and simultaneously cover the upper surface and two side surfaces of the second finned active region FA2.

[0064] Each of the first gate line GL1 and the second gate line GL2 may extend in a second direction (direction Y) and may have an upper surface extending parallel to the upper surface of the substrate 110 at a first horizontal height LV1 on the substrate 110. The upper surfaces of the first gate line GL1 and the second gate line GL2 may extend in a direction parallel to the extension direction of the substrate 110 (that is, the extension direction of the XY plane).

[0065] According to an example embodiment, the first gate line GL1 and the second gate line GL2 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are stacked in sequence. Each of the metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf. Each of the metal nitride layer and the metal layer may be formed by atomic layer deposition (ALD), metal-organic ALD (MOALD), or metal-organic chemical vapor deposition (MOCVD). The conductive capping layer may serve as a protective layer that limits and / or prevents surface oxidation of the metal layer. In addition, the conductive capping layer may serve as a wetting layer that facilitates the deposition process when another conductive layer is deposited on the metal layer. The conductive capping layer may be formed of metal nitrides such as TiN and TaN or combinations thereof. However, the conductive capping layer is not limited thereto. The gap-filling metal layer may be disposed on the sidewalls and top surfaces of the first finned active region FA1 and the second finned active region FA2 on the conductive capping layer. The interstitial metal layer can be formed of a tungsten (W) layer or a TiN layer. The interstitial metal layer can be formed by ALD, CVD, or physical vapor deposition (PVD). The interstitial metal layer can conceal the depressions formed on the sidewalls and upper surfaces of the first fin active region FA1 and the second fin active region FA2 due to the stepped portion on the upper surface of the conductive capping layer, without creating voids.

[0066] A gate insulating layer 120 may be located between a first gate line GL1 and a first finned active region FA1, and a gate spacer 130 may be formed on two sidewalls of the first gate line GL1. Alternatively, the gate insulating layer 120 may be located between the first gate line GL1 and the gate spacer 130. A gate insulating layer 120 may also be located between a second gate line GL2 and a second finned active region FA2, and a gate spacer 130 may be formed on two sidewalls of the second gate line GL2. Alternatively, the gate insulating layer 120 may also be located between the second gate line GL2 and the gate spacer 130.

[0067] The first contact structure CS1 may be formed on one side of the first gate line GL1 on the first fin-type active region FA1, and the second contact structure CS2 may be formed on one side of the second gate line GL2 on the second fin-type active region FA2.

[0068] The first contact structure CS1 may include: a first lower contact portion CT1L, which covers the upper surface and two sidewalls of the first fin-type active region and the upper surface and two sidewalls of the second fin-type active region on the isolation layer 112; and a first upper contact portion CT1U, which is disposed on the first lower contact portion CT1L and contacts the first gate line GL1.

[0069] The first lower contact portion CT1L may extend along the extension direction (direction Y) of the first gate line GL1 on one side. The first lower contact portion CT1L may extend to cover the upper surface and two sidewalls of the first finned active region FA1 and the upper surface and two sidewalls of the second finned active region FA2. The height of the upper surface of the first lower contact portion CT1L may be equal to or greater than the height of the upper surfaces of the first gate line GL1 and the second gate line GL2. However, the exemplary embodiment is not limited thereto. The first upper contact portion CT1U may be formed on the first lower contact portion CT1L and may contact a portion of the upper surface of the first gate line GL1. The first upper contact portion CT1U may have a long side extending along a direction intersecting the extension direction (direction X) of the first gate line GL1 and a short side extending along the extension direction (direction Y) of the first gate line GL1.

[0070] like Figure 1E and Figure 1F As shown, the first lower contact portion CT1L extends along the extension directions of the first gate line GL1 and the second gate line GL2, and the first upper contact portion CT1U extends on the first lower contact portion CT1L in a direction intersecting the extension direction of the first lower contact portion CT1L. That is, the first width W1Ua of the first upper contact portion CT1U in direction X is greater than the second width W1La of the first lower contact portion CT1L in direction X. Simultaneously, the third width W1Ub of the first upper contact portion CT1U in direction Y is less than the fourth width W1Lb of the first lower contact portion CT1L in direction Y. Therefore, the first upper contact portion CT1U and the first lower contact portion CT1L, extending in directions X and Y respectively, can vertically overlap each other on one side of the first gate line GL1 in the first fin-type active region FA1.

[0071] According to an example embodiment, the first lower contact portion CT1L may include a metal silicide. For example, the first lower contact portion CT1L may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, etc. However, the material of the first lower contact portion CT1L is not limited to this. According to an example embodiment, the first upper contact portion CT1U may include a conductive material such as a metal, a metal nitride, or polycrystalline silicon doped with impurities. However, the material of the first upper contact portion CT1U is not limited to this.

[0072] A first lower barrier layer 142L may cover the sidewalls and bottom surface of the first lower contact portion CT1L, and a first upper barrier layer 142U may cover the sidewalls and bottom surface of the first upper contact portion CT1U. The first lower barrier layer 142L and the first upper barrier layer 142U may be conformally formed on the sidewalls and bottom surfaces of the first lower contact portion CT1L and the first upper contact portion CT1U, respectively, with a desired (and / or alternatively, predetermined) thickness. For example, the first lower barrier layer 142L and the first upper barrier layer 142U may include titanium nitride, tantalum nitride, tungsten nitride, titanium carbonitride, etc. According to an example embodiment, the first lower barrier layer 142L and the first upper barrier layer 142U may have approximately to The thickness. However, the example embodiments are not limited to this.

[0073] A first lower barrier layer 142L may be located between the first lower contact portion CT1L and the first finned active region FA1 to serve as a barrier to limit and / or prevent direct contact between the first lower contact portion CT1L and the first finned active region FA1. Specifically, the first lower barrier layer 142L may limit and / or prevent performance degradation of the integrated circuit device 100 that may occur when materials (e.g., source gas) used in the process of forming the first lower contact portion CT1L permeate into the first finned active region FA1. In addition, a first upper barrier layer 142U may limit and / or prevent damage to the first upper contact portion CT1U and the first lower contact portion CT1L caused by undesirable chemical reactions due to direct contact between the first upper contact portion CT1U and the first lower contact portion CT1L.

[0074] The second contact structure CS2 may include: a second lower contact portion CT2L, which covers the upper surface and two sidewalls of the second fin-type active region FA2 on the isolation layer 112; and a second upper contact portion CT2U, which is disposed on the second lower contact portion CT2L.

[0075] The second lower contact portion CT2L may cover the upper surface and two sidewalls of the second finned active region FA2 on one side of the second gate line GL2. While the second lower contact portion CT2L is arranged on one side of the second gate line GL2 on the second finned active region FA2, the first lower contact portion CT1L may be arranged on the other side of the second gate line GL2 on the second finned active region FA2. Therefore, the first lower contact portion CT1L and the second lower contact portion CT2L (each arranged to intersect the second finned active region FA2) may be separated from each other with the second gate line GL2 between them. The second lower contact portion CT2L does not contact the first finned active region FA1. According to the exemplary embodiment, the height of the upper surface of the second lower contact portion CT2L may be equal to or greater than the height of the upper surfaces of the first gate line GL1 and the second gate line GL2. However, the exemplary embodiment is not limited to this.

[0076] The second upper contact portion CT2U may be formed on the second lower contact portion CT2L. The height of the bottom surface of the second upper contact portion CT2U is substantially equal to the height of the bottom surface of the first upper contact portion CT1U. However, the example embodiment is not limited thereto.

[0077] The second lower barrier layer 144L can cover the sidewall and bottom surface of the second lower contact portion CT2L, and the second upper barrier layer 144U can cover the sidewall and bottom surface of the second upper contact portion CT2U.

[0078] According to an example embodiment, the second lower contact portion CT2L may include a metal silicide. For example, the second lower contact portion CT2L may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, etc. However, the material of the second lower contact portion CT2L is not limited to this. According to an example embodiment, the second upper contact portion CT2U may include a conductive material such as a metal, a metal nitride, or polycrystalline silicon doped with impurities. However, the material of the second upper contact portion CT2U is not limited to this.

[0079] According to an example embodiment, the first contact structure CS1 can be used as a storage node contact portion of a static random access memory (SRAM) device. For example, the first contact structure CS1 can connect the drains of a pull-down transistor and a pull-up transistor implemented using a first gate line GL1 to a pass gate implemented using a second gate line GL2. Additionally, the second contact structure CS2 can be used as a bit line contact portion, a complementary bit line contact portion, a power node contact portion, or a ground node contact portion of the SRAM device. However, the example embodiment is not limited to these.

[0080] In reference Figures 1A-1F In the described integrated circuit device 100, the first contact structure CS1 and the second contact structure CS2 respectively include a first lower contact portion CT1L and a second lower contact portion CT2L comprising metal silicide. Furthermore, a first lower barrier layer 142L and a second lower barrier layer 144L respectively cover the sidewalls and bottom surfaces of the first lower contact portion CT1L and the second lower contact portion CT2L. Since the first contact structure CS1 and the second contact structure CS2 comprise metal silicide, the first contact structure CS1 and the second contact structure CS2 can have reduced contact resistance. Therefore, the performance of the integrated circuit device 100 including the first contact structure CS1 and the second contact structure CS2 can be improved.

[0081] Furthermore, since the first contact structure CS1 and the second contact structure CS2 have reduced contact resistance due to the inclusion of metal silicide, an integrated circuit device 100 with sufficiently low contact resistance can be implemented using contact structures CS1 and CS2, which have relatively small dimensions (e.g., width or height). Therefore, the integration density of the integrated circuit device 100 can be increased.

[0082] Furthermore, in the process of forming the first lower contact portion CT1L and the second lower contact portion CT2L, the first finned active region FA1 and the second finned active region FA2 and / or the adjacent first gate line GL1 and second gate line GL2 may be subject to physical and chemical damage, while the first lower barrier layer 142L and the second lower barrier layer 144L can protect the first finned active region FA1 and the second finned active region FA2 from such physical and chemical damage. Therefore, the enlarged first contact structure CS1 and the second contact structure CS2 can be formed in a relatively narrow space between the first finned active region FA1 and the second finned active region FA2 and between the first gate line GL1 and the second gate line GL2 (for example, the distance between the first contact structure CS1 and the second contact structure CS2 and the distance between the first gate line GL1 and the second gate line GL2 can be reduced), thereby increasing the integration density of the integrated circuit device 100.

[0083] The first gate line GL1 may include a first portion GL1_a and a second portion GL1_b. The first portion GL1_a of the first gate line GL1 may be disposed on the upper surface of the channel region CH1 of the first conductivity type, and the second portion GL1_b of the first gate line GL1 may be disposed on the isolation layer 112 between the sidewall of the channel region CH1 of the first conductivity type and the gate spacer 130.

[0084] Figure 2 This is a circuit diagram used to describe an integrated circuit device 200 according to an example embodiment. Figure 2 A circuit diagram of a 6T SRAM cell including six transistors is shown.

[0085] Reference Figure 2 The integrated circuit device 200 may include a pair of inverters INV1 and INV2 connected in parallel between a power node Vcc and a ground node Vss, and a first transfer transistor PS1 and a second transfer transistor PS2 connected to the output nodes of the pair of inverters INV1 and INV2, respectively. The first transfer transistor PS1 and the second transfer transistor PS2 may be connected to a bit line BL and a complementary bit line / BL, respectively. The gates of the first transfer transistor PS1 and the second transfer transistor PS2 may be connected to a word line WL.

[0086] The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 includes a second pull-up transistor PU2 and a second pull-down transistor PD2 connected in series. The first pull-up transistor PU1 and the second pull-up transistor PU2 can be formed as PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 can be formed as NMOS transistors.

[0087] The input node of the first inverter INV1 can be connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 can be connected to the output node of the first inverter INV1, so that the first inverter INV1 and the second inverter INV2 form a latching circuit.

[0088] Figures 3A-3G Plan view, layout view and cross-sectional view of an integrated circuit device according to an example embodiment are shown. Figure 3A This is a plan view of the main components of the 200A integrated circuit device. Figure 3B It is a concise representation Figure 3A The layout diagram shows the arrangement of the fin-type active region (FA) and the gate line (SGL). Figure 3C yes Figure 3A An enlarged view of the static random access memory (SRAM) cell 210A. Figure 3D It is along Figure 3A A 3D-3D sectional view of the line. Figure 3E It is along Figure 3A A sectional view taken from line 3E-3E'. Figure 3F It is along Figure 3A A sectional view taken from line 3F-3F'. Figure 3G It is along Figure 3A A sectional view taken from line 3G-3G'. Figures 3A-3G In the same figures, the same reference numerals refer to Figures 1A-1F The same elements in the text will be used, and their detailed descriptions will be omitted.

[0089] Reference Figures 3A-3G The integrated circuit device 200A includes an SRAM array 210, which includes a plurality of SRAM cells 210A, 210B, 210C and 210D arranged in a matrix on a substrate 110. Figures 3A-3F Four SRAM cells 210A, 210B, 210C and 210D are shown, each of which includes six FinFETs.

[0090] SRAM array 210 may include reference Figures 1A-1F Features of the integrated circuit device 100 described.

[0091] Each of the plurality of SRAM cells 210A, 210B, 210C, and 210D includes a plurality of finned active regions FA (e.g., FA1 to FA10) extending parallel to each other along a first direction (direction X). Each of the plurality of finned active regions FA may protrude from the substrate 110 in a direction Z perpendicular to the main surface of the substrate 110.

[0092] Additionally, the plurality of SRAM cells 210A, 210B, 210C, and 210D may include a plurality of gate lines SGL extending to cover the two sidewalls and the upper surface of the plurality of finned active regions FA, and extending parallel to each other in a second direction (direction Y) intersecting the first direction (direction X). Two adjacent gate lines SGL extending in a straight line among the plurality of gate lines SGL may have a reference [missing information]. Figures 1A-1F The first gate line described ( Figure 1A GL1) and the second gate line ( Figure 1A The structure corresponding to the structure of GL2).

[0093] Each of the first pull-up transistor PU1, the first pull-down transistor PD1, the first transfer transistor PS1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the second transfer transistor PS2 forming the plurality of SRAM cells 210A, 210B, 210C, and 210D can be formed as a fin-type transistor. Specifically, each of the first pull-up transistor PU1 and the second pull-up transistor PU2 can be formed as a PMOS transistor, and each of the first pull-down transistor PD1, the second pull-down transistor PD2, the first transfer transistor PS1, and the second transfer transistor PS2 can be formed as an NMOS transistor.

[0094] Each transistor can be formed at the intersection of the plurality of finned active regions FA extending in the X direction and the plurality of gate lines SGL extending in the Y direction. For example, in SRAM cell 210A, each transistor can be formed at each of the six intersections between the plurality of finned active regions FA and the plurality of gate lines SGL, thereby forming six transistors in SRAM cell 210A.

[0095] like Figure 3BAs shown, in SRAM cell 210A, a first transmission transistor PS1 is formed at the intersection of the finned active region FA5 and the gate line SGL3. A second transmission transistor PS2 is formed at the intersection of the finned active region FA1 and the gate line SGL2. A first pull-down transistor PD1 is formed at the intersection of the finned active region FA5 and the gate line SGL1. A second pull-down transistor PD2 is formed at the intersection of the finned active region FA1 and the gate line SGL4. A first pull-up transistor PU1 is formed at the intersection of the finned active region FA4 and the gate line SGL1. A second pull-up transistor PU2 is formed at the intersection of the finned active region FA2 and the gate line SGL4.

[0096] Each of the multiple gate lines SGL1 to SGL5 can be shared by two transistors. For example, in SRAM cell 210A, gate line SGL1 can be shared by a first pull-down transistor PD1 and a first pull-up transistor PU1. In addition, gate line SGL2, which extends in a straight line along the extension direction of gate line SGL1, can form a second transmission transistor PS2.

[0097] In two adjacent SRAM cells 210A and 210C, gate line SGL1 (located in SRAM cell 210A) of two adjacent gate lines SGL extending in a straight line in the extension direction of gate line SGL can be shared by the first pull-up transistor PU1 and the first pull-down transistor PD1 forming SRAM cell 210A, and gate line SGL5 of the two adjacent gate lines SGL located in SRAM cell 210C can be shared by the first pull-up transistor PU1 and the first pull-down transistor PD1 forming SRAM cell 210C.

[0098] In an example embodiment, each of two adjacent gate lines SGL1 to SGL5 (the two adjacent gate lines SGL extend in a straight line in the direction of extension of the gate line SGL) can be shared by two transistors with channels having the same conductivity type.

[0099] In an example embodiment, each of two adjacent gate lines SGL1 to SGL5 (the two adjacent gate lines SGL extend in a straight line in the direction of extension of the gate line SGL) can be shared by two transistors with channels having different conductivity types.

[0100] In an example embodiment, any one of two adjacent gate lines SGL1 to SGL5 (the two adjacent gate lines SGL extend in a straight line in the direction of extension of the gate line SGL) can be shared by two transistors with channels of the same conductivity type, and the other gate line SGL can be shared by two transistors with channels of different conductivity types.

[0101] like Figure 3B As shown, the gate line SGL1 forming SRAM cell 210A can be shared by the first pull-down transistor PD1, which is formed as an NMOS transistor, and the first pull-up transistor PU1, which is formed as a PMOS transistor. The gate line SGL5, which is adjacent to the gate line SGL1 and forms SRAM cell 210C, can be shared by the first pull-down transistor PD1, which is formed as an NMOS transistor, and the first pull-up transistor PU1, which is formed as a PMOS transistor.

[0102] In addition, in two adjacent SRAM cells 210A and 210B, the gate line SGL4 (located in SRAM cell 210A) of two adjacent gate lines SGL extending in a straight line can be shared by the second pull-up transistor PU2, which is formed as a PMOS transistor, and the second pull-down transistor PD2, which is formed as an NMOS transistor, and the gate line SGL3 adjacent to the gate line SGL4 can be shared by the two first transfer transistors PS1, which are formed as NMOS transistors.

[0103] like Figure 3C As shown, various contact structures can be arranged in the SRAM cell 210A. Specifically, one word line contact C_WL can be connected to the gate line SGL3 of the first transfer transistor PS1, and another word line contact C_WL can be connected to the gate line SGL2 of the second transfer transistor PS2. A bit line contact C_BL can be connected to the drain of the first transfer transistor PS1, and a complementary bit line contact C_ / BL can be connected to the drain of the second transfer transistor PS2. A power node contact C_Vcc can be connected to the source of the first pull-up transistor PU1, and another power node contact C_Vcc can be connected to the source of the second pull-up transistor PU2. A ground node contact C_Vss can be connected to the source of the first pull-down transistor PD1, and another ground node contact C_Vss can be connected to the source of the second pull-down transistor PD2. A first memory node contact C_SN1 can be connected to the source of the first transfer transistor PS1 and the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1. The second storage node contact C_SN2 can be connected to the source of the second transmission transistor PS2 and the drain of the second pull-up transistor PU2 and the second pull-down transistor PD2.

[0104] At least one of the first storage node contact portion C_SN1 and the second storage node contact portion C_SN2 may include reference to Figures 1A-1F The first contact structure of the described integrated circuit device 100 ( Figure 1A Features similar to those of CS1), and at least one of the bit line contact portion C_BL, complementary bit line contact portion C_ / BL, power node contact portion C_Vcc, and ground node contact portion C_Vss may include a second contact structure with the integrated circuit device 100. Figure 1A The features are similar to those of CS2). Here, for ease of explanation, at least one of the first memory node contact portion C_SN1 and the second memory node contact portion C_SN2 will be referred to as the first contact structure CS11, and at least one of the bit line contact portion C_BL, the complementary bit line contact portion C_ / BL, the power node contact portion C_Vcc, and the ground node contact portion C_Vss will be referred to as the second contact structure CS22.

[0105] like Figure 3A As shown, the plurality of finned active regions FA1 to FA10 can be arranged to be separated from each other in the direction X, and a first contact structure CS11 or a second contact structure CS22 can be formed on one side of the gate line SGL on the plurality of finned active regions FA.

[0106] A first contact structure CS11 may be formed on one side of a gate line SGL shared by two transistors with different conductivity types in one of the plurality of fin active regions FA1 to FA10, which has a channel region of the first conductivity type. A second contact structure CS22 may be formed on the other side of a fin active region FA in the plurality of fin active regions FA1 to FA10, which has a channel region of the second conductivity type, on the other side of a gate line SGL shared by two transistors with different conductivity types. According to an example embodiment, the channel region of the first conductivity type may be a PMOS channel region, and the channel region of the second conductivity type may be an NMOS channel region.

[0107] like Figure 3C As shown, in SRAM cell 210A, a first storage node contact portion C_SN1 may be formed at the intersection of a gate line SGL4 shared by two transistors with different conductivity types and a fin active region FA4 having a channel region of the first conductivity type, and a second storage node contact portion C_SN2 may be formed at the intersection of a gate line SGL1 shared by two transistors with different conductivity types and a fin active region FA2 having a channel region of the first conductivity type.

[0108] Additionally, for ease of explanation, here, a gate line SGL shared by two transistors with channels of different conductivity types will be referred to as the first gate line SGLA, and a gate line SGL shared by two transistors with channels of the same conductivity type will be referred to as the second gate line SGLB. The first gate line SGLA and the second gate line SGLB may include, as referenced... Figures 1A-1F The first gate line GL1 and the second gate line GL2 of the described integrated circuit device 100 have similar characteristics.

[0109] The first contact structure CS11 may be formed on one side of the first gate line SGLA on the fin active region FA, which has a channel region of the first conductivity type among the plurality of fin active regions FA1 to FA10, and the upper part of the first contact structure CS11 may contact a portion of the upper surface of the first gate line SGLA.

[0110] The first contact structure CS11 may include: a first lower contact portion CT11L, which is formed on a fin active region FA having a channel region of a first conductivity type in one of the plurality of fin active regions FA1 to FA10; and a first upper contact portion CT11U, which is formed on the first lower contact portion CT11L and contacts the first gate line SGLA.

[0111] like Figures 3A-3C As shown, the first lower contact portion CT11L may extend in a direction (direction Y) parallel to the first gate line SGLA and the second gate line SGLB (for example, the first lower contact portion CT11L may have two long sides extending in a direction (direction Y) parallel to the first gate line SGLA and the second gate line SGLB). In SRAM cell 210A of the plurality of SRAM cells 210A, 210B, 210C and 210D, the first lower contact portion CT11L may be formed on one side of the gate line SGL1 on the fin active region FA2, and the first lower contact portion CT11L may extend to cover the adjacent fin active region FA1. In addition, in SRAM cell 210A, the first lower contact portion CT11L may be formed on one side of the gate line SGL4 on the fin active region FA4, and the first lower contact portion CT11L may extend to cover the adjacent fin active region FA5.

[0112] The first upper contact portion CT11U may extend in a direction (direction X) intersecting with the first gate line SGLA, and may contact the adjacent first gate line SGLA (e.g., the first upper contact portion CT11U may have two long sides extending in a direction intersecting with the first gate line SGLA). Figure 3CAs shown, in SRAM cell 210A, one of the plurality of SRAM cells 210A, 210B, 210C, and 210D, the first upper contact portion CT11U may be arranged on the first lower contact portion CT11L (arranged on the fin-type active region FA2) on one side of the gate line SGL1, so that the first upper contact portion CT11U contacts the gate line SGL1. Additionally, in SRAM cell 210A, the first upper contact portion CT11U may be arranged on the first lower contact portion CT11L (arranged on the fin-type active region FA4) on one side of the gate line SGL4, so that the first upper contact portion CT11U contacts the gate line SGL4.

[0113] like Figure 3D and Figure 3E As shown, the first upper contact portion CT11U includes a first portion CT11U_1 and a second portion CT11U_2 with different heights on their bottom surfaces, and the first portion CT11U_1 may be formed on the first lower contact portion CT11L. The second portion CT11U_2 may contact the upper surface of the adjacent first gate line SGLA on one side of the first portion CT11U_1.

[0114] The horizontal height LV1 of the upper surface of the first gate line SGLA can be lower than the horizontal height LV_C1 of the upper surface of the first lower contact portion CT11L. Therefore, the height of the bottom surface of the first portion CT11U_1 of the first upper contact portion CT11U is basically the same as the horizontal height LV_C1 of the upper surface of the first lower contact portion CT11L. Furthermore, the horizontal height LV_C2 of the lower surface of the second portion CT11U_2 of the first upper contact portion CT11U can be lower than the horizontal height LV_C1 of the upper surface of the first lower contact portion CT11L or the horizontal height of the lower surface of the first portion CT11U_1 of the first upper contact portion CT11U. For example... Figure 3D and Figure 3E As shown, for example, due to regional differences in the etching rate during the etching process used to form the first upper contact portion CT11U, the lower surface level height LV_C2 of the second portion CT11U_2 of the first upper contact portion CT11U may be lower than the upper surface level height LV1 of the first gate line SGLA. However, the example embodiment is not limited to this, and the lower surface level height LV_C2 of the second portion CT11U_2 of the first upper contact portion CT11U may be located at a level substantially the same as the upper surface level height LV1 of the first gate line SGLA.

[0115] like Figure 3D and Figure 3EAs shown, the portion of the first gate line SGLA that contacts the first upper contact portion CT11U can vertically overlap with the sidewall of the short side of the finned active region FA. The first gate line SGLA may include a first portion SGLA_a and a second portion SGLA_b, and the first portion SGLA_a may be disposed on the upper surface of the finned active region FA, and the second portion SGLA_b may be disposed on the sidewall of the short side of the finned active region FA. The second portion SGLA_b of the first gate line SGLA can form a dummy transistor in the SRAM cell 210A.

[0116] With reference Figures 1A-1F Similar to the description, a first lower barrier layer 142L may be formed on the sidewall and bottom surface of the first lower contact portion CT11L, and a first upper barrier layer 142U may be formed on the sidewall and bottom surface of the first upper contact portion CT11U.

[0117] The second contact structure CS22 can be formed on the finned active region FA in the plurality of finned active regions FA where the first contact structure CS11 is not arranged. For example... Figure 3C As shown, in SRAM cell 210A, the first contact structure CS11 (or the second memory node contact portion C_SN2) and the second contact structure CS22 (or the power node contact portion C_Vcc) can be formed on the fin-type active regions FA2 on both sides of the gate line SGL4. Additionally, the first contact structure CS11 (or the first memory node contact portion C_SN1) and the second contact structure CS22 (or the bit line contact portion C_BL) can be formed on the fin-type active regions FA5 on both sides of the gate line SGL3.

[0118] The second contact structure CS22 may include a second lower contact portion CT22L formed on the finned active region FA and a second upper contact portion CT22U formed on the second lower contact portion CT22L. The second contact structure CS22 does not contact the first gate line SGLA or the second gate line SGLB.

[0119] The height of the upper surface of the second lower contact portion CT22L can be approximately equal to the height of the upper surface of the first lower contact portion CT11L. Therefore, the horizontal height of the upper surface of the second lower contact portion CT22L can be the same as the horizontal height LV_C1 of the upper surface of the first lower contact portion CT11L.

[0120] With reference Figures 1A-1F Similar to the description, the second lower barrier layer 144L may be formed on the sidewall and bottom surface of the second lower contact portion CT22L, and the second upper barrier layer 144U may be formed on the sidewall and bottom surface of the second upper contact portion CT22U.

[0121] likeFigure 3E As shown, the sidewalls of the first lower contact portion CT11L and the second lower contact portion CT22L can be surrounded by a first inter-gate insulating layer 232 and a first insulating interlayer 234, which are sequentially stacked on the isolation layer 112 and the plurality of finned active regions FA. The first inter-gate insulating layer 232 can extend in the Y direction between adjacent gate lines SGLA and SGLB. The horizontal height of the upper surface of the first inter-gate insulating layer 232 can be the same as the horizontal height of the upper surface of the first gate line SGLA. Figure 3D The first gate inter-insulating layer 232 and the first insulating interlayer 234 may include insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0122] The sidewalls of the first upper contact portion CT11U and the second upper contact portion CT22U may be surrounded by an etch stop layer 242 and a second insulating interlayer 244 stacked in sequence. The etch stop layer 242 and the second insulating interlayer 244 may comprise insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc. In addition, the etch stop layer 242 may comprise a material that has etch selectivity relative to the first insulating interlayer 234.

[0123] The second part CT11U_2 of the first upper contact portion CT11U can be surrounded by the first insulating interlayer 234, and the bottom surface of the second part CT11U_2 can contact the first gate line SGLA. Although Figure 3E The image shown represents a portion of the bottom contact of the second part CT11U_2 with the first gate inter-insulating layer 232, but the example embodiment is not limited thereto.

[0124] like Figure 3D As shown, an insulating capping layer 240 may be formed on the first gate line SGLA and the second gate line SGLB, and the insulating capping layer 240 may be located between the first gate inter-insulator layer 232 and the first insulating interlayer 234. The insulating capping layer 240 may serve as a protective layer that limits and / or prevents damage to the first gate line SGLA and the second gate line SGLB that may occur during subsequent processing after the formation of the first gate line SGLA and the second gate line SGLB. The insulating capping layer 240 may include insulating materials such as silicon dioxide, silicon nitride, silicon oxynitride, etc. However, the material of the insulating capping layer 240 is not limited to these.

[0125] like Figure 3F As shown, the first gate line SGLA and the second gate line SGLB can be separated by a second inter-gate insulating layer 250. The second inter-gate insulating layer 250 can be disposed between the first gate line SGLA and the second gate line SGLB, which extend in a straight line along the Y direction and are adjacent to each other. According to an example embodiment, the height of the upper surface of the second inter-gate insulating layer 250 can be substantially equal to the height of the upper surface of the first inter-gate insulating layer 232.

[0126] like Figure 3B As shown, in the plurality of SRAM cells 210A, 210B, 210C, and 210D, the distance S1 between a fin active region FA having a channel region of a first conductivity type and an adjacent fin active region FA having a channel region of the first conductivity type can be substantially equal to the distance S2 between a fin active region FA having a channel region of the first conductivity type and an adjacent fin active region FA having a channel region of a second conductivity type. For example, in SRAM cell 210A, the plurality of fin active regions FA1, FA2, FA4, and FA5 can be arranged to be equidistant from each other.

[0127] For reference Figures 1A-1F The description of the integrated circuit device 100 shows that, since the first contact structure CS11 and the second contact structure CS22 include metal silicide, the first contact structure CS11 and the second contact structure CS22 can have reduced contact resistance, and an integrated circuit device 200 with sufficiently small contact resistance can be realized even if the size of the first contact structure CS11 and the second contact structure CS22 is small. Furthermore, since the first contact structure CS11 and the second contact structure CS22 include barrier layers 142L, 142U, 144L, and 144U, damage to the plurality of finned active regions FA and adjacent gate lines SGL caused during the process of forming the first contact structure CS11 and the second contact structure CS22 can be limited and / or prevented, and the increased size of the contact structures CS11 and CS22 can be formed in a relatively small space. Therefore, the plurality of finned active regions FA can be arranged as an SRAM cell array 210 separated from each other by the same distance. Therefore, the integrated circuit device 200A can have increased integration density.

[0128] Figures 4A-4D Plan view, layout view and cross-sectional view of an integrated circuit device according to an example embodiment are shown. Figure 4A This is a plan view of the main components of integrated circuit device 300. Figure 4B It is simply shown Figure 4A The layout diagram shows the arrangement of the fin-type active region (FA) and the gate line (SGL). Figure 4C It is along Figure 4A The sectional view taken from line 4C-4C'. Figure 4D It is along Figure 4A A sectional view taken from the line 4D-4D'. Figures 4A-4D In the same figures, the same reference numerals refer to Figures 1A-3G The same elements in the text will be used, and their detailed descriptions will be omitted.

[0129] Reference Figures 4A-4D Integrated circuit device 300 can be compared with reference Figures 3A-3GThe described integrated circuit device 200A has similar components. However, with regard to the integrated circuit device 300, the fin active region FA having a channel region of a second conductivity type among the plurality of fin active regions FA may be a pair of channel regions FA having a second conductivity type, the pair of channel regions extending parallel to each other.

[0130] In SRAM cell 310A, a pair of fin active regions F1A and F1B having a channel region of a second conductivity type may be arranged on one side of a fin active region F2 adjacent to a channel region of a first conductivity type. Additionally, a pair of fin active regions F5A and F5B having a channel region of a second conductivity type may be arranged on one side of a fin active region F4 adjacent to a channel region of a first conductivity type.

[0131] In SRAM cell 310A, a first transfer transistor PS1A comprising two transistors connected in series through the pair of finned active regions F5A and F5B can be implemented, and a first pull-down transistor PD1A comprising two transistors connected in series through the pair of finned active regions F5A and F5B can be implemented. Additionally, a second transfer transistor PS2A comprising two transistors connected in series through the pair of finned active regions F1A and F1B can be implemented, and a second pull-down transistor PD2A comprising two transistors connected in series through the pair of finned active regions F1A and F1B can be implemented. Figure 4A In the middle, fin regions F6A and F6B, as well as F10A and F10B, can be similar to fin regions F1A and F1B, as well as F5A and F5B, respectively.

[0132] The first lower contact portion CT31L of the first contact structure CS31 may extend to cover the sidewalls and upper surface of the finned active region F4 having a channel region of a first conductivity type, and to cover the sidewalls and upper surface of a pair of adjacent finned active regions F5A and F5B having a channel region of a second conductivity type. Additionally, the second lower contact portion CT32L of the second contact structure CS32 may be formed to cover the sidewalls and upper surface of the pair of finned active regions F5A and F5B.

[0133] Because the first pull-down transistor PD1A and the second pull-down transistor PD2A, as well as the first transmission transistor PS1A and the second transmission transistor PS2A, are connected in series through the paired fin active regions F5A and F5B and F1A and F1B, which have a second conductivity type, the integrated circuit device 300 can have improved performance.

[0134] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 ,Figure 8A , Figure 8B and Figures 9-11 This is a cross-sectional view used to illustrate the process sequence for manufacturing an integrated circuit device according to an example embodiment. (Refer to...) Figures 5A-11 Description of manufacturing reference according to example embodiments Figures 3A-3G The method described for the integrated circuit device 200A. Figure 5A , Figure 6A , Figure 8A and Figures 9-11 It corresponds to along Figure 3A A sectional view of some parts of the section view taken by line 3E-3E'. Figure 5B , Figure 6B and Figure 7 It corresponds to along Figure 3A A sectional view of some parts of the section view taken by line 3F-3F', and Figure 8B It corresponds to along Figure 3A A sectional view of some portions of the section view taken from line 3G-3G'. Figures 5A-11 In the same figures, the same reference numerals refer to Figures 3A-3G The same elements in the text will be used, and their detailed descriptions will be omitted.

[0135] Reference Figure 5A and Figure 5B By forming a mask pattern (not shown) on the substrate 110 and using the mask pattern as an etching mask to etch a portion of the substrate 110, a first trench T1 extending in the Y direction and a second trench T2 connected to the first trench T1 and extending in the X direction can be formed on the substrate 110.

[0136] When the first trench T1 and the second trench T2 are formed on the substrate 110, a plurality of fin-type active regions FA can be obtained, which protrude upward from the substrate 110 in a direction perpendicular to the main surface of the substrate 110 (direction Z) and extend in a direction (direction X).

[0137] According to an example embodiment, the mask pattern may be formed from a silicon nitride layer, a silicon oxynitride layer, a spin-on glass (SOG) layer, a spin-on hard mask (SOH) layer, a photoresist layer, or a combination thereof. However, the mask pattern is not limited to these.

[0138] Optionally, a process of oxidizing the exposed surfaces of the plurality of finned active regions FA can be performed to form a liner (not shown) covering the exposed surfaces of the plurality of finned active regions FA.

[0139] Then, an isolation layer 112 filling the first trench T1 and the second trench T2 can be formed on the substrate 110. The isolation layer 112 can be formed on the lower sidewalls of the plurality of fin active regions FA. In addition, the upper surface of the isolation layer 112 can be lower than the upper surface of the plurality of fin active regions FA, so that some portions of the upper surface and sidewalls of the plurality of fin active regions FA may not be covered by the isolation layer 112. According to an example embodiment, the isolation layer 112 can be formed using FSG, USG, BPSG, PSG, FOX, PE-TEOS, or TOSZ via a flowable CVD (FCVD) process or a spin-coating process.

[0140] Reference Figure 6A and Figure 6B An initial gate line SGL_p can be formed on the substrate 110 extending in the direction (direction Y) intersecting with the plurality of finned active regions FA.

[0141] An exemplary process for forming the initial gate line SGL_p may be a displacement multi-gate (RPG) process (or a post-gate process). For example, a plurality of gate spacers 130 providing a plurality of gate spaces and a first inter-gate insulating layer 232 may be formed. Then, a gate insulating layer 120 and the initial gate line SGL_p may be formed in the plurality of gate spaces defined by the plurality of gate spacers 130.

[0142] Here, the sidewalls of the plurality of finned active regions FA and a portion of the initial gate line SGL_P can vertically overlap each other, such that a portion of the initial gate line SGL_P, SGL_pb, can be formed on the sidewalls of the plurality of finned active regions FA.

[0143] According to an example embodiment, the gate insulating layer 120 may be formed of a silicon dioxide layer, a high-k dielectric layer, or a combination thereof. The high-k dielectric layer may be formed of a material with a dielectric constant greater than that of the silicon dioxide layer. For example, the dielectric constant of the gate insulating layer 120 may be from about 10 to about 25. The high-k dielectric layer may be formed of a material selected from hafnium dioxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium dioxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. However, the material of the high-k dielectric layer is not limited to these. According to an example embodiment, the gate insulating layer 120 may be formed by an ALD, CVD, or PVD process.

[0144] The initial gate line SGL_p may include a metal work function adjustment layer and a metal gap-filling layer filling the space formed above the metal work function adjustment layer. According to an example embodiment, the initial gate line SGL_p may have a multilayer structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal layer are stacked in sequence. Each of the metal nitride layer and the metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. Each of the metal nitride layer and the metal layer may be formed by an ALD, metal-organic ALD (MOALD), or metal-organic CVD (MOCVD) process. The conductive capping layer may serve as a protective layer to confine and / or prevent oxidation of the surface of the metal layer. Additionally, the conductive capping layer may serve as a wetting layer that facilitates the deposition process when another conductive layer is deposited on the metal layer. The conductive capping layer may be formed from metal nitrides such as TiN, TaN, or combinations thereof, but is not limited thereto. The gap-filling metal layer can extend onto the conductive capping layer. The gap-filling metal layer can be formed from a tungsten layer. The gap-filling metal layer can be formed using ALD, CVD, or PVD processes. The gap-filling metal layer can conceal depressions formed by steps on the upper surface of the conductive capping layer without creating voids.

[0145] Next, source / drain regions 116 may be formed on both sides of the initial gate line SGL_p on the plurality of finned active regions FA. Although not shown, source / drain regions 116 may include semiconductor layers epitaxially grown from the plurality of finned active regions FA. Source / drain regions 116 may be formed as: an embedded SiGe structure including a plurality of epitaxially grown SiGe layers, an epitaxially grown Si layer, or an epitaxially grown SiC layer.

[0146] Then, an insulating capping layer 240 may be formed on the initial gate line SGL_p and the first gate-to-gate insulating layer 232.

[0147] Reference Figure 7 A mask pattern (not shown) may be formed on the insulating capping layer 240, and the mask pattern may be used as an etching mask to remove a portion of the insulating capping layer 240 and a portion of the initial gate line SGL_p, thereby forming the first gate line SGLA and the second gate line SGLB.

[0148] Then, an insulating layer (not shown) may be formed on the insulating capping layer 240, and the upper part of the insulating layer may be planarized until the upper surface of the insulating capping layer 240 is exposed, so as to form a second gate inter-gate insulating layer 250 between the first gate line SGLA and the second gate line SGLB.

[0149] Reference Figure 8A and Figure 8BThe first insulating interlayer 234 may be formed on the insulating capping layer 240 and the second gate insulating layer 250.

[0150] Then, a first opening H11L and a second opening H22L can be formed on the second insulating interlayer 234, which expose the upper surfaces of the plurality of finned active regions FA on both sides of the first gate line SGLA and the second gate line SGLB.

[0151] Reference Figure 9 A first lower barrier layer 142L and a second lower barrier layer 144L may be formed in the first opening H11L and the second opening H22L. According to an example embodiment, the first lower barrier layer 142L and the second lower barrier layer 144L may be conformally formed on the inner walls of the first opening H11L and the second opening H22L. The first lower barrier layer 142L and the second lower barrier layer 144L may be formed using titanium nitride, tantalum nitride, tungsten nitride, titanium carbonitride, etc.

[0152] Next, conductive layers (not shown) can be formed on the first lower barrier layer 142L and the second lower barrier layer 144L to fill the first opening H11L and the second opening H22L, and the upper part of the conductive layer can be planarized until the upper surface of the first insulating interlayer 234 is exposed, thereby forming the first lower contact portion CT11L and the second lower contact portion CT22L that fill the first opening H11L and the second opening H22L.

[0153] According to an example embodiment, the conductive layer can be formed from a metal silicide using a CVD or ALD process. For example, the metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, etc. The first lower barrier layer 142L and the second lower barrier layer 144L protect the plurality of finned active regions FA from damage that could occur if materials (e.g., source gas) used in the process of forming the conductive layer using metal silicides penetrate into the plurality of finned active regions FA or the first insulating interlayer 234.

[0154] Reference Figure 10 The etching stop layer 242 and the second insulating interlayer 244 may be formed sequentially on the first lower contact portion CT11L, the second lower contact portion CT22L, and the first insulating interlayer 234.

[0155] Then, a third opening H11U and a fourth opening H22U can be formed on the etch stop layer 242 and the second insulating interlayer 244, exposing the upper surfaces of the first lower contact portion CT11L and the second lower contact portion CT22L. Here, the third opening H11U can also expose the upper surface of the first gate line SGLA.

[0156] In the etching process used to form the third opening H11U, the width of the third opening H11U can be formed to be greater than the width of the first lower contact portion CT11L. Therefore, the portion of the first insulating interlayer 234 adjacent to the first lower contact portion CT11L can also be etched. According to an example embodiment, by performing the etching process using an etchant that has etching selectivity between the first insulating interlayer 234 and the first lower contact portion CT11L, a third opening H11U with a bottom lower than the upper surface of the first lower contact portion CT11L can be formed.

[0157] Reference Figure 11 The first upper barrier layer 142U and the second upper barrier layer 144U may be formed in the third opening H11U and the fourth opening H22U.

[0158] Then, a conductive layer (not shown) filling the third opening H11U and the fourth opening H22U can be formed on the first upper barrier layer 142U and the second upper barrier layer 144U, and the upper part of the conductive layer can be planarized until the upper surface of the second insulating interlayer 244 is exposed, thereby forming the first upper contact portion CT11U and the second upper contact portion CT22U filling the third opening H11U and the fourth opening H22U.

[0159] The integrated circuit device 200A can be manufactured by performing the above processes.

[0160] Figure 12 This is a block diagram of a non-volatile memory device 900 according to an example embodiment. (Refer to...) Figure 12 The following describes a non-volatile memory device 900 that includes an integrated circuit device according to an example embodiment.

[0161] Reference Figure 12 The non-volatile memory device 900 can be configured as, for example, a NAND flash memory device. However, according to exemplary embodiments of the present invention, the non-volatile memory device 900 is not limited to a NAND flash memory device, but can be configured as various devices such as NOR flash memory, resistive random access memory (RRAM), phase-change RAM (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory, etc.

[0162] The non-volatile memory device 900 can be implemented as a three-dimensional array structure. The non-volatile memory device 900 can be applied to both flash memory devices in which the charge storage layer is formed by a conductive floating gate and charge trap flash (CTF) memory devices in which the charge storage layer is formed by an insulating layer.

[0163] The non-volatile memory device 900 may include a memory cell array 910, a line decoder circuit 920, a read / write circuit 930, a voltage generator circuit 940, and control logic and an input or output interface block 950.

[0164] The memory cell array 910 may include memory cells, which include word lines arranged in the row direction and bit lines arranged in the column direction. The memory cells may form a memory block.

[0165] The line decoder circuit 920 can be controlled by control logic and input or output interface block 950, and can select and drive word lines of memory cell array 910.

[0166] The read / write circuit 930 is controllable by control logic and input / output interface block 950, and can operate as either a read circuit or a write circuit depending on the operating mode. For example, in a read operation, the read / write circuit 930 operates as a read circuit, used to read data from the memory cell array 910 under the control of the control logic and input / output interface block 950. In a write (or programming) operation, the read / write circuit 930 operates as a write circuit, used to write data to the memory cell array 910 under the control of the control logic and input / output interface block 950.

[0167] The voltage generator circuit 940 is controllable by control logic and an input / output interface block 950, and can generate voltages for operating the non-volatile memory device 900. For example, the voltage generator circuit 940 can generate: word line voltages (such as programming voltage, turn-on voltage, verification voltage, select voltage, etc.), which will be provided to the word lines of the memory cell array 910; and a well bias voltage Vbb, which will be provided to or formed on the substrate of the memory cell array 910. Depending on the operating mode, the well bias voltage Vbb can be either 0V or a negative voltage.

[0168] The control logic and input / output interface block 950 controls the overall operation of the non-volatile memory device 900. The control logic and input / output interface block 950 provides a data transfer path between the non-volatile memory device 900 and external devices (e.g., a memory controller or host). When a programming operation is requested, the control logic and input / output interface block 950 controls the voltage generator circuit 940 to bias the substrate on which memory cells are formed, or the wells formed on the substrate, to a negative voltage.

[0169] The control logic and input or output interface block 950 may include at least one of the integrated circuit devices 100, 200, 200A and 300 according to the exemplary embodiments, or an integrated circuit device modified or changed according to the integrated circuit devices 100, 200, 200A and 300 within the scope of the exemplary embodiments of the inventive concept.

[0170] Figure 13 It is a block diagram of an electronic system 1000 including integrated circuit devices according to an example embodiment.

[0171] Reference Figure 13 The electronic system 1000 includes an input device 1010, an output device 1020, a processor device 1030, and a memory device 1040.

[0172] The processor device 1030 can control each of the input device 1010, output device 1020, and memory device 1040 via corresponding interfaces. The processor device 1030 may include at least one selected from microprocessors, digital signal processors, microcontrollers, and logic devices capable of performing functions similar to those of the microprocessors.

[0173] At least one of the processor device 1030 and the memory device 1040 includes at least one of the integrated circuit devices 100, 200, 200A and 300 according to the exemplary embodiments, or an integrated circuit device modified or changed according to the integrated circuit devices 100, 200, 200A and 300 within the scope of the exemplary embodiments of the inventive concept.

[0174] Each of the input device 1010 and the output device 1020 may include a keypad, a keyboard, or a display device.

[0175] For example, memory device 1040 may include memory 1042, volatile memory device, or non-volatile memory device such as flash memory device.

[0176] Figure 14 This is a block diagram of a memory system 1100 including an integrated circuit device according to an example embodiment.

[0177] Reference Figure 14 The memory system 1100 may include an interface unit 1130, a controller 1140, and a memory device 1120.

[0178] Interface unit 1130 can connect the host and memory systems (e.g., Figure 13The electronic system 1000 shown provides communication between itself and the host. Interface unit 1130 may include a data exchange protocol corresponding to the host for interacting with the host. Interface unit 1130 can communicate with the host via one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc.

[0179] Controller 1140 can receive data or addresses provided from an external source via interface unit 1130. Controller 1140 can access memory devices (e.g., by referring to data and addresses provided from the host). Figure 13 (The memory device 1040 shown). The controller 1140 can transfer data read from the memory device 1120 to the host via the interface unit 1130.

[0180] The controller 1140 may include a buffer memory 1150. The buffer memory 1150 may temporarily store write data provided by the host or data read from the memory device 1120.

[0181] Memory device 1120 may be configured as a storage medium for memory system 1100. For example, memory device 1120 may be formed of PRAM, MRAM, RERAM, FRAM, NOR flash memory, or combinations thereof. Memory device 1120 includes at least one of integrated circuit devices 100, 200, 200A, and 300 according to exemplary embodiments, or integrated circuit devices modified or altered from integrated circuit devices 100, 200, 200A, and 300 within the scope of exemplary embodiments of the inventive concept.

[0182] Figure 14 The memory system 1100 shown can be installed in information processing devices such as personal digital assistants (PDAs), portable computers, network tablets, digital cameras, portable media players (PMPs), mobile phones, cordless phones, and notebook computers. The memory system 1100 can be implemented as an MMC card, a Secure Digital (SD) card, a MicroSD card, a Memory Stick, an ID card, a PCMCIA (Personal Computer Memory Card International Association) card, a chip card, a USB card, a smart card, a Compact Flash (CF) card, etc.

[0183] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various modifications in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A plurality of fins extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the plurality of fins including a first fin and a second fin; The first lower contact portion extends over the first and second fins in the second direction, includes metal silicide, and covers the opposite sidewalls of the first fin in the second direction; A first lower barrier layer surrounds the sidewalls and bottom surface of the first lower contact portion and is at least located between the first lower contact portion and the opposite sidewalls of the first fin and between the first lower contact portion and the upper surface of the first fin. A first grid line located on the first fin and a second grid line located on the second fin, the first grid line and the second grid line extending in the second direction; as well as The first upper contact portion is located on the first gate line and the first lower contact portion. The first upper contact portion contacts the first gate line and the first lower contact portion. The width of the bottom surface of the first upper contact portion in the first direction is greater than the width of the top surface of the first lower contact portion in the first direction, and The interface between the first upper contact portion and the first lower contact portion is coplanar with the interface between the first upper contact portion and the first gate line.

2. The integrated circuit device according to claim 1, wherein, The bottom surface of the first upper contact portion contacts the top surface of the first gate line. Wherein, the sidewall of the first lower contact portion is spaced apart from the sidewall of the first gate line in the first direction, and The first gate line and the second gate line are spaced apart from each other.

3. The integrated circuit device according to claim 1, further comprising: The second lower contact portion is located on the second fin and is spaced apart from the first lower contact portion; as well as The second upper contact portion is located on the second lower contact portion. The bottom surface of the first upper contact portion is coplanar with the bottom surface of the second upper contact portion.

4. The integrated circuit device according to claim 1, wherein, The width of the bottom surface of the first upper contact portion in the first direction is greater than the width of the top surface of the first gate line in the first direction.

5. The integrated circuit device according to claim 1, wherein, The width of the first upper contact portion in the first direction is greater than the width of the first upper contact portion in the second direction, and The width of the first lower contact portion in the second direction is greater than the width of the first lower contact portion in the first direction.

6. An integrated circuit device, comprising: Substrate; as well as A static random access memory (SRAM) array located on the substrate, the SRAM array comprising: A plurality of fins extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the plurality of fins including a first fin and a second fin; The first lower contact portion extends over the first and second fins in the second direction, includes metal silicide, and covers the opposite sidewalls of the first fin in the second direction; A first lower barrier layer surrounds the sidewalls and bottom surface of the first lower contact portion and is at least located between the first lower contact portion and the opposite sidewalls of the first fin and between the first lower contact portion and the upper surface of the first fin; A first grid line located on the first fin and a second grid line located on the second fin, the first grid line and the second grid line extending in the second direction; and The first upper contact portion is located on the first gate line and the first lower contact portion. The first upper contact portion contacts the first gate line and the first lower contact portion. The width of the bottom surface of the first upper contact portion in the first direction is greater than the width of the top surface of the first gate line in the first direction, and The interface between the first upper contact portion and the first lower contact portion is coplanar with the interface between the first upper contact portion and the first gate line.

7. The integrated circuit device according to claim 6, wherein, The width of the first upper contact portion in the first direction is greater than the width of the first upper contact portion in the second direction, and the width of the first lower contact portion in the second direction is greater than the width of the first lower contact portion in the first direction.

8. The integrated circuit device according to claim 6, further comprising: The second lower contact portion is located on the second fin and is spaced apart from the first lower contact portion; as well as The second upper contact portion is located on the second lower contact portion. The bottom surface of the first upper contact portion is coplanar with the bottom surface of the second upper contact portion.

9. The integrated circuit device according to claim 6, wherein, The width of the bottom surface of the first upper contact portion in the first direction is greater than the width of the top surface of the first lower contact portion in the first direction.

10. The integrated circuit device according to claim 6, wherein, The bottom surface of the first upper contact portion contacts the top surface of the first gate line. Wherein, the sidewall of the first lower contact portion is spaced apart from the sidewall of the first gate line in the first direction, and The first gate line and the second gate line are spaced apart from each other.

11. An integrated circuit device, comprising: Substrate; A first finned active region and a second finned active region are spaced apart from each other on the substrate and extend in a first direction. A first gate line and a second gate line are located on the substrate, the first gate line and the second gate line extend in a straight line in a second direction that intersects the first direction, and the first gate line and the second gate line intersect the first fin active region and the second fin active region, respectively; A first contact structure is located on the first fin-type active region, the first contact structure is located on one side of the first gate line, the first contact structure contacts the first gate line, and the first contact structure includes: The first lower contact portion includes a metal silicide extending in the second direction and covering the opposite sidewall of the first finned active region in the second direction; A first lower barrier layer surrounds the sidewalls and bottom surface of the first lower contact portion, and is at least located between the opposing sidewalls of the first lower contact portion and the first finned active region, and between the first lower contact portion and the top surface of the first finned active region; and A first upper contact portion is located on the first lower contact portion; and a second contact structure is located on the second fin-type active region, the second contact structure being located on one side of the second gate line, the second contact structure comprising: The second lower contact portion includes metal silicide; A second lower barrier layer surrounds the sidewalls and bottom surface of the second lower contact portion; and The second upper contact portion is located on the second lower contact portion. The interface between the first upper contact portion and the first lower contact portion is coplanar with the interface between the first upper contact portion and the first gate line.

12. The integrated circuit device according to claim 11, wherein, The first upper contact portion contacts the upper surface of the first gate line.

13. The integrated circuit device according to claim 11, wherein, The first fin-type active region and the second fin-type active region protrude from the substrate in a direction perpendicular to the main surface of the substrate. The first lower contact portion extends to cover the sidewall and upper surface of the second fin-type active region.

14. The integrated circuit device according to claim 11, wherein, The width of the first upper contact portion in the first direction is greater than the width of the second upper contact portion in the first direction.

15. The integrated circuit device according to claim 11, wherein, The portion of the first gate line that contacts the first upper contact portion is a dummy gate.

16. The integrated circuit device according to claim 11, wherein, The portion of the first gate line that contacts the first upper contact portion vertically overlaps with the sidewall of the first fin-type active region.

17. The integrated circuit device according to claim 11, wherein, The first upper contact portion includes a first part and a second part. The first portion of the first upper contact portion contacts the first lower contact portion, and The second portion of the first upper contact portion protrudes downward from one side of the first portion and contacts the first gate line.

18. The integrated circuit device according to claim 17, wherein, The bottom surface of the second portion of the first upper contact portion is lower than the upper surface of the first lower contact portion.

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