PMOS transistor and manufacturing method thereof
By forming an inverted trapezoidal polysilicon gate in a PMOS transistor and protecting it with a hard mask layer, the problem of high-resistivity phase transition of polysilicon gate metal silicides was solved, achieving a reduction in metal contact resistance and performance improvement in the low-resistivity phase.
Patent Information
- Application Number
- CN202411085896.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-08
- Publication Date
- 2026-02-13
AI Technical Summary
During the shrinking of feature size in MOS transistors, the metal silicide of the polysilicon gate is difficult to transition from a high-resistivity phase to a low-resistivity phase, leading to increased contact resistance and affecting the threshold voltage and high-frequency characteristics of the transistor.
By forming an inverted trapezoidal structure on the polysilicon gate and using a hard mask layer and sidewalls to protect the polysilicon gate during the epitaxial process, the surface area of the polysilicon gate is increased, forming a low-resistivity metal silicide phase.
This effectively reduces the resistance between the polysilicon gate and the metal contact hole, improves the performance of the PMOS transistor, simplifies the manufacturing process, and reduces costs.
Smart Images
Figure CN121531734A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a PMOS transistor and a manufacturing method of the PMOS transistor. BACKGROUND
[0002] The polysilicon gate surface in the MOS transistor is usually formed with metal silicide to reduce the contact resistance, and the metal contact hole formed above the polysilicon gate is electrically connected with the polysilicon gate through the metal silicide. However, as the feature size of the MOS transistor is reduced, the size of the polysilicon gate is reduced, and the metal silicide (such as cobalt silicide (CoSi)) on the surface of the polysilicon gate is difficult to be converted from high resistance phase to low resistance phase due to the line width effect, which results in the increase of the resistance of the metal silicide, and the hole diameter of the metal contact hole is correspondingly small, which finally results in the increase of the resistance between the metal contact hole and the polysilicon gate, which can cause the threshold voltage of the MOS transistor to rise and also affect the high frequency characteristics of the MOS transistor.
[0003] If the polysilicon gate is formed in an inverted trapezoidal structure, the upper surface area of the polysilicon gate can be increased while the feature size of the MOS transistor is reduced, which is beneficial to the conversion of the metal silicide from high resistance phase to low resistance phase, thereby reducing the risk of the increase of the resistance between the metal contact hole and the polysilicon gate. However, when manufacturing the PMOS transistor, a polysilicon material layer is usually formed and covered with a hard mask layer, and the polysilicon material layer and the hard mask layer are patterned, the polysilicon gate is formed from the polysilicon material layer, and the hard mask layer covers the upper surface of the polysilicon gate. In this way, when the source / drain epitaxial layer is formed by using a trench epitaxial process, the hard mask layer can protect the upper surface of the polysilicon gate to avoid epitaxial growth. However, the longitudinal section of the PMOS transistor formed by using the process is rectangular, which is not conducive to reducing the contact resistance of the gate surface. SUMMARY
[0004] The present application provides a manufacturing method of a PMOS transistor, which can increase the area of the upper surface of the polysilicon gate when forming the source / drain epitaxial layer by using an epitaxial process, so as to form metal silicide in low resistance phase and improve the performance of the PMOS transistor. The present application further provides a PMOS transistor.
[0005] In one aspect, the present application provides a manufacturing method of a PMOS transistor, which comprises:
[0006] forming a first dielectric layer on a substrate, and forming a first trench penetrating through the first dielectric layer;
[0007] forming a first sidewall covering the sidewall of the first trench, and forming a gate dielectric layer connecting the first sidewall and covering the bottom wall of the first trench, the first sidewall gradually increases in width from top to bottom;
[0008] filling a polysilicon material layer in the first trench, an upper surface of the polysilicon material layer being flush with an upper surface of the first dielectric layer;
[0009] etching the polysilicon material layer to form a second trench on top of the first trench, the remaining polysilicon material layer forming a polysilicon gate;
[0010] filling a hard mask layer in the second trench, an upper surface of the hard mask layer being flush with an upper surface of the first dielectric layer;
[0011] removing the first dielectric layer; and
[0012] forming a recess on both sides of the polysilicon gate and forming a source / drain epitaxial layer in the recess by an epitaxial process, wherein the polysilicon gate is covered by the first sidewall on the side and the hard mask layer on the upper surface when the epitaxial process is performed.
[0013] Optionally, the manufacturing method further comprises:
[0014] removing the hard mask layer covering the upper surface of the polysilicon gate; and
[0015] forming a metal silicide on the upper surface of the polysilicon gate and the source / drain epitaxial layer.
[0016] Optionally, before the first sidewall is formed, the first trench exposes the substrate.
[0017] Optionally, forming the first sidewall covering the sidewall of the first trench and forming the gate dielectric layer connecting the first sidewall and covering the bottom wall of the first trench comprises:
[0018] forming a second dielectric layer along the surface of the first dielectric layer and the inner wall of the first trench;
[0019] etching the second dielectric layer by a non-isotropic etching process to expose the upper surface of the first dielectric layer and the substrate in the first trench, the remaining second dielectric layer covering the sidewall of the first trench and gradually increasing in width from top to bottom; and
[0020] forming a third dielectric layer along the first dielectric layer, the second dielectric layer and the surface of the substrate, the stack of the second dielectric layer and the third dielectric layer forming the sidewall, and the part of the third dielectric layer covering the substrate forming the gate dielectric layer.
[0021] Optionally, after the first dielectric layer and the first trench are formed, the bottom wall of the first trench has a pad oxide layer covering the substrate.
[0022] Optionally, forming a first spacer on sidewalls of the first trench and forming a gate dielectric layer on a bottom wall of the first trench comprises:
[0023] forming a second dielectric layer along a surface of the first dielectric layer and an inner wall of the first trench;
[0024] etching the second dielectric layer by an anisotropic etching process to expose a top surface of the first dielectric layer and the substrate inside the trench, and the remaining second dielectric layer covers sidewalls of the trench and gradually increases in width from top to bottom; and
[0025] forming a third dielectric layer along the first dielectric layer, the second dielectric layer and a surface of the substrate, the third dielectric layer and the second dielectric layer form the spacer, and the third dielectric layer between the spacer and the pad oxide layer inside the trench forms the gate dielectric layer.
[0026] Optionally, after the epitaxial process is completed, the manufacturing method further comprises:
[0027] forming a second spacer on a surface of the first spacer away from the polysilicon gate; and
[0028] performing source / drain ion implantation on the source / drain epitaxial layer.
[0029] In another aspect, the present application provides a PMOS transistor formed by the manufacturing method, the PMOS transistor comprising:
[0030] a substrate;
[0031] a gate dielectric layer, a polysilicon gate, a hard mask layer and a first spacer formed on the substrate, the hard mask layer covers a top surface of the polysilicon gate, the first spacer covers sidewalls of the gate dielectric layer, the polysilicon gate and the hard mask layer, wherein the polysilicon gate gradually decreases in width from top to bottom; and
[0032] a source / drain epitaxial layer embedded in the substrate on both sides of the polysilicon gate.
[0033] Optionally, a second dielectric layer and a third dielectric layer are formed on the substrate, the second dielectric layer is located on both sides of the polysilicon gate, the second dielectric layer gradually increases in width from top to bottom, and the third dielectric layer is between the polysilicon gate and the second dielectric layer and between the polysilicon gate and the substrate; wherein the first spacer comprises the second dielectric layer and the third dielectric layer on the sidewalls of the polysilicon gate, and the gate dielectric layer comprises the third dielectric layer between the polysilicon gate and the substrate.
[0034] Optionally, a pad oxide layer is also formed on the substrate below the third dielectric layer, and the gate dielectric layer further includes the pad oxide layer.
[0035] Optionally, the substrate forms Σ-shaped grooves on both sides of the polysilicon gate, and the source / drain epitaxial layer fills the grooves.
[0036] The PMOS transistor fabrication method and the PMOS transistor provided by this invention have at least the following advantages:
[0037] First, the width of the polysilicon gate gradually decreases from top to bottom. When the transistor feature size is small, the upper surface area of the polysilicon gate can be increased. This is beneficial for the metal silicide formed on the upper surface of the polysilicon gate to be converted from a high-resistivity phase to a low-resistivity phase. It avoids the increase in contact resistance on the upper surface of the polysilicon gate due to the high-resistivity phase of the metal silicide, which helps to improve the performance of the PMOS transistor.
[0038] Secondly, by forming the second trench at the top of the first trench and filling it with a hard mask layer, the hard mask layer covers the upper surface of the polysilicon gate. The hard mask layer and the first sidewall can protect the polysilicon gate during the epitaxial process of forming the source and drain epitaxial layer, preventing the polysilicon gate from epitaxial growth and helping to improve the quality of the PMOS transistor.
[0039] Furthermore, using this fabrication method, the formation of the polysilicon gate and the hard mask layer does not require photolithography and etching processes, resulting in a simple, efficient, and low-cost process. Attached Figure Description
[0040] Figure 1 This is a schematic flowchart illustrating the fabrication method of a PMOS transistor according to an embodiment of the present invention.
[0041] Figures 2A to 2K This is a cross-sectional schematic diagram of a method for fabricating a PMOS transistor according to an embodiment of the present invention.
[0042] Figures 3A to 3K This is a cross-sectional schematic diagram of a method for fabricating a PMOS transistor according to another embodiment of the present invention. Detailed Implementation
[0043] The PMOS transistor and its fabrication method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the terms "first," "second," etc., used in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms can be replaced where appropriate. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, and are only used to facilitate clarity in illustrating the embodiments of the present invention. Furthermore, spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.
[0044] This invention relates to a method for fabricating a PMOS transistor. The method will be described below with reference to the accompanying drawings.
[0045] Reference Figure 1 , Figure 2A and Figure 3A According to the method for fabricating a PMOS transistor according to an embodiment of the present invention, in step S1, a first dielectric layer 110 is formed on a substrate 100, and a first trench 10 is formed through the first dielectric layer 110.
[0046] Substrate 100 may be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or other substrates known to those skilled in the art for supporting semiconductor devices. In the following description, substrate 100 is, for example, a silicon substrate. Substrate 100 may include configurations depending on the semiconductor device design requirements, such as implanting certain dopant ions to adjust electrical parameters according to design needs, and isolation structures (not shown) may be formed within substrate 100.
[0047] The first dielectric layer 110 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (nitrogen-doped silicon carbide). The first dielectric layer 110 may be one or a combination of borosilicate glass (BPSG), undoped silicate glass (USG), spin-coated glass (SOG), tetraethyl orthosilicate (TEOS), or high-density plasma CVD (HDP-CVD) oxide. In the following description, the first dielectric layer 110 is, for example, silicon oxide formed by tetraethyl orthosilicate (TEOS). It should be noted that the materials, thicknesses, and formation methods of the layers mentioned above and below are merely examples of embodiments of the present invention. Different materials, thicknesses, and formation methods may be used according to different needs, and these should not constitute a limitation of the present invention.
[0048] like Figure 2A As shown, in one embodiment, no other material is formed on the surface of the substrate 100 before the formation of the first dielectric layer 110. However, the invention is not limited to this; for example, in another embodiment, an oxide layer or other materials may be formed on the surface of the substrate 100 before the formation of the first dielectric layer 110.
[0049] The first trench 10, penetrating the first dielectric layer 110, can be formed using photolithography and etching processes. For example... Figure 2B As shown, in one embodiment, the first trench 10 exposes the substrate 100, meaning the substrate 100 forms the bottom wall of the first trench 10. The invention is not limited thereto; for example, in another embodiment, see... Figure 3A Before the formation of the first dielectric layer 110, no other material is formed on the surface of the substrate 100. After the first dielectric layer 110 is etched to form the first trench 10, a pad oxide layer 101 (e.g., silicon oxide) is formed on the exposed surface of the substrate 100 by means of thermal oxidation, so that the bottom wall of the first trench 10 has the pad oxide layer 101 before proceeding to subsequent steps.
[0050] Reference Figure 1 In step S2, a first sidewall is formed covering the sidewall of the first trench 10, and a grid dielectric layer is formed connecting the first sidewall and covering the bottom wall of the first trench 10. The width of the first sidewall gradually increases from top to bottom. The width direction of the first sidewall is parallel to the length direction of the trench.
[0051] As an example, in one embodiment, in Figure 2A Based on the structure shown, step S2 may include the following process:
[0052] First, refer to Figure 2BA second dielectric layer 120 is formed along the surface of the first dielectric layer 110 and the inner wall of the first trench 10. The second dielectric layer 120 conformally covers the surface of the first dielectric layer 110 and the inner wall of the first trench 10, for example, using silicon nitride.
[0053] Then, refer to Figure 2C The second dielectric layer 120 is etched using an anisotropic etching process to expose the upper surface of the first dielectric layer 110 and the substrate 100 in the first trench 10. The remaining second dielectric layer 120 covers the sidewalls of the first trench 10 and its width gradually increases from top to bottom. For example, the etching selectivity of the second dielectric layer 120 with the first dielectric layer 110 and the substrate 100 can be used to use the first dielectric layer 110 and the substrate 100 as the etching stop layer of the anisotropic etching process.
[0054] Then, refer to Figure 2D A third dielectric layer 130 is formed along the surface of the first dielectric layer 110, the second dielectric layer 120, and the substrate 100. The third dielectric layer 130 conformally covers the first dielectric layer 110, the second dielectric layer 120, and the surface of the substrate 100 within the first trench 10. The third dielectric layer 130 is, for example, made of silicon oxide. In this embodiment, the stack of the third dielectric layer 130 and the second dielectric layer 120 constitutes a first sidewall SP1, and the portion of the substrate 100 within the first trench 10 covered by the third dielectric layer 130 constitutes a gate dielectric layer GOX.
[0055] As an example, in another embodiment, in Figure 3A Based on the structure shown, step S2 may include the following process:
[0056] First, refer to Figure 3B A second dielectric layer 120 is formed along the surface of the first dielectric layer 110 and the inner wall of the first trench 10. The second dielectric layer 120 conformally covers the surface of the first dielectric layer 110 and the inner wall of the first trench 10, for example, using silicon nitride.
[0057] Then, refer to Figure 3C The second dielectric layer 120 is etched using an anisotropic etching process, exposing the upper surface of the first dielectric layer 110 and the pad oxide layer 101 in the first trench 10. The remaining second dielectric layer 120 covers the sidewall of the first trench 10 and its width gradually increases from top to bottom. For example, the etching selectivity of the second dielectric layer 120 with the first dielectric layer 110 and the pad oxide layer 101 can be used to use the first dielectric layer 110 and the pad oxide layer 101 as the etching stop layer of the anisotropic etching process.
[0058] Then, refer to Figure 3DA third dielectric layer 130 is formed along the first dielectric layer 110, the second dielectric layer 120, and the pad oxide layer 101 within the first trench 10. The third dielectric layer 130 conformally covers the surfaces of the first dielectric layer 110, the second dielectric layer 120, and the pad oxide layer 101 within the first trench 10. The third dielectric layer 130 is, for example, made of silicon oxide. In this embodiment, the stack of the third dielectric layer 130 and the second dielectric layer 120, and the pad oxide layer 101 they cover, constitute a first sidewall SP1'. The stack of the third dielectric layer 130 and the pad oxide layer located between the first sidewalls SP1' within the first trench 10 constitutes a gate dielectric layer GOX'.
[0059] like Figure 2D and Figure 3D The difference between the two embodiments of step S2 described above lies in the different structures of the first sidewall and the gate dielectric layer. In step S2, by setting suitable thicknesses for the second dielectric layer 120 and / or the third dielectric layer 130, and by setting suitable parameters for the aforementioned anisotropic etching process, the first sidewall (e.g., Figure 2D The first sidewall SP shown or as Figure 3D The width of the first sidewall (SP1') gradually increases from top to bottom, and the thickness of the second dielectric layer 120 and / or the third dielectric layer 130, as well as the parameters of the anisotropic etching process, can be adjusted as needed. For example, anisotropic dry etching is performed using a dry etching apparatus to carry out the anisotropic etching process, wherein the process gas includes, for example, CH2F2 and O2. The morphology of the second dielectric layer 120 after the anisotropic etching process can be adjusted by adjusting parameters such as the process gas flow rate, pressure, ion acceleration voltage, RF source power, and etching time.
[0060] In the above embodiments, the gate dielectric layer (such as...) Figure 2D The gate dielectric layer shown is GOX or as shown Figure 3D The gate dielectric layer (GOX') shown is formed after the first trench 10 is formed. Compared with forming the first trench after the gate dielectric layer is formed, the gate dielectric layer can avoid being damaged by the etching process that makes the first trench.
[0061] Reference Figure 1 , Figure 2E , Figure 2F as well as Figure 3E , Figure 3F In step S3, a polycrystalline silicon material layer 140 is filled in the first trench 10, and the upper surface of the polycrystalline silicon material layer 140 is flush with the upper surface of the first dielectric layer 110.
[0062] Specifically, refer to Figure 2E and Figure 3EFirst, a chemical vapor deposition process can be used to deposit polycrystalline silicon material on the substrate 100, so that the polycrystalline silicon material fills the first trench 10 and covers the third dielectric layer 130 outside the first trench 10, with the upper surface of the polycrystalline silicon material higher than the upper surface of the third dielectric layer 130; then, referring to... Figure 2F and Figure 3F A planarization process is performed to remove the polysilicon material above the first dielectric layer 110. For example, CMP (chemical mechanical polishing) can be used to remove the polysilicon material above the first dielectric layer 110. After this planarization process, the upper surface of the first dielectric layer 110 outside the first trench 10 is exposed, and the remaining polysilicon material fills the first trench 10 with its upper surface flush with the upper surface of the first dielectric layer 110. Optionally, after completing the planarization process, ion implantation can be performed on the polysilicon material in the first trench 10 to adjust its electrical properties.
[0063] Reference Figure 1 , Figure 2G as well as Figure 3G In step S4, the polysilicon material layer 140 is etched to form a second trench 20 on top of the first trench 10, and the remaining polysilicon material layer 140 forms a polysilicon gate PG. The polysilicon gate PG is the gate of a PMOS transistor.
[0064] As an example, a dry etching process with a set etching time is performed on the polysilicon material layer 140 to form a second trench 20 on top of the first trench 10. The second trench 20 consists of the remaining polysilicon material layer 140 and the first sidewall (e.g., ...). Figure 2G The first sidewall SP shown or as Figure 3G The first sidewall SP1' shown is used to enclose the area. The etching time can be specifically set according to the depth of the second trench 20 to be formed.
[0065] Through the above process, a polysilicon gate PG is formed within the first trench 10. The first sidewall and the gate dielectric layer are located on the side and bottom surfaces of the polysilicon gate PG, respectively. Since the first sidewall has a gradually increasing width from top to bottom, the width of the polysilicon gate PG gradually decreases from top to bottom. With a relatively short trench length, compared to a conventional polysilicon gate structure with uniform width at both the top and bottom, the area of the upper surface of the polysilicon gate can be increased. Furthermore, by controlling the morphology of the first sidewall, the morphology of the polysilicon gate PG is effectively adjusted. Compared to directly forming a polysilicon gate that is wider at the top and narrower at the bottom using an etching process and then forming sidewalls on its sides, the method of this embodiment allows for more convenient control of the morphology of the polysilicon gate PG. Furthermore, research has found that if a polysilicon gate that is wider at the top and narrower at the bottom is formed first, and then a sidewall is formed on the side, it is difficult for the sidewall material to adhere to the bottom of the narrower polysilicon gate, which can easily lead to voids and affect the performance of the PMOS transistor. In this embodiment of the invention, the first sidewall that is narrower at the top and wider at the bottom is formed first in the first trench 10. The space between the first sidewalls in the first trench 10 is wider at the top and narrower at the bottom, which makes it easier to fill the polysilicon material and less likely to form voids.
[0066] Reference Figure 1 , Figure 2H , Figure 2I as well as Figure 3H as well as Figure 3I In step S5, a hard mask layer HM is filled into the second trench 20, the upper surface of which is flush with the upper surface of the first dielectric layer 110. Since the second trench 20 exposes the upper surface of the polysilicon gate PG and the top inner side of the first sidewall, after the hard mask layer HM is filled into the second trench 20, it covers the upper surface of the polysilicon gate PG and the top inner side of the first sidewall, thus completely covering the polysilicon gate PG with the hard mask layer HM and the first sidewall.
[0067] Specifically, refer to Figure 2H and Figure 3H A chemical vapor deposition process can be used to first deposit a hard mask material 150 (e.g., silicon nitride) on the substrate 100, so that the hard mask material 150 fills the second trench 20 and covers the surface of the first dielectric layer 110 outside the second trench 20, with the upper surface of the hard mask material 150 higher than the upper surface of the first dielectric layer 110; then, referring to... Figure 2I and Figure 3IA planarization process is performed to remove the hard mask material 150 above the first dielectric layer 110. For example, CMP (chemical mechanical polishing) can be used to grind and remove the hard mask material 150 above the first dielectric layer 110. After this planarization process, the upper surface of the first dielectric layer 110 outside the second trench 20 is exposed, and the remaining hard mask material 150 fills the second trench 20 to form a hard mask layer HM, whose upper surface is flush with the upper surface of the first dielectric layer 110.
[0068] Reference Figure 1 , Figure 2J and Figure 3J In step S6, the first dielectric layer 110 is removed. By selecting suitable materials, the first dielectric layer 110 (e.g., silicon oxide) and the second dielectric layer 120 (e.g., silicon nitride) can have high etching selectivity, as can the first dielectric layer 110 (e.g., silicon oxide) and the hard mask layer HM (e.g., silicon nitride). In this way, step S6 may not require setting a mask. Instead, by utilizing the etching selectivity of the first dielectric layer 110, the second dielectric layer 120, and the hard mask layer HM, a dry or wet etching process is used to remove the first dielectric layer 110. During this process, the second dielectric layer 120 and the hard mask layer HM are essentially not etched.
[0069] By forming a second trench 20 within the first trench 10 and a hard mask layer HM within the second trench 20 (using the first dielectric layer as a protective layer for the substrate 100), a hard mask layer HM with controllable thickness can be formed, facilitating precise removal later (because the thickness is controllable). At the same time, a difference in film layers can be formed between the surface of the substrate 100 and the surface of the polysilicon gate PG, thereby ensuring that no epitaxial film layer grows on the top of the gate structure when epitaxially growing the source and drain portions on the substrate 100 (both sides of the gate structure) (i.e., when performing epitaxial growth at the source and drain on both sides of the gate structure).
[0070] After step S6, the first dielectric layer 110 is removed, and a gate structure is formed on the substrate 100. The gate structure includes a gate dielectric layer (such as...) stacked on the substrate 100. Figure 2J The gate dielectric layer shown is GOX or as shown Figure 3J The diagram shows a gate dielectric layer (GOX'), a polysilicon gate (PG), and a hard mask layer (HM), and also includes a first sidewall (e.g., a slab) covering the sides of the gate dielectric layer, the polysilicon gate (PG), and the hard mask layer (HM). Figure 2J The first sidewall SP1 shown or as Figure 3J The first sidewall SP1' shown.
[0071] Optionally, before removing the first dielectric layer 110 and proceeding with subsequent steps, the fabrication method may further include an LDD ion implantation step, such as p-type ion implantation, to form PLDD regions in the substrate 100 on both sides of the polysilicon gate PG.
[0072] Reference Figure 1 , Figure 2K and Figure 3K In step S7, grooves are formed on both sides of the polysilicon gate PG and source / drain epitaxial layers 160 are formed in the grooves by an epitaxial process. During the epitaxial process, the polysilicon gate PG is covered by the first sidewall and the upper surface is covered by a hard mask layer HM.
[0073] The source / drain epitaxial layer 160 formed in the grooves on both sides of the polysilicon gate PG serves as the source / drain of the PMOS transistor. The hard mask layer HM and the first sidewall can protect the polysilicon gate PG from epitaxial growth during the epitaxial process of forming the source / drain epitaxial layer 160, which helps to improve the quality of the PMOS transistor.
[0074] As an example, step S7 may include:
[0075] First, for example, anisotropic dry etching is used to form grooves in the substrate 100 regions on both sides of the gate structure to serve as source / drain.
[0076] Subsequently, the grooves are etched using a suitable alkaline etchant such as tetramethylammonium hydroxide (TMAH), forming concave angles on the sidewalls of the grooves, thereby making the longitudinal section of the grooves ∑-shaped (see reference). Figure 2K and Figure 3K By forming a concave corner, the source / drain epitaxial layer 160 formed in the groove can generate compressive stress on the substrate 100 in the channel region, thereby improving the carrier mobility.
[0077] Subsequently, an epitaxial process (e.g., selective epitaxy) is performed within the Σ-shaped groove to form the source / drain epitaxial layer 160. As an example, a germanium-silicon seed layer can be formed first on the inner wall of the groove, and then an epitaxial growth process can be performed to grow a germanium-silicon layer on the seed layer to fill the groove. A single-crystal silicon capping layer is formed on top of the groove. The germanium-silicon seed layer, the germanium-silicon layer, and the capping layer form the source / drain epitaxial layer 160. During epitaxial growth, an impurity gas such as borane (B₂H₆) can be introduced as needed to introduce p-type dopant ions. In other embodiments, the specific process for forming the source / drain epitaxial layer 160 may differ from this.
[0078] After completing the epitaxial process, the fabrication method may further include covering the surface of the first sidewall away from the polysilicon gate PG with a second sidewall (not shown) and performing source / drain ion implantation on the source / drain epitaxial layer 160 (not shown). The second sidewall may be formed using sidewall processes known in the art, and may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. The source / drain ion implantation is, for example, a p-type heavily doped implantation.
[0079] The fabrication method of the PMOS transistor in this embodiment of the invention may further include the following steps: removing the hard mask layer HM covering the upper surface of the polysilicon gate PG; then forming a metal silicide (not shown) on the upper surface of the polysilicon gate PG and the source / drain epitaxial layer, wherein the metal silicide may include at least one of titanium silicide, cobalt silicide, nickel silicide, and tantalum silicide. Subsequently, an interlayer dielectric layer (ILD) may be formed on the substrate 100, and a metal contact hole may be formed through the interlayer dielectric layer. The metal contact hole connects to the corresponding polysilicon gate PG or the source / drain epitaxial layer 160 through the metal silicide. Compared to not forming a metal silicide, the metal silicide can reduce the contact resistance of the polysilicon gate PG; furthermore, since the width of the polysilicon gate PG gradually decreases from top to bottom, when the transistor feature size is small, the upper surface area of the polysilicon gate PG can be increased, making it easier for the metal silicide to transition from a high-resistance phase to a low-resistance phase, thereby effectively reducing the resistance between the metal contact hole and the polysilicon gate PG, which helps to improve the performance of the PMOS transistor.
[0080] In the PMOS transistor fabrication method described in the above embodiments, while forming the source and drain epitaxial layers 160 using epitaxial technology, the area of the upper surface of the polysilicon gate PG can be increased, which facilitates the formation of low-resistivity metal silicides and improves the performance of the PMOS transistor. Moreover, using this fabrication method, the formation of the polysilicon gate PG and the hard mask layer HM does not require photolithography and etching processes, which makes the process simple, low in cost, and highly efficient.
[0081] This invention also relates to a PMOS transistor, which can be formed using the PMOS transistor fabrication method described in the above embodiments. (Refer to...) Figure 2K and Figure 3K The PMOS transistor includes a substrate 100 and a gate dielectric layer (e.g., ...) formed on the substrate 100. Figure 2K The gate dielectric layer shown is GOX or as shown Figure 3K The diagram shows the gate dielectric layer GOX', the polysilicon gate PG, the hard mask layer HM, and the first sidewall (as shown). Figure 2K The first sidewall SP1 shown or as Figure 3KThe first sidewall SP1' shown also includes source / drain epitaxial layers 160 embedded in the substrate 100 on both sides of the polysilicon gate PG. The hard mask layer HM covers the upper surface of the polysilicon gate PG, and the first sidewall covers the gate dielectric layer, the polysilicon gate PG and the side of the hard mask layer HM. The width of the polysilicon gate PG gradually decreases from top to bottom.
[0082] As an example, a groove with a Σ-shaped longitudinal section is formed in the substrate 100 on both sides of the polysilicon gate PG, and the source / drain epitaxial layer 160 fills the groove.
[0083] like Figure 2K and Figure 3K As shown, a second dielectric layer 120 and a third dielectric layer 130 may be formed on the substrate 100. The second dielectric layer 120 is located on both sides of the polysilicon gate PG, and the width of the second dielectric layer 120 gradually increases from top to bottom. The third dielectric layer 130 is located between the polysilicon gate PG and the second dielectric layer 120, and between the polysilicon gate 130 and the substrate 100. The first sidewall includes the second dielectric layer 120 and the third dielectric layer 130 located on the side of the polysilicon gate PG, and the gate dielectric layer includes the third dielectric layer 130 located between the polysilicon gate PG and the substrate 100. Optionally, referring to… Figure 3K A pad oxide layer 101 may also be formed on the substrate 100 below the third dielectric layer 130, and the gate dielectric layer may further include the pad oxide layer 101 located between the polysilicon gate PG and the substrate 100. (Refer to...) Figure 2K In one embodiment, the gate dielectric layer GOX is formed of a third dielectric layer 130 located between the polysilicon gate PG and the substrate 100. (Refer to...) Figure 3K In another embodiment, the gate dielectric layer GOX is formed by a third dielectric layer 130 and a pad oxide layer 101 located between the polysilicon gate PG and the substrate 100.
[0084] In the PMOS transistor, the width of the polysilicon gate PG gradually decreases from top to bottom. When the transistor feature size is small, the upper surface area of the polysilicon gate PG can be increased. This helps to prevent the upper surface area of the polysilicon gate PG from becoming too small while reducing the transistor feature size. It also facilitates the transformation of the metal silicide formed on the upper surface of the polysilicon gate PG from a high-resistivity phase to a low-resistivity phase, which helps to avoid an increase in the contact resistance on the upper surface of the polysilicon gate PG. This helps to improve the performance of the PMOS transistor. Furthermore, the hard mask layer HM covers the upper surface of the polysilicon gate PG. The hard mask layer HM and the first sidewall can protect the polysilicon gate PG from epitaxial growth during the epitaxial process of forming the source-drain epitaxial layer 160, which helps to improve the quality of the PMOS transistor.
[0085] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and relevant parts can be understood by referring to them.
[0086] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for fabricating a PMOS transistor, characterized in that, include: A first dielectric layer is formed on the substrate, and a first trench is formed through the first dielectric layer; A first sidewall is formed to cover the sidewall of the first trench, and a grid dielectric layer is formed to connect the first sidewall and cover the bottom wall of the first trench, wherein the width of the first sidewall gradually increases from top to bottom; A polycrystalline silicon material layer is filled in the first trench, and the upper surface of the polycrystalline silicon material layer is flush with the upper surface of the first dielectric layer. The polysilicon material layer is etched to form a second trench at the top of the first trench, and the remaining polysilicon material layer forms a polysilicon gate. A hard mask layer is filled in the second trench, and the upper surface of the hard mask layer is flush with the upper surface of the first dielectric layer; Remove the first dielectric layer; and Grooves are formed on both sides of the polysilicon gate, and source / drain epitaxial layers are formed in the grooves by an epitaxial process. During the epitaxial process, the polysilicon gate is covered by the first sidewall and the upper surface is covered by the hard mask layer.
2. The manufacturing method as described in claim 1, characterized in that, Also includes: Remove the hard mask layer covering the upper surface of the polysilicon gate; as well as Metal silicides are formed on the upper surfaces of the polysilicon gate and the source / drain epitaxial layers.
3. The manufacturing method as described in claim 1, characterized in that, The first trench exposes the substrate before the first sidewall is formed.
4. The manufacturing method as described in claim 3, characterized in that, Forming a first sidewall covering the sidewall of the first trench, and forming a grid dielectric layer connecting the first sidewall and covering the bottom wall of the first trench, includes: A second dielectric layer is formed along the surface of the first dielectric layer and the inner wall of the first trench; The second dielectric layer is etched using an anisotropic etching process, exposing the upper surface of the first dielectric layer and the substrate within the first trench. The remaining second dielectric layer covers the sidewalls of the first trench and its width gradually increases from top to bottom. A third dielectric layer is formed along the first dielectric layer, the second dielectric layer, and the surface of the substrate. The stack of the second dielectric layer and the third dielectric layer constitutes the sidewall, and the portion of the third dielectric layer covering the substrate constitutes the gate dielectric layer.
5. The manufacturing method as described in claim 1, characterized in that, After the first dielectric layer and the first trench are formed, the bottom wall of the first trench has a pad oxide layer covering the substrate.
6. The manufacturing method as described in claim 5, characterized in that, Forming a first sidewall covering the sidewall of the first trench, and forming a grid dielectric layer connecting the first sidewall and covering the bottom wall of the first trench, includes: A second dielectric layer is formed along the surface of the first dielectric layer and the inner wall of the first trench; The second dielectric layer is etched using an anisotropic etching process, exposing the upper surface of the first dielectric layer and the substrate within the trench. The remaining second dielectric layer covers the sidewalls of the trench and its width gradually increases from top to bottom. A third dielectric layer is formed along the first dielectric layer, the second dielectric layer, and the surface of the substrate. The stack of the third dielectric layer and the second dielectric layer and the covering pad oxide layer constitute the sidewall. The stack of the third dielectric layer and the pad oxide layer located between the sidewalls in the trench constitutes the gate dielectric layer.
7. The manufacturing method according to any one of claims 1 to 6, characterized in that, After completing the epitaxial process, the fabrication method further includes: A second sidewall is covered on the surface of the first sidewall away from the polysilicon gate; and Source / drain ion implantation is performed on the source / drain epitaxial layer.
8. A PMOS transistor, characterized in that, The PMOS transistor is formed using the fabrication method according to any one of claims 1 to 7, and comprises: Substrate; A gate dielectric layer, a polysilicon gate, a hard mask layer, and a first sidewall are formed on the substrate. The hard mask layer covers the upper surface of the polysilicon gate, and the first sidewall covers the gate dielectric layer, the polysilicon gate, and the sidewall of the hard mask layer. The width of the polysilicon gate gradually decreases from top to bottom. Source / drain epitaxial layers embedded in the substrate on both sides of the polysilicon gate.
9. The PMOS transistor as claimed in claim 8, characterized in that, A second dielectric layer and a third dielectric layer are formed on the substrate. The second dielectric layer is located on both sides of the polysilicon gate and its width gradually increases from top to bottom. The third dielectric layer is located between the polysilicon gate and the second dielectric layer, and between the polysilicon gate and the substrate. The first sidewall includes the second dielectric layer and the third dielectric layer located on the side of the polysilicon gate, and the gate dielectric layer includes the third dielectric layer located between the polysilicon gate and the substrate.
10. The PMOS transistor as claimed in claim 9, characterized in that, A pad oxide layer is also formed on the substrate below the third dielectric layer, and the gate dielectric layer further includes the pad oxide layer.
11. The PMOS transistor as claimed in claim 8, characterized in that, The substrate has Σ-shaped grooves formed on both sides of the polysilicon gate, and the source / drain epitaxial layer fills the grooves.