Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. According to the forming method, an MOS device is formed in an active region, at least one groove is further formed in a source-drain lead-out region, and when a self-aligned metal silicification process is carried out, metal silicification reaction is carried out on the inner surface of the groove and the surface of the source-drain region outside the groove to form a metal silicide layer. According to the method, a metal silicide layer is formed in a source-drain lead-out region, so that the upper surface of the metal silicide layer located in the source-drain lead-out region is a curved surface, and a source-drain through hole formed corresponding to the source-drain lead-out region exposes the metal silicide layer of which the upper surface is the curved surface. The area of the metal silicide layer exposed by the source-drain through hole is increased, after the source-drain plug is formed, the contact area between the source-drain plug and the metal silicide layer exposed by the source-drain through hole is large, the contact resistance between the contact plug and the corresponding source-drain region can be reduced, and the device performance can be improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] Self-aligned metal silicide (Salicide) technology is widely used in semiconductor devices. It enables metal and semiconductor silicon (such as monocrystalline or polycrystalline silicon) to form ohmic contacts through metal silicides, which can reduce the contact resistance and series resistance between the metal and silicon and improve the transmission speed of the device.

[0003] like Figure 1 As shown, in a conventional semiconductor process, after forming a gate G, sidewalls (not shown) on both sides of the gate G, and source / drain regions (including source region S and drain region D) on the surface of a substrate 11, a metal silicide layer 12 is formed on the surface of the source / drain regions and the surface of the gate G using a self-aligned metal silicide process. Then, a dielectric layer 13 is covered on the substrate 11, and vias 13a are formed corresponding to the source / drain regions to expose the metal silicide layer 12. Corresponding to the gate G, vias 13b are formed in the dielectric layer 13 to expose the metal silicide layer 12. Then, conductive material is filled into the vias 13a and 13b to form source / drain plugs that contact the corresponding source / drain regions through the metal silicide layer 12 and gate plugs that contact the gate G through the metal silicide layer 12 (not shown).

[0004] As technology nodes advance, device linewidths continue to shrink. The cross-section of the via 13a in the aforementioned existing process becomes increasingly smaller, leading to increased contact resistance between the source / drain plugs and their corresponding source / drain regions. This, in turn, increases the device's RC (resistance-capacitance) ratio, affecting device performance such as response speed. Although using a self-aligned metal silicide process with a metal material of low resistivity can help reduce this contact resistance, the contact resistance between the source / drain plugs and their corresponding source / drain regions remains high as device linewidths shrink, impacting device performance. Summary of the Invention

[0005] To reduce the contact resistance between the source / drain plug and the corresponding source / drain region, the present invention provides a semiconductor device and a method for forming a semiconductor device.

[0006] On one hand, the present invention provides a method for forming a semiconductor device, the method comprising:

[0007] A substrate is provided, the substrate including trench isolation and an active region defined by the trench isolation, the active region having a source-drain formation region for forming a source-drain region of a MOS device, the surface of the source-drain formation region including a source-drain lead-out region for connecting a source-drain plug;

[0008] A MOS device is formed in the active region, and at least one groove is formed in the source-drain lead-out region. The MOS device includes a gate formed on the active region and source-drain regions formed on both sides of the gate in the active region. The depth of the source-drain regions is greater than the depth of the groove.

[0009] A self-aligned metallization process is performed to cause a metallization reaction on the inner surface of the groove and the surface of the source / drain region outside the groove to form a metallization layer. The upper surface of the metallization layer located in the source / drain lead-out region is curved.

[0010] A dielectric layer is deposited on the substrate, and source / drain vias are formed corresponding to the source / drain exit regions, penetrating the dielectric layer and exposing the metal silicide layer, the source / drain vias exposing the metal silicide layer corresponding to the source / drain exit regions; and

[0011] A source / drain plug is formed by filling the source / drain via with conductive material. The source / drain plug contacts the metal silicide layer exposed by the source / drain via to connect with the corresponding source / drain region.

[0012] Optionally, after the groove is formed, the surface of the source / drain outlet region includes the inner surface of the groove and a portion of the active region surface outside the groove.

[0013] Optionally, the source / drain outlet region forms at least two grooves.

[0014] Optionally, the groove is formed by etching the substrate before or after forming the MOS device or during the formation of the MOS device.

[0015] Optionally, forming the MOS device and the recess includes:

[0016] A gate dielectric material layer is formed on the surface of the substrate;

[0017] The gate dielectric material layer is etched to give the gate dielectric material layer an opening located in the forming region of the groove;

[0018] A gate material layer is formed on the substrate;

[0019] The gate material layer and the gate dielectric material layer are etched to form a gate and a gate dielectric layer between the gate and the active region, while a groove is formed in the substrate corresponding to the opening in the gate dielectric material layer;

[0020] Sidewalls are formed on the gate dielectric layer and the side of the gate, and source / drain regions are respectively located on both sides of the gate. The surface of the source / drain region includes a source / drain lead-out region, and the source / drain lead-out region forms at least one of the grooves.

[0021] Optionally, in the process of etching the gate dielectric material layer to form the opening, the substrate exposed by the opening is also etched.

[0022] On the other hand, the present invention provides a semiconductor device, the semiconductor device comprising:

[0023] The substrate includes trench isolation and an active region defined by the trench isolation;

[0024] A MOS device formed in the active region, the MOS device including a gate formed on the active region and source / drain regions formed on both sides of the gate respectively, the surface of the source / drain region including a source / drain lead-out region, the source / drain lead-out region including at least one groove and a portion of the source / drain region located outside the groove;

[0025] The metal silicide layer formed on the surface of the source / drain region inside and outside the groove has a curved upper surface located in the source / drain lead-out region.

[0026] A dielectric layer is disposed on the substrate, the dielectric layer having source / drain vias corresponding to the source / drain lead-out regions, the source / drain vias exposing the metal silicide layer corresponding to the source / drain lead-out regions; and

[0027] Source / drain plugs fill the source / drain vias and contact the metal silicide layer exposed by the corresponding source / drain vias to connect to the corresponding source / drain regions.

[0028] Optionally, the source / drain outlet region includes at least two grooves and a region located between the at least two grooves.

[0029] Optionally, the cross-section of the groove includes at least one of a circle, a semi-circle, an ellipse, a semi-ellipse, and a polygon.

[0030] Optionally, the metal silicide layer includes at least one of nickel silicide, titanium silicide, tantalum silicide, tungsten silicide, and cobalt silicide.

[0031] In the semiconductor device formation method provided by the present invention, a MOS device is formed in the active region, and at least one groove is also formed in the source / drain lead-out region. During the self-aligned metallization process, metallization reaction occurs on the inner surface of the groove and the surface of the source / drain region outside the groove to form a metal silicide layer, such that the upper surface of the metal silicide layer located in the source / drain lead-out region is curved. The source / drain via formed in the source / drain lead-out region exposes the metal silicide layer with the curved upper surface. Compared with the case where no groove is formed in the source / drain lead-out region before the self-aligned metallization process, the formation method of the present invention increases the area of ​​the metal silicide layer exposed by the source / drain via. After the source / drain plug is formed, the source / drain plug contacts the metal silicide layer exposed by the source / drain via, and the contact area is large, which can reduce the contact resistance between the contact plug and the corresponding source / drain region, which helps to reduce the RC (resistance-capacitance) of the device and improve the device performance.

[0032] In the semiconductor device provided by the present invention, a MOS device is formed in the active region. The source-drain region surface of the MOS device includes a source-drain lead-out region. The source-drain lead-out region includes at least one groove and a portion of the source-drain region located outside the groove. A source-drain plug fills the source-drain via exposed in the source-drain lead-out region and contacts the metal silicide layer exposed by the corresponding source-drain via. Since the upper surface of the metal silicide layer located in the source-drain lead-out region is curved and has a large area, the contact area between the source-drain plug and the metal silicide layer is large, which can reduce the contact resistance between the source-drain plug and the corresponding source-drain region, help reduce the RC (resistance-capacitance) of the device, and improve the device performance. Attached Figure Description

[0033] Figure 1 This is a schematic cross-sectional view of the source / drain vias formed using existing methods to expose the metal silicide layer.

[0034] Figure 2 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0035] Figures 3A to 3J This is a cross-sectional schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0036] The semiconductor device and its formation method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed; some steps may be omitted and / or other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or otherwise positioned (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0037] This invention first relates to a method for forming a semiconductor device, which reduces the contact resistance between the source / drain plug and the corresponding source / drain region. The following refers to... Figure 2 as well as Figures 3A to 3J The formation method is described below.

[0038] Reference Figure 2 and Figure 3A According to the semiconductor device formation method of the present invention, step S1 is first performed, in which a substrate 100 is provided. The substrate 100 includes a trench isolation (e.g., a shallow trench isolation STI) and an active region AA defined by the trench isolation. The active region AA has a source drain formation region 10 for forming a source drain region of a MOS device. The surface of the source drain formation region 10 includes a source drain lead-out region 10a for connecting a source drain plug.

[0039] The substrate 100 can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or other substrates known to those skilled in the art for supporting semiconductor devices. The substrate 100 can also be implanted with certain dopant ions to change electrical parameters according to design requirements. The trench isolation is, for example, shallow trench isolation (STI), which includes an isolation material (such as silicon oxide) embedded in the surface of the substrate 100. It is understood that, as needed, the trench isolation can define two or more active regions AA in the substrate. This embodiment uses the process of one active region AA as an example for illustration; other active regions AA may or may not use the processes described in the following embodiments.

[0040] The active region AA is designed to form a MOS device. The formation regions of the gate and source / drain regions of the MOS device can be determined according to the specific design. The source / drain formation region 10 is used to form the source / drain regions of the MOS device. The source / drain regions are subsequently electrically led out from the substrate 100 through source / drain plugs. The formation position of the source / drain plugs can be determined according to specific settings. The source / drain lead-out region 10a is the surface area of ​​the source / drain formation region 10 used to connect the source / drain plugs.

[0041] Reference Figure 1 and Figure 3F According to the semiconductor device formation method of the present invention, step S2 is then performed, in which a MOS device is formed in the active region AA, and at least one groove 20 is formed in the source / drain lead-out region 10a. The MOS device includes a gate G formed on the active region AA and source / drain regions (e.g., on both sides of the gate G) of the active region. Figure 3F The first source / drain region 31 and the second source / drain region 32 shown are provided, and the depth of the source / drain region is greater than the depth of the groove 20.

[0042] The formation of a MOS device in the active region AA can be achieved using known processes. In this embodiment, in addition to forming the MOS device, step S2 also forms at least one groove 20 in the source / drain lead-out region 10a. Depending on the specific process design, the groove 20 can be formed by etching the substrate of the source / drain lead-out region 10a before, after, or during the formation of the MOS device.

[0043] As an example, in one embodiment, before forming the gate dielectric material layer, a dielectric layer (such as silicon oxide and / or silicon nitride) and a photoresist layer are formed on the surface of the active region AA. Then, photolithography is performed to give the photoresist layer a pattern that defines the groove 20. Afterward, the dielectric layer and the substrate 100 of the source / drain lead-out region 10a are etched using a dry or wet etching process or a SiCoNi process to form at least one groove 20 in the source / drain lead-out region 10a.

[0044] As an example, in another embodiment, a gate and a gate dielectric layer between the gate and the substrate of the active region AA are first formed on the active region AA. Then, sidewalls are formed on the side of the gate and the gate dielectric layer. Then, ion implantation is performed on the active regions AA on both sides of the gate to form source and drain regions, thereby forming a MOS device. Next, a photoresist layer is formed on the substrate 100, and photolithography is performed to give the photoresist layer a pattern that defines the groove 20. The substrate of the source and drain regions is etched using a dry or wet etching process or a SiCoNi process to form at least one groove 20 in the source and drain lead-out region 10.

[0045] As an example, in the following embodiments, the groove 20 is formed during the formation of a MOS device, which may specifically include the following process.

[0046] First, refer to Figure 3B A gate dielectric material layer 101 is formed on the surface of the substrate 100, and the gate dielectric material layer 101 is, for example, silicon oxide.

[0047] Then, refer to Figure 3C The gate dielectric material layer 101 is etched to give the gate dielectric material layer 101 an opening 101a located in the formation region of the groove 20. For example, a photoresist layer can be coated on the substrate 100 and photolithography can be performed to define the position of the opening 101a. Then the gate dielectric material layer 101 is etched to form the opening 101a located above the source / drain lead-out region 10a.

[0048] The arrangement and pattern of the openings 101a in the gate dielectric material layer 101 can be configured according to the specific needs of the grooves 20 to be formed in the source / drain lead-out regions 10a. For example, corresponding to a source / drain lead-out region 10a, one, two, or more openings 101a can be formed in the gate dielectric material layer 101. Figure 3B (Two are shown in the example) so that one, two or more grooves 20 can be formed in the corresponding source / drain outlet region 10a. For the same source / drain outlet region 10a, the total area of ​​the formed openings 101a can be less than or equal to the area of ​​the source / drain outlet region 10.

[0049] Next, refer to Figure 3D A gate material layer 102 is formed on the substrate 100. In order to subsequently etch the gate material layer 102 to form a gate, a photoresist layer PR is also formed on the gate material layer 102 and the photoresist layer PR is patterned. The gate material layer 102 fills the opening 101a in the gate dielectric material layer 101.

[0050] Then, refer to Figure 3E The gate material layer 102 and the gate dielectric material layer 101 are etched to form the gate G from the gate material layer 102, and the gate dielectric material layer 110, located between the gate G and the active region AA, is formed from the gate dielectric material layer 101. Furthermore, during the etching of the gate material layer 102, due to the etching selectivity between the gate material layer 102, the substrate 100, and the gate dielectric material layer 101, after the gate material layer 102 is etched to form the gate G, the gate dielectric material layer 101 covers the active region AA except for the opening 101a. The substrate 100 at the opening 101a is exposed. During over-etching, the etch rate of the substrate 100 exposed at the opening 101a is greater than the etch rate of the area covered by the gate dielectric material layer 101, thereby forming a groove 20 in the source / drain lead-out region 10a corresponding to the opening 101a. The etching of the gate material layer 102, the gate dielectric material layer 101, and the substrate 100 of the source / drain lead-out region 10a can be performed using dry or wet etching processes.

[0051] Next, refer to Figure 3F This forms sidewalls SP located on the sides of the gate dielectric layer 110 and the gate G, as well as source and drain regions AA located on both sides of the gate G, such as... Figure 3F The first source / drain region 31 and the second source / drain region 32 are shown. The source / drain region is formed in the source / drain formation region 10, and its surface includes the source / drain lead-out region 10a, which has at least one groove 10 formed as described above. In this embodiment, the subsequently formed source / drain plug fills the groove 10 and connects to the metal silicide layer on the surface of the source / drain region, thus setting the depth of the source / drain region to be greater than the depth of the groove 20.

[0052] As an example, firstly, offset sidewalls (not shown) are formed on the gate dielectric layer 110 and the side of the gate G using a sidewall process. Then, LDD implantation is performed to form LDD regions in the active regions AA on both sides of the gate G. Next, a main sidewall is formed outside the offset sidewalls using the same sidewall process. The offset sidewalls and the main sidewalls form sidewall SP. Then, source / drain ion implantation is performed to form source / drain regions in the active regions AA on both sides of the gate G. The range of the source / drain regions covers the aforementioned source / drain lead-out region 10a, and the surface of the source / drain regions includes the inner surface of the groove 20 and the source / drain region surface outside the groove 20.

[0053] Utilize Figures 3B to 3F The process shown involves forming at least one trench 20 in the source / drain lead-out region 10a during the formation of the MOS device. In this process, the substrate 100 is not etched during the formation of the opening 101a in the gate dielectric material layer 101. However, the present invention is not limited to this. In another embodiment, when the gate dielectric material layer 101 is etched to form the opening 101a, the substrate 100 exposed by the opening 101a is also etched (i.e., forming part of the depth of the trench 20). Subsequently, when the gate material layer 102 and the gate dielectric material layer 101 are etched to form the gate G and the gate dielectric layer 110, the area of ​​the substrate 100 exposed by the opening 101a is further etched to form the trench 20.

[0054] After the above process, grooves 20 are formed in the source / drain lead-out regions 10a on both sides of the gate G. Depending on the needs, one, two, or more grooves 20 can be formed in the same source / drain lead-out region 10a. In order to increase the surface area of ​​the source / drain lead-out region 10a and thus increase the area of ​​the metal silicide layer subsequently formed in this region, in one embodiment, at least two grooves 20 are formed in the same source / drain lead-out region 10a.

[0055] After the groove 20 is formed, the surface of the source / drain lead-out region 10a may only include the inner surface of the groove 20, or the surface of the source / drain lead-out region 10a may include the inner surface of the groove 20 and a portion of the active region AA surface outside the groove 20. For example... Figure 3FAs shown, as an example, the source / drain formation region 10a has a remaining area not occupied by the groove 20 after the groove 20 is formed. After the source / drain region is formed, the source / drain formation region 10a includes the inner surface of the groove 20 and a portion of the source / drain region surface outside the groove 20. Furthermore, for a single groove 20, it may be entirely located within the corresponding source / drain formation region 10a (i.e., the orthographic projection of the groove 20 onto the upper surface of the substrate 100 is located within the corresponding source / drain formation region 10a), or it may be partially located within the corresponding source / drain formation region 10a and partially located outside the corresponding source / drain formation region 10a (i.e., a portion of the orthographic projection of the groove 20 onto the upper surface of the substrate 100 is located within the corresponding source / drain formation region 10a, and another portion is located outside the corresponding source / drain formation region 10a).

[0056] Reference Figure 2 and Figure 3G Next, step S3 is executed to perform a self-aligned metal silicide process, so that the inner surface of the groove 20 and the source / drain region surface outside the groove 20 undergo a metal silicide reaction to form a metal silicide layer 130. The upper surface of the metal silicide layer 130 located in the source / drain lead-out region 10a is curved.

[0057] In the self-aligned metal silicide process, a metal layer may first be deposited on the substrate 100. This metal layer may include at least one of Ni, Ti, W, Co, Mn, Mo, Zr, Ta, W, Pd, Pt, and Yb. For example, the metal layer may be a NiPt alloy. Optionally, a titanium nitride layer may also be formed on the surface of the metal layer. Subsequently, thermal annealing is performed to react the metal layer with the silicon on the surface of the source / drain regions and the silicon on the upper surface of the gate G to form metal silicides. The unreacted metal layer is then removed.

[0058] In this embodiment, a groove 20 is formed in the source / drain lead-out region 10a within the source / drain region. During the self-aligned metallization process, the inner wall of the groove 20 reacts with the metal layer. After the self-aligned metallization process is completed, a metal silicide layer 130 is formed on the surface of the source / drain region, including the inner wall of the groove 20. That is, the metal silicide layer 130 formed in the source / drain region follows the undulating surface of the source / drain region, and the upper surface of the metal silicide layer 130 in the source / drain lead-out region 10a is curved. It can be seen that compared to the case where the groove 20 is not formed during the self-aligned metallization process, resulting in a basically planar upper surface of the metal silicide layer, the upper surface of the metal silicide layer 130 formed using the method of this embodiment is curved, thus increasing the area.

[0059] Reference Figure 2 , Figure 3H and Figure 3INext, step S4 is performed, in which a dielectric layer 140 is deposited on the substrate 100, and a source / drain via 140a is formed corresponding to the source / drain exit region 10a, penetrating the dielectric layer 140 and exposing the metal silicide layer 130. The source / drain via 140a exposes the groove 20 of the corresponding source / drain exit region 10a. Furthermore, through step S4, a gate via 140b can also be formed corresponding to the gate G, penetrating the dielectric layer 140 and exposing the metal silicide layer 130 on the upper surface of the gate.

[0060] like Figure 3H As shown, in step S4, a dielectric layer 140 is first deposited on the active region AA. The dielectric layer 140 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogen-doped Silicon Carbide). As an example, the dielectric layer 140 may include a contact hole etch stop layer formed conformally on the substrate 100 and an interlayer dielectric layer covering the contact hole etch stop layer. Furthermore, in order to etch the dielectric layer 140 to form source / drain vias and gate vias, a patterned mask layer 150 may be formed on the dielectric layer 140 after its formation to define the locations of the source / drain vias and gate vias. The mask layer 150 may be, for example, a photoresist layer or a stack of a photoresist layer and an anti-reflective layer.

[0061] like Figure 3I As shown, the dielectric layer 140 is etched to form source / drain vias 140a and gate vias 140b. The dielectric layer 140 can be etched using a dry etching process.

[0062] In this embodiment, the source / drain via 140a is formed corresponding to the source / drain exit region 10a, and the orthographic projection of the source / drain via 140a onto the upper surface of the substrate 100 coincides with, for example, the source / drain exit region 10a. After the source / drain via 140a is formed, it exposes a portion of the source / drain region of the source / drain exit region 10a, thereby exposing the aforementioned groove 20. In some embodiments, during the etching process of forming the source / drain via 140a, a portion of the metal silicide layer 130 may also be etched away. However, even if the metal silicide layer 130 is etched, the upper surface of the metal silicide layer 130 in the source / drain exit region 10a remains curved and its area further increases because the inner wall of the groove 20 is etched.

[0063] Reference Figure 2 and Figure 3J In step S5, conductive material is filled into the source / drain via 140a to form a source / drain plug CT1, which contacts the metal silicide layer 30 exposed by the corresponding source / drain via 140a. Additionally, step S5 may also fill conductive material into the gate via 140b to form a gate plug CT2.

[0064] As an example, an adhesion layer (such as Ti / TiN) can be first formed on the sidewalls and bottom walls of the source / drain via 140a and the gate via 140b, then a metal material (such as tungsten) can be filled in, and a planarization process (such as CMP) can be performed to expose the upper surface of the dielectric layer 140. The remaining metal material is filled in the source / drain via 140a and the gate via 140b to form source / drain plugs CT1 and gate plugs CT2, respectively.

[0065] In the semiconductor device formation method described in the above embodiments, a MOS device is formed in the active region AA, and at least one groove 20 is also formed in the source / drain lead-out region 10a. During the self-aligned metal silicide process, a metal silicide layer 130 is formed on both the inner surface of the groove 20 and the surface of the source / drain region outside the groove 20, such that the upper surface of the metal silicide layer 130 located in the source / drain lead-out region 10a is curved. When a source / drain via 140a is formed corresponding to the source / drain lead-out region 10a, the source / drain via 140a will expose the corresponding source / drain lead-out region. After the curved metal silicide layer 130 of domain 10a forms a source / drain plug CT1 in the source / drain via 140a, the source / drain plug CT1 fills the groove 20 exposed by the source / drain via 140a and contacts the curved metal silicide layer 130 exposed by the source / drain via 140a. The contact area between the source / drain plug CT1 and the metal silicide layer 130 is large, which can reduce the contact resistance between the source / drain plug CT1 and the corresponding source / drain region, which helps to reduce the resistance-capacitance (RC) of the device and improve the device performance (such as response speed).

[0066] This invention also relates to a semiconductor device. (See attached image.) Figure 3J The semiconductor device includes a substrate 100, the substrate 100 including trench isolation (such as shallow trench isolation, STI) and an active region AA defined by the trench isolation, the semiconductor device further including a MOS device formed in the active region AA, the MOS device including a gate G formed on the active region AA and source / drain regions formed on both sides of the gate G in the active region AA (such as shallow trench isolation, STI) Figure 3J The first source / drain region 31 and the second source / drain region 32 are shown. The surface of the source / drain region includes a source / drain lead-out region 10a for connecting the source / drain plug CT1. The source / drain lead-out region 10a includes at least one groove 20 and a portion of the source / drain region located outside the groove 20. The depth of the source / drain region is greater than the depth of the groove 20. The semiconductor device also includes a metal silicide layer 130 formed within and outside the groove 20 on the surface of the source / drain region, a dielectric layer 140 covering the substrate 100, and the source / drain plug CT1.

[0067] like Figure 3JAs shown, the MOS device may further include a gate dielectric layer 110 between the gate G and the substrate 100, and sidewalls SP formed on the sides of the gate G and the gate dielectric layer 110.

[0068] Since the source / drain lead-out region 10a has a groove 20, the upper surface of the metal silicide layer 130 located in the source / drain lead-out region 10a is curved. In addition, the metal silicide layer 130 may also be formed on the upper surface of the gate G.

[0069] The dielectric layer 140 has a source / drain via 140a corresponding to the source / drain lead-out region 10a, which exposes the metal silicide layer 130 corresponding to the source / drain lead-out region 10a. The dielectric layer 140 may also have a gate via 140b corresponding to the gate G, which exposes the metal silicide layer 130 on the upper surface of the gate G.

[0070] The source / drain plug CT1 fills the source / drain via 140a corresponding to the source / drain lead-out region 10a, thus filling the groove 20 of the corresponding source / drain lead-out region 10a. The source / drain plug CT1 contacts the metal silicide layer 130 exposed by the corresponding source / drain via 140a, thereby connecting to the corresponding source / drain region through the metal silicide layer 130. The semiconductor device may also include a gate plug CT2, which fills the gate via 140b and contacts the metal silicide layer 130 formed on the upper surface of the gate G exposed by the gate via 140b, thereby connecting to the gate G through the metal silicide layer 130.

[0071] like Figure 3J As shown, in some embodiments, the source / drain lead-out region 10a may include at least two grooves 20 and a region located between the at least two grooves 20. Accordingly, the source / drain plug CT1 formed corresponding to the source / drain lead-out region 10a will contact the metal silicide layer 130 located between the at least two grooves 20.

[0072] As an example, the cross-section of the groove 20 may include at least one of a circle, a semi-circle, an ellipse, a semi-ellipse, and a polygon. The metal silicide layer 130 may include at least one of nickel silicide, titanium silicide, tantalum silicide, tungsten silicide, and cobalt silicide.

[0073] In the semiconductor device described in the above embodiments, an active region AA is formed with a MOS device. The source / drain region surface of the MOS device includes a source / drain lead-out region 10a. The source / drain lead-out region 10a includes at least one groove 20 and a portion of the source / drain region located outside the groove 20. The source / drain plug CT1 fills the source / drain via 140a that exposes the source / drain lead-out region 10a and contacts the metal silicide layer 130 exposed by the corresponding source / drain via 140a. Since the upper surface of the metal silicide layer 130 located in the source / drain lead-out region 10a is curved and has a large area, the contact area between the source / drain plug CT1 and the metal silicide layer 130 is large, which can reduce the contact resistance between the source / drain plug CT1 and the corresponding source / drain region, help reduce the device RC (resistance-capacitance), and improve device performance.

[0074] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided, the substrate including trench isolation and an active region defined by the trench isolation, the active region having a source-drain formation region for forming a source-drain region of a MOS device, the surface of the source-drain formation region including a source-drain lead-out region for connecting a source-drain plug; A MOS device is formed in the active region, and at least one groove is formed in the source-drain lead-out region. The MOS device includes a gate formed on the active region and source-drain regions formed on both sides of the gate in the active region. The depth of the source-drain regions is greater than the depth of the groove. A self-aligned metallization process is performed to cause a metallization reaction on the inner surface of the groove and the surface of the source / drain region outside the groove to form a metallization layer. The upper surface of the metallization layer located in the source / drain lead-out region is curved. A dielectric layer is covered on the substrate, and a source / drain via is formed corresponding to the source / drain lead-out region, penetrating the dielectric layer and exposing the metal silicide layer, the source / drain via exposing the metal silicide layer corresponding to the source / drain lead-out region; as well as A source / drain plug is formed by filling the source / drain via with conductive material. The source / drain plug contacts the metal silicide layer exposed by the source / drain via to connect with the corresponding source / drain region.

2. The forming method as described in claim 1, characterized in that, After the groove is formed, the surface of the source / drain lead-out region includes the inner surface of the groove and a portion of the active region surface outside the groove.

3. The forming method as described in claim 1, characterized in that, The source / drain outlet region forms at least two grooves.

4. The forming method as described in claim 1, characterized in that, The groove is formed by etching the substrate before, after, or during the formation of the MOS device.

5. The forming method according to any one of claims 1 to 4, characterized in that, Forming the MOS device and the groove includes: A gate dielectric material layer is formed on the surface of the substrate; The gate dielectric material layer is etched to give the gate dielectric material layer an opening located in the forming region of the groove; A gate material layer is formed on the substrate; Etching the gate material layer and the gate dielectric material layer to form a gate and a gate dielectric layer between the gate and the active region, while simultaneously forming the groove in the substrate corresponding to the opening in the gate dielectric material layer; and Sidewalls are formed on the gate dielectric layer and the side of the gate, and source / drain regions are respectively located on both sides of the gate. The surface of the source / drain region includes a source / drain lead-out region, and the source / drain lead-out region forms at least one of the grooves.

6. The forming method as described in claim 5, characterized in that, In the process of etching the gate dielectric material layer to form the opening, the substrate exposed by the opening is also etched.

7. A semiconductor device, characterized in that, include: The substrate includes trench isolation and an active region defined by the trench isolation; A MOS device formed in the active region, the MOS device including a gate formed on the active region and source / drain regions formed on both sides of the gate respectively, the surface of the source / drain region including a source / drain lead-out region, the source / drain lead-out region including at least one groove and a portion of the source / drain region located outside the groove, the depth of the source / drain region being greater than the depth of the groove; The metal silicide layer formed on the surface of the source / drain region inside and outside the groove has a curved upper surface located in the source / drain lead-out region. A dielectric layer is provided on the substrate, wherein the dielectric layer has source / drain vias formed corresponding to the source / drain lead-out regions, and the source / drain vias expose the metal silicide layer corresponding to the source / drain lead-out regions; as well as Source / drain plugs fill the source / drain vias and contact the metal silicide layer exposed by the corresponding source / drain vias to connect to the corresponding source / drain regions.

8. The semiconductor device as claimed in claim 7, characterized in that, The source / drain outlet region includes at least two grooves and a region located between the at least two grooves.

9. The semiconductor device as claimed in claim 7, characterized in that, The cross-section of the groove includes at least one of the following: circular, semi-circular, elliptical, semi-elliptical, and polygonal.

10. The semiconductor device according to any one of claims 7 to 9, characterized in that, The metal silicide layer includes at least one of nickel silicide, titanium silicide, tantalum silicide, tungsten silicide, and cobalt silicide.

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